Wafer test box

Abstract

The invention discloses a wafer test box, which is provided with a fluid inlet and a fluid outlet, and comprises a first shell, a second shell, a heat source and an isolation device, the first shell is provided with a probe card, and the probe card is provided with a probe. The second shell is combined with the first shell to form a test space, a wafer is carried in the second shell, the wafer is located in the test space, and the probe is electrically contacted with the upper surface of the wafer to execute a test program. The heat source is used for heating the lower surface of the wafer, and a high-temperature area is defined between the lower surface and the second shell. The isolation device surrounds the high-temperature area and is used for thermally isolating the high-temperature area from the test space. The fluid inlet receives gas, the gas circulates in the test space and fills the space between the probe card and the upper surface of the wafer, and the gas flows out through the fluid outlet.

Description

Technical Field

[0001] The present application relates to a wafer testing box, and in particular to a wafer testing box with heat conduction and heat isolation. Background Art

[0002] When the wafer completes the design of the integrated circuit, the wafer needs to undergo a burn-in test and an electrical test. Traditionally, the wafer burn-in and reliability test is performed by testing each wafer separately through a test machine and a probe card. Each wafer is placed on a carrier and electrically contacted with the probe of the probe card to complete the test. Therefore, when the number of wafers is large, more test machines and probe cards are required, and the test process generates greater time and equipment costs.

[0003] Recently, a wafer test box has been developed, which pre-positions the probe card and wafer and places them in the wafer test box. The wafer test box is directly connected to the test machine electrically, and the wafer test box is placed in the test unit to perform a burn-in test or electrical test. During the burn-in test, the wafer test box is placed in a high temperature environment, and the thermal effect may affect the operation of the probe and the test machine, reducing the efficiency of the test process.

[0004] Therefore, how to improve the use effect of the wafer test box through structural design improvement to overcome the above-mentioned defects has become one of the important issues to be solved in the technical field. Summary of the invention

[0005] The technical problem to be solved by the present application is to provide a wafer test box to address the deficiencies of the prior art, which has a thermal isolation effect to prevent the thermal effect provided by the wafer test box during pre-burning from affecting the operation of the probe and the test host.

[0006] The present application provides a wafer test box having a fluid inlet and a fluid outlet, and the wafer test box includes: a first shell, a second shell, a heat source and an isolation device. The first shell has a probe card, and the probe card has a probe. The second shell is combined with the first shell to form a test space, and the second shell carries a wafer, and the wafer is located in the test space. The probe electrically contacts the upper surface of the wafer to perform a test procedure. The heat source is used to heat the lower surface of the wafer, and a high-temperature area is defined between the lower surface and the second shell. The isolation device surrounds the high-temperature area and is used to thermally isolate the high-temperature area from the test space. The fluid inlet receives gas, and the gas circulates in the test space and fills between the probe card and the upper surface of the wafer, and the gas flows out through the fluid outlet.

[0007] According to a feasible embodiment, the pressure inside the test space is greater than the pressure outside the test space.

[0008] According to a feasible embodiment, the wafer test box also includes a valve, a sensor and a control circuit. The sensor and the valve are respectively connected to the control circuit, and the valve can open or close at least one fluid outlet; the sensor senses at least one of the pressure or temperature in the test space and transmits the sensing information to the control circuit, and the control circuit controls the opening and closing of the valve based on the sensing information.

[0009] According to a feasible embodiment, the wafer testing box further includes at least one exhaust device, and the at least one exhaust device is connected to the at least one fluid outlet to increase the gas flow rate in the testing space.

[0010] According to a feasible embodiment, the wafer testing box further includes an air intake device, which is connected to the fluid inlet to increase the gas flow in the testing space.

[0011] According to a possible embodiment, the gas is formed by air or an inert gas.

[0012] According to a feasible embodiment, the thermal conductivity of the gas is less than 0.026 W / mK.

[0013] According to a feasible embodiment, the specific heat of the gas is less than 1.015 kJ / (kga·K).

[0014] According to a feasible embodiment, the second shell has a heat flow inlet and a heat flow outlet corresponding to the high temperature area, and the heat source is hot air, which enters from the heat flow inlet and flows out from the heat flow outlet.

[0015] One of the beneficial effects of the present application is that the wafer test box provided by the present application can fill the gas between the probe card and the upper surface of the wafer and isolate it from the high-temperature area through the technical solutions of "an isolation device surrounding the high-temperature area and used for thermally isolating the high-temperature area and the test space" and "a fluid inlet receiving gas, the gas circulating in the test space, and flowing out through the fluid outlet", thereby preventing the probe card from being affected by the high temperature of the wafer when executing the test program and affecting the test results, and protecting the test device (such as the probe card) and the test end (such as the test host) of the wafer test box, thereby improving the efficiency of the wafer test box detection process.

[0016] To further understand the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the drawings provided are only for reference and illustration and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the wafer testing box in use according to one embodiment of the present application.

[0018] Figure 2It is a schematic diagram of the wafer testing box in use according to one embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of the wafer testing box in use according to one embodiment of the present application.

[0020] Figure 4 It is a schematic diagram of the wafer testing box in use according to one embodiment of the present application.

[0021] Figure 5 It is a schematic diagram of the wafer testing box in use according to one embodiment of the present application.

[0022] Figure 6 It is a schematic diagram of the wafer testing box in use according to one embodiment of the present application.

[0023] Figure 7 It is a schematic diagram of the wafer testing box in use according to one embodiment of the present application. DETAILED DESCRIPTION

[0024] The following is an explanation of the implementation of the "wafer test box" disclosed in this application through specific embodiments. Those skilled in the art can understand the advantages and effects of this application from the contents disclosed in this specification. This application can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this application. In addition, the drawings of this application are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementation methods will further explain the relevant technical content of this application in detail, but the disclosed content is not intended to limit the scope of protection of this application.

[0025] See also Figure 1, is a schematic diagram of the use state of a wafer test box 1A of an embodiment of the present application. The wafer test box 1A has a fluid inlet 113 and a fluid outlet 114, and the wafer test box 1A includes: a first shell 11, a second shell 12, a heat source 14 and an isolation device 15. The first shell 11 has a probe card 111, and the probe card 111 has a plurality of probes 1111. The second shell 12 is combined with the first shell 11 to form a test space S1. The second shell 12 carries a wafer 13 and is located in the test space S1. The probe 1111 electrically contacts the upper surface of the wafer 13 (such as electrically contacts the pad 131 on the wafer 13) to perform the test procedure. The heat source 14 is used to heat the lower surface of the wafer 13, and a high temperature area S2 is defined between the lower surface and the second shell 12. The high temperature area S2 can be a space or a heated "surface". The isolation device 15 surrounds the high temperature area S2 and is used to thermally isolate the high temperature area S2 from the test space S1. In this embodiment, the isolation device 15 is used to isolate the heat energy transmitted by the heat source 14 from entering the test space S1, so as to avoid reducing the heat dissipation efficiency of the gas CA due to the heat transfer. The fluid inlet 113 receives the gas CA, and the gas CA flows in the test space S1 and fills between the probe card 111 and the upper surface of the wafer 13, and the gas CA flows out through the fluid outlet 114. The temperature of the gas CA can be room temperature or a cold gas below room temperature.

[0026] According to some embodiments, the gas CA is formed of air or an inert gas. In addition, according to some embodiments, the thermal conductivity of the gas is less than 0.026 W / mK. According to some other embodiments, the specific heat of the gas is less than 1.015 kJ / (kga·K).

[0027] According to some embodiments, the heat source 14 is a heater, but is not limited thereto. According to other embodiments, the heat source 14 may also be hot air or hot gas (see the following embodiments for details).

[0028] In this embodiment, the fluid inlet 113 and the fluid outlet 114 are opened in the first housing 11. However, according to some embodiments, one of the fluid inlet 113 and the fluid outlet 114 is opened in the first housing 11 and the other is opened in the second housing 12, and the present invention is not limited thereto. When the probe performs a test procedure, the gas CA flows through the test space S1 and then leaks out, so as to prevent the temperature of the wafer 13 during pre-burning from affecting the operation of the probe and the test host electrically connected thereto.

[0029] See also Figure 2, is a schematic diagram of the use state of a wafer test box 1B according to an embodiment of the present application. According to this embodiment, the heat source 14 is located outside the second shell 12 corresponding to the wafer 13, and the second shell 12 is provided with an isolation device 15, which surrounds the wafer 13. The isolation device 15 is projected along the projection direction D, and its projection area covers the heat source 14. In this way, the heat source 14 can heat the wafer 13 through the second shell 12, and the isolation device 15 can prevent heat energy from entering the test space S1, or prevent heat energy from being transmitted to the first shell 11 through the second shell 12 to affect the temperature in the test space S1.

[0030] See also Figure 3 , is a schematic diagram of the use state of a wafer test box 1C according to an embodiment of the present application. According to this embodiment, the heat source 14 is hot air, and the second housing 12 has a heat flow inlet and a heat flow outlet corresponding to the high temperature area S2, and the hot air enters from the heat flow inlet and flows out from the heat flow outlet. In other words, the isolation device 15 supports the wafer 13, and the hot air flows in the high temperature area S2 to heat the wafer 13.

[0031] According to some embodiments, when the probe performs a test procedure, the first housing 11 and the second housing 12 are tightly combined, and the pressure in the test space S1 is greater than the pressure outside the test space S1. In this way, the discharge of the probe tip to the wafer 13 can be suppressed, and the wafer 13 can be prevented from being damaged by the tip discharge phenomenon.

[0032] See also Figure 4 , is a schematic diagram of the use status of a wafer test box 1D according to an embodiment of the present application. The wafer test box 1D also includes a valve 16, a sensor 17 and a control circuit 18. The sensor 17 and the valve 16 are respectively connected to the control circuit 18. The valve 16 can open or close the fluid outlet 114. The sensor 17 senses at least one of the pressure or temperature in the test space S1, and transmits the sensing information to the control circuit 18. The control circuit 18 controls the opening and closing of the valve 16 according to the sensing information. In other words, the control circuit 18 receives the sensing information, corresponds to the pressure and / or temperature in the test space S1, and decides whether to discharge the gas CA from the fluid outlet 114, so as to achieve the purpose of controlling the pressure and / or temperature in the test space S1.

[0033] See also Figure 5 , is a schematic diagram of the use status of a wafer test box 1E according to an embodiment of the present application. According to the embodiment, the wafer test box 1E also includes an exhaust device 19, and the exhaust device 19 is connected to the fluid outlet 114. The exhaust device 19 can extract the gas CA flow rate of the test space S1. According to some embodiments, the exhaust device 19 can extract the gas CA of the test space S1 in sections, and can also extract gas CA with different flow rates, depending on the degree of heat conduction required by the test space S1. According to some embodiments, the exhaust device 19 is connected to the control circuit 18 (see Figure 4), the flow rate extracted by the exhaust device is determined by the control circuit 18.

[0034] See also Figure 6 , is a schematic diagram of the use status of a wafer test box 1F according to an embodiment of the present application. According to the embodiment, the wafer test box 1F also includes an air intake device 20, and the air intake device 20 is connected to the fluid inlet 113. The air intake device 20 can determine the flow rate of the gas CA input into the test space S1. According to some embodiments, the air intake device 20 can input the gas CA into the test space S1 in sections, or input gas CA with different flow rates, depending on the required flow rate of the test space S1. According to some embodiments, the air intake device 20 is connected to the control circuit 18 (see Figure 4 ), the control circuit 18 determines the flow rate of the gas CA input (increased) by the intake device 20.

[0035] See also Figure 7 , is a schematic diagram of the use state of a wafer test box 1G according to an embodiment of the present application. According to the embodiment, the wafer test box 1G includes an exhaust device 19 and an air intake device 20. In this way, the wafer test box 1G can extract the flow of the gas CA in the test space S1 through the exhaust device 19, input the flow of the gas CA in the test space S1 through the air intake device 20, or a combination thereof, to increase the flow of the gas CA in the test space S1.

[0036] One of the beneficial effects of the present application is that the wafer test box provided by the present application can fill the gas between the probe card and the upper surface of the wafer and isolate it from the high-temperature area through the technical solutions of "an isolation device surrounding the high-temperature area and used for thermally isolating the high-temperature area and the test space" and "a fluid inlet receiving gas, the gas circulating in the test space, and flowing out through the fluid outlet", thereby preventing the probe card from being affected by the high temperature of the wafer when executing the test program and affecting the test results, and protecting the test device (such as the probe card) and the test end (such as the test host) of the wafer test box, thereby improving the efficiency of the wafer test box detection process.

Claims

1. A wafer testing box, characterized in that: The wafer testing box has at least one fluid inlet and at least one fluid outlet, and the wafer testing box includes: A first housing having a probe card, wherein the probe card has at least one probe; A second shell is combined with the first shell to form a test space, wherein a wafer is carried in the second shell, and the wafer is located in the test space, and the at least one probe electrically contacts the upper surface of the wafer to perform a test procedure; a heat source for heating a lower surface of the wafer, wherein a high temperature region is defined between the lower surface and the second shell; and an isolation device, the isolation device surrounding the high temperature area and used for thermally isolating the high temperature area from the test space; The fluid inlet receives gas, the gas flows in the test space and fills the space between the probe card and the upper surface of the wafer, and the gas flows out through the at least one fluid outlet.

2. The wafer testing box according to claim 1, characterized in that: The pressure inside the test space is greater than the pressure outside the test space.

3. The wafer testing box according to claim 1, characterized in that: The wafer testing box also includes a valve, a sensor and a control circuit. The sensor and the valve are respectively connected to the control circuit. The valve can open or close the at least one fluid outlet. The sensor senses at least one of the pressure or temperature in the testing space and transmits the sensing information to the control circuit. The control circuit controls the opening and closing of the valve based on the sensing information.

4. The wafer testing box according to claim 1, characterized in that: The wafer testing box further includes at least one exhaust device, and the at least one exhaust device is connected to the at least one fluid outlet to increase the gas flow rate in the testing space.

5. The wafer testing box according to claim 1, characterized in that: The wafer testing box further includes an air intake device, which is connected to the fluid inlet and is used to increase the gas flow in the testing space.

6. The wafer testing box according to claim 1, characterized in that: The gas is formed from air or an inert gas.

7. The wafer testing box according to claim 1, characterized in that: The thermal conductivity of the gas is less than 0.026 W / mK.

8. The wafer testing box according to claim 1, characterized in that: The specific heat of the gas is less than 1.015 kJ / (kga·K).

9. The wafer testing box according to claim 1, characterized in that: The second shell has a heat flow inlet and a heat flow outlet corresponding to the high temperature area. The heat source is hot air, which enters from the heat flow inlet and flows out from the heat flow outlet.

10. The wafer testing box according to claim 1, characterized in that: The heat source is located inside or outside the second shell corresponding to the wafer, and provides thermal energy to heat the high temperature area or the wafer.

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