Variable gain high-current test circuits and electronic devices for automated chip testing

Abstract

This disclosure provides a variable gain high-current test circuit and electronic device for automatic chip testing, comprising: a sensor module, a reference voltage calibration module, a first differential module, and an output voltage determination module. The sensor module is configured to generate a sampling voltage based on a sampling current. The reference voltage calibration module is configured to generate a target reference voltage based on an initial reference voltage, wherein the initial reference voltage is related to the chip's rated current, and the target reference voltage is related to the sensor module's current range. The first differential module is configured to determine the conduction state based on the chip's rated current and to determine the conduction gain based on the target reference voltage and the sampling voltage. The output voltage determination module is configured to determine the target output voltage based on the sensor module's sensitivity, the sensor module's sampling current, and the first differential module's conduction gain. This enables direct measurement of high currents such as chip overload current and short-circuit current.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of integrated circuit technology and related technical fields, and more specifically, to a variable gain high current test circuit and electronic device suitable for automated chip testing. Background Technology

[0002] A chip, short for integrated circuit, also known as a microcircuit or microchip, is made by integrating various electronic components, including semiconductor devices, onto a tiny dielectric substrate through a series of processes. Chips are characterized by high performance, long lifespan, and high reliability. Thanks to these advantages, chips have become an indispensable part of modern electronic devices. Currently, chips can be broadly classified into analog chips, digital chips, and mixed-signal chips. Although chip design and manufacturing processes are now quite mature, it is still not guaranteed that a completed chip can be directly put into mass production. Chips still need to undergo a series of tests before being officially released to the market.

[0003] Automated Test Equipment (ATE) plays a crucial role in chip testing. After chip packaging, various electrical parameters need to be measured on ATE equipment, with current being a key test. In some testing scenarios, we need to measure large currents such as short-circuit current, overload current, or surge current.

[0004] However, existing automated testers, such as the STS8200, have a maximum current range of 10A for the FPVI channel. Measuring currents exceeding 10A often requires conversions in the test program. The measurement process itself contains errors, and these errors are further amplified by the conversions and amplification processes in the test program. Therefore, the 10A current range of existing testers is insufficient for the current measurement requirements of the aforementioned application scenarios. Summary of the Invention

[0005] The embodiments described herein provide a variable gain high-current test circuit and electronic device for automated chip testing, addressing the problems existing in the prior art.

[0006] According to a first aspect of this disclosure, a variable gain high current test circuit for automatic chip testing is provided, comprising: a sensor module, a reference voltage calibration module, a first differential module, and an output voltage determination module;

[0007] The sensor module is configured to generate a sampling voltage based on the sampling current.

[0008] The reference voltage calibration module is configured to generate a target reference voltage based on an initial reference voltage, wherein the initial reference voltage is related to the rated current of the chip, and the target reference voltage is related to the current range of the sensor module.

[0009] The first differential module is configured to determine the conduction state based on the chip's rated current, and to determine the conduction gain based on the target reference voltage and the sampling voltage;

[0010] The output voltage determination module is configured to determine the target output voltage based on the sensitivity of the sensor module, the sampling current of the sensor module, and the conduction gain of the first differential module.

[0011] In some embodiments of this disclosure, a second differential module is also included;

[0012] The second differential module is configured to generate a first initial output voltage and a second initial output voltage based on the target reference voltage and the sampled voltage, wherein the absolute values ​​of the first initial voltage and the second initial voltage are the same;

[0013] The first differential module is also configured to determine the turn-on gain based on the first initial output voltage and the second initial output voltage.

[0014] In some embodiments of this disclosure, the sensor module includes a current sensor connected in series with a chip. The current sensor collects the sampling current flowing through the chip and generates a sampling voltage based on the sampling current.

[0015] In some embodiments of this disclosure, the reference voltage calibration module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier, a diode, and a potentiometer. The first end of the first resistor and the first end of the diode are electrically connected to an initial reference voltage node. The second end of the first resistor is electrically connected to the first end of the third resistor and the positive input terminal of the first operational amplifier. The second end of the third resistor and the second end of the diode are electrically connected to a ground node. The first end of the potentiometer is electrically connected to the first end of the second resistor. The second end of the potentiometer is electrically connected to the inverting input terminal of the first operational amplifier. The third end of the potentiometer is electrically connected to the first end of the fourth resistor. The second end of the fourth resistor is electrically connected to a ground node. The second end of the second resistor is electrically connected to the output terminal of the first operational amplifier.

[0016] In some embodiments of this disclosure, the first differential module includes a first switching unit, a second switching unit, and a differential unit;

[0017] The first switching unit is configured to turn off when the rated current of the chip is less than or equal to the first range, turn off when the rated current of the chip is greater than the first range and less than or equal to the second range, and turn on when the rated current of the chip is greater than the second range and less than or equal to the third range.

[0018] The second switching unit is configured to turn off when the rated current of the chip is less than or equal to the first range, turn on when the rated current of the chip is greater than the first range and less than or equal to the second range, and turn off when the rated current of the chip is greater than the second range and less than or equal to the third range.

[0019] The differential unit is configured to generate a target output voltage based on the conduction states of the first switching unit and the second switching unit.

[0020] In some embodiments of this disclosure, the first switching unit includes a first switch and a second switch, the second switching unit includes a third switch and a fourth switch, the differential unit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a second operational amplifier, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a seventh capacitor. The first terminal of the fifth resistor receives a sampling voltage, and the second terminal of the fifth resistor is electrically connected to the first terminal of the sixth resistor. The second terminal of the sixth resistor, the first terminal of the first switch, the first terminal of the third switch, the first terminal of the ninth resistor, and the first terminal of the third capacitor are respectively electrically connected to the inverting input terminal of the second operational amplifier. The second terminal of the first switch is electrically connected to the first terminal of the seventh resistor and the first terminal of the first capacitor, respectively. The second terminal of the third switch is electrically connected to the first terminal of the eighth resistor and the first terminal of the second capacitor, respectively. The second terminal of the seventh resistor, the second terminal of the first capacitor, the second terminal of the eighth resistor, the second terminal of the second capacitor, and the second terminal of the ninth resistor are respectively electrically connected to the inverting input terminal of the second operational amplifier. The first terminal of the third capacitor and the first terminal of the fifteenth resistor are electrically connected to the positive output terminal of the second operational amplifier. The second terminal of the fifteenth resistor and the first terminal of the seventh capacitor are electrically connected to the first output node. The first terminal of the tenth resistor receives the target reference voltage. The second terminal of the tenth resistor is electrically connected to the first terminal of the eleventh resistor. The second terminal of the eleventh resistor, the first terminal of the fourth capacitor, the first terminal of the twelfth resistor, the first terminal of the fourth switch, and the first terminal of the second switch are electrically connected to the positive input terminal of the second operational amplifier. The second terminal of the fourth switch is electrically connected to the first terminal of the fifth capacitor and the first terminal of the thirteenth resistor. The second terminal of the second switch is electrically connected to the first terminal of the sixth capacitor and the first terminal of the fourteenth resistor. The second terminals of the fourth capacitor, the twelfth resistor, the fifth capacitor, the thirteenth resistor, the sixth capacitor, the fourteenth resistor, and the sixteenth resistor are electrically connected to the inverting output terminal of the second operational amplifier. The second terminal of the sixteenth resistor and the second terminal of the seventh capacitor are electrically connected to the second output node.

[0021] In some embodiments of this disclosure, the gain of the second differential module is zero, and the cutoff frequency of the second differential module is less than the switching frequency of the sensor module.

[0022] In some embodiments of this disclosure, the second differential module includes a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and a third operational amplifier. The first terminal of the sixteenth resistor receives a target reference voltage. The second terminals of the sixteenth resistor, the seventeenth resistor, and the eighth capacitor are electrically connected to the inverting input terminal of the third operational amplifier. The second terminals of the seventeenth resistor, the eighth capacitor, and the eighteenth resistor are electrically connected to the non-inverting output terminal of the third operational amplifier. The second terminal of the eighteenth resistor and the tenth capacitor are electrically connected to a third output node. The first terminal of the nineteenth resistor receives a sampling voltage. The second terminals of the nineteenth resistor, the ninth capacitor, and the twentieth resistor are electrically connected to the non-inverting input terminal of the third operational amplifier. The second terminals of the ninth capacitor, the twentieth resistor, and the twentieth resistor are electrically connected to the inverting output terminal of the third operational amplifier. The second terminals of the twentieth resistor and the tenth capacitor are electrically connected to a fourth output node.

[0023] In some embodiments of this disclosure, the target output voltage satisfies:

[0024] V out =I sensor SG(1)

[0025] Where Isensor is the sampling current of the sensor module, S is the sensitivity of the sensor module, and G is the conduction gain of the first differential module.

[0026] According to a second aspect of this disclosure, an electronic device is provided, including the variable gain high current test circuit as described in any of the first aspects.

[0027] This disclosure provides a variable gain high-current test circuit and electronic device for automatic chip testing, comprising a sensor module, a reference voltage calibration module, a first differential module, and an output voltage determination module. The sensor module generates a sampling voltage based on the sampling current; the reference voltage calibration module generates a target reference voltage based on an initial reference voltage; the first differential module determines the conduction state based on the chip's rated current and determines the conduction gain based on the target reference voltage and the sampling voltage. By configuring the parameters of the reference voltage calibration module, the value of the target reference voltage generated by the reference voltage calibration module can be changed, thereby changing the current range of the sensor module. This allows the sensor module to be used for direct measurement of high currents such as overload current and short-circuit current. Furthermore, by using the current sampled by the sensor module and the conduction gain determined by the first differential module, the target output voltage corresponding to the sampling current is determined, enabling the testing of currents with different gains on the chip. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0029] Figure 1 This is a schematic diagram of a variable gain high current test circuit provided in an embodiment of this disclosure;

[0030] Figure 2 This is a schematic diagram of the structure of a sensor module provided in an embodiment of this disclosure;

[0031] Figure 3 This is a schematic diagram of the circuit structure of a reference voltage calibration module provided in an embodiment of this disclosure;

[0032] Figure 4 This is a schematic diagram of the circuit structure of a first differential module provided in an embodiment of this disclosure;

[0033] Figure 5 This is a schematic diagram of another variable gain high current test circuit provided in this embodiment of the present disclosure;

[0034] Figure 6 This is a schematic diagram of the circuit structure of a second differential module provided in an embodiment of this disclosure. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0037] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0038] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0039] In view of the problems existing in the prior art, the present disclosure provides a variable gain high current test circuit for automatic chip testing. Figure 1 This is a schematic diagram of a variable gain high-current test circuit for automatic chip testing provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the variable gain high-current test circuit for automatic chip testing includes: a sensor module 10, a reference voltage calibration module 20, a first differential module 30, and an output voltage determination module 40; wherein, the sensor module 10 is configured to generate a sampling voltage based on the sampling current; the reference voltage calibration module 20 is configured to generate a target reference voltage based on an initial reference voltage, wherein the initial reference voltage is related to the rated current of the chip, and the target reference voltage is related to the current range of the sensor module; the first differential module 30 is configured to determine the conduction state based on the rated current of the chip, and determine the conduction gain based on the target reference voltage and the sampling voltage; the output voltage determination module 40 is configured to determine the target output voltage based on the sensitivity of the sensor module, the sampling current of the sensor module, and the conduction gain of the first differential module.

[0040] It should be noted that the rated current of a chip refers to the maximum current that the chip can withstand when operating at its rated voltage and rated power.

[0041] In a specific implementation, the sensor module is connected in series with the chip. The sensor module collects the operating current flowing through the chip, which is also called the sampling current. Based on the collected sampling current, the sensor module couples and generates a sampling voltage corresponding to the sampling current.

[0042] Because the operating current of the chip acquired by the sensor module is uncertain, the value of the reference voltage generated by the sensor module is also uncertain, resulting in an uncertain current range for the sensor module. However, by setting up a reference voltage calibration module, the initial reference voltage is calibrated to a target reference voltage. The target reference voltage generated by the calibration module determines the current range of the sensor module. Furthermore, by configuring the reference voltage calibration module, the target reference voltage generated by the reference voltage calibration module can be changed, thereby changing the current range of the sensor module. This allows the sensor module to be used for the direct measurement of large currents such as overload current and short-circuit current.

[0043] In a specific implementation, the reference voltage calibration module generates a target reference voltage based on the initial reference voltage of the sensor module. That is, by calibrating the initial reference voltage, a calibrated target reference voltage is obtained. The target reference voltage is a defined value; therefore, the current range of the sensor module can be determined under this target reference voltage. By configuring the reference voltage calibration module, the target reference voltage generated by the module can be changed, thereby altering the current range of the sensor module. In one specific embodiment, when the target reference voltage generated by the calibration module is less than 1.29V, the current range of the sensor module is -7.8A to 80A, and the sensitivity is 41.6mV / A. In other words, by changing the value of the target reference voltage obtained by calibrating the initial reference voltage using the reference voltage calibration module, the current range of the sensor module can be changed.

[0044] In the above embodiments, the initial reference voltage can be determined based on the chip's rated current.

[0045] It should be noted that once the sensor module model is determined, the correspondence between the sensor module's reference voltage and current range can be determined.

[0046] In a specific implementation, the first differential module first determines the conduction state based on the chip's rated current, and then determines the conduction gain based on the target reference voltage and the sampling voltage. By configuring the first differential module, different conduction gain values ​​can be obtained under different conduction states.

[0047] Furthermore, the conduction state of the first differential module can be determined by the rated current of the chip, thereby changing the gain of the first differential module. Therefore, the variable gain high current test circuit provided in this embodiment can be used for the direct measurement of high currents such as overload current and short circuit current. Based on the gain of the first differential module, the sampling current collected by the sensor module is directly amplified by the corresponding gain, avoiding the additional errors caused by the conversion in the test program and expanding the application range of the automatic test machine.

[0048] Then, the output voltage determination module obtains the target output voltage based on the sensitivity of the sensor module, the sampling current of the sensor module, and the conduction gain of the first differential module.

[0049] Specifically, the target output voltage satisfies:

[0050] V out =I sensor SG(1)

[0051] In equation (1), Isensor is the sampling current of the sensor module, S is the sensitivity of the sensor module, and G is the conduction gain of the first differential module.

[0052] It should be noted that when the current sensor model selected for the sensor module is fixed, the sensitivity of the sensor module is a fixed value.

[0053] This disclosure provides a variable gain high-current test circuit for automatic chip testing, comprising a sensor module, a reference voltage calibration module, a first differential module, and an output voltage determination module. The sensor module generates a sampling voltage based on the sampling current; the reference voltage calibration module generates a target reference voltage based on an initial reference voltage; the first differential module determines the conduction state based on the chip's rated current and determines the conduction gain based on the target reference voltage and the sampling voltage. By configuring the parameters of the reference voltage calibration module, the value of the target reference voltage generated by the reference voltage calibration module can be changed, thereby changing the current range of the sensor module. This allows the sensor module to be used for direct measurement of high currents such as overload current and short-circuit current. Furthermore, by using the current sampled by the sensor module and the conduction gain determined by the first differential module, the target output voltage corresponding to the sampling current is determined, enabling the testing of currents with different gains on the chip.

[0054] In specific implementation methods, such as Figure 2 As shown, the sensor module 10 includes a current sensor connected in series with the chip. The current sensor collects the sampling current flowing through the chip and generates a sampling voltage based on the sampling current.

[0055] like Figure 2 As shown, the current sensor is connected in series to the chip circuit. The current flows in from the primary side Iin terminal of the current sensor and flows out from the primary side Iout terminal of the current sensor. The current sensor is a Hall current sensor. The primary side and the secondary side of the current sensor are isolated. The current flows through the inside of the current sensor from the primary side and does not contact the secondary side. The current flowing through it will generate a magnetic field. The Hall voltage is calculated based on the magnetic induction intensity of the magnetic field. After internal amplification and filtering, a sampling voltage Vo is finally output.

[0056] This disclosure provides a method for setting a current sensor, acquiring the operating current (i.e., sampling current) of a chip based on the current sensor, and generating a sampling voltage through coupling based on the sampling current of the chip.

[0057] In specific implementation methods, such as Figure 3 As shown, the reference voltage calibration module 20 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first operational amplifier U1, a diode D1, and a potentiometer P1. The first end of the first resistor R1 and the first end of the diode D1 are electrically connected to the initial reference voltage node, respectively. The second end of the first resistor R1 is electrically connected to the first end of the third resistor R3 and the positive input terminal of the first operational amplifier U1, respectively. The second end of the third resistor R3 and the second end of the diode D1 are electrically connected to the ground node. The first end of the potentiometer P1 is electrically connected to the first end of the second resistor R2. The second end of the potentiometer P1 is electrically connected to the inverting input terminal of the first operational amplifier U1. The third end of the potentiometer P1 is electrically connected to the first end of the fourth resistor R3. The second end of the fourth resistor R4 is electrically connected to the ground node. The second end of the second resistor R2 is electrically connected to the output terminal of the first operational amplifier U1.

[0058] like Figure 3 As shown, the reference voltage calibration module 20 consists of a first operational amplifier U1, a potentiometer P1, a diode D1, and several resistors (including a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4). By changing the resistance value of the potentiometer P1, a target reference voltage can be generated based on the initial reference voltage.

[0059] Specifically, in combination Figure 3 When diode D1 is turned on, it has a forward conduction voltage of approximately 0.7V. Therefore, the target reference voltage Vrefo output by the reference voltage calibration module can be calculated to satisfy:

[0060]

[0061] Where Vrefo represents the target reference voltage generated by the reference voltage calibration module, Vf represents the forward conduction voltage of diode D1, R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, R3 is the resistance value of the third resistor, P1 is the resistance value of the potentiometer, and x represents the position of the potentiometer.

[0062] From formula (2), it can be concluded that when the position of the potentiometer is set and the resistance values ​​of the first resistor R1, the second resistor R2 and the third resistor R3 are determined, the generated target reference voltage is a fixed value. Based on the voltage value of the generated target reference voltage, the current range corresponding to the voltage value of the generated target reference voltage can be obtained from the manual of the current sensor.

[0063] In a specific example, when the first resistor R1 and the third resistor R3 are selected to have a resistance of 330kΩ, 1%, and 125mW, the second resistor R2 and the fourth resistor R4 are selected to have a resistance of 10kΩ, 0.1%, and 125mW, and the potentiometer P1 is selected to have a resistance of 1kΩ, 10%, and the potentiometer position is 50%, substituting the above values ​​into equation (2), the target reference voltage Vrefo can be calculated to be 0.7V.

[0064] For example, if the current sensor selected in this application is the CKSR-15 model, the current range corresponding to a target reference voltage of 0.7V can be obtained from the CKSR-15 model current sensor's manual. Specifically, the relationship between the target reference voltage and the current range for the CKSR-15 model current sensor is as follows: when the target reference voltage is less than 1.29V, its current range is -7.8A to 80A, its sensitivity is 41.6mV / A, and the current sensor's output voltage amplitude range is 0.375V to 4.03V. That is, when the target reference voltage generated by the reference voltage calibration module is less than 1.29V, the sensor module's current range is -7.8A to 80A.

[0065] It should be noted that in the above embodiments, the first operational amplifier is a non-inverting operational amplifier.

[0066] In this embodiment, different target reference voltages can be generated by setting different potentiometer positions, thereby changing the upper and lower limits of the measurement current and the sensitivity of the sensor module, which is highly flexible and widely applicable.

[0067] In specific implementation methods, such as Figure 4 As shown, the first differential module 30 includes a first switching unit, a second switching unit, and a differential unit. The first switching unit is configured to turn off when the chip's rated current is less than or equal to a first range, turn off when the chip's rated current is greater than the first range and less than or equal to a second range, and turn on when the chip's rated current is greater than the second range and less than or equal to a third range. The second switching unit is configured to turn off when the chip's rated current is less than or equal to the first range, turn on when the chip's rated current is greater than the first range and less than or equal to the second range, and turn off when the chip's rated current is greater than the second range and less than or equal to the third range. The differential unit is configured to generate a target output voltage based on the on / off states of the first and second switching units.

[0068] In a specific implementation, the first switching unit includes a first switch S1 and a second switch S2; the second switching unit includes a third switch S3 and a fourth switch S4; the differential unit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16; a second operational amplifier U2; a first capacitor C1; a second capacitor C2; a third capacitor C3; a fourth capacitor C4; a fifth capacitor C5; a sixth capacitor C6; and a seventh capacitor C7. The fifth resistor R5... One end receives the sampling voltage Vo. The second end of the fifth resistor R5 is electrically connected to the first end of the sixth resistor R6. The second end of the sixth resistor R6, the first end of the first switch S1, the first end of the third switch S3, the first end of the ninth resistor R9, and the first end of the third capacitor C3 are respectively electrically connected to the inverting input of the second operational amplifier U2. The second end of the first switch S1 is electrically connected to the first end of the seventh resistor R7 and the first end of the first capacitor C1. The second end of the third switch S2 is electrically connected to the first end of the eighth resistor R8 and the first end of the second capacitor C2. The second end of the seventh resistor R7, the second end of the first capacitor C2, the second end of the eighth resistor R8, and the first end of the second capacitor C3 are respectively connected to the inverting input of the second operational amplifier U2. The second terminal of capacitor C2, the second terminal of resistor R9, the second terminal of capacitor C3, and the first terminal of resistor R15 are electrically connected to the positive output terminal of the second operational amplifier U2. The second terminal of resistor R15 and the first terminal of capacitor C7 are electrically connected to the first output node. The first terminal of resistor R10 receives the target reference voltage Vrefo. The second terminal of resistor R10 is electrically connected to the first terminal of resistor R11. The second terminal of resistor R11, the first terminal of capacitor C4, the first terminal of resistor R12, the first terminal of switch S4, and the first terminal of switch S2 are electrically connected to the positive input terminal of the second operational amplifier U2. The terminals are electrically connected as follows: the second terminal of the fourth switch S4 is electrically connected to the first terminal of the fifth capacitor C5 and the first terminal of the thirteenth resistor R13, respectively; the second terminal of the second switch S2 is electrically connected to the first terminal of the sixth capacitor C6 and the first terminal of the fourteenth resistor R14, respectively; the second terminals of the fourth capacitor C4, the twelfth resistor R12, the fifth capacitor C5, the thirteenth resistor R13, the sixth capacitor C6, the fourteenth resistor R14, and the sixteenth resistor R16 are electrically connected to the inverting output terminal of the second operational amplifier U2, respectively; and the second terminal of the sixteenth resistor R16 and the second terminal of the seventh capacitor C7 are electrically connected to the second output node.

[0069] Specifically, in combination Figure 4The first differential module consists of a second operational amplifier U2, several capacitors, resistors, and a first switch, a second switch, a third switch, and a fourth switch. By selecting the conduction mode of the switches, different feedback networks can be selected to achieve current measurement with different gains. Its gain G is calculated as shown in the following formula (3):

[0070]

[0071] When the first and second switches are turned on, the gain of the differential unit satisfies: When the third and fourth switches are turned on, the gain of the differential unit satisfies: When the first, second, third, and fourth switches are all off, the gain of the differential unit satisfies:

[0072] Since the rated current of the chip connected to the sensor module can be determined based on the chip's properties, when the sensor module and the chip are connected in series, the conduction mode of the first and second switching units can be determined based on the rated current of the chip connected in series, thereby enabling the selection of the differential unit gain.

[0073] As an example, when the first and second switches are closed and the third and fourth switches are closed, the gain of the differential unit is determined to satisfy the following condition based on the voltage signal output from the output terminal and the voltage signal input to the input terminal:

[0074]

[0075] When the third and fourth switches are closed, and the first and second switches are closed, the gain of the differential unit is determined to satisfy the following conditions based on the voltage signal output from the output terminal and the voltage signal input to the input terminal:

[0076]

[0077] When the third switch, fourth switch, first switch, and second switch are all off, the gain of the differential unit is determined to satisfy the following condition based on the voltage signal output from the output terminal and the voltage signal input to the input terminal:

[0078]

[0079] That is, by configuring the resistance values ​​of the fifth, sixth, seventh, eighth, and ninth resistors, the gain of the differential unit can be changed.

[0080] In a specific example, the seventh resistor R7 is selected as a 6.2kΩ resistor, the eighth resistor R8 as a 31.6kΩ resistor, the ninth resistor R9 as a 95.3kΩ resistor, and the fifth resistor R5 and the sixth resistor R6 are each selected as 2kΩ resistors. At this time, closing the first switch S1 and the second switch S2 can set the gain of the differential unit to the minimum of 1.46V / V, with a corresponding current range of 80A; closing the third switch S3 and the fourth switch S4 can set the gain of the differential unit to the middle of 5.93V / V, with a corresponding current range of 20A; opening the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 can set the gain of the differential unit to the maximum of 24V / V, with a corresponding current range of 5A.

[0081] Based on the above embodiments, Figure 5 This is a schematic diagram of another variable gain high-current test circuit for automated chip testing provided in this disclosure embodiment, as shown below. Figure 5 As shown, the variable gain high current test circuit for automatic chip testing further includes: a second differential module 50; the second differential module 50 is configured to generate a first initial output voltage and a second initial output voltage based on the target reference voltage and the sampling voltage, wherein the absolute values ​​of the first initial voltage and the second initial voltage are the same; the first differential module is further configured to determine the conduction gain based on the first initial output voltage and the second initial output voltage.

[0082] The second differential module includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, and a third operational amplifier U3. The first terminal of the sixteenth resistor R16 receives the target reference voltage Vrefo. The second terminal of the sixteenth resistor R16, the first terminal of the seventeenth resistor R17, and the first terminal of the eighth capacitor C8 are electrically connected to the inverting input terminal of the third operational amplifier U3. The second terminal of the seventeenth resistor R17, the second terminal of the eighth capacitor C8, and the first terminal of the eighteenth resistor R18 are electrically connected to the third operational amplifier U3. The positive output terminal of operational amplifier U3 is electrically connected. The second terminal of the eighteenth resistor R18 and the first terminal of the tenth capacitor C10 are electrically connected to the third output node. The first terminal of the nineteenth resistor R19 receives the sampling voltage Vo. The second terminal of the nineteenth resistor R19, the first terminal of the ninth capacitor C9, and the first terminal of the twentieth resistor R20 are electrically connected to the positive input terminal of the third operational amplifier. The second terminal of the ninth capacitor C9, the second terminal of the twentieth resistor R20, and the first terminal of the twentyth resistor R21 are electrically connected to the inverting output terminal of the third operational amplifier U3. The second terminal of the twenty-first resistor R21 and the second terminal of the tenth capacitor C10 are electrically connected to the fourth output node.

[0083] In this embodiment of the disclosure, the circuit further includes a second differential module, which consists of a third operational amplifier U3, several capacitors, and resistors. The inputs of the second differential module are the output voltage Vo of the sensor module and the target reference voltage Vrefo generated by the reference voltage calibration module. The first initial output voltage output by the second differential module satisfies:

[0084]

[0085] The second initial output voltage satisfies:

[0086]

[0087] The gain Gv of the second differential module satisfies:

[0088]

[0089] The cutoff frequency f-3dB of the second differential module satisfies:

[0090]

[0091] In an exemplary manner, in the above formulas (7), (8), (9), and (10), the sixteenth, seventeenth, and nineteenth resistors are selected with a resistance of 2kΩ, 0.1%, and 125mW; the eighteenth and twenty-first resistors have a resistance of 33.2Ω, 1%, and 125mW; the eighth and ninth capacitors are selected with a capacitance of 470pF, 50V, and X7R type; and the tenth capacitor is selected with a capacitance of 10nF, 50V, and X7R type. At this point, the gain Gv of the second differential module can be calculated to be 0, and the cutoff frequency f-3db of the second differential module can be calculated to be 237.9kHz. The second differential module can convert the single-ended sampling voltage output from the current sensor into a differential voltage output, and by setting the cutoff frequency of the second differential module to 237.9kHz, the interference of the current sensor's 900kHz switching frequency can be effectively eliminated. That is, the second differential module can completely eliminate the offset voltage of the sensor module's sampling voltage Vo. Furthermore, the second differential module does not change the current range or sensitivity.

[0092] When the variable gain high current test circuit also includes a second differential module, the voltage at the first terminal of the fifth resistor is the first initial output voltage, and the voltage at the first terminal of the tenth resistor is the second initial output voltage.

[0093] Furthermore, by selecting capacitors C1 (180pF), C2 (33pF), and C4 (15pF) in the first differential module, the cutoff frequency f-3dB of the first differential module can be calculated to be 142.61kHz when the first and second switches are on, 152.62kHz when the third and fourth switches are on, and 113.33kHz when the first, second, and third switches are off. The cutoff frequency of the first differential module is lower than that of the second differential module in all three conduction modes. This variable gain high-current test circuit can achieve a maximum current measurement of 80A, can be configured with three different gains, and can obtain a maximum sensitivity of 41.6mV / A, effectively enabling high-current testing scenarios in chips.

[0094] In this embodiment of the disclosure, the single-ended output of the sensor module is configured as a differential signal output through the second differential module, which reduces the bandwidth and adjusts the amplitude, thereby increasing the measurement anti-interference capability and accuracy.

[0095] Based on the above embodiments, this disclosure also provides an electronic device, including the variable gain high current test circuit described in any of the above embodiments, which has the beneficial effects described in any of the above embodiments. This disclosure will not provide specific examples of each of these features.

[0096] The electronic device provided in this disclosure can be applied to flexible electronic devices to realize technologies such as Augmented Reality (AR), Virtual Reality (VR), Extended Reality (XR), and Mixed Reality (MR). For example, the display device can be the projection part of the electronic device, such as a projector or a head-up display (HUD); or, for example, the display device can be the display part of the electronic device, such as a smartphone, smartwatch, laptop, tablet, dashcam, navigator, head-mounted device, or any device with a display screen.

[0097] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0098] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. Moreover, the above embodiment numbers are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0099] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0100] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A variable gain high-current test circuit for automated chip testing, characterized in that, include: The module consists of a sensor module, a reference voltage calibration module, a first differential module, and an output voltage determination module. The sensor module is configured to generate a sampling voltage based on the sampling current. The reference voltage calibration module is configured to generate a target reference voltage based on an initial reference voltage, wherein the initial reference voltage is related to the rated current of the chip, and the target reference voltage is related to the current range of the sensor module. The first differential module is configured to determine the conduction state based on the chip's rated current, and to determine the conduction gain based on the target reference voltage and the sampling voltage; The output voltage determination module is configured to determine the target output voltage based on the sensitivity of the sensor module, the sampling current of the sensor module, and the conduction gain of the first differential module. The reference voltage calibration module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier, a diode, and a potentiometer. The first end of the first resistor and the first end of the diode are electrically connected to the initial reference voltage node, respectively. The second end of the first resistor is electrically connected to the first end of the third resistor and the positive input terminal of the first operational amplifier, respectively. The second end of the third resistor and the second end of the diode are electrically connected to the ground node. The first end of the potentiometer is electrically connected to the first end of the second resistor and the second end of the potentiometer is electrically connected to the inverting input terminal of the first operational amplifier. The third end of the potentiometer is electrically connected to the first end of the fourth resistor and the second end of the fourth resistor is electrically connected to the ground node. The second end of the second resistor is electrically connected to the output terminal of the first operational amplifier.

2. The circuit according to claim 1, characterized in that, It also includes a second difference module; The second differential module is configured to generate a first initial output voltage and a second initial output voltage based on the target reference voltage and the sampled voltage, wherein the absolute values ​​of the first initial output voltage and the second initial output voltage are the same; The first differential module is also configured to determine the turn-on gain based on the first initial output voltage and the second initial output voltage.

3. The circuit according to claim 1, characterized in that, The sensor module includes a current sensor connected in series with the chip. The current sensor collects the sampling current flowing through the chip and generates a sampling voltage based on the sampling current.

4. The circuit according to claim 1, characterized in that, The first differential module includes a first switching unit, a second switching unit, and a differential unit; The first switching unit is configured to turn off when the rated current of the chip is less than or equal to the first range, turn off when the rated current of the chip is greater than the first range and less than or equal to the second range, and turn on when the rated current of the chip is greater than the second range and less than or equal to the third range. The second switching unit is configured to turn off when the rated current of the chip is less than or equal to the first range, turn on when the rated current of the chip is greater than the first range and less than or equal to the second range, and turn off when the rated current of the chip is greater than the second range and less than or equal to the third range. The differential unit is configured to generate a target output voltage based on the conduction states of the first switching unit and the second switching unit.

5. The circuit according to claim 4, characterized in that, The first switching unit includes a first switch and a second switch, the second switching unit includes a third switch and a fourth switch, the differential unit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a second operational amplifier, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a seventh capacitor. The first terminal of the fifth resistor receives a sampling voltage, the second terminal of the fifth resistor is electrically connected to the first terminal of the sixth resistor, the second terminal of the sixth resistor, the first terminal of the first switch, the first terminal of the third switch, the first terminal of the ninth resistor, and the first terminal of the third capacitor are respectively electrically connected to the inverting input terminal of the second operational amplifier, the second terminal of the first switch is electrically connected to the first terminal of the seventh resistor and the first terminal of the first capacitor, the second terminal of the third switch is electrically connected to the first terminal of the eighth resistor and the first terminal of the second capacitor, the second terminal of the seventh resistor, the second terminal of the first capacitor, the second terminal of the eighth resistor, the second terminal of the second capacitor, the second terminal of the ninth resistor, and the first... The second terminal of the three capacitors and the first terminal of the fifteenth resistor are electrically connected to the positive output terminal of the second operational amplifier. The second terminal of the fifteenth resistor and the first terminal of the seventh capacitor are electrically connected to the first output node. The first terminal of the tenth resistor receives the target reference voltage. The second terminal of the tenth resistor is electrically connected to the first terminal of the eleventh resistor. The second terminal of the eleventh resistor, the first terminal of the fourth capacitor, the first terminal of the twelfth resistor, the first terminal of the fourth switch, and the first terminal of the second switch are electrically connected to the positive input terminal of the second operational amplifier. The second terminal of the fourth switch is electrically connected to the first terminal of the fifth capacitor and the first terminal of the thirteenth resistor. The second terminal of the second switch is electrically connected to the first terminal of the sixth capacitor and the first terminal of the fourteenth resistor. The second terminal of the fourth capacitor, the second terminal of the twelfth resistor, the second terminal of the fifth capacitor, the second terminal of the thirteenth resistor, the second terminal of the sixth capacitor, the second terminal of the fourteenth resistor, and the first terminal of the sixteenth resistor are electrically connected to the inverting output terminal of the second operational amplifier. The second terminal of the sixteenth resistor and the second terminal of the seventh capacitor are electrically connected to the second output node.

6. The circuit according to claim 2, characterized in that, The gain of the second differential module is zero, and the cutoff frequency of the second differential module is less than the switching frequency of the sensor module.

7. The circuit according to claim 2, characterized in that, The second differential module includes a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and a third operational amplifier. The first terminal of the sixteenth resistor receives the target reference voltage. The second terminal of the sixteenth resistor, the first terminal of the seventeenth resistor, and the first terminal of the eighth capacitor are electrically connected to the inverting input terminal of the third operational amplifier. The second terminal of the seventeenth resistor, the second terminal of the eighth capacitor, and the first terminal of the eighteenth resistor are electrically connected to the non-inverting output terminal of the third operational amplifier. The second terminal of the eighteenth resistor and the first terminal of the tenth capacitor are electrically connected to the third output node. The first terminal of the nineteenth resistor receives the sampling voltage. The second terminal of the nineteenth resistor, the first terminal of the ninth capacitor, and the first terminal of the twentieth resistor are electrically connected to the non-inverting input terminal of the third operational amplifier. The second terminal of the ninth capacitor, the second terminal of the twentieth resistor, and the first terminal of the twentieth resistor are electrically connected to the inverting output terminal of the third operational amplifier. The second terminal of the twentieth resistor and the second terminal of the tenth capacitor are electrically connected to the fourth output node.

8. The circuit according to claim 1, characterized in that, The target output voltage satisfies: V out =I sensor SG Among them, I sensor Let S be the sampling current of the sensor module, S be the sensitivity of the sensor module, and G be the conduction gain of the first differential module.

9. An electronic device, characterized in that, Includes the variable gain high current test circuit as described in any one of claims 1-8.

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