Device gate oxide degradation monitoring circuit and chip

Abstract

The invention relates to the technical field of integrated circuits and chips, and provides a device gate oxide degradation monitoring circuit and a chip. A first branch and a second branch of the circuit are connected through a current mirror or a bipolar transistor. The first branch comprises an MOS capacitor bank, and the second branch comprises a phase inverter; the MOS capacitor bank comprises a plurality of high-voltage MOS tubes which are connected in parallel; the grid electrodes of the high-voltage MOS tubes are connected, and the source electrode and the drain electrode of each high-voltage MOS tube are in short circuit. The defect that an existing monitoring circuit is only suitable for monitoring a low-voltage SOC chip and cannot monitor a high-voltage circuit and the chip is overcome, gate oxide degradation monitoring of a high-voltage device and the circuit can be supported, the gate oxide degradation monitoring circuit can be embedded into a power supply and an isolation driving chip, and the defect that at present, only aging reliability prediction is carried out on the chip when the chip leaves a factory initially, and the reliability is poor is overcome. And early warning cannot be performed on real-time dynamic aging monitoring of the high-voltage power supply and the isolation chip along with working time.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits and chips, and in particular to a device gate oxide degradation monitoring circuit and chip. Background Art

[0002] Industrial chips used in the fields of power, rail transit, and automobiles are usually mounted outdoors with terminals, and are very susceptible to strong transient electromagnetic interference generated by the operation of power devices such as IGBTs, as well as environmental factors such as high temperature and high humidity. Industrial chips need to operate stably 24 hours a day, 7 days a week, in high / low temperature, high humidity, and strong electromagnetic environments, with a lifespan of more than 15 years, which poses a huge challenge to the reliability of chip pins that are susceptible to environmental interference.

[0003] The gate oxide layer of the device in the industrial chip will produce gate oxide degradation under the influence of environmental factors. The gate oxide degradation mechanism is: when there is an electric field in the gate dielectric, defects will be induced at the interface of the insulating layer and inside the insulating layer under the action of the electric field, and these defects may diffuse or capture charges. With the increase of defects and captured charges, these defects and charges may form carrier pathways, and carriers may cross the insulating layer barrier and pass through the insulating layer to the polysilicon gate, forming gate leakage current. When the leakage current reaches the critical value, the insulating layer will quickly break down. There are mainly two types of defects in the Si-SiO2 system: charge in the gate dielectric; current in the oxide layer. The breakdown of the gate oxide can be divided into two categories: instantaneous breakdown and time-dependent breakdown from the perspective of breakdown time. Among them, the time-dependent breakdown of gate oxide degradation is related to time. The applied electric field is lower than the intrinsic breakdown field strength of the gate oxide, and no intrinsic breakdown is caused, but breakdown still occurs after a certain period of time.

[0004] Existing monitoring circuits for device gate oxide degradation (gate oxide breakdown over time) are mainly used for low-voltage devices of 5V and are only for SOC chips. They cannot support the monitoring of high-voltage devices and circuit systems above 40V, and are not suitable for power chips and isolation driver chips containing high-voltage devices. Summary of the invention

[0005] In order to solve the above technical defects, the present invention provides a high voltage device gate oxide degradation monitoring circuit.

[0006] A high-voltage device gate oxide degradation monitoring circuit provided by an embodiment of the present invention includes a first branch and a second branch, wherein the first branch and the second branch are connected via a current mirror;

[0007] The first branch includes a MOS capacitor group, and the second branch includes an inverter;

[0008] The MOS capacitor group includes a plurality of high-voltage MOS tubes connected in parallel, and the source and drain of each high-voltage MOS tube are short-circuited to be equivalent to a capacitor;

[0009] The common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end short-circuited between the source and the drain of each high-voltage MOS tube serves as the second end of the MOS capacitor group;

[0010] The second end of the MOS capacitor group is grounded, and the first end of the MOS capacitor group is connected to a stress voltage, where the stress voltage is greater than the working voltage of the high-voltage MOS tube to accelerate gate oxide degradation of the high-voltage MOS tube;

[0011] The current mirror is used to copy the current mirror image of the first branch to the input end of the inverter of the second branch, and the level signal output by the inverter is used to determine the gate oxide degradation degree of the high-voltage MOS tube.

[0012] In an embodiment of the present invention, the current mirror comprises: a first resistor, a second resistor, a first MOS transistor and a second MOS transistor;

[0013] The gate of the first MOS tube is connected to the gate of the second MOS tube;

[0014] The source of the first MOS tube is connected to the stress voltage through the first resistor, and the drain of the first MOS tube is connected to the first end of the MOS capacitor group;

[0015] The source of the second MOS tube is connected to the stress voltage through the second resistor and is connected to the first resistor, and the drain of the second MOS tube is connected to the input end of the inverter.

[0016] In the embodiment of the present invention, a common end at which the gate of the first MOS transistor and the gate of the second MOS transistor are connected is connected to the first end of the MOS capacitor group.

[0017] In the embodiment of the present invention, the second branch further includes a third resistor, a first end of the third resistor is connected to the input end of the inverter and to the drain of the second MOS tube, and a second end of the third resistor is grounded.

[0018] In the embodiment of the present invention, the second branch further includes a Zener diode, a cathode of the Zener diode is connected to the input end of the inverter and to the drain of the second MOS tube, and an anode of the Zener diode is grounded.

[0019] In the embodiment of the present invention, gate oxide degradation occurs to the high-voltage MOS tube in the MOS capacitor group under the stress voltage. When the gate oxide of the high-voltage MOS tube is not broken down, there is no current in the first branch, there is no mirrored current in the second branch, the third resistor pulls down the input voltage of the inverter, and the inverter outputs a high level.

[0020] In the embodiment of the present invention, gate oxide degradation occurs to the high-voltage MOS tube in the MOS capacitor group under the action of stress voltage. When the gate oxide of the high-voltage MOS tube is broken down, a large current is generated in the first branch, and a mirrored large current is generated in the second branch. The mirrored large current generates a voltage through the third resistor, the input end of the inverter is a high level, and the inverter outputs a low level.

[0021] Another embodiment of the present invention provides a high-voltage device gate oxide degradation monitoring circuit, comprising a first branch and a second branch, wherein the first branch and the second branch are connected via a bipolar transistor;

[0022] The first branch includes a MOS capacitor group, and the second branch includes an inverter;

[0023] The MOS capacitor group includes a plurality of high-voltage MOS tubes connected in parallel, and the source and drain of each high-voltage MOS tube are short-circuited to be equivalent to a capacitor;

[0024] The common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end short-circuited between the source and the drain of each high-voltage MOS tube serves as the second end of the MOS capacitor group;

[0025] A first end of the MOS capacitor group is connected to the base of the bipolar transistor, and a second end of the MOS capacitor group is grounded;

[0026] The emitter of the bipolar transistor is connected to a stress voltage, which is greater than the operating voltage of the high-voltage MOS tube to accelerate the gate oxide degradation of the high-voltage MOS tube;

[0027] The collector of the bipolar transistor is connected to the input end of the inverter, and the level signal output by the inverter is used to determine the degree of gate oxide degradation of the high-voltage MOS tube.

[0028] In the embodiment of the present invention, the emitter of the bipolar transistor is connected to the stress voltage through a first resistor.

[0029] In the embodiment of the present invention, the second branch further includes a second resistor, a first end of the second resistor is connected to the collector of the bipolar transistor and the input end of the inverter, and a second end of the second resistor is grounded.

[0030] In the embodiment of the present invention, the second branch further includes a Zener diode, a cathode of the Zener diode is connected to the collector of the bipolar transistor and the input end of the inverter, and an anode of the Zener diode is grounded.

[0031] In the embodiment of the present invention, when the bipolar transistor is turned off, the gate oxide of the high-voltage MOS tube in the MOS capacitor group degrades under the action of the stress voltage. When the gate oxide of the high-voltage MOS tube is broken down, the base of the bipolar transistor is pulled down to ground, so that the bipolar transistor is turned on, and the voltage at the first end of the second resistor is raised, so that the input end of the inverter is high level and the inverter outputs a low level.

[0032] In the embodiment of the present invention, the high-voltage MOS tube in the MOS capacitor group is one of LDMOS, VDMOS, and DEMOS, and the source-drain voltage of the high-voltage MOS tube is 12V to 750V.

[0033] The present invention also provides a power chip, which includes the above-mentioned high-voltage device gate oxide degradation monitoring circuit.

[0034] The present invention also provides an isolation driving chip, which includes the above-mentioned high-voltage device gate oxide degradation monitoring circuit.

[0035] The high-voltage device gate oxide degradation monitoring circuit of the present invention can support gate oxide degradation monitoring of high-voltage devices and circuits, can perform real-time dynamic internal monitoring of picoampere-level current, has adjustable stress voltage, and controllable degradation time, and can realize dynamic monitoring of reliability failures of power supply and isolation drive circuits over time; moreover, it can be embedded in power supply and isolation drive chips to form power supply and isolation drive chips with high-voltage MOS device failure monitoring functions.

[0036] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0038] Figure 1 Schematic diagram of a high voltage device gate oxide degradation monitoring circuit provided in Embodiment 1 of the present invention;

[0039] Figure 2 Schematic diagram of a high voltage device gate oxide degradation monitoring circuit provided by Embodiment 2 of the present invention

[0040] Figure 3 A cross-sectional view of a capacitor structure formed by a LDMOS with source and drain shorted;

[0041] Figure 4 A cross-sectional view of a capacitor structure formed by a DEMOS with source and drain shorted;

[0042] Figure 5is a block diagram of a power chip provided by an embodiment of the present invention;

[0043] Figure 6 4 is a block diagram of an isolation driver chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0045] In the description of the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0046] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected" and "connection" should be understood in a broad sense, for example, it can be an electrical connection or mutual communication, it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0047] The present invention designs a corresponding monitoring circuit for gate oxide degradation of high-voltage devices, and the gate oxide of the gate oxide breakdown monitoring circuit and the host circuit (circuit under test) adopt the same gate oxide thickness and work under the same temperature environment, but the gate oxide area and voltage stress are different. Assume that the area of ​​the gate oxide breakdown monitoring circuit is N*A (A represents the area of ​​a single MOS device), and the voltage stress is Vstress; the area of ​​the host circuit is B, and the voltage stress of the host circuit is VDD. A voltage stress greater than its working condition is applied to the gate dielectric of the monitoring circuit, so that the gate dielectric of the monitoring circuit fails earlier than the circuit under test. When the life of the circuit under test (chip) leaves the wear-out failure zone and there is a pre-set "prediction advance amount", the monitoring circuit subjected to a larger voltage stress enters the wear-out failure zone in advance, thereby achieving the purpose of early warning of gate oxide degradation failure.

[0048] Embodiment 1

[0049] The gate oxide degradation monitoring circuit of a high-voltage device provided in this embodiment includes a first branch and a second branch, wherein the first branch and the second branch are connected via a current mirror; the first branch includes a MOS capacitor group, and the second branch includes an inverter; the MOS capacitor group includes a plurality of high-voltage MOS tubes connected in parallel, wherein the source and the drain of each high-voltage MOS tube are short-circuited and are equivalent to a capacitor; the common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end short-circuited between the source and the drain of each high-voltage MOS tube serves as the second end of the MOS capacitor group; the second end of the MOS capacitor group is grounded, and the first end of the MOS capacitor group is connected to a stress voltage, wherein the stress voltage is greater than the working voltage of the high-voltage MOS tube, so as to accelerate the gate oxide degradation of the high-voltage MOS tube; the current mirror copies the current image of the first branch to the input end of the inverter of the second branch, and the level signal output by the inverter is used to determine the gate oxide degradation degree of the high-voltage MOS tube. The present invention can support gate oxide degradation monitoring of high-voltage devices and circuits of 12V to 750V, and can perform real-time dynamic internal monitoring of PA (picoampere) level current. The stress voltage is adjustable and the degradation time is controllable, thereby realizing dynamic monitoring of reliability failures of power supply and isolation drive circuits over time.

[0050] like Figure 1 As shown, the gate oxide degradation monitoring circuit of the high-voltage device provided in this embodiment includes a first branch (left branch) and a second branch (right branch). The first branch includes a MOS capacitor group, and the MOS capacitor group includes two high-voltage MOS tubes connected in parallel. The source and drain of each high-voltage MOS tube are short-circuited, which is equivalent to a capacitor; the common end connected to the gate of each high-voltage MOS tube is used as the first end of the MOS capacitor group, and the common end of the source and drain of each high-voltage MOS tube is short-circuited as the second end of the MOS capacitor group; the second end of the MOS capacitor group is grounded, and the first end of the MOS capacitor group is connected to a stress voltage, which is greater than the working voltage of the high-voltage MOS tube to accelerate the gate oxide degradation of the high-voltage MOS tube in the MOS capacitor group. The second branch includes an inverter, and the first branch and the second branch are connected through a current mirror. The current mirror copies the current image of the first branch to the input end of the inverter of the second branch, and the gate oxide degradation degree of the high-voltage MOS tube is determined according to the level signal output by the inverter, so as to achieve the purpose of early warning.

[0051] In this embodiment, the current mirror includes a first resistor R1, a second resistor R2, a first MOS transistor PM1 and a second MOS transistor PM2, wherein the first MOS transistor PM1 and the second MOS transistor PM2 are PMOS. The gate of the first MOS transistor PM1 is connected to the gate of the second MOS transistor PM2; the source of the first MOS transistor PM1 is connected to the stress voltage through the first resistor R1, and the drain of the first MOS transistor PM1 is connected to the first end of the MOS capacitor group. The common end at which the gate of the first MOS transistor PM1 and the gate of the second MOS transistor PM2 are connected is connected to the first end of the MOS capacitor group. The source of the second MOS transistor PM2 is connected to the stress voltage through the second resistor R2 and is connected to the first resistor R1, and the drain of the second MOS transistor PM2 is connected to the input end of the inverter.

[0052] In this embodiment, the second branch further includes a third resistor R3 and a Zener diode D1, wherein a first end of the third resistor R3 is connected to the input end of the inverter and to the drain of the second MOS transistor PM2, and a second end of the third resistor R3 is grounded GND. A cathode of the Zener diode D1 is connected to the input end of the inverter and to the drain of the second MOS transistor PM2, and a positive electrode of the Zener diode D1 is grounded GND.

[0053] In the high-voltage device gate oxide degradation monitoring circuit provided by the present embodiment, gate oxide degradation occurs to the high-voltage MOS tube in the MOS capacitor group under the action of stress voltage. When the gate oxide of the high-voltage MOS tube is not broken down, there is no current in the first branch, and there is no mirrored current in the second branch. The third resistor R3 pulls down the voltage at the input end of the inverter, and the inverter outputs a high level. Gate oxide degradation occurs to the high-voltage MOS tube in the MOS capacitor group under the action of stress voltage. When the gate oxide of the high-voltage MOS tube is broken down, a large current is generated in the first branch, and a large mirrored current is generated in the second branch. The large mirrored current generates a voltage through the third resistor R3, and the input end of the inverter is a high level, and the inverter outputs a low level.

[0054] Specifically, when the high-voltage MOS tube as a MOS capacitor has not degraded, the capacitor group can be equivalent to an open circuit. At this time, there is no current in the branch where the first resistor R1 on the left side of the current mirror is located, so there is no current in the branch where the second resistor R2 on the right side is located. At this time, the third resistor R3 pulls down the input voltage of the inverter, and the output inverter outputs a high level. When the high-voltage MOS tube as a MOS capacitor degrades and breaks down, it can be equivalent to a short circuit. At this time, a current appears in the branch where the first resistor R1 on the left side of the current mirror is located, and the current size is determined by the size of R1 and the PMOS tube below R1. The current size of the left branch is limited by the first resistor R1 and will not exceed the safe working range of the circuit. At the same time, due to the characteristics of the proportional current mirror, a current also appears in the branch where the second resistor R2 on the right side of the current mirror is located. The current generates a voltage through the third resistor R3, and the Zener diode D1 limits the voltage within the safe working range to protect the inverter from being damaged by high voltage. At this time, the inverter input is high level and the output is low level. The degree of degradation of the MOS capacitor is judged according to the level of the inverter output.

[0055] Embodiment 2

[0056] like Figure 2 As shown, the high-voltage device gate oxide degradation monitoring circuit provided in this embodiment includes a first branch and a second branch, and the first branch and the second branch are connected through a bipolar junction transistor (BJT). The first branch includes a MOS capacitor group, and the second branch includes an inverter. The MOS capacitor group includes a plurality of high-voltage MOS tubes ( Figure 2 Only the MOS capacitor group structure composed of high-voltage MOS1 and high-voltage MOS2 is shown, and the short-circuiting of the source and drain of each high-voltage MOS tube is equivalent to a capacitor. The common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end of the short-circuiting of the source and drain of each high-voltage MOS tube serves as the second end of the MOS capacitor group. The first end of the MOS capacitor group is connected to the base of the bipolar transistor, and the second end of the MOS capacitor group is grounded GND. The bipolar transistor Q1 is a high-voltage bipolar transistor. The emitter of the bipolar transistor Q1 is connected to a stress voltage, which is greater than the working voltage of the high-voltage MOS tube to accelerate the gate oxide degradation of the high-voltage MOS tube; the collector of the bipolar transistor is connected to the input end of the inverter, and the level signal output by the inverter is used to determine the degree of gate oxide degradation of the high-voltage MOS tube.

[0057] In this embodiment, the emitter of the bipolar transistor Q1 is connected to the stress voltage through the first resistor R1. The second branch also includes a second resistor R2 and a Zener diode D1, the first end of the second resistor R2 is connected to the collector of the bipolar transistor Q1 and the input end of the inverter, and the second end of the second resistor R2 is grounded GND. The cathode of the Zener diode D1 is connected to the collector of the bipolar transistor Q1 and the input end of the inverter, and the anode of the Zener diode D1 is grounded GND.

[0058] In this embodiment, under normal circumstances, the gate capacitor of the monitoring circuit is in an open circuit state, the bipolar transistor Q1 is in a turned-off state, and the gate capacitor can be divided into all stress voltages for aging, that is, the high-voltage MOS tube in the MOS capacitor group undergoes gate oxide degradation under the stress voltage, and when the gate oxide is not broken down, the first end of the second resistor R2 is at a low level, and the inverter outputs a high level. When the gate oxide of the high-voltage MOS tube is broken down, the base of the bipolar transistor Q1 is pulled down to ground, so that the bipolar transistor Q1 is turned on, and the voltage of the first end of the second resistor R2 is raised, so that the input end of the inverter is at a high level, and the inverter outputs a low level.

[0059] In the above embodiment, the high-voltage MOS tube in the MOS capacitor group can be one of the high-voltage devices such as LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor), DEMOS (Drain-Extended MOS), etc. The withstand voltage of the high-voltage MOS tube in the embodiment of the present invention ranges from 12V to 750V.

[0060] In a specific embodiment, the high-voltage MOS tube in the gate oxide degradation monitoring circuit adopts LDMOS with a withstand voltage of 12V to 750V to monitor the gate oxide degradation of LDMOS in the circuit under test. The source and drain of LDMOS are short-circuited together to form a capacitor. The cross-sectional view of the capacitor structure formed by the LDMOS with the source and drain short-circuited is as follows: Figure 3 Since in actual power chips and isolation driver chips, LDMOS are designed with an even number of fingers, an even number of LDMOS is designed in the embodiment of the present invention.

[0061] In another specific embodiment, the high-voltage MOS tube in the above-mentioned gate oxide degradation monitoring circuit can also use a DEMOS (Drain-Extended MOS) with a withstand voltage of 40V to 750V to monitor the gate oxide degradation of the DEMOS in the circuit under test. The drain end of the DEMOS has an extended layer of a lightly doped region. The extended layer increases the withstand voltage of the drain end by maintaining charge balance, using appropriate vertical profiles, and increasing the length of the low-doped region. The lightly doped region forms a high resistance that can withstand higher voltages. Most of the high drain voltage will fall on this lightly doped region, so the lightly doped extended layer can increase the withstand voltage of the drain end. As a high-voltage resistant device, DEMOS is used in high-voltage power supplies and isolation driver chips. The source and drain of the DEMOS are short-circuited together to form a capacitor. The cross-sectional view of the capacitor structure formed by the DEMOS with source and drain short-circuited is shown in the figure below. Figure 4 shown.

[0062] It should be noted that in the embodiment of the present invention, the number of high-voltage MOS tubes in the MOS capacitor group can be an even number or an odd number. The more high-voltage MOS tubes there are in the MOS capacitor group, the more accurate the monitoring is. By adjusting the magnitude of the stress voltage applied to the MOS capacitor group, the degradation time of the MOS capacitor can be controlled, and dynamic internal monitoring of PA (picoampere) level current can be performed in real time.

[0063] The high-voltage device gate oxide degradation monitoring circuit of the present invention can support the gate oxide degradation monitoring of high-voltage devices and circuits, can perform real-time dynamic internal monitoring of picoampere-level current, the stress voltage is adjustable, the degradation time is controllable, and the dynamic monitoring of reliability failures of power supply and isolation drive circuits over time can be realized; moreover, it can be embedded in the power supply and isolation drive chip to form a power supply and isolation drive chip with high-voltage MOS device failure monitoring function. The present invention fills the gap that the current process monitoring module only monitors low-voltage processes and does not monitor high-voltage processes; it overcomes the current problem of only predicting the aging reliability of the chip at the initial factory, and failing to warn the high-voltage power supply and isolation chip of real-time dynamic aging monitoring over time as the working time increases.

[0064] The embodiment of the present invention further provides a power chip, which has the high-voltage device gate oxide degradation monitoring circuit of the above embodiment embedded therein. Figure 5 As shown, the high-voltage device gate oxide degradation monitoring circuit of the above embodiment is embedded in a power chip, integrating a power chip capable of monitoring degradation faults of 12V-750V high-voltage devices.

[0065] The embodiment of the present invention further provides an isolation driver chip, in which the high voltage device gate oxide degradation monitoring circuit of the above embodiment is embedded. Figure 6As shown, the high-voltage device gate oxide degradation monitoring circuit of the above embodiment is embedded in the isolation driver chip, integrating the isolation driver chip with the function of monitoring the degradation fault of the 12V-750V high-voltage device.

[0066] The manufacturing process of the power chip or the isolation driver chip can adopt the ultra-high voltage bipolar CMOS-DMOS (BCD) process technology. By using the ultra-high voltage BCD process of non-epitaxial technology, a MOS device with a withstand voltage of up to 750V can be realized, and the device has higher reliability. The high-voltage device gate oxide degradation monitoring and early warning circuit of the above embodiment is compatible with the ultra-high voltage BCD process.

[0067] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A device gate oxide degradation monitoring circuit, characterized in that: It includes a first branch and a second branch, wherein the first branch and the second branch are connected via a current mirror; The first branch includes a MOS capacitor group, and the second branch includes an inverter; The MOS capacitor group includes a plurality of high-voltage MOS tubes connected in parallel, and the source and drain of each high-voltage MOS tube are short-circuited to be equivalent to a capacitor; The common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end short-circuited between the source and the drain of each high-voltage MOS tube serves as the second end of the MOS capacitor group; The second end of the MOS capacitor group is grounded, and the first end of the MOS capacitor group is connected to a stress voltage, where the stress voltage is greater than the working voltage of the high-voltage MOS tube to accelerate gate oxide degradation of the high-voltage MOS tube; The current mirror is used to copy the current mirror image of the first branch to the input end of the inverter of the second branch, and the level signal output by the inverter is used to determine the gate oxide degradation degree of the high-voltage MOS tube.

2. The device gate oxide degradation monitoring circuit according to claim 1, characterized in that: The current mirror comprises: a first resistor, a second resistor, a first MOS tube and a second MOS tube; The gate of the first MOS tube is connected to the gate of the second MOS tube; The source of the first MOS tube is connected to the stress voltage through the first resistor, and the drain of the first MOS tube is connected to the first end of the MOS capacitor group; The source of the second MOS tube is connected to the stress voltage through the second resistor and is connected to the first resistor, and the drain of the second MOS tube is connected to the input end of the inverter.

3. The device gate oxide degradation monitoring circuit according to claim 2, characterized in that: The common end at which the gate of the first MOS tube is connected to the gate of the second MOS tube is connected to the first end of the MOS capacitor group.

4. The device gate oxide degradation monitoring circuit according to claim 2, characterized in that: The second branch further includes a third resistor, a first end of the third resistor is connected to the input end of the inverter and to the drain of the second MOS tube, and a second end of the third resistor is grounded.

5. The device gate oxide degradation monitoring circuit according to claim 4, characterized in that: The second branch further includes a Zener diode, a cathode of the Zener diode is connected to the input end of the inverter and to the drain of the second MOS tube, and an anode of the Zener diode is grounded.

6. The device gate oxide degradation monitoring circuit according to claim 4, characterized in that: The high-voltage MOS tube in the MOS capacitor group undergoes gate oxide degradation under the stress voltage. When the gate oxide of the high-voltage MOS tube is not broken down, there is no current in the first branch, there is no mirrored current in the second branch, the third resistor pulls down the input voltage of the inverter, and the inverter outputs a high level.

7. The device gate oxide degradation monitoring circuit according to claim 4, characterized in that: The gate oxide of the high-voltage MOS tube in the MOS capacitor group degrades under the stress voltage. When the gate oxide of the high-voltage MOS tube is broken down, the first branch generates current, the second branch has a mirrored current, the mirrored current generates a voltage through the third resistor, the input end of the inverter is high level, and the inverter outputs a low level.

8. A device gate oxide degradation monitoring circuit, characterized in that: It includes a first branch and a second branch, wherein the first branch and the second branch are connected via a bipolar transistor; The first branch includes a MOS capacitor group, and the second branch includes an inverter; The MOS capacitor group includes a plurality of high-voltage MOS tubes connected in parallel, and the source and drain of each high-voltage MOS tube are short-circuited to be equivalent to a capacitor; The common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end short-circuited between the source and the drain of each high-voltage MOS tube serves as the second end of the MOS capacitor group; A first end of the MOS capacitor group is connected to the base of the bipolar transistor, and a second end of the MOS capacitor group is grounded; The emitter of the bipolar transistor is connected to a stress voltage, which is greater than the operating voltage of the high-voltage MOS tube to accelerate the gate oxide degradation of the high-voltage MOS tube; The collector of the bipolar transistor is connected to the input end of the inverter, and the level signal output by the inverter is used to determine the degree of gate oxide degradation of the high-voltage MOS tube.

9. The device gate oxide degradation monitoring circuit according to claim 8, characterized in that: The emitter of the bipolar transistor is connected to the stress voltage through a first resistor.

10. The device gate oxide degradation monitoring circuit according to claim 8, characterized in that: The second branch further includes a second resistor, a first end of the second resistor is connected to the collector of the bipolar transistor and the input end of the inverter, and a second end of the second resistor is grounded.

11. The device gate oxide degradation monitoring circuit according to claim 10, characterized in that: The second branch further includes a Zener diode, a cathode of the Zener diode is connected to the collector of the bipolar transistor and the input end of the inverter, and an anode of the Zener diode is grounded.

12. The device gate oxide degradation monitoring circuit according to claim 10, characterized in that: When the bipolar transistor is turned off, the gate oxide of the high-voltage MOS tube in the MOS capacitor group degrades under the stress voltage. When the gate oxide of the high-voltage MOS tube is broken down, the base of the bipolar transistor is pulled down to ground, so that the bipolar transistor is turned on, and the voltage at the first end of the second resistor is raised, so that the input end of the inverter is high level and the inverter outputs low level.

13. The device gate oxide degradation monitoring circuit according to claim 1 or 8, characterized in that: The high-voltage MOS tube in the MOS capacitor group is one of LDMOS, VDMOS and DEMOS, and the source-drain voltage of the high-voltage MOS tube is 12V to 750V.

14. A power chip, characterized in that: The power chip comprises the device gate oxide degradation monitoring circuit according to any one of claims 1 to 13.

15. An isolation driver chip, characterized in that: The isolation driving chip comprises the device gate oxide degradation monitoring circuit according to any one of claims 1 to 13.

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