Multi-channel photon time-of-flight processing circuit

Abstract

The invention provides a multichannel photon flight time processing circuit, and relates to the technical field of laser radar three-dimensional imaging. The multichannel photon time-of-flight processing circuit comprises a time-to-digital conversion circuit which comprises a plurality of parallel time-to-digital conversion channels and is used for performing time quantization processing on a first signal at a current moment based on a target time-to-digital conversion channel in the plurality of parallel time-to-digital conversion channels and outputting a digital code value; the delay circuit is used for receiving a plurality of first signals according to a time sequence and outputting delay signals corresponding to the first signals; the first circuit is used for determining a channel code of the first signal at the current moment according to the delay signal corresponding to the first signal at the current moment, and the channel codes of two first signals at adjacent moments are different; and the second circuit is used for determining a target time-digital conversion channel from a plurality of parallel time-digital conversion channels according to the channel code of the first signal at the current moment.

Description

Technical Field

[0001] The present disclosure relates to the technical field of laser radar three-dimensional imaging, and more specifically, to a multi-channel photon time-of-flight processing circuit. Background Art

[0002] Direct Time of Flight (D-ToF) measurement technology is the current mainstream depth measurement technology and is widely used in the field of LiDAR 3D imaging. Its basic working principle is that a pulsed laser source emits a pulsed laser to the target object to be measured. The laser is reflected by the surface of the object and converges to the image sensor through the receiving end lens. The single-photon detector, such as a single-photon avalanche diode, responds to the incident photon signal and generates an electrical signal. Then the time-to-digital converter quantifies the time difference between the laser emission time and the detector response time to calculate the distance between the image sensor and the target to be measured.

[0003] Since the time-to-digital converter channel (TDC) has a quantification dead time when quantifying the photon flight time, new photon signals cannot be quantified during this period, resulting in signal loss. Based on this, in order to improve the accuracy of the measurement results, the number of laser emissions is usually increased. Although sufficient signal volume is guaranteed for statistical analysis, it will also increase the power consumption of the system, increase costs, and reduce the imaging frame rate. Summary of the invention

[0004] In view of this, the present disclosure provides a multi-channel photon flight time processing circuit, including: a time-to-digital conversion circuit, including multiple parallel time-to-digital conversion channels, for performing time quantization processing on a first signal at a current moment based on a target time-to-digital conversion channel among the multiple parallel time-to-digital conversion channels, and outputting a digital code value, wherein the digital code value includes the flight time of a reflected photon, and the reflected photon represents a photon formed after the emitted pulse signal is reflected by a target object; a delay circuit, for receiving multiple first signals in time sequence, and outputting a delay signal corresponding to each first signal, wherein each first signal includes at least one reflected photon; a first circuit, for determining the channel coding of the first signal at a current moment according to the delay signal corresponding to the first signal at a current moment, wherein the channel coding of two first signals at adjacent moments is different; a second circuit, for determining the target time-to-digital conversion channel from the multiple parallel time-to-digital conversion channels according to the channel coding of the first signal at a current moment.

[0005] According to an embodiment of the present disclosure, a first circuit includes: k cascaded D flip-flops, determining initial valid bits of the k cascaded D flip-flops; when a delay signal corresponding to a first first signal is input, the first D flip-flop outputs an inverted initial valid bit, and the remaining k-1 D flip-flops retain the initial valid bits; when a delay signal corresponding to a second first signal is input, the first D flip-flop outputs an initial valid bit, the second D flip-flop outputs an inverted initial valid bit, and the remaining k-2 D flip-flops retain the initial valid bits; until ... inverted initial valid bit, and the remaining k-2 D flip-flops retain the initial valid bits. k -1 first signal corresponding to the delay signal, the cascaded k-1 D flip-flops retain the reverse initial valid bit, the kth D flip-flop outputs the reverse initial valid bit; k When a delayed signal corresponding to a first signal is output, the cascaded k D flip-flops all output initial valid bits, wherein 1≦k.

[0006] According to an embodiment of the present disclosure, it also includes: each D flip-flop in the k cascaded D flip-flops outputs a reverse valid bit, wherein the reverse valid bit represents the reverse state of the valid bit output by each D flip-flop, and the valid bits output by each D flip-flop constitute a channel code; and the state of the valid bit of the i+1th D flip-flop is switched according to the reverse valid bit output by the i-th D flip-flop; 1≦i≦k.

[0007] According to an embodiment of the present disclosure, determining the channel coding of the first signal at the current moment according to the delayed signal corresponding to the first signal at the current moment includes: determining the channel coding of the first signal at the current moment based on the channel coding of the first signal at the previous moment.

[0008] According to an embodiment of the present disclosure, based on the channel coding of the first signal at the previous moment, determining the channel coding of the first signal at the current moment includes: determining an initial channel coding; based on the initial channel coding, counting the delayed signals corresponding to the first signal input in time sequence to determine the channel coding; when the count reaches 2 k When the second k The delayed signal corresponding to the first signal is k The channel coding of the first signal is the initial channel coding; k +1 The delayed signal corresponding to the first signal, the second k The channel code of the +1 first signal is the channel code of the first first signal.

[0009] According to an embodiment of the present disclosure, based on the initial channel coding, the delayed signal corresponding to the first signal input in time sequence is counted to determine the channel coding, and further includes: when the count is less than or equal to 2 kWhen the delayed signal corresponding to the first first signal input in time sequence is input, the channel code of the first first signal is determined according to the initial channel code; when the delayed signal corresponding to the second first signal is input, the channel code of the second first signal is determined according to the channel code of the first first signal; until the second first signal is input k When the delayed signal corresponding to the first signal is k -1 The channel coding of the first signal determines the second k Channel coding of a first signal.

[0010] According to an embodiment of the present disclosure, the i-th D flip-flop includes: a clock input terminal, which is set to be connected to the inverting output terminal of the i-1th D flip-flop when i is greater than 1, and is used to receive the inverted valid bit output from the i-1th D flip-flop; when i is 1, the clock input terminal of the first D flip-flop is set to be connected to the output terminal of the delay circuit, and is used to receive the delay signal corresponding to the first signal at the current moment; a non-inverting output terminal, which is set to be connected to the input terminal corresponding to the second circuit, and is used to output the valid bit of the i-th D flip-flop; a reset input terminal, which is used to reset the valid bit to the initial valid bit according to the input reset signal.

[0011] According to an embodiment of the present disclosure, the second circuit includes: a plurality of AND gates, the number of the plurality of AND gates is the same as the number of the plurality of parallel time-to-digital conversion channels, and the output ends of the plurality of AND gates are correspondingly connected to the input ends of the plurality of parallel time-to-digital conversion channels; a plurality of inverters, the number of the plurality of inverters is the same as the number of cascaded D flip-flops, and the input ends of the plurality of inverters are correspondingly connected to the output ends of the cascaded D flip-flops; wherein each AND gate includes: a signal input end, for inputting a first signal at a current moment; k first input ends, the i-th first input end is connected to a non-inverting output end of the i-th D flip-flop or to an output end of an inverter correspondingly connected to the i-th D flip-flop; when the i-th first input end is connected to the non-inverting output end of the i-th D flip-flop, the i-th first input end is used to input a valid bit output by the i-th D flip-flop; when the i-th first input end is connected to an output end of an inverter correspondingly connected to the i-th D flip-flop, the i-th first input end is used to input an inverted valid bit of the valid bit output by the i-th D flip-flop; and a first output end, for outputting the first signal received at the current moment.

[0012] According to an embodiment of the present disclosure, the first delay circuit includes: N inverters connected in series, where N is an even number.

[0013] According to an embodiment of the present disclosure, it also includes: a macro pixel circuit, which is used to respond and shape multiple photon signals input at the current moment, and output multiple square wave signals; a signal combination circuit, which is used to combine the multiple square wave signals and output a first signal.

[0014] The multi-channel photon flight time processing circuit provided by the embodiment of the present disclosure has at least the following beneficial effects:

[0015] In the embodiment of the present disclosure, by designing multiple quantization channels, each channel can independently perform time quantization processing on the first signal input at the current moment. Even if a channel is in the quantization dead time, other channels can still continue to process the new first signal, reducing the probability of signal loss, improving the accuracy of the measurement result without increasing the number of laser emissions, and significantly improving the imaging frame rate.

[0016] The first circuit determines the channel coding according to the delayed signal corresponding to the first signal at the current moment, and the channel coding of two first signals at adjacent moments is different, ensuring that each first signal can be assigned to a channel that is not in the quantization dead time, further improving the photon flux of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram showing a structure of a multi-channel photon flight time processing circuit according to an embodiment of the present disclosure;

[0019] Figure 2 The structure diagram of the first circuit according to the embodiment of the present disclosure is schematically shown;

[0020] Figure 3 The schematic diagram of the structure of the second circuit according to the embodiment of the present disclosure is shown;

[0021] Figure 4 The structure diagram of the delay circuit according to the embodiment of the present disclosure is schematically shown;

[0022] Figure 5 The schematic diagram of the structure of the macro pixel circuit according to the embodiment of the present disclosure is shown;

[0023] Figure 6 The structure diagram of the signal combination circuit according to the embodiment of the present disclosure is schematically shown;

[0024] Figure 7 The schematic diagram shows the structure of the time-to-digital conversion circuit according to an embodiment of the present disclosure;

[0025] Figure 8 The structure diagram of the histogram processing circuit according to the embodiment of the present disclosure is schematically shown;

[0026] Fig. 9 The structure diagram of the peak detection circuit according to the embodiment of the present disclosure is schematically shown;

[0027] Fig.10 A comparison diagram of simulation results of a measurement circuit histogram according to an embodiment of the present disclosure and a traditional measurement circuit histogram is schematically shown. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known systems and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0029] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0030] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0031] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0032] Since single-photon detectors are extremely sensitive to photons, in addition to laser photons reflected by the target object, photons from ambient light and false triggering signals caused by internal noise in the device may also trigger the detector to respond, causing interference. In order to effectively suppress the influence of ambient light, the time-correlated single photon counting (TCSPC) technology is usually used to perform multiple laser irradiations on the target object and perform histogram statistics on the results of each irradiation.

[0033] However, when TDC quantifies the flight time of photons, the quantization process of TDC takes a certain amount of time, during which no new photon signals can be processed. This period of time is called the quantization dead time of TDC. A longer dead time will result in more photon signal loss and reduce the photon flux of the system; while a shorter dead time can increase the photon flux and reduce signal loss.

[0034] Based on this, the present invention overcomes the signal loss problem caused by TDC quantization dead time by introducing multiple parallel time-to-digital conversion channels and a dynamic channel selection mechanism, thereby improving the accuracy of the measurement results and avoiding the high power consumption and cost increase caused by simply increasing the number of laser emissions, thereby achieving more efficient photon flight time measurement.

[0035] Figure 1 The structure diagram of the multi-channel photon flight time processing circuit of the embodiment of the present disclosure is schematically shown.

[0036] like Figure 1 As shown, the present disclosure provides a multi-channel photon flight time processing circuit, comprising:

[0037] The time-to-digital conversion circuit 6 includes a plurality of parallel time-to-digital conversion channels, and is used to perform time quantization processing on the first signal at the current moment based on a target time-to-digital conversion channel among the plurality of parallel time-to-digital conversion channels, and output a digital code value. The digital code value includes the flight time of the reflected photon, and the reflected photon represents a photon formed after the emitted pulse signal is reflected by the target object.

[0038] The delay circuit 3 is used to receive a plurality of first signals Photon_signal in time sequence and output a delay signal Photon_delay corresponding to each first signal, wherein each first signal includes at least one reflected photon.

[0039] The first circuit 4 is used to determine the channel coding of the first signal at the current moment according to the delay signal Photon_delay corresponding to the first signal at the current moment, wherein the channel codings of two first signals at adjacent moments are different.

[0040] The second circuit 5 is used to determine a target time-to-digital conversion channel from a plurality of parallel time-to-digital conversion channels according to the channel code of the first signal at a current moment.

[0041] In the embodiments of the present disclosure, by setting up multiple parallel time-to-digital conversion channels, each channel can independently perform time quantization processing on different first signals input in time sequence, effectively solving the signal loss problem caused by TDC quantization dead time, and can increase the photon flux under single illumination, thereby reducing the number of illumination times required to generate a histogram peak, reducing system power consumption, and improving the imaging frame rate.

[0042] A delay circuit is set to delay multiple first signals input in time sequence. After each first signal passes through the delay circuit, a time delay signal corresponding to the signal is output. The first circuit generates a channel code for the signal according to the delay signal of the current signal. Among them, the two first signals at adjacent moments are controlled to have different channel codes, thereby avoiding the first signals at adjacent moments from entering the same channel. Since TDC has the characteristic of quantization dead time, the first signal of the same channel input at the next moment will not be received, thereby losing the signal. The second circuit inputs the first signal at the current moment into the target TDC channel according to the generated channel code.

[0043] In some possible embodiments, the number of multiple parallel time-to-digital conversion channels can be set as needed, and the number of TDC channels can be 4, but is not limited thereto.

[0044] Figure 2 The structure diagram of the first circuit according to the embodiment of the present disclosure is schematically shown.

[0045] like Figure 2 As shown, according to an embodiment of the present disclosure, the first circuit 4 includes: k cascaded D flip-flops. Initial valid bits of the k cascaded D flip-flops are determined.

[0046] When the delay signal corresponding to the first first signal is input, the first D flip-flop outputs an inverted initial valid bit, and the remaining k-1 D flip-flops retain the initial valid bits.

[0047] When the delay signal corresponding to the second first signal is input, the first D flip-flop outputs the initial valid bit, the second D flip-flop outputs the inverted initial valid bit, and the remaining k-2 D flip-flops retain the initial valid bits.

[0048] Until the second k -1 delayed signal corresponding to the first signal, the cascaded k-1 D flip-flops retain the reverse initial valid bit, and the kth D flip-flop outputs the reverse initial valid bit;

[0049] When entering the 2nd k When a delayed signal corresponding to a first signal is output, the cascaded k D flip-flops all output initial valid bits, wherein 1≦k.

[0050] In the embodiment of the present disclosure, the number of cascaded D flip-flops is determined according to the number of TDC channels. k The Q terminal of the first D flip-flop outputs the least significant bit S of the binary channel code. <0> The Q end of the second D flip-flop outputs the second least significant bit S of the binary channel code <1> , and so on until the Q end of the last D flip-flop outputs the most significant bit S of the binary channel code <max>The binary channel code is generated by setting a cascaded D flip-flop, so that two first signals at adjacent moments have different channel codes, thereby avoiding signal loss.

[0051] For example, the first circuit includes two cascaded D flip-flops. When the delay signal corresponding to the first inputted first signal is not received, the two D flip-flops are both in the initial state. <0> and S <1> They are all reset to 0, which is the initial valid bit, and the channel code is 00.

[0052] As Photon_delay inputs the first signal, the Q end of the first D flip-flop will be pulled high, that is, S <0> becomes 1, which is the reverse initial valid bit, S <1> Keep 0, channel encoding is 01.

[0053] As Photon_delay inputs the second signal, the Q end of the first D flip-flop will be pulled low, that is, S <0> becomes 0, which is the initial valid bit, and at the same time the Q end of the second D flip-flop will be pulled high, that is, S <1> It becomes 1, which is the reverse initial valid bit, and the channel code is 10.

[0054] As Photon_delay inputs the third signal, the channel code becomes 11. As Photon_delay inputs the fourth signal, the Q terminals of the first and second D flip-flops are pulled low, that is, S <0> and S <1> All become 0, and the channel code switches back to 00.

[0055] Based on the above embodiment, it further includes: each of the k cascaded D flip-flops outputs an inverted valid bit, wherein the inverted valid bit represents the inverted state of the valid bit output by each D flip-flop, and the valid bit output by each D flip-flop constitutes a channel code.

[0056] The state of the valid bit of the i+1th D flip-flop is switched according to the inverted valid bit output by the i-th D flip-flop; 1≦i≦k.

[0057] In the embodiment of the present disclosure, the state of the next trigger is switched by the reverse valid bit of the previous trigger, which can ensure that the state of each D trigger is updated more accurately and timely, avoiding false triggering or missed triggering caused by CK signal synchronization problems. At the same time, each D trigger changes its state only when necessary, and the overall power consumption is effectively controlled, so that the system can maintain a low energy consumption level during long-term operation.

[0058] For example, when k is 2, the state of the valid bit of the second D flip-flop is switched according to the inverted valid bit output by the first D flip-flop. When the first signal is input, the valid bit output by the first D flip-flop is 1, that is, S <0> =1, the reverse valid bit is 0, which will serve as the CK signal of the second D flip-flop. At this time, the output valid bit of the second D flip-flop is 0, that is, S <1> = 0. At this time, the channel code becomes 01.

[0059] When the second signal is input, the valid bit of the output of the first D flip-flop is 0, that is, S <0> =0, the reverse valid bit is 1, which will serve as the CK signal of the second D flip-flop. At this time, the output valid bit of the second D flip-flop is 1, that is, S <1> = 1. At this time, the channel code becomes 10.

[0060] When the third signal is input, the valid bit of the output of the first D flip-flop is 1, that is, S <0> =1, the reverse valid bit is 0, which will serve as the CK signal of the second D flip-flop. At this time, the output valid bit of the second D flip-flop is 1, that is, S <1> =1. At this time, the channel code becomes 11.

[0061] When the fourth signal is input, the valid bit of the output of the first D flip-flop is 0, that is, S <0> =0, the reverse valid bit is 1, which will serve as the CK signal of the second D flip-flop. At this time, the output valid bit of the second D flip-flop is 0, that is, S <1> = 0. At this time, the channel code becomes 00.

[0062] According to an embodiment of the present disclosure, determining the channel coding of the first signal at the current moment according to the delayed signal corresponding to the first signal at the current moment includes: determining the channel coding of the first signal at the current moment based on the channel coding of the first signal at the previous moment.

[0063] In the embodiments of the present disclosure, it can be ensured that the channel coding of the first signals at adjacent moments is different and they can enter different target TDC channels respectively, thus avoiding signal loss.

[0064] On the basis of the above embodiment, determining the channel coding of the first signal at the current moment based on the channel coding of the first signal at the previous moment includes: determining the initial channel coding.

[0065] Based on the initial channel code, delayed signals corresponding to the first signal input in time sequence are counted to determine the channel code.

[0066] When the count reaches 2 k When the second k The delayed signal corresponding to the first signal is k The channel coding of the first signal is the initial channel coding.

[0067] When entering the 2nd k +1 The delayed signal corresponding to the first signal, the second k The channel code of the +1 first signal is the channel code of the first first signal.

[0068] In an embodiment of the present disclosure, for example, when k is 2, the initial channel coding is determined to be 00. Based on this initial channel coding, when the first signal is input, the channel coding is switched to 01. When the second signal is input, the channel coding is switched to 10. When the third signal is input, the channel coding is switched to 11. When the fourth signal is input, the channel coding is switched to 00. When the fifth signal is input, the channel coding is switched to 01, which corresponds to the channel coding of the first signal. At this time, the cycle period of the channel coding is 4. For each subsequent input signal, the channel coding corresponds to one of the channel codings in the cycle period. By counting the delayed signals, it is ensured that each first signal can be assigned to a TDC channel that is not in the quantization dead time. When the count reaches 2 k When the TDC channel is fully utilized, a complete cycle is completed, thereby achieving effective recycling of the TDC channel.

[0069] On the basis of the above embodiment, based on the initial channel coding, the delayed signals corresponding to the first signals input in time sequence are counted to determine the channel coding, further comprising:

[0070] When count is less than or equal to 2 k When the delay signal corresponding to the first first signal input in the time sequence is input, the channel code of the first first signal is determined according to the initial channel code;

[0071] When a delayed signal corresponding to the second first signal is input, the channel code of the second first signal is determined according to the channel code of the first first signal;

[0072] Until the second k When the delayed signal corresponding to the first signal is k -1 The channel coding of the first signal determines the second k Channel coding of a first signal.

[0073] In the embodiment of the present disclosure, the channel coding of the first signal at the current moment is determined by introducing the channel coding based on the first signal at the previous moment, and the delayed signal is counted until a cycle is completed.

[0074] like Figure 2 As shown, according to an embodiment of the present disclosure, the i-th D flip-flop includes:

[0075] The clock input terminal CK, when i is greater than 1, is set to be connected to the reverse output terminal QN of the i-1th D flip-flop, for receiving the reverse valid bit output from the i-1th D flip-flop; when i is 1, the clock input terminal of the first D flip-flop is set to be connected to the output terminal of the delay circuit, for receiving the delayed signal corresponding to the first signal at the current moment.

[0076] A non-inverting output terminal Q is arranged to be connected to an input terminal corresponding to the second circuit, and is used to output a valid bit of the i-th D flip-flop;

[0077] The reset input terminal RN is used to reset the valid bit to an initial valid bit according to an input reset signal.

[0078] According to an embodiment of the present disclosure, the i-th D flip-flop also includes a D terminal, which is connected to the QN terminal of the i-th D flip-flop, and the D terminal represents the state of the valid bit of the i-th D flip-flop at the current moment. When the CK terminal receives a rising edge, the Q terminal switches and outputs the valid bit according to the state of the D terminal. In addition, the current state is output to the QN terminal, and the reverse valid bit of the i-th D flip-flop at the current moment is output through the QN terminal.

[0079] The i-th D flip-flop also includes a buffer buffer, which is connected to the non-inverting output terminal Q and is used to enhance the driving capability of the output valid bit.

[0080] Figure 3 The structural diagram of the second circuit according to the embodiment of the present disclosure is schematically shown.

[0081] like Figure 3 As shown, according to an embodiment of the present disclosure, the second circuit includes: a plurality of AND gates AND, the number of the plurality of AND gates is the same as the number of the plurality of parallel time-to-digital conversion channels, and the output ends of the plurality of AND gates are correspondingly connected to the input ends of the plurality of parallel time-to-digital conversion channels.

[0082] A plurality of inverters, the number of the plurality of inverters is the same as the number of the cascaded D flip-flops, and the input ends of the plurality of inverters are correspondingly connected to the output ends of the cascaded D flip-flops.

[0083] Each AND gate includes:

[0084] A signal input terminal, used to input the first signal Photon_signal at the current moment;

[0085] k first input terminals, the i-th first input terminal is connected to the non-inverting output terminal of the i-th D flip-flop or the output terminal of an inverter correspondingly connected to the i-th D flip-flop; when the i-th first input terminal is connected to the non-inverting output terminal of the i-th D flip-flop, the i-th first input terminal is used to input the valid bit output by the i-th D flip-flop; when the i-th first input terminal is connected to the output terminal of an inverter correspondingly connected to the i-th D flip-flop, the i-th first input terminal is used to input the inverted valid bit of the valid bit output by the i-th D flip-flop.

[0086] The first output terminal is used to output the first signal received at the current moment.

[0087] In the embodiment of the present disclosure, for example, when the number of TDC channels is 4, the number of AND gates in the second circuit is 4, and each AND gate is provided with a first output terminal respectively connected to each TDC channel. <1> , C <2> , C <3> or C <4> Each AND gate is provided with two first input terminals, each of which is connected to a D flip-flop or an inverter connected to the D flip-flop, and is used to input a valid bit of the D flip-flop or an inverted valid bit of the valid bit.

[0088] For example, the first AND gate connects S <0> The inverting valid bit and S <1> The second AND gate is connected to S <0> The effective bit and S <1> The third AND gate is connected to S <0> The inverting valid bit and S <1> The fourth AND gate is connected to S <0> The effective bit and S <1> The valid position of .

[0089] When the input channel code S <1> S <0> When it is 00, S <1> The reverse and S <0> The reverse of is 11. At this time, the outputs of the second, third and fourth three-input AND gates are always 0. Only the channel code received by the first three-input AND gate is 11. At this time, the channel of the first AND gate is opened, and the Photon_signal signal will enter the first channel C <1> is quantized, while the other three channels are not quantized. <1> S <0> When it is 01, S <1> Reverse and S <0> The reverse direction is 10. At this time, the outputs of the first, third and fourth three-input AND gates are always 0. Only the channel code received by the second three-input AND gate is 11. At this time, the channel of the second AND gate is turned on and the Photon_signal signal enters the second channel C. <2> is quantized, while the other three channels are not quantized; similarly, when the channel encoding is 10, the Photon_signal signal will enter the third channel C <3> quantized; when the channel coding is 11, the Photon_signal signal will enter the fourth channel C <4> is quantified.

[0090] Among them, by setting two inverters, the valid bits output by two cascaded D flip-flops are switched to inverted valid bits, so that the TDC channel that meets the channel coding of the first signal at the current moment can be turned on, and flexible control of the TDC channel is achieved. And it is ensured that only when the two input ends meet the conditions at the same time, the AND gate will output a valid signal, thereby avoiding the possibility of false triggering.

[0091] Figure 4 The structural diagram of the delay circuit according to the embodiment of the present disclosure is schematically shown.

[0092] like Figure 4 As shown, according to an embodiment of the present disclosure, the delay circuit includes: N inverters connected in series, where N is an even number.

[0093] The first signal Photon_signal is input to the input end of the first inverter of the delay circuit, the output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter, and so on, until the output end of the last inverter outputs the delayed photon signal Photon_delay. The number of inverters can be set as needed.

[0094] like Figure 1 As shown, according to an embodiment of the present disclosure, it also includes: a macro pixel circuit 1 and a signal combination circuit 2.

[0095] The macro pixel circuit 1 is used to respond to and shape a plurality of photon signals input at a current moment, and output a plurality of square wave signals.

[0096] The signal combination circuit 2 is used to combine multiple square wave signals and output a first signal.

[0097] In the embodiments of the present disclosure, by responding and shaping the reflected multiple photon signals, noise components can be effectively removed, signal quality can be improved, and subsequent circuit processing can be facilitated.

[0098] Figure 5 The schematic diagram of the structure of the macro pixel circuit according to the embodiment of the present disclosure is shown;

[0099] like Figure 5 As shown, the macro pixel circuit includes: a plurality of pixel circuits; each of the plurality of pixel circuits includes a single photon detection unit and a pulse width shaping circuit.

[0100] Among them, the single photon detection unit is used to respond to the input photon signal and output a pulse signal.

[0101] The pulse width shaping circuit has an input end connected to the output end of the single photon detection unit and is used to perform reverse delay processing on the pulse signal and AND the voltage pulse after reverse delay processing with the pulse signal to output a square wave signal.

[0102] The pulse width shaping circuit comprises: an inverter INV, an input end of which is connected to the output end of the single photon detection unit.

[0103] The delay circuit has an input terminal connected to the output terminal of the inverter.

[0104] The AND gate AND has a first input end connected to the output end of the single photon detection unit, a second input end of the AND gate connected to the output end of the delay device, and an output end of the AND gate correspondingly connected to the input end of the signal combination circuit.

[0105] In the embodiments of the present disclosure, a structure in which multiple single-photon detectors jointly respond to photons and finally merge the signals can effectively reduce signal loss caused by the response dead time of a single detector.

[0106] For example, the detection window of a single-photon detector is set to 100ns. At 46ns, 50ns, and 53ns, three photon signals arrive at the detector. Assuming that there is a 10ns dead time after the detector responds to the photon, after the single detector responds to the photon arriving at 46ns, the next two incident photons will be lost due to the dead time, and only one photon information can be output in the end. However, when there are multiple detectors, after the first detector responds to the photon arriving at 46ns, the photons arriving at 50ns and 53ns can be responded to by the second and third detectors respectively. Finally, the information of the photons incident at 46ns, 50ns, and 53ns can be output through the signal combination circuit, thereby increasing the photon flux.

[0107] For example, the single photon detector may be a single photon avalanche diode (SPAD), but is not limited thereto.

[0108] The cathode of SPAD is connected to a high voltage HV, the anode is connected to a high resistance node, and is connected in series with a resistor. The other end of the resistor is grounded, and the entire SPAD is in Geiger working mode.

[0109] When a photon hits a SPAD, the photon energy triggers an avalanche effect inside the SPAD, generating an avalanche current. When this avalanche current flows through a high-resistance node, a voltage pulse is generated, which indicates the incident photon signal. Since the SPAD cannot quickly recover to its initial state after an avalanche occurs, a quenching circuit is required to restore normal operation.

[0110] Specifically, a large amount of avalanche current generated after the avalanche passes through the quenching circuit, making the bias voltage at both ends of the SPAD lower than the breakdown voltage, thereby suppressing the avalanche current. As the SPAD anode voltage gradually decreases, the SPAD eventually returns to its initial state, waiting for the arrival of the next photon. During this quenching and recovery process, the SPAD cannot respond to new photon signals, and this period of time is called the SPAD dead time.

[0111] In addition, the voltage pulse width generated by SPAD is inconsistent, which is not conducive to the processing of subsequent circuits, and the pulse needs to be shaped by a pulse width shaping circuit.

[0112] Based on this, the pulse width shaping circuit of this embodiment includes an inverter, a delay circuit and an AND gate. The voltage pulse output by the single photon detector is subjected to an inverting delay operation and then ANDed with the original voltage pulse to generate a square wave signal Pixel_out with a narrower pulse width, wherein the pulse width is determined by the delay of the delay circuit. The square wave signal indicates the incoming photon signal and can be processed by subsequent circuits.

[0113] According to an embodiment of the present disclosure, a square wave signal with a narrow pulse width can be a square wave with time as the horizontal axis and voltage value as the vertical axis. The voltage value is generally the power supply voltage. The pulse width can be preset according to the actual application scenario, for example, it can be 1ns, but it is not limited to this.

[0114] For example, when the macro pixel circuit includes four pixel circuits, four square wave signals Pixel_out<0:3> are output, such as Pixel_out <0> 、Pixel_out <1> 、Pixel_out <2> and Pixel_out <3> . But it is not limited to this, and can be set as needed.

[0115] Figure 6 The structure diagram of the signal combination circuit according to the embodiment of the present disclosure is schematically shown.

[0116] like Figure 6 As shown, the signal combination circuit 2 includes: a plurality of input terminals, the number of which is the same as the number of the output terminals of the macro-pixel circuit, and each input terminal is correspondingly connected to each macro-pixel circuit output terminal.

[0117] The signal combination circuit 2 includes a plurality of XOR gates connected in a tree structure, wherein the output of each XOR gate is connected to the input of the next XOR gate, until the output of the last XOR gate outputs a combined square wave signal, namely, the first signal Photon_signal.

[0118] Each XOR gate inputs two square wave signals, and combines the two square wave signals into a combined square wave signal, which is output through the output terminal.

[0119] In an embodiment of the present disclosure, a signal combination circuit is provided to combine square wave signals generated by a plurality of pixel circuits in a macro pixel circuit and merge them into one bus.

[0120] For example, when the macro pixel circuit includes four pixel circuits, it outputs four square wave signals, such as Pixel_out <0> 、Pixel_out <1> 、Pixel_out <2> and Pixel_out <3> Based on this, a tree structure of three XOR gates can be set up to convert Pixel_out <0> and Pixel_out <1> Merge through the first-level XOR gate 1, Pixel_out <2> and Pixel_out <3> Merge through the first-level XOR gate 2, Pixel_out <0> and Pixel_out <1> The merged result is the same as Pixel_out <2> and Pixel_out <3> The merged results are merged through the second-level XOR gate 3, and finally all the Pixel_out results are merged into a bus Photon_signal.

[0121] Figure 7 The schematic diagram shows the structure of a time-to-digital conversion circuit according to an embodiment of the present disclosure.

[0122] like Figure 7 As shown, the time-to-digital conversion circuit 6 includes a plurality of parallel time-to-digital conversion channels. Each TDC channel includes: a reset signal input terminal RSTN, a clock input terminal CLK, a shift pulse input terminal PULSET, a first signal input terminal and an output terminal, wherein the first signal input terminal is used to be connected to a corresponding AND gate.

[0123] Each TDC channel includes a 32-stage shift register chain and a 32-stage sample register chain for outputting a 32-bit digital signal TDC<1:32>.

[0124] The CLK signal is connected to the clock input terminal of each shift register, the PULSET signal is connected to the D terminal of the first shift register, the Q terminal of the first shift register is connected to the D terminal of the second shift register, and so on. The first signal at the current moment output by the second circuit is connected to the clock terminal of each sampling register, the Q terminal of each shift register is also connected to the sampling terminal of the sampling register, and the reset terminals of all shift registers and sampling registers are connected to the same reset signal RSTN.

[0125] In an embodiment of the present disclosure, when TDC is started, the PULSET signal as a shift pulse will shift on the shift register chain with the cycle of CLK. When a photon signal is input in the channel, it will trigger the sampling register for sampling. The number of levels transmitted by PULSET can quantify the flight time of the photon.

[0126] The entire detection window is divided into X uniform time partitions according to the quantization accuracy required. Each time partition corresponds to a digital code value. The size of a single time partition is also called a least significant bit (LSB) of TDC quantization, which marks the time accuracy of TDC quantization. According to the digital code value of the time partition corresponding to the photon flight time, the function of converting continuous time information into discrete digital code value output is realized.

[0127] For example, with a 16ns detection window, the distance measurement accuracy is 7.5cm. The time quantization accuracy corresponding to the distance accuracy of 7.5cm is 0.5ns, so the entire detection window of 16ns can be divided into 32 even time partitions, each time partition corresponds to 0.5ns, and the digital code values ​​of the 32 time partitions are 00000 for 0~0.5ns, 00001 for 0.5ns~1ns, 00010 for 1ns~1.5ns, and so on until 15.5ns~16ns corresponds to 11111. Assuming that a photon signal is input at 12.7ns, the time partition it is in is 12.5ns~13ns, and the corresponding digital code value is 11001, so the digital code value obtained by quantizing the time information of the photon is 11001.

[0128] Figure 8 The schematic diagram shows the structure of a histogram processing circuit according to an embodiment of the present disclosure.

[0129] like Figure 8 As shown, the multi-channel photon flight time measurement circuit further includes: a histogram processing circuit 7. The histogram processing circuit includes a plurality of 5-bit counters and adders.

[0130] Each 5-bit counter corresponds to a time bin of the histogram, and also corresponds to a least significant bit (LSB) of the TDC, which is used to count the photon signals arriving in the time bin. For the preset X time bins in a single TDC channel, X counters need to be allocated, corresponding to the X time bins of the histogram. The counter value corresponding to each time bin represents the number of photons whose flight time is in the time bin in the photon signal quantized in the channel. The statistical results of multiple channels in the same time bin are combined through an adder, and the total number of photons counted in each time bin is finally output.

[0131] For example, if the TDC has 4 channels, the output TDC1 of the first time partition of the first to fourth channels TDC <1> 、TDC2 <1> 、TDC3 <1> and TDC4 <1> They are connected to the input of a 5-bit counter respectively. The counting results of the four counters TDC1-1<4:0>, TDC2-1<4:0>, TDC3-1<4:0> and TDC4-1<4:0> are summed through an adder, and the output result Bin1<6:0> is used as the count value of the first time bin Bin1 of the histogram; the output TDC1 of the second time partition of the first to fourth channel TDC <2> 、TDC2 <2> 、TDC3 <2> and TDC4 <2> They are also connected to the input of a 5-bit counter. The counting results of the four counters TDC1-2<4:0>, TDC2-2<4:0>, TDC3-2<4:0> and TDC4-2<4:0> are summed through an adder, and the output result Bin2<6:0> is used as the count value of the second time bin Bin2 of the histogram, and so on, to finally obtain the count values ​​of all 32 time bins.

[0132] Fig. 9 The schematic diagram shows the structure of a peak detection circuit according to an embodiment of the present disclosure.

[0133] like Fig. 9 As shown, the multi-channel photon flight time measurement circuit further includes: a peak detection circuit 8. The peak detection circuit includes a 7-bit value comparator array in a tree structure and a multiplexer array in a tree structure.

[0134] Each 7-bit numerical comparator in the 7-bit numerical comparator array compares the count values ​​of different time bins of the histogram in pairs, and selects the time bin with the largest count value.

[0135] The multiplexer array outputs the position corresponding to the peak time bin according to the comparison result output by each level of 7-bit numerical comparator.

[0136] In the embodiment of the present disclosure, the input ends of the first-stage 16 comparators are respectively connected to the outputs Bin1<6:0>-Bin32<6:0> of the 32 time bins of the histogram, and the Q output end of each comparator outputs the larger count value, and the A output end outputs the result of the comparison. If INP>INN, A outputs 1, otherwise A outputs 0. The results of Bin1<6:0> to Bin32<6:0> are compared in pairs through a tree structure, and the count value Peak_Num<6:0> of the peak time bin is finally output. At the same time, the result output by the A end of each comparator is input to the multiplexer array of the tree structure, and the position Peak_Loc<4:0> corresponding to the peak time bin is selected step by step. Peak_Loc<4:0> is the final quantization result of the flight time of the laser photon. For example, the INP end of the first 7-bit comparator inputs Bin1<6:0>, the INN end inputs Bin2<6:0>, the Q end outputs Q1-1<6:0>, and the A end outputs A1-1.

[0137] For example, the entire detection window is evenly divided into eight time partitions, that is, the histogram data includes eight time bins. In the eight time bins, the count value of the first time bin is 1, the count value of the second time bin is 4, the count value of the third time bin is 5, the count value of the fourth time bin is 8, the count value of the fifth time bin is 16, the count value of the sixth time bin is 9, the count value of the seventh time bin is 4, and the count value of the eighth time bin is 2. The digital code values ​​of these eight time bins are 000, 001, 010, 011, 100, 101, 110, and 111, respectively. Then the digital code value corresponding to the peak time bin is 100, and the accumulated number of photon events is 16, of which 100 is output as the final photon flight time quantization result.

[0138] Fig.10 A comparison diagram of histogram simulation results of a circuit according to an embodiment of the present disclosure and a traditional measurement circuit is schematically shown.

[0139] like Fig.10 As shown, the histogram output results of the multi-channel photon flight time processing circuit solution using the embodiment of the present disclosure and the traditional single-channel photon flight time measurement circuit solution are compared through simulation. The TDC in the two solutions adopts the same circuit structure and has a consistent quantization dead time. And the traditional single-channel photon flight time measurement circuit includes the macro pixel circuit of the embodiment, the signal combination circuit, the single TDC channel, the histogram processing circuit and the peak detection circuit.

[0140] When the number of illumination times is 100, the cumulative number of photons in the histogram peak of this embodiment is 169, while the cumulative number of photons in the histogram peak of the traditional measurement circuit solution is 73. It can be seen that the photon flux of the scheme using the embodiment of the present disclosure is much higher than that of the traditional scheme, reflecting its superiority in improving the photon flux. On this basis, the number of laser illumination times can be reduced, thereby reducing system power consumption and improving the imaging frame rate.

[0141] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0142] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.< / max>

Claims

1. A multi-channel photon flight time processing circuit, characterized in that: include: A time-to-digital conversion circuit, comprising a plurality of parallel time-to-digital conversion channels, for performing time quantization processing on a first signal at a current moment based on a target time-to-digital conversion channel among the plurality of parallel time-to-digital conversion channels, and outputting a digital code value, wherein the digital code value comprises a flight time of a reflected photon, and the reflected photon represents a photon formed after the emitted pulse signal is reflected by a target object; A delay circuit, used for receiving a plurality of first signals in time sequence and outputting a delay signal corresponding to each first signal, wherein each of the first signals includes at least one reflected photon; A first circuit is used to determine the channel coding of the first signal at the current moment according to the delayed signal corresponding to the first signal at the current moment, wherein the channel codings of two first signals at adjacent moments are different; The second circuit is used to determine the target time-to-digital conversion channel from the multiple parallel time-to-digital conversion channels according to the channel coding of the first signal at the current moment.

2. The multi-channel photon flight time processing circuit according to claim 1, characterized in that: The first circuit comprises: k cascaded D flip-flops; Determining initial valid bits of the k cascaded D flip-flops; When the delay signal corresponding to the first first signal is input, the first D flip-flop outputs an inverted initial valid bit, and the remaining k-1 D flip-flops retain the initial valid bits; When the second delay signal corresponding to the first signal is input, the first D flip-flop outputs an initial valid bit, the second D flip-flop outputs an inverted initial valid bit, and the remaining k-2 D flip-flops retain the initial valid bits; Until the second k -1 of the delayed signals corresponding to the first signal, the first D flip-flop outputs an inverted initial valid bit, and the remaining k-1 D flip-flops retain the inverted initial valid bit; When entering the 2nd k When the delayed signal corresponding to the first signal is output, the cascaded k D flip-flops all output initial valid bits, wherein 1≦k.

3. The multi-channel photon flight time processing circuit according to claim 2, characterized in that: Also includes: Each of the k cascaded D flip-flops outputs an inverted valid bit, wherein the inverted valid bit represents an inverted state of a valid bit output by each D flip-flop, and the valid bits output by each D flip-flop constitute the channel code; as well as The state of the valid bit of the i+1th D flip-flop is switched according to the inverted valid bit output by the i-th D flip-flop; 1≦i≦k.

4. The multi-channel photon flight time processing circuit according to claim 2 or 3, characterized in that: The determining, according to the delayed signal corresponding to the first signal at the current moment, the channel coding of the first signal at the current moment comprises: The channel coding of the first signal at the current moment is determined based on the channel coding of the first signal at the previous moment.

5. The multi-channel photon flight time processing circuit according to claim 4, characterized in that: The determining the channel coding of the first signal at the current moment based on the channel coding of the first signal at the previous moment comprises: Determine initial channel coding; Based on the initial channel code, counting the delayed signals corresponding to the first signals input in time sequence to determine the channel code; When the count reaches 2 k When the second k When the delayed signal corresponds to the first signal, the second k The channel code of the first signal is the initial channel code; When entering the 2nd k +1 first signal corresponding to the delayed signal, the second k The channel code of the +1 first signal is the channel code of the first first signal.

6. The multi-channel photon flight time processing circuit according to claim 5, characterized in that: Based on the initial channel code, counting the delayed signals corresponding to the first signals input in time sequence to determine the channel code further includes: When the count is less than or equal to 2 k when the delayed signal corresponding to the first first signal input in time sequence is input, the channel coding of the first first signal is determined according to the initial channel coding; When the delayed signal corresponding to the second first signal is input, determining the channel coding of the second first signal according to the channel coding of the first first signal; Until the second k When the delayed signal corresponding to the first signal is k -1 channel coding of the first signal determines the second k channel coding of the first signal.

7. The multi-channel photon flight time processing circuit according to claim 3, characterized in that: The i-th D flip-flop comprises: A clock input terminal, when i is greater than 1, is set to be connected to the inverting output terminal of the i-1th D flip-flop, for receiving the inverted valid bit output from the i-1th D flip-flop; when i is 1, the clock input terminal of the first D flip-flop is set to be connected to the output terminal of the delay circuit, for receiving the delayed signal corresponding to the first signal at the current moment; a non-inverting output terminal, arranged to be connected to an input terminal corresponding to the second circuit, and used to output a valid bit of the i-th D flip-flop; A reset input terminal is used to reset the valid bit to an initial valid bit according to an input reset signal.

8. The multi-channel photon flight time processing circuit according to claim 7, characterized in that: The second circuit comprises: A plurality of AND gates, the number of the plurality of AND gates is the same as the number of the plurality of parallel time-to-digital conversion channels, and the output ends of the plurality of AND gates are correspondingly connected to the input ends of the plurality of parallel time-to-digital conversion channels; A plurality of inverters, the number of the plurality of inverters is the same as the number of the cascaded D flip-flops, and the input ends of the plurality of inverters are correspondingly connected to the output ends of the cascaded D flip-flops; Wherein, each of the AND gates comprises: A signal input terminal, used for inputting the first signal at the current moment; k first input terminals, the ith first input terminal is connected to the non-inverting output terminal of the ith D flip-flop or the output terminal of an inverter correspondingly connected to the ith D flip-flop; when the ith first input terminal is connected to the non-inverting output terminal of the ith D flip-flop, the ith first input terminal is used to input the valid bit output by the ith D flip-flop; when the ith first input terminal is connected to the output terminal of an inverter correspondingly connected to the ith D flip-flop, the ith first input terminal is used to input the inverted valid bit of the valid bit output by the ith D flip-flop; The first output terminal is used to output the first signal received at the current moment.

9. The multi-channel photon flight time processing circuit according to claim 1, characterized in that: The first delay circuit comprises: N inverters are connected in series, wherein N is an even number.

10. The multi-channel photon flight time processing circuit according to claim 1, characterized in that: Also includes: The macro pixel circuit is used to respond to and shape multiple photon signals input at the current moment and output multiple square wave signals; The signal combination circuit is used to combine the multiple square wave signals and output the first signal.

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