Dynamic page mapping with compression

Abstract

Various applications can include memory devices with dynamic page mapping with compression. The memory device can include a mapping table having entry locations to associate a virtual page with a physical address of a first stripe of data for the virtual page. The entry location can include a flag and the physical address of the first stripe. The flag is capable of identifying data of the virtual page as being compressed or decompressed. In response to the flag identifying that the data for a virtual page is compressed, a controller of the memory device is structured to generate a format of compressed data for the first stripe with a header. The header can include a count of additional physical addresses that store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to electronic devices, and more particularly, to storage memory devices and operations thereof. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices in various manufactured products. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and examples of volatile memory include random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and examples of non-volatile memory include flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistance random access memory (RRAM), magnetoresistive random access memory (MRAM), and three-dimensional (3D) XPoint TM Memory, etc.

[0003] Various types of memory may be used in applications where manufacturers of consumer products use an architecture of memory devices, which may include one or more memory subsystems with multiple individual storage memory media, where the memory devices interact with a host device to store user data in the one or more memory subsystems. The host device and the memory devices may operate using one or more protocols, which may include standardized protocols. The operation and properties of memory devices and other electronic devices in a system may be improved by enhancing the programming and design of these electronic devices for introduction into the system in which the electronic devices are intended to be used. Summary of the invention

[0004] On the one hand, the present disclosure provides a memory device comprising: a mapping table having entry locations to associate a virtual page with a physical address of a first stripe of data of the virtual page together with a flag, the flag identifying the data of the virtual page as compressed or decompressed; and a controller, responsive to the flag identifying that the data of the virtual page is compressed, generating a format of compressed data of the first stripe having a header, the header including a count of additional physical addresses storing the compressed data of the virtual page and the additional physical addresses.

[0005] On the other hand, the present disclosure provides a method, which includes: accessing an indirection table based on a virtual address received in a read request from a host device; reading a first stripe of compressed data from a physical memory at a physical address listed in the indirection table corresponding to the virtual address, the first stripe of compressed data including a header and the compressed data; decompressing the compressed data of the first stripe to generate decompressed data of the first stripe; and sending the decompressed data of the first stripe to the host.

[0006] On the other hand, the present disclosure provides a method, which includes: accessing an indirection table based on a virtual address received in a write request from a host device; compressing data corresponding to a user page size of the write request; obtaining a physical address of a physical memory from a free space manager based on a size of the compressed data corresponding to the write request; updating the indirection table with a first physical address among the physical addresses; generating a header including the physical addresses other than the first physical address and a count of the physical addresses other than the first physical address; formatting compressed data to include the header; and writing the formatted compressed data with the header to the first physical address of the physical memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed in this document by way of example and not limitation.

[0008] Figure 1 is a representation of two parts of a mapping procedure for a dynamic mapping table of a memory device according to various embodiments.

[0009] Figure 2 Description of the various embodiments of the present invention Figure 1 The data format implemented in the dynamic mapping scheme.

[0010] Figure 3 Description of the various embodiments of the present invention Figure 1 Another data format implemented in the dynamic mapping scheme of .

[0011] Figure 4 is a flow diagram of features of an example method of reading data from a memory device, wherein the data is stored in the memory device as compressed data, according to various embodiments.

[0012] Figure 5 is a flow diagram of features of an example method of writing data to a memory device, wherein the data is stored in the memory device as compressed data, in accordance with various embodiments.

[0013] Figure 6A block diagram illustrating example component features of a compute fast link system including dynamic page mapping with compression of user data in accordance with various embodiments.

[0014] Figure 7 Description of various embodiments Figure 6 An instance of a compression zone manager for a computationally fast link controller.

[0015] Figure 8 Description of various embodiments Figure 7 An embodiment of an instance of a table manager of a compression zone manager.

[0016] Fig. 9 is a block diagram of an example system including a host operating with a memory device having one or more memory media that can implement a dynamic page mapping scheme with compression of user data, in accordance with various embodiments. DETAILED DESCRIPTION

[0017] The following detailed description refers to the accompanying drawings that show, by way of illustration and not limitation, various embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical, and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be considered as intended to be limiting.

[0018] In order to improve the utilization of physical space in the memory device, a data compression feature may be implemented in the memory device to compress the data received from the host. The memory device may include one or more memory media to store user data. This feature may be structured to compress the data when writing host data and decompress the compressed data when reading in response to a host read request. Compared with a memory device without compression, the compression of user data can change the target capacity of the memory device and provide better physical capacity utilization. Compression can be characterized by a compression ratio, which can depend on the properties of the data blocks used as the basis for storing data in the memory device. Compression can be used to change the data block size of the stored data. For an example unit block size of 4096 bytes (referred to as 4K bytes (4KB)), compression can result in data being stored in units between a few bytes and 4KB. In conventional methods, after compression, an additional indirect method will be used to locate the data blocks in the memory medium of the memory device.

[0019] The memory devices may be implemented in many different memory device architectures. For example, compression may be performed in, but not limited to, a compute express link (CXL) memory device, a solid state drive (SSD), or other memory device. One or more memory devices may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host while the computer or electronic system is operating. During operation of the computing or other electronic system, data, commands, or instructions may be transferred between the host and the one or more memory devices.

[0020] Various protocols or standards may be applied to facilitate communication between a host and one or more other devices, such as a memory device, a memory buffer, an accelerator, or other input / output (I / O) device. For example, an out-of-order protocol such as CXL may be used to provide high bandwidth and low latency connectivity. Other protocols may be used as an alternative to or in conjunction with CXL.

[0021] CXL is an open standard interconnect configured for high-bandwidth, low-latency connectivity between host devices and other devices (such as accelerators, memory buffers, or other I / O devices). CXL is designed to facilitate high-performance computing workloads by supporting heterogeneous processing and memory systems. CXL implements coherency and memory semantics in addition to Peripheral Component Interconnect Express (PCIe)-based I / O semantics for optimized performance.

[0022] CXL can be used in applications such as artificial intelligence, machine learning, analytics, cloud infrastructure, edge computing devices, communication systems, and others. Data processing in such applications can use various scalar, vector, matrix, and spatial architectures that can be deployed in central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), application specific integrated circuits (ASICs), other programmable logic devices, intelligent network interface cards (NICs), or other accelerators that can be coupled using CXL links. A processing module (e.g., a CPU) can be implemented as a host device or host processor in an architecture where the CPU is structured.

[0023] CXL supports dynamic multiplexing using a set of protocols that include I / O (CXL.io, based on PCIe), cache (CXL.cache), and memory (CXL.memory) semantics. CXL can be used to maintain a unified, consistent memory space between the CPU and any memory on an attached CXL device. This configuration allows the CPU and CXL devices to share resources and operate on the same memory region to achieve higher performance, reduce data movement, and reduce software stack complexity. In an example, the CPU may be primarily responsible for maintaining or managing consistency in a CXL environment. Therefore, CXL can be utilized to help reduce device cost and complexity as well as the overhead typically associated with consistency across I / O links.

[0024] CXL runs on top of the PCIe physical layer (PHY) and provides full interoperability with PCIe. CXL devices can start link training at PCIe Gen 1 data rates and can negotiate CXL as their operating protocol when their link partner supports CXL. CXL can be used as an operating protocol, for example using the alternative protocol negotiation mechanism defined in the PCIe 5.0 specification. As a result, devices and platforms can more easily adopt CXL by leveraging the PCIe infrastructure and without having to design and validate PHYs, channels, channel extension devices, or other upper layers of PCIe.

[0025] CXL technology can maintain memory consistency between the CPU memory space and the memory on the attached device, which enables resource sharing to achieve higher performance, reduce software stack complexity and reduce overall system cost. Three main types of devices can adopt the CXL interconnect protocol. Type 1 devices can include accelerators, such as smart NICs that typically lack local memory. Via CXL, these Type 1 devices can communicate with the memory of the host processor to which they are coupled. Type 1 devices can use CXL.io+CXL.cache protocols. Type 2 devices can include GPUs, ASICs, and FPGAs, which are equipped with tools such as (but not limited to) double data rate (DDR) memory or high bandwidth memory (HBM) and can use CXL to make the host processor's memory available locally to the accelerator and the accelerator's memory available to the host processor. Type 2 devices can also be co-located in the same cache coherent domain and help increase heterogeneous workloads. Type 2 devices can use CXL.io+CXL.cache+CXL.memory protocols. Type 3 devices can include memory devices, which can be attached via CXL to provide additional bandwidth and capacity to the host processor. The type of memory is independent of the host's main memory. Type 3 devices can use the CXL.io + CXL.memory protocol.

[0026] Compression in a memory device, such as, but not limited to, a CXL memory device, may be implemented by a mechanism for locating a block of data in a storage medium after compression. The ability to refer to data using a reference other than the value of the data itself, such as operating on data by the memory address of the data, is an indirection mechanism. An indirection table may contain entries that are pointers to one or several locations of data in the storage medium. A linear indirection table may be used for address translation of compressed data. A linear indirection table of a memory device may be arranged with an entry for each address of a page of data provided by a host device. Such data addresses and pages are provided by the host device and are independent of data management in the memory device. With respect to a memory device, the host-supplied address and page are a virtual address (VA) and a virtual page (VP), which are mapped by the memory device to a physical address (PA). A PA is an address used by a memory device to point to a memory medium (such as a memory die or a packaged memory die), a row, and a column to store one or more bits of data, wherein the pointing mechanism may be calculated based on the type of memory used for the memory medium.

[0027] In a memory device, the user page size may be set equal to 4KB, where the VP is structured to be equal to 64 consecutive PAs of the memory device (64B*64=4096B(4KB)). The media unit of the memory device may be defined as the minimum amount of data that can be written to the memory device. The media unit may be set to 256B. The media unit may be referred to as a stripe. For a user page size of 4KB user data, 16 stripes may be used to store the user data. Other sizes of user pages and sizes of stripes may be used. In a first conventional method or first option for managing data compression in a memory device, a mapping table in the memory device may be implemented as a linear indirect table structured to have one entry per user block (e.g., 4K). The entry may include a starting PA of a stripe of data in a storage medium of the memory device and a count (specified number) of consecutive PAs storing compressed data after the starting PA. Optionally, the entry of the starting PA may be an index, where the count identifies a subsequent specified index. The index may be a pointer to a location in the stripe table having the PA. This first option may provide a relatively small mapping table, but may result in the implementation of defragmentation. Defragmentation is the process of freeing up storage space. In this first option, defragmentation in the memory device can be challenging and complex. For example, in the first option, defragmentation can be used to create free continuous data stripes, which can cause the compression process to become complicated. In the second general option, the use of defragmentation can be avoided by having an entry for each VA in a linear indirect table, which contains the PA for each stripe of data written by a given VA. Optionally, the entry for the PA associated with a given VA can be a set of indexes, where each index can point to a location in the stripe table that has a different PA for each index. However, in this second option, this indirect table is a mapping table that can be significantly larger in size than the first option. For a user page size of 4KB and a stripe size of 256B, the size of the mapping table of the second option can be 16 times the size of the mapping table of the first option.

[0028] In various embodiments, a dynamic mapping table in the memory storage that translates VA to PA may be implemented for data that may be compressed. The mapping table size may depend on the compression ratio of the data written to the memory storage. If the page may be compressed, the dynamic mapping table may have an entry to hold the PA of the starting stripe of the compressed data, which may be used to identify the PA of each stripe in addition to being used to store the compressed data on a given medium. The mapping procedure may be divided into two parts. The first of the two parts may use a linear table as the dynamic mapping table and the second of the two parts may use a header formatted with the compressed data, which is stored in the physical memory of the memory device at the PA identified in the linear table.

[0029] Figure 1A representation 100 of two parts of a mapping program (scheme) that is a dynamic mapping table of a memory device. Representation 100 shows an entry 107 of data corresponding to a VP of a VA in a linear table 105. Entry 107 includes a PA for a first stripe 125 of data corresponding to the VP along with a flag (c / r) indicating the VP as compressed or decompressed in the memory device. If the flag identifies no compression, then the stripe of data is decompressed data with a VA, where each stripe has a corresponding PA in the linear table 105. If the flag identifies compression, then the stripe of data is compressed data and a single PA may be listed in the linear table 105 to manage the stripe of data, where the compressed data is derived from compressed data of a VP corresponding to data from a host with a VA.

[0030] Representation 100 shows physical memory 110 having a plurality of blocks 115 for storing data. Each block may be arranged as a fixed-size stripe of data, such as 256B. Other fixed sizes may be implemented depending on the architecture of a given storage medium. In response to the flag of entry 107 identifying compression, a first stripe 125 of data is formatted with a header 120. The header 120 of the first stripe of data is constructed with information about the other stripes of data 126, 127, and 128 of the compressed VP. The compressed data of the VP is not limited to being stored in 4 stripes, which are in Figure 1 The information in header 120 may include PAs for data stripes 126, 127, and 128, where the PAs for data stripes 126, 127, and 128 are not included in linear table 105. These other data stripes 126, 127, and 128 do not include formatted headers, such as the format of header 120 for first stripe 125. In response to the flag identifying data decompression, the data of the VP may be stored as decompressed data that is not formatted with a header and stored in a plurality of blocks 115 in physical memory 110. These plurality of blocks may correspond to consecutive PAs for stripes of physical memory 110, where the consecutive PAs may be stored in linear table 105. The indirect table for a given VA of uncompressed data may be implemented according to the conventional first or second options previously discussed. Depending on the memory architecture, compressed data or decompressed data for storage in physical memory 110 may also be formatted with a header or elements of a header to contain information in addition to dynamic mapping information.

[0031] Figure 2 Description can be found in Figure 11. The data format 202 is implemented in a dynamic mapping scheme of the present invention. The data format 202 has a header plus data format. The data format 202 may be generated when the c / r flag of the entry 107 identifies that the received VA is compressible. The data format 202 may be generated for the first stripe of compressed data, wherein in the dynamic mapping scheme, the first stripe is generated with the header 120, and other stripes of compressed data may not be formatted with the header 120. The PA stored in the entry 107 in which the c / r identifies that the VP is compressed is the PA of the first stripe in the physical memory 110. The data format 202 may be generated using a fixed data structure.

[0032] The data format 202 may include Figure 1 222-N of the data of the first stripe 125 of the data format 202. Depending on the architecture of a given memory device, each of these segments may have a fixed number of bytes. Considering a memory device using a 4KVP size and a 256B stripe size, N may be set to 4 and the size of each of the segments 222-1, 222-2...222-N may be set to 64 bytes. Segment 222-1 may include header 120, user data blocks (UDBs), and error correction codes (ECCs). Each of segments 222-1, 222-2...222-N may include UDBs and ECCs. The data structure of data format 202 may include segment 222-1 as a first segment, which has a field to contain a fixed number of bits identifying a data location indicating where the compressed data begins in data format 202. The fixed number of bits may be predefined prior to operation of a given memory device. The data location field is followed by a field containing the PA of the stripe, which contains compressed data for VPs other than the first stripe. The size of the data location field and the PA field depends on the architecture of a given memory device. Considering a 4K VP size and a 256B stripe size, the data location field can be generated as the first 4 bits of the header 120 followed by a 4-byte PA field. The data location field can store the data starting position, and the subsequent bits (5th bit continued) in the header 120 can store the PA address of the subsequent stripe. The data location that identifies the start of the data can be implemented as the number of additional PAs that store the compressed data of the VP. When the PA address of the subsequent stripe is in the header 120, the PA address of the subsequent stripe is not stored in the linear table 105. Using the header to store these subsequent PAs provides a dynamic mapping scheme that can reduce the size of a linear table (such as the linear table 105).

[0033] Figure 3 Description can be found in Figure 1The data format 303 is implemented in a dynamic mapping scheme of the present invention. When the PA address of the subsequent stripe is stored in the header 120, a subsequent stripe that does not include a header structured similar to the header 120 may be generated. The data structure of the data format 303 may be generated as a full data format. The full data format of the stripe has only compressed user data. The data format 303 may include segments 323-1, 323-2 ... 323-N and each of the segments 323-1, 323-2 ... 323-N may include UDB and ECC. The data format 303 may be structured in the same size as the data format 202, wherein no header is generated in the segment 323-1. In addition to the compressed data for the subsequent PA in the header 120 corresponding to the data format 202, the data format 303 may also be used to have Figure 1 The decompressed data of the corresponding PA in the linear table 105.

[0034] Figure 4 4 is a flow chart of features of an embodiment of an example method 400 of reading data from a memory device, wherein the data is stored in the memory device as compressed data. A controller of the memory device may be used to manage providing data from the compressed data and managing a read procedure. The read procedure may be managed by a processing circuit system of the controller that may execute instructions stored in the memory device. The controller may be implemented as one or more processing devices that may execute instructions stored in the memory device. At 410, an indirect table is accessed based on a VA received in a read request from a host device. Accessing the indirect table may include loading the indirect table when the indirect table is not cached.

[0035] At 420, a first stripe of compressed data is read from the PA of physical memory corresponding to the VA listed in the indirection table. The first stripe of compressed data includes a header and the first stripe of compressed data.

[0036] At 430, the compressed data of the first stripe is decompressed to generate the decompressed data of the first stripe. After decompressing the first stripe, the header of the first stripe can be obtained for decomposition, wherein the information in the header can be further processed when operating on the read request. At 440, the decompressed data of the first stripe is sent to the host.

[0037] Variations of method 400 or methods similar to method 400 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of the system including the electronic device in which such methods are implemented. Such methods may include reading a next stripe of compressed data from a PA of a physical memory retrieved from a header of a first stripe of compressed data. The retrieved compressed data of the next stripe may be decompressed, thereby generating decompressed data of the next stripe. The decompressed data from the next stripe may be sent to a host along with the decompressed data of the first stripe.

[0038] A variation of method 400 or a method similar to method 400 may include: after decompressing the first stripe of compressed data, successively reading stripes of compressed data having the PA in the header of the first stripe. The compressed data of the stripe having the PA in the header of the first stripe may be decompressed and copied to the cache along with the decompressed data of the first stripe. The read request may be a series of read requests and the decompressed data of the stripe having the PA in the header of the first stripe along with the decompressed data from the first stripe may be copied to the read buffer for the series of read requests.

[0039] Figure 5 Flowchart of features of an embodiment of an example method 500 for writing data to a memory device, wherein the data is stored in the memory device as compressed data. A controller of the memory device may be used to manage providing compressed data and a write procedure. The write procedure may be managed by a processing circuit system of the controller that may execute instructions stored in the memory device. The controller may be implemented as one or more processing devices that may execute instructions stored in the memory device. At 510, an indirect table is accessed based on a VA received in a write request from a host device. Accessing the indirect table may include loading the indirect table for processing. The indirect table may be loaded from a component of the memory device, such as a storage device of the memory device.

[0040] At 520, data corresponding to a user page size of the write request is compressed. The user page size may be 4KB. At 530, PAs of physical memory of the memory device are obtained from a free space manager (FSM) based on the size of the compressed data corresponding to the write request. These PAs may be PAs that are released for use by performing an invalidation process by the FSM. The invalidation process identifies the currently used PAs as no longer associated with valid data and identifies these PAs as available for future use. The stripes corresponding to these released PAs may be overwritten with the data provided in the newly received write request. At 540, an indirect table is updated with a first PA from the PAs provided by the FSM. The update may include setting a flag in the entry updated with the first PA, wherein the flag indicates that the data of the first PA is compressed data.

[0041] At 550, a header is generated. The generated header includes a PA other than the first PA and a count of the PAs other than the first PA. At 560, the compressed data is formatted to include the header. At 570, the formatted compressed data with the header is written to the first PA of the physical memory. The remaining compressed data corresponding to the write request may be written to the PAs other than the first PA identified in the data structure of the first stripe.

[0042] Variations of method 500 or methods similar to method 500 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of the system including the electronic device in which such methods are implemented. Such methods may include accessing an indirection table in a cache, wherein the indirection table in the cache includes a first PA corresponding to the VA. Contents of the PA in the cache regarding the compressed data may initiate operation of the first PA to modify the PA set for writing the compressed data.

[0043] A variation of method 500 or a method similar to method 500 may include an operation by the FSM to release the PA for a write operation. Such an operation may include obtaining the PA corresponding to the VA from an indirection table, wherein the indirection table has a flag identifying that the data stripe at the PA is compressed data. A header may be read from the stripe corresponding to the PA. In response to reading the header, the FSM may set the PA and additional PAs listed in the header as free for future use to store user data.

[0044] The dynamic mapping scheme of memory devices discussed herein can be implemented in many different applications of electronic devices. Electronic devices, such as mobile electronic devices (e.g., smartphones, tablets, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and networked appliances or devices (e.g., Internet of Things (IoT) devices, etc.) have different storage requirements, which depend in particular on the type of electronic device, the usage environment, performance expectations, etc. An electronic device can be decomposed into several main components: a processor (e.g., a CPU or other main processor); a memory (e.g., one or more volatile or non-volatile RAM memory devices, such as DRAM, mobile or low-power DDR SDRAM, etc.); and a storage device (e.g., a non-volatile memory (NVM) device, such as flash memory, ROM, SSD, MMC or other memory card structures or assemblies, etc.). Such electronic devices can be associated with a range of architectures, including CXL systems and managed memory systems. SSD, Universal Flash Storage (UFS TM ) and embedded multimedia card (eMMC TM ) devices may be included in a managed memory system, which may also include processing circuitry (e.g., one or more of a memory processing device, a direct memory access (DMA) controller, and a flash memory interface circuitry) to manage access to the physical memory media. Many such electronic devices may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, etc.), a GPU, a power management circuit, a baseband processor, or one or more transceiver circuits, etc.

[0045] Figure 6is a block diagram of an embodiment of example component features of a CXL system 600 including dynamic page mapping with compression of user data. The CXL system 600 may include a CXL host 635 and a CXL memory device 640 that may operate according to the CXL protocol. The CXL memory device 640 may include a controller 645 that interfaces with a medium 642 of the CXL host 635 and the CXL memory device 640 to write user data directed from the host to the medium 642 using one or more write requests and read user data from the medium 642 using one or more read requests for the CXL host 625. The execution of the write requests and the read requests may be performed using the dynamic page mapping scheme with compression of the user data.

[0046] The controller 645 may include a CXL front end (FE) 641 that interfaces with the CXL host 635 using the CXL protocol and a cache manager 643 that manages the flow of intermediate user data associated with read and write requests received from the CXL host 635. The user data may be stored in a medium 642, where the medium 642 may be structured as one or more memory structures arranged as a data storage channel. The user data may be processed by an Advanced Encryption Standard (AES) 647 and ECC 648. Processing the user data with ECC 648 by a memory controller (MC) and an interface (INF) 649 may control input and output of the user data from the medium 642. The user data operated by AES 647, ECC 648, and MC&INF 649 may be compressed data. Compressing the user data and decompressing the user data may be controlled by a compression region manager (CRM) 646.

[0047] Figure 7 illustrate Figure 66. The CRM 646 of the CXL controller 645 of FIG. 646 may include a read buffer 751 that handles requested user data and a write buffer 753 that handles write requested user data. The read buffer 751 and the write buffer 753 may be first-in-first-out (FIFO) structures that may be implemented in many formats, including one or more registers or one or more other buffer structures that may cache user data. Data from the read buffer 751 and the write buffer 753 may be directed to the table manager 755 and the compression logic 759 through a multiplexer (MUX) 752. The CRM 646 also includes decompression logic 758 that decompresses received compressed read data using logic circuitry within the decompression logic 758, where the compressed read data is compressed data received from the media 642 in response to a read request. If the input user data meets the compression criteria, the compression logic 759 may use the received compression ratio data to compress the input user data using logic circuitry within the compression logic 759. The criteria may be provided in the compression ratio data or from the table manager 755. The compression logic 759 may provide the compressed data to the table manager 755 which may output the compressed data, or the compression logic 759 may output the compressed data alternatively or in conjunction with the table manager 755. The compression logic 759 may also provide compression ratio data for subsequent operations associated with compression. The compression logic 759 may be structured to perform compression calculations. In addition to operating on the output of read / write compressed data, the table manager 755 may also operate on read / write mapping data to receive and output read / write mapping data. The table manager 755 may be operable to manage the dynamic mapping scheme with compressed data taught herein.

[0048] Figure 8 illustrate Figure 7866. The table manager 755 may include a register 862. The register 862 may be a FIFO structure that may be implemented in many formats, including one or more register structures or one or more other buffer structures that may hold data. The table manager 755 may include one or more tables 867. The table 867 may include a table for mapping and looking up information about cached data along with updating mappings associated with read and write requests. The table 867 may be operated by the FSM 865 to enable the PA to be used in invalidation processes, including evicting data pages from identified memory locations in response to write operations, as taught herein. The table 867 may include an indirection table for mapping and updating information to translate received VAs with associated PAs, as taught herein. Frequently read data may be cached and the table 867 may be used to determine whether such data is currently part of a read or write (read / write) request. Determining that the current data of a read / write request is cached is a hit, and determining that the current data of a read / write request is not cached is a miss. Table 867 may provide data from lookup hit data, data from lookup miss data, and data for page evictions associated with mapping for write operations.

[0049] Fig. 9 is a block diagram of an embodiment of an example system 900 that includes a host 935 operating with a memory device 940 having one or more memory media that can implement a dynamic page mapping scheme for compressing user data in an application in which the memory device 940 is implemented. The dynamic page mapping scheme can be used with and Figure 1 The associated mapping program, Figure 2 and 3 The data structure of Figure 4 and 5 Methods and Figures 6 to 8 The system 900 and its components may be structured in many different arrangements. For example, the system 900 may be arranged with variations of component types including a host 935, an interface 950, a memory device 940, memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6, a processing device 945, and a bus 957.

[0050] The host 935 is coupled to the memory device 940 through an interface 950, wherein the host 935 is a host device that may include one or more processors, which may vary in type to be compatible with the interface 950 and the memory device 940. The memory device 940 may include a processing device 945 coupled to memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6 through a bus 957, wherein each memory medium has one or more memory cell arrays. The memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6 may be implemented as a memory structure that may be selected from different types of memory. Although Fig. 9 6 memory media are shown in FIG, but memory device 940 can be implemented with more or less than 6 memory media, that is, memory device 940 can include one or more memory media. The memory media can be implemented in many formats, including (but not limited to) multiple memory dies or multiple packaged memory dies.

[0051] Processing device 945 may include processing circuitry or be structured as one or more processors. Processing device 945 may be structured as a memory system controller of memory device 940. Processing device 945 may be implemented in many different formats. Processing device 945 may include or be structured as one or more types of processors compatible with memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6. Processing device 945 may include processing circuitry that may be structured with a DSP, an ASIC, other types of processing circuits (including a group of processors or a multi-core device), or a combination thereof.

[0052] Memory device 940 may include firmware 955 having code executable by processing device 945 to manage at least memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6. Firmware 955 may reside in a storage device of memory device 940 coupled to processing device 945. Firmware 955 may be coupled to processing device 945 using bus 957 or some other interface on memory device 940. Alternatively, firmware 955 may reside in processing device 945 or may be distributed in memory device 940 with firmware components, such as, but not limited to, code, including one or more components in processing device 945. Firmware 955 may include code having instructions executable by processing device 945 to operate on memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6. The instructions may include instructions to perform operations using a dynamic mapping scheme as taught herein to store user data as compressed data in one or more of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6.

[0053] Memory device 940 may include storage device 944, which may be implemented to provide data and parameters for maintaining memory device 940. Storage device 944 may include one or more of a non-volatile memory structure or RAM. Fig. 9 In the memory device 940 of FIG. 9A , the memory device 944 is external to the processing device 945, but the memory device 944 may be integrated into the processing device 945. The memory device 944 may be coupled to the bus 957 to communicate with other components of the memory device 940. Alternatively, the memory device 944 may be coupled to the processing device 945, where the processing device 945 handles the communication between the memory device 944 and the other components of the memory device 940. The memory device 944 may be coupled to the bus 957 and the processing device 945.

[0054] Each of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, 942-6, firmware 955, storage device 944, and other memory structures of memory device 940 is implemented as a machine-readable medium. Non-limiting examples of machine-readable media may include solid-state memory, optical media, and magnetic media. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory media (e.g., EPROM, EEPROM), and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and compact disk-ROM (CD-ROM) and digital versatile disk-read only memory (DVD-ROM) disks.

[0055] Firmware 955, storage device 944, or other components of memory device 940 may include a mapping table having entry locations to associate a virtual page with the PA of the first stripe of data for the virtual page along with a flag identifying the data for the virtual page as compressed or decompressed. The mapping table may be similar to Figure 1 The processing device 945 may be implemented as a controller to identify the data of the virtual page as a format of compressed data that is compressed to produce a first stripe with a header in response to a flag in the table in the memory device 940. The header may include a count of additional PAs and additional PAs for storing the compressed data of the virtual page.

[0056] The firmware 955, storage device 944, or other components of the memory device 940 may have instructions that are executable by the processing device 945 to operate on the user data so that the user data is stored in one or more of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6 in a compressed format. The firmware 955, storage device 944, or other components of the memory device 940 may have instructions that are executable by the processing device 945 to operate on the compressed user data to be read from one or more of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6 and the resulting decompressed user data. The compression format may be similar to or identical to the data structure that defines the compressed format. Figure 2 and 3 The format is generated.

[0057] Processing device 945 may execute instructions stored on one or more components in memory device 940 that, when executed by processing device 945, cause memory device 940 to perform operations. The operations may include method 400, method 500, methods similar to method 400 or method 500, and methods similar to those of method 400 or method 500. Figures 6 to 8 The operations may include operations to read data from physical memory of one or more of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6, wherein the data is stored in a compressed format. The operations may include accessing an indirection table in the memory device 940 based on a VA received in a read request from the host 935. The operations performed may include accessing an indirection table by loading the indirection table when the indirection table is not cached. A first stripe of compressed data may be read from the physical memory at a PA listed in the indirection table corresponding to the VA, wherein the first stripe of compressed data includes a header and compressed data. The operations may include decompressing the compressed data of the first stripe and sending the decompressed data of the first stripe to the host 935.

[0058] The operations performed by the processing device 945 may include reading a next stripe of compressed data at the PA retrieved from the header of the first stripe of compressed data. After decompressing the first stripe, the header of the first stripe may be obtained for decomposition. The compressed data of the next stripe may be decompressed and sent to the host 935 along with the decompressed data of the first stripe. After decompressing the first stripe of compressed data, the compressed data of the stripe having the PA in the header of the first stripe may be read successively.

[0059] The operations performed by processing device 945 may include decompressing compressed data of the stripe having the PA in the header of the first stripe, and copying the decompressed data of the stripe having the PA in the header of the first stripe to a cache along with the decompressed data of the first stripe.

[0060] The read request executed by the processing device 945 operating the instructions stored in the memory device 940 may be a series of read requests. The decompressed data of the stripe with the PA in the header of the first stripe together with the decompressed data from the first stripe may be copied to the read buffer for the series of read requests. The read buffer may be implemented by the circuit system of the memory device 944 or the processing device 945.

[0061] The processing device 945 may execute instructions stored on one or more components in the memory device 940 that, when executed by the processing device 945, cause the memory device 940 to perform operations. The operations may include operations that write data to physical memory of one or more of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6 in a compressed format. The operations may include accessing an indirection table based on a VA received in a write request from the host 935. The indirection table may be accessed by loading the indirection table to process or accessing the indirection table from a cache, wherein the indirection table has an entry corresponding to the PA of the VA.

[0062] The operations performed by the processing device 945 may include compressing data of a user page size corresponding to the write request and obtaining a PA of the physical memory from the FSM based on the size of the compressed data corresponding to the write request. The user page size may be (but not limited to) 4KB. The FSM may be implemented by the tools, circuit systems, and storage instructions of the firmware 955. The indirect table may be updated with a first PA among the PAs obtained from the FSM. The operations performed may include generating a header, wherein the header includes a PA other than the first PA and a count of the PAs other than the first PA. The compressed data may be formatted to include a header. The formatted compressed data may be written to the first PA of the physical memory together with the header. The operations performed by the processing device 945 may include writing the remaining compressed data corresponding to the write request to the PA of the physical memory other than the first PA.

[0063] Operations performed by processing device 945 may include the FSM releasing the PA for a write operation. The operations may include obtaining the PA corresponding to the VA from an indirection table, wherein the indirection table has a flag identifying that the data stripe at the PA is compressed data. The header may be read from the stripe corresponding to the PA. The FSM may release the PA listed in the header and additional PAs for future use.

[0064]

[0013] Following are example embodiments of systems, devices, and methods according to the teachings herein.

[0065] The example memory device 1 may include: a mapping table having entry locations to associate a VP with a PA of a first stripe of data for the VP together with a flag identifying the data of the VP as compressed or decompressed; and a controller that generates a format of compressed data of the first stripe having a header in response to the flag identifying that the data of the VP is compressed, the header including a count of additional PAs storing compressed data of the VP and the additional PAs.

[0066] Example memory device 2 may include the features of example memory device 1 and may include that the additional PA is a PA for the additional stripe of compressed data for the VP.

[0067] Example memory device 3 may include features of example memory device 2 and any of the preceding example memory devices and may include the additional stripe of data for the VP having a format without a header.

[0068] Example memory device 4 may include features of example memory device 3 and any of the preceding example memory devices and may include that the format includes a block of user data and an ECC following the count of additional PAs.

[0069] Example memory device 5 may include features of any of the aforementioned example memory devices and may include that the header has a predefined format that depends on a size of the first stripe.

[0070] Example memory device 6 may include features of any of the aforementioned example memory devices and may include a FSM to enable a PA to be used to write data from a host to a memory subsystem of the memory device.

[0071] Example memory device 7 may include features of any of the aforementioned example memory devices and may include a CXL 3 type memory device.

[0072] In example memory device 8, any of example memory devices 1-7 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0073] In example memory device 9, any one of example memory devices 1-8 may be modified to include any structure present in another one of example memory devices 1-8.

[0074] In example memory device 10, any apparatus associated with a memory device in example memory devices 1-9 may further include a machine-readable storage device configured to store instructions as a physical state, where the instructions may be used to perform one or more operations of the apparatus.

[0075] In example memory device 11, any of example memory devices 1-10 may operate according to any of the following example methods 1-20.

[0076] Example method 1 may include: accessing an indirection table based on a VA received in a read request from a host device; reading a first stripe of compressed data from a PA in the indirection table corresponding to the VA, the first stripe of compressed data including a header and the compressed data; decompressing the first stripe of compressed data, thereby generating decompressed data for the first stripe; and sending the first stripe of decompressed data to the host.

[0077] Example method 2 may include features of example method 1 and may include: reading a next stripe of compressed data at the PA retrieved from the header of the first stripe of compressed data; decompressing the compressed data of the next stripe, thereby generating decompressed data of the next stripe; and sending the decompressed data of the next stripe along with the decompressed data of the first stripe to the host.

[0078] Example method 3 may include features of any of the preceding example methods and may include, after decompressing the first stripe of compressed data, successively reading stripes of compressed data having a PA in the header of the first stripe.

[0079] Example method 4 may include features of method 3 and any of the aforementioned example methods 1 to 2 and may include: decompressing the compressed data of the stripe having the PA in the header of the first stripe; and copying the decompressed data of the stripe having the PA in the header of the first stripe to a cache together with the decompressed data of the first stripe.

[0080] Example method 5 may include features of method 4 and any of the aforementioned example methods 1 to 3 and may include the read request being a series of read requests and the decompressed data of the stripe having the PA in the header of the first stripe being copied to a read buffer along with the decompressed data from the first stripe for the series of read requests.

[0081] Example method 6 may include the features of example method 5 and any of the preceding example methods and may include obtaining the header of the first stripe for decomposition after decompressing the first stripe.

[0082] Example method 7 may include features of any of the preceding examples and may include accessing the indirection table to include loading the indirection table when the indirection table is not cached.

[0083] In example method 8, any of example methods 1-7 may be performed while operating an electronic device further comprising a host processor and a communication bus extending between the host processor and a memory device.

[0084] In example method 9, any of example methods 1-8 may be modified to include operations described in any other of example methods 1-8.

[0085] In example method 10, any of example methods 1-9 may be implemented at least in part by using instructions stored as physical states in one or more machine-readable storage devices.

[0086] Example method 11 may include features of any of the foregoing example methods 1-10 and may include performing functions associated with any features of example memory devices 1-11.

[0087] Example method 12 may include: accessing an indirection table based on a VA received in a write request from a host device; compressing data corresponding to a user page size of the write request; obtaining a PA from an FSM based on a size of the compressed data corresponding to the write request; updating the indirection table with a first PA among the PAs; generating a header including the PAs other than the first PA and a count of the PAs other than the first PA; formatting compressed data to include the header; and writing the formatted compressed data with the header to the first PA.

[0088] Example method 13 may include features of example method 12 and may include writing remaining compressed data corresponding to the write request to the PA of physical memory other than the first PA.

[0089] Example method 14 may include features of any of the foregoing example methods 12-13 and may include accessing the indirection table to include loading the indirection table for processing.

[0090] Example method 15 may include features of any of the foregoing example methods 12-14 and may include accessing the indirection table to include accessing the indirection table in a cache, the indirection table including the first PA corresponding to the VA.

[0091] Example method 16 may include features of any of the aforementioned example methods 12 to 15 and may include the FSM freeing a PA for a write operation by: obtaining a PA corresponding to the VA from the indirection table, the indirection table having a flag identifying that the stripe of data at the PA is compressed data; reading a header from the stripe corresponding to the PA; and freeing the PA and additional PAs listed in the header for use.

[0092] Example method 17 may include the features of any of the foregoing example methods 12-16 and may include the user page size being 4 KB.

[0093] In example method 18, any of example methods 12-17 may be performed while operating an electronic device further comprising a host processor and a communication bus extending between the host processor and a memory device.

[0094] In example method 19, any of example methods 12-18 may be modified to include the operations described in any other of examples 12-18.

[0095] In example method 20, any of example methods 12-19 may be implemented at least in part by using instructions stored as physical states in one or more machine-readable storage devices.

[0096] Example method 21 may include features of any of the foregoing example methods 12-20 and may include performing functions associated with any features of example memory devices 1-11.

[0097] Example method 22 may include features of any of the foregoing example methods 1-11 and example methods 12-21 and may include performing functions associated with any features of example memory devices 1-11.

[0098] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause the machine to perform operations may include instructions to perform functions associated with any feature of example memory devices 1-11 or to perform methods associated with any feature of example methods 1-21.

[0099] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments utilize permutations and / or combinations of the embodiments described herein. It should be understood that the above description is intended to be illustrative and not limiting, and that the phraseology or terminology employed herein is for descriptive purposes.

Claims

1. A memory device, comprising: a mapping table having entry locations to associate a virtual page with a physical address of a first stripe of data for the virtual page along with a flag identifying the data for the virtual page as compressed or decompressed; and A controller that, in response to the flag identifying that the data of the virtual page is compressed, generates a format of compressed data of the first stripe having a header including a count of additional physical addresses storing compressed data of the virtual page and the additional physical addresses.

2. The memory device of claim 1, wherein the additional physical addresses are physical addresses of additional stripes of the compressed data for the virtual page.

3. The memory device of claim 2, wherein the additional stripe of data for the virtual page has a format without a header.

4. The memory device of claim 1, wherein the format includes a block of user data and an error correction code following the count of additional physical addresses.

5. The memory device of claim 1, wherein the header has a predefined format that depends on a size of the first stripe.

6. The memory device of claim 1, wherein the memory device includes a free space manager to make physical addresses available to write data from a host to a memory subsystem of the memory.

7. The memory device of claim 1, wherein the memory device is a Compute Express Link (CXL) 3 type memory device.

8. A method comprising: accessing an indirection table based on a virtual address received in a read request from a host device; reading a first stripe of compressed data from physical memory at a physical address listed in the indirection table corresponding to the virtual address, the first stripe of compressed data comprising a header and the compressed data; decompressing the compressed data of the first stripe to generate decompressed data of the first stripe; and The decompressed data of the first stripe is sent to the host.

9. The method according to claim 8, wherein the method comprises: reading a next strip of compressed data at a physical address retrieved from the header of the first strip of compressed data; decompressing the compressed data of the next strip, thereby generating decompressed data of the next strip; and The decompressed data of the next stripe is sent to the host along with the decompressed data of the first stripe.

10. The method of claim 8, wherein the method comprises, after decompressing the first stripe of compressed data, successively reading stripes of compressed data having physical addresses in the header of the first stripe.

11. The method of claim 10, wherein the method comprises: decompressing the compressed data of the stripe having the physical address in the header of the first stripe; and copying the decompressed data of the stripe having the physical address in the header of the first stripe to a cache together with the decompressed data of the first stripe.

12. The method of claim 11, wherein the read request is a series of read requests and the decompressed data of the stripe having the physical address in the header of the first stripe is copied to a read buffer along with the decompressed data from the first stripe for the series of read requests.

13. The method of claim 8, wherein the method comprises obtaining the header of the first stripe for decomposition after decompressing the first stripe.

14. The method of claim 8, wherein accessing the indirection table comprises loading the indirection table when the indirection table is not cached.

15. A method comprising: accessing an indirection table based on a virtual address received in a write request from a host device; compressing data of a user page size corresponding to the write request; obtaining a physical address of a physical memory from a free space manager based on a size of the compressed data corresponding to the write request; updating the indirection table with a first one of the physical addresses; generating a header including the physical addresses other than the first physical address and a count of the physical addresses other than the first physical address; formatting the compressed data to include the header; and The formatted compressed data with the header is written to the physical memory at the first physical address.

16. The method of claim 15, wherein the method includes writing remaining compressed data corresponding to the write request to the physical memory at the physical addresses other than the first physical address.

17. The method of claim 15, wherein accessing the indirection table comprises loading the indirection table for processing.

18. The method of claim 15, wherein accessing the indirection table comprises accessing the indirection table in a cache, the indirection table comprising a first physical address corresponding to the virtual address.

19. The method of claim 15, wherein the method comprises the free space manager freeing up physical addresses for write operations by: obtaining a physical address corresponding to the virtual address from the indirection table, the indirection table having a flag identifying that the stripe of data at the physical address is compressed data; reading a header from the stripe corresponding to the physical address; and The physical address and additional physical addresses listed in the header are released for use.

20. The method of claim 15, wherein the user page size is 4 KB.

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