Pseudo-random sequence generation circuit and address sampling circuit

Abstract

The embodiment of the invention provides a pseudo-random sequence generation circuit and an address sampling circuit, and the circuit comprises an initial sequence generation circuit which is used for generating an initial pseudo-random sequence; the clock generation circuit is used for generating a target clock signal, and pulse widths of different pulses in the target clock signal are different; the target sequence generation circuit is used for receiving the initial pseudo-random sequence and a target clock signal, sampling the initial pseudo-random sequence according to the target clock signal, and generating a target pseudo-random sequence; wherein the initial pseudo-random sequence comprises N bits of initial data, the target pseudo-random sequence comprises N bits of target data, and N is an integer greater than 1. According to the embodiment of the invention, the degree of randomness of the pseudo-random sequence can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a pseudo-random sequence generating circuit and an address sampling circuit. Background Art

[0002] Linear Feedback Shift Register (LFSR) is a common device for generating sequences. Applications of LFSR include generating pseudo-random numbers, pseudo-random noise sequences, fast digital counters, etc. Because the operation of LFSR is deterministic, the value of the pseudo-random sequence output by LFSR is a repeated cycle. The next sequence can be easily inferred from the previous known sequence, resulting in insufficient randomness of the sequence. Summary of the invention

[0003] In a first aspect, an embodiment of the present disclosure provides a pseudo-random sequence generating circuit, comprising an initial sequence generating circuit, a clock generating circuit and a target sequence generating circuit, wherein the initial sequence generating circuit and the clock generating circuit are both connected to the target sequence generating circuit; wherein:

[0004] The initial sequence generating circuit is used to generate an initial pseudo-random sequence;

[0005] The clock generating circuit is used to generate a target clock signal, and the pulse widths of different pulses in the target clock signal are different;

[0006] The target sequence generating circuit is used to receive the initial pseudo-random sequence and the target clock signal, and perform sampling processing on the initial pseudo-random sequence according to the target clock signal to generate a target pseudo-random sequence;

[0007] The initial pseudo-random sequence includes N bits of initial data, the target pseudo-random sequence includes N bits of target data, and N is an integer greater than 1.

[0008] In some embodiments, the clock generation circuit includes an initial clock generation circuit, a sequence cycle circuit and a clock selection circuit; wherein:

[0009] The initial clock generating circuit is used to receive a preset clock signal and at least one bit of initial data among the N bits of initial data, and to perform logic processing according to the preset clock signal and the at least one bit of initial data to generate an initial clock signal; wherein the pulse widths of different pulses in the preset clock signal are the same, and the pulse widths of different pulses in the initial clock signal are different;

[0010] The sequence cycle circuit is used to perform logic processing according to the initial pseudo-random sequence to generate a periodic cycle signal; wherein, when the level state of each initial data in the initial pseudo-random sequence is a preset level state, the level state of the periodic cycle signal is flipped;

[0011] The clock selection circuit is used to receive the initial clock signal and the periodic cycle signal, perform logic processing according to the initial clock signal and the periodic cycle signal, and generate the target clock signal; wherein, when the periodic cycle signal is in a first level state, the level state of the target clock signal is the same as that of the initial clock signal, and when the periodic cycle signal is in a second level state, the level state of the target clock signal is opposite to that of the initial clock signal.

[0012] In some embodiments, the initial clock generation circuit includes a clock generation subcircuit and a pulse adjustment circuit, the clock generation subcircuit and the pulse adjustment circuit are connected, and the at least one bit of initial data includes first initial data and second initial data, wherein:

[0013] The clock generation subcircuit is used to receive the preset clock signal, perform delay processing on the preset clock signal to generate a delayed clock signal; perform a logical AND-NOT processing on the preset clock signal and the delayed clock signal to generate a preset square wave signal;

[0014] The pulse adjustment circuit is used to receive the preset square wave signal, the first initial data and the second initial data, perform delay processing on the preset square wave signal to generate a delayed square wave signal; and perform AND logic processing on the first initial data and the preset square wave signal to generate a first clock signal, and perform AND logic processing on the second initial data and the delayed square wave signal to generate a second clock signal; and perform OR logic processing on the first clock signal and the second clock signal to generate the initial clock signal.

[0015] In some embodiments, the sequence cycle circuit includes a flag signal generating circuit and a flip control circuit, wherein:

[0016] The flag signal generating circuit is used to generate a flip flag signal according to the initial pseudo-random sequence; wherein, when the level state of each initial data in the initial pseudo-random sequence is the preset level state, the flip flag signal is in an enabled state;

[0017] The flip control circuit is used to receive the flip flag signal and generate the periodic cycle signal according to the flip flag signal; wherein, when the flip flag signal is in an enabled state, the level state of the periodic cycle signal is flipped.

[0018] In some embodiments, the flag signal generating circuit includes a sequence processing circuit, a second OR gate, a third delay unit, and a second NAND gate, wherein:

[0019] The sequence processing circuit is used to generate at least one logic signal according to the initial pseudo-random sequence; wherein, when the level state of each initial data in the initial pseudo-random sequence is the preset level state, the level state of the at least one logic signal is the second level state;

[0020] The second OR gate is connected to the sequence processing circuit, and the input end of the second OR gate is used to receive the at least one logic signal; the output end of the second OR gate is respectively connected to the input end of the third delay unit and the second input end of the second NAND gate; the output end of the third delay unit is connected to the first input end of the second NAND gate; the output end of the second NAND gate is used to output the flip flag signal.

[0021] In some embodiments, the flip control circuit includes a master-slave JK flip-flop, wherein:

[0022] The clock end of the master-slave JK trigger is used to receive the flip flag signal, the J end of the master-slave JK trigger is used to receive the set signal, the K end of the master-slave JK trigger is used to receive the reset signal, and the output end of the master-slave JK trigger is used to output the periodic cycle signal.

[0023] In some embodiments, the target sequence generation circuit comprises a latch circuit, wherein:

[0024] The latch circuit is used to receive the initial pseudo-random sequence and the target clock signal, and to perform sampling processing on the initial pseudo-random sequence according to the target clock signal or an inverted signal of the target clock signal to generate the target pseudo-random sequence.

[0025] In some embodiments, the target sequence generation circuit includes a latch circuit and a first sampling circuit, and the first sampling circuit is connected to the latch circuit; wherein:

[0026] The latch circuit is used to receive the initial pseudo-random sequence and the target clock signal, and perform sampling processing on the initial pseudo-random sequence according to the target clock signal or the inverted signal of the target clock signal to generate a first target pseudo-random sequence;

[0027] The first sampling circuit is used to receive a preset clock signal and the first target pseudo-random sequence, and to perform sampling processing on the first target pseudo-random sequence according to the preset clock signal or an inverted signal of the preset clock signal to generate the target pseudo-random sequence.

[0028] In some embodiments, the initial sequence generating circuit comprises an N-stage linear feedback shift register; wherein, at each preset cycle interval, the level state of each initial data in the initial pseudo-random sequence output by the N-stage linear feedback shift register is a preset level state.

[0029] In a second aspect, an embodiment of the present disclosure provides an address sampling circuit, comprising a pseudo-random sequence generating circuit, a counting circuit, a comparison circuit, and a second sampling circuit as described in any one of the first aspects, wherein:

[0030] The pseudo-random sequence generating circuit is used to generate the target pseudo-random sequence;

[0031] The counting circuit is used to count the command signal and generate a counting sequence signal;

[0032] The comparison circuit is used to compare the counting sequence signal with the target pseudo-random sequence to generate a comparison signal;

[0033] The second sampling circuit is used to sample the address signal according to the comparison signal to generate a target address signal.

[0034] The disclosed embodiment provides a pseudo-random sequence generating circuit and an address sampling circuit, wherein the pseudo-random sequence generating circuit includes: an initial sequence generating circuit for generating an initial pseudo-random sequence; a clock generating circuit for generating a target clock signal, wherein the pulse widths of different pulses in the target clock signal are different; a target sequence generating circuit for receiving the initial pseudo-random sequence and the target clock signal, sampling and processing the initial pseudo-random sequence according to the target clock signal, and generating a target pseudo-random sequence; wherein the initial pseudo-random sequence includes N bits of initial data, and the target pseudo-random sequence includes N bits of target data, and N is an integer greater than 1. In this way, the initial pseudo-random sequence is sampled using a target clock signal with different pulse widths, disrupting the regularity of the sequence, and obtaining a target pseudo-random sequence with a higher degree of randomness. Furthermore, since the randomness of the pseudo-random sequence is improved, it cannot be easily predicted by the previous sequence. When applied to circuits such as circuits for preventing hammering, noise generators, etc., certain required sequences can be generated multiple times within a cycle, thereby also realizing a scheme with more probability sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of a six-stage LFSR provided in an embodiment of the present disclosure;

[0036] Figure 2 A schematic diagram of the structure of a pseudo-random sequence generating circuit provided in an embodiment of the present disclosure;

[0037] Figure 3 A timing diagram of a target clock signal provided by an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram of the structure of a clock generation circuit provided by an embodiment of the present disclosure;

[0039] Figure 5 A detailed structural diagram of a clock generation circuit provided in an embodiment of the present disclosure;

[0040] Figure 6 A signal timing diagram provided for an embodiment of the present disclosure Figure 1 ;

[0041] Figure 7 A signal timing diagram provided for an embodiment of the present disclosure Figure 2 ;

[0042] Figure 8 A detailed structural diagram of a master-slave JK flip-flop provided in an embodiment of the present disclosure;

[0043] Fig. 9 A signal timing diagram provided for an embodiment of the present disclosure Figure 3 ;

[0044] Fig.10 A signal timing diagram provided for an embodiment of the present disclosure Figure 4 ;

[0045] Fig.11 A signal timing diagram provided for an embodiment of the present disclosure Figure 5 ;

[0046] Fig.12 A schematic diagram of the structure of a target sequence generation circuit provided in an embodiment of the present disclosure Figure 1 ;

[0047] Fig.13 A schematic diagram of the structure of a target sequence generation circuit provided in an embodiment of the present disclosure Figure 2 ;

[0048] Fig.14 A signal timing diagram provided for an embodiment of the present disclosure Figure 7 ;

[0049] Fig.15 A schematic diagram of the structure of an address sampling circuit provided in an embodiment of the present disclosure;

[0050] Fig.16 A schematic diagram of the values ​​of an initial pseudo-random sequence and a target pseudo-random sequence provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0053] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0054] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0055] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0056] Linear Feedback Shift Register (LFSR);

[0057] D flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF);

[0058] Flip-Flop (FF);

[0059] Row Hammer;

[0060] Row Hammer Refresh (RHR);

[0061] Latch;

[0062] Activate (Active, ACT);

[0063] Row Address (RA).

[0064] See also Figure 1 , which shows a schematic diagram of the composition structure of a six-stage LFSR provided by an embodiment of the present disclosure. Figure 1 As shown, it includes 6 DFFs (DFF0 to DFF5), a NOT gate inv1, and an XOR gate xor. In each DFF, D is the input terminal, Ck is the clock terminal (Ck also represents the clock signal), CkN is the inverted clock terminal, SN is the set terminal, RN is the reset terminal, and Q is the output terminal. Each device has the following Figure 1 The connection relationship shown. The set terminal of DFFi (i=0,1,2,3,4,5) receives the set signal SN , the reset terminal receives the reset signal RN , the clock end receives the clock signal Ck, the inverted clock end receives the inverted clock signal CkN, and the output end outputs Q The input of DFF1 receives the signal output by xor, and the input of DFF2 to DFF5 receives the signal output by the previous DFF. The Q outputs of the six DFFs are <0> ~Q <5> (combined and recorded as Q<5:0>) form a pseudo-random sequence.

[0065] It should be noted that LFSR is used to generate pseudo-random numbers in digital circuits. N-level LFSR can generate at most 2 N -1 pseudo-random sequence, xor as feedback circuit. For example, the initial value is: Q <0> =1,Q <1> ~Q <5> are all 0, and each DFF uses the rising edge of the clock signal Ck to sample the signal received at the input terminal D to obtain the corresponding Q , then at the first rising edge of Ck, the output signal of each DFF (denoted as Q' ) is: Q' <0> =Q <5> ^Q <0> =1(Q <5> and Q <0> Do XOR operation); Q' <1> =Q <0> =1;Q' <2> =Q <1> =0;Q' <3> =Q <2> =0;Q' <4> =Q <3> =0;Q' <5> =Q <4> =0.

[0066] according to Figure 1 The circuit shown in the figure takes the initial value of Q<5:0> as 000001 as an example. The pseudo-random sequence generated by the LPSR is traceable and is repeated every 2 seconds. N -1 times, the sequence will return to the initial value and cycle again. This will result in the pseudo-random sequence being not random enough, and the subsequent sequence can be easily inferred based on the previous sequence.

[0067] One application of LFSR is to use LFSR to implement probabilistic sampling in the circuit to defend against row hammering. When the cumulative number of activations is the same as the value corresponding to the pseudo-random sequence, the row address is sampled once. However, based on this LFSR, it can only be sampled once every 4, 8, 16, 32, 64... times on average, and it is impossible to achieve an average of 10 times or more options; in addition, since the next sequence can be easily inferred from the previous known sequence, sampling can be bypassed, which increases the failure rate of row hammering protection.

[0068] Another application of LFSR is noise generator. When measuring the performance of communication system, it is often necessary to use noise generator, which can generate noise with required statistical and frequency characteristics, and its intensity can be controlled at will, so as to obtain system performance under different signal-to-noise ratio conditions. However, due to the overall regularity of pseudo-random sequence, it may cause loopholes in system testing. When N is large, due to the long distance between adjacent cycles and each address is only generated once in a cycle, it is sometimes impossible to obtain address information that needs to be measured multiple times from the pseudo-random sequence.

[0069] LFSR can also be applied to more circuits, but due to insufficient randomness, it may have adverse effects.

[0070] Based on this, the embodiment of the present disclosure provides a pseudo-random sequence generation circuit, which uses a target clock signal with different pulse widths to sample an initial pseudo-random sequence, disrupts the regularity of the sequence, and obtains a target pseudo-random sequence with a higher degree of randomness. Furthermore, since the randomness of the pseudo-random sequence is improved, it cannot be easily predicted by the previous sequence. When applied to circuits such as hammer protection circuits and noise generators, some required sequences can be generated multiple times within a cycle, thereby also realizing a scheme with more probability sampling.

[0071] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0072] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a pseudo-random sequence generating circuit provided by an embodiment of the present disclosure. Figure 2 As shown, the pseudo-random sequence generating circuit 20 includes an initial sequence generating circuit 21, a clock generating circuit 22 and a target sequence generating circuit 23, and the initial sequence generating circuit 21 and the clock generating circuit 22 are both connected to the target sequence generating circuit 23; wherein:

[0073] An initial sequence generating circuit 21, used for generating an initial pseudo-random sequence;

[0074] A clock generating circuit 22, used for generating a target clock signal, wherein different pulses in the target clock signal have different pulse widths;

[0075] The target sequence generating circuit 23 is used to receive the initial pseudo-random sequence and the target clock signal, sample the initial pseudo-random sequence according to the target clock signal, and generate the target pseudo-random sequence;

[0076] The initial pseudo-random sequence includes N bits of initial data, the target pseudo-random sequence includes N bits of target data, and N is an integer greater than 1.

[0077] It should be noted that the initial sequence generating circuit 21 may be as follows: Figure 1 The LPSR shown in FIG. 1 is used to generate N bits of initial data to form an initial pseudo-random sequence. Figure 1 In the example shown, N=6, and the initial pseudo-random sequence includes 6 bits of initial data.

[0078] The clock generation circuit 22 is used to generate target clock signals with different pulse widths. Figure 3 , which shows a timing diagram of a target clock signal provided by an embodiment of the present disclosure, such as Figure 3 As shown, taking the sampling process of the initial pseudo-random sequence during the high level (logic 1) pulse of the target clock signal as an example, Figure 3 Six high-level pulses are shown, and the pulse widths (or pulse times, pulse durations) of the six high-level pulses are t1 to t6, respectively, and the six pulse widths are different.

[0079] It should also be noted that, in the target clock signal, two or more pulses are allowed to have the same width, but for the target clock signal as a whole, all pulse widths cannot be the same.

[0080] In this way, the initial pseudo-random sequence is sampled using pulses of the target clock signal with different pulse widths (high-level pulses or low-level pulses, taking the high-level pulse as an example in this embodiment) to obtain a target pseudo-random sequence, thereby disrupting the order of the initial pseudo-random sequence that has a traceable sequence, making the randomness of the target pseudo-random sequence greater than the randomness of the initial pseudo-random sequence, thereby improving the randomness of the sequence.

[0081] In the following, taking N=6 as an example, the specific circuit implementation of the pseudo-random sequence generating circuit 20 is described in detail.

[0082] For the initial sequence generating circuit 21, its structure can refer to Figure 1 , the initial sequence generation circuit 21 includes N-stage linear feedback shift registers. Figure 1 As shown, the initial sequence generating circuit 21 may also include a set-reset circuit. Here, the invertor inv2, the NAND gate na1, and the NAND gate na2 are connected in the manner shown in the figure to form a set-reset subcircuit, and the set-reset circuit includes N such set-reset subcircuits, which respectively provide a set signal SN for each DFF in the LFSR. and reset signal RN Among them, the NAND gate na1 receives the initial reset signal RST and the set reset control signal Init The inverted signal and output reset signal RN , and the NAND gate na2 receives the initial reset signal RST and the set reset control signal Init , and output the set signal SN , thereby controlling each DFF to set and reset according to actual needs, where i = 0, 1, 2, 3, 4, 5. For the specific control of setting and resetting, reference can be made to the control of setting and resetting in the related art, which will not be described in detail here.

[0083] It can be understood that the initial pseudo-random sequence generated by the LFSR is traceable, and the cycle period of the initial pseudo-random sequence is recorded as the preset cycle period. N The level state of the initial data corresponding to any one of the -1 initial pseudo-random sequences is recorded as the preset level state, then at each preset cycle interval, the level state of each initial data in the initial pseudo-random sequence output by the N-stage linear feedback shift register is the preset level state.

[0084] In this way, the initial pseudo-random sequence Q<5:0> is generated by using LFSR, and the value of the initial pseudo-random sequence Q<5:0> (i.e., the level state of each initial data) can be easily inferred. In order to improve the randomness of the sequence, the embodiment of the present disclosure uses the clock generation circuit 22 to generate a target clock signal with different pulse widths to sample the initial pseudo-random sequence, disrupt the order of the initial pseudo-random sequence, and increase the randomness of the sequence.

[0085] For the clock generation circuit 22, see Figure 4 , which shows a schematic diagram of the composition structure of a clock generation circuit provided by an embodiment of the present disclosure, such as Figure 4 As shown, in some embodiments, the clock generation circuit 22 includes an initial clock generation circuit 221, a sequence cycle circuit 222 and a clock selection circuit 223; wherein:

[0086] The initial clock generating circuit 221 is used to receive a preset clock signal and at least one bit of initial data among the N bits of initial data, and to perform logic processing according to the preset clock signal and the at least one bit of initial data to generate an initial clock signal; wherein the pulse widths of different pulses in the preset clock signal are the same, and the pulse widths of different pulses in the initial clock signal are different;

[0087] The sequence circulation circuit 222 is used to perform logic processing according to the initial pseudo-random sequence to generate a periodic cycle signal; wherein, when the level state of each initial data in the initial pseudo-random sequence is a preset level state, the level state of the periodic cycle signal is flipped;

[0088] The clock selection circuit 223 is used to receive the initial clock signal and the periodic cycle signal, perform logic processing according to the initial clock signal and the periodic cycle signal, and generate a target clock signal; wherein, when the periodic cycle signal is in a first level state, the level state of the target clock signal is the same as the initial clock signal, and when the periodic cycle signal is in a second level state, the level state of the target clock signal is opposite to the initial clock signal.

[0089] It should be noted that in the embodiment of the present disclosure, the first level state represents a high level of logic 1 and the second level state represents a low level of logic 0 as an example, but the second level state may also represent a high level of logic 1 and the first level state represents a low level of logic 0, and there is no specific limitation on this.

[0090] like Figure 4 As shown, the signal received by the initial clock generation circuit 221 includes a preset clock signal and several bits of initial data in the initial pseudo-random sequence (such as initial data a, initial data m and other initial data). Among them, the preset clock signal is a regular clock signal with the same pulse width, such as a system clock or an external clock, and the several bits of initial data can be any one, two or more of the N bits of initial data. It can be understood that the level value (or level state) of each bit of initial data varies between 1 and 0, with continuous 1 or continuous 0 as a pulse. Obviously, the pulse width of each initial data is different. At least one initial data with different pulse widths is logically processed with a preset clock signal with the same pulse width using devices such as logic gates, disrupting the pulse equality state of the preset clock signal, and obtaining initial clock signals with different pulse widths.

[0091] The sequence circulation circuit 222 receives the N-bit initial data contained in the initial pseudo-random sequence. It can be understood that the initial pseudo-random sequence has 2 N- 1 value (i.e. 2 N- 1 different level state combination), each interval 2 N- 1 value, the initial pseudo-random sequence value is repeated. Here, you can set 2 N- Any of the 1 values ​​is used as the preset level state. For example, when N=6, Q<5:0>=000011 is set as the preset level state of the 6-bit initial data in the initial pseudo-random sequence. When the initial pseudo-random sequence is 000011, it indicates that the initial pseudo-random sequence has entered the next cycle. Whenever the level state of each initial data of the initial pseudo-random sequence meets the preset level state, the level state (level value) of the periodic cycle signal is flipped once. For example, if the level value of the periodic cycle signal is originally 1, it is flipped to 0, and if it is originally 0, it is flipped to 1.

[0092] Here, the effect of the periodic cycle signal is to make the period of the target clock signal twice that of the initial clock signal. Specifically, the clock selection circuit 223 is connected to the output end of the initial clock generation circuit 221 and the output end of the sequence cycle circuit 222, respectively, and receives the initial clock signal and the periodic cycle signal. The clock selection circuit 223 will invert the initial clock signal to obtain an inverted clock signal. According to the level state of the periodic cycle signal, one of the initial clock signal and the inverted clock signal is output as the target clock signal. When the periodic cycle signal is 1, the target clock signal is the same as the level state of the initial clock signal. After the initial pseudo-random sequence completes a cycle, the periodic cycle sequence number is 0, and the target clock signal is an inverted clock signal (i.e., the level state is opposite to the initial clock signal). It can be understood that in the initial clock generation circuit 221, since at least one initial data received by it will also be repeated after the initial pseudo-random sequence is circulated once, the period of the initial clock signal is the preset cycle period of the initial pseudo-random sequence. Further in the clock selection circuit 223, the clock selection circuit 223 will output the initial clock signal and the inverted clock signal as the target clock signal in two cycles of the initial pseudo-random sequence, respectively. Therefore, the period of the target clock signal is twice that of the initial clock signal, that is, twice the cycle period of the initial pseudo-random sequence.

[0093] In this way, the pulse width of the target clock signal is different, so sampling the initial pseudo-random sequence according to the target clock signal can disrupt the regularity of the initial pseudo-random sequence and increase the randomness; in addition, the period of the target clock signal is twice the period of the initial clock signal, which also ensures that within the period of twice the initial pseudo-random sequence, the time of 1 and 0 each accounts for half, and when random sampling of addresses is performed based on this, it is guaranteed that all addresses are traversed.

[0094] exist Figure 4 Based on Figure 5 , which shows a detailed structural diagram of a clock generation circuit provided by an embodiment of the present disclosure. Figure 5 As shown, in some embodiments, the initial clock generation circuit 221 includes a clock generation subcircuit S1 and a pulse adjustment circuit S2, the clock generation subcircuit S1 and the pulse adjustment circuit S2 are connected, and at least one initial data includes a first initial data Q <5> and the second initial data Q <4> ,in:

[0095] The clock generation subcircuit S1 is used to receive a preset clock signal Ck, perform delay processing on the preset clock signal Ck, and generate a delayed clock signal Ckdly; perform a logical AND-NOT processing on the preset clock signal Ck and the delayed clock signal Ckdly, and generate a preset square wave signal squ;

[0096] The pulse adjustment circuit S2 is used to receive the preset square wave signal squ, the first initial data Q <5> and the second initial data Q <4> , delay processing is performed on the preset square wave signal squ to generate a delayed square wave signal squdly; and the first initial data Q <5> The preset square wave signal squ is processed by AND logic to generate the first clock signal clk1, and the second initial data Q <4> The delayed square wave signal squdly is processed by AND logic to generate the second clock signal clk2; and the first clock signal clk1 and the second clock signal clk2 are processed by OR logic to generate the initial clock signal rand.

[0097] It should be noted that in Figure 5 In the example, at least one bit of initial data received by the initial clock generation circuit 221 is Q in Q<5:0>. <5> (first initial data) and Q <4> (second initial data) as an example.

[0098] Specifically, the clock generation sub-circuit S1 and the pulse adjustment circuit S2 can be composed of Figure 5 The logic gates shown are implemented as Figure 5 As shown, the clock generation sub-circuit S1 includes a first delay unit DLY1 and a first NAND gate NAND1, wherein:

[0099] The input end of the first delay unit DLY1 and the second input end of the first NAND gate NAND1 are connected as the input end of the clock generation sub-circuit S1, and the input end of the first delay unit DLY1 and the second input end of the first NAND gate NAND2 are both used to receive the preset clock signal Ck;

[0100] The output end of the first delay unit DLY1 is connected to the first input end of the first NAND gate NAND1, and the output end of the first delay unit NAND1 is used to output the delayed clock signal Ckdly;

[0101] The first input end of the first NAND gate NAND1 is used to receive the delayed clock signal Ckdly, and the output end of the first NAND gate NAND1 serves as the output end of the clock generating sub-circuit S1, and is used to output a preset square wave signal squ.

[0102] The pulse adjustment circuit S2 includes a second delay unit DLY2, a first AND gate AND1, a second AND gate AND2 and a first OR gate OR1, wherein:

[0103] The first input end of the first AND gate AND1 is connected to the input end of the second delay unit DLY2. The first input end of the first AND gate AND1 and the input end of the second delay unit DLY2 are both used to receive the preset square wave signal squ; the second input end of the first AND gate AND1 is used to receive the first initial data Q <5> The output end of the first AND gate AND1 is connected to the first input end of the first OR gate OR1, and the output end of the first AND gate AND1 is used to output the first clock signal clk1;

[0104] The output end of the second delay unit DLY2 is connected to the second input end of the second AND gate AND2, and the output end of the second delay unit DLY2 is used to output a delayed square wave signal squdly;

[0105] The first input terminal of the second AND gate AND2 is used to receive the second initial data Q <4> The second input terminal of the second AND gate AND2 is used to receive the delayed square wave signal squdly; the input terminal of the second AND gate AND2 is connected to the second input terminal of the first OR gate OR1, and the output terminal of the second AND gate AND2 is used to output the second clock signal clk2;

[0106] The first input end of the first OR gate OR1 is used to receive the first clock signal clk1; the second input end of the first OR gate OR1 is used to receive the second clock signal clk2; the output end of the first OR gate OR1 serves as the output end of the pulse adjustment circuit S2, and is used to output the initial clock signal rand.

[0107] It should be noted that the first delay unit DLY1 and the second delay unit DLY2 may include an even number of NOT gates connected in series to achieve delay processing of the signals input therein, and the specific number of NOT gates may be determined in combination with the actual required delay time. Alternatively, the first delay unit DLY1 and the second delay unit DLY2 may also be other devices with delay functions, such as triggers, etc., which are not specifically limited here.

[0108] It should also be noted that if Figure 5 As shown, the first AND gate AND1 and the second AND gate AND2 are both composed of a NAND gate and a NOT gate in series, and the first OR gate OR is composed of a NOR gate and a NOT gate in series.

[0109] Figure 6 For the corresponding Figure 5 Schematic diagram of the timing of each signal in the initial clock generating circuit 221. Figure 5 and Figure 6 As shown, the clock generation subcircuit S1 performs a logical AND-NOT process on the preset clock signal Ck and the delayed clock signal Clkdly, thereby generating a preset square wave signal squ synchronized with the preset clock signal Ck. Then the pulse adjustment circuit S2 generates a pulse signal according to the preset square wave signal squ, the first initial data Q <5> , the second initial data Q <4> Perform logical processing to disrupt the regular arrangement of the preset square wave signal squ and generate an initial clock signal rand with unequal pulses.

[0110] It should also be noted that more AND gates may be added to perform AND logic processing on more initial data and signals after delays of different lengths on the preset square wave signal squ, and then perform OR logic processing with the first clock signal clk2 and the second clock signal clk2, so as to obtain an initial clock signal rand with unequal pulses. Alternatively, only one initial data may be received, for example, clk1 or clk2 may be used as the initial clock signal rand, which is not specifically limited here.

[0111] It should also be noted that Figure 5 The circuit shown is only an exemplary implementation. There are many ways to form a preset square wave signal squ synchronized with the preset clock signal Ck. For example, the first NAND gate NAND1 is changed into a NOR gate or an OR gate, or XOR, XOR, etc. logic can be used to finally obtain the initial clock signal rand with unequal pulses.

[0112] For the sequence loop circuit 222, if Figure 5 As shown, in some embodiments, the sequence cycle circuit 222 includes a flag signal generating circuit S3 and a flip control circuit S4, wherein:

[0113] The flag signal generating circuit S3 is used to generate a flip flag signal flag according to the initial pseudo-random sequence Q<5:0>; wherein each initial data Q in the initial pseudo-random sequence Q<5:0> When the level state is the preset level state, the flip flag signal flag is in the enabled state;

[0114] The flip control circuit S4 is used to receive the flip flag signal flag, and generate the periodic cycle signal cir according to the flip flag signal flag; wherein, when the flip flag signal flag is in an enabled state, the level state of the periodic cycle signal cir is flipped.

[0115] It should be noted that after the initial pseudo-random sequence Q<5:0> completes a cycle, the initial data Q in the initial pseudo-random sequence Q<5:0> The level state of (i=0, 1, ..., N-1) is the aforementioned preset level state. At this time, the flag signal generating circuit S3 will generate a flip flag signal flag in an enabled state, thereby causing the level state of the periodic cycle signal cir to flip once, thereby controlling the output of the clock selection circuit 223.

[0116] It should also be noted that, in this embodiment, a high level of logic 1 is used to represent an enabled state, and a low level of logic 0 is used to represent a disabled state. However, in other implementations, a low level of logic 0 may represent an enabled state, and a high level of logic 1 may represent a disabled state. There is no specific limitation on this.

[0117] That is to say, the function of the flag signal generating circuit S3 is to generate the flip flag signal flag according to the initial pseudo-random sequence Q<5:0>. Only when the initial pseudo-random sequence Q<5:0> is in the preset level state, the flip flag signal flag is in the enabled state to control the periodic cycle signal cir to undergo a level flip; when the initial pseudo-random sequence Q<5:0> is not in the preset level state, the flip flag signal flag is in the disabled state, and the periodic cycle signal cir will not undergo a level flip.

[0118] The flag signal generating circuit S3 can be composed of Figure 5 The logic gates shown are implemented as Figure 5 As shown, the flag signal generating circuit S3 includes a sequence processing circuit S31, a second OR gate OR2, a third delay unit DLY3 and a second NAND gate NAND2, wherein:

[0119] The sequence processing circuit S31 is used to generate at least one logic signal lg according to the initial pseudo-random sequence Q<5:0> <j>; Among them, in the initial pseudo-random sequence Q<5:0>, each initial data Q When the level state is the preset level state, at least one logic signal lg <j>The level states of are all in the second level state;

[0120] The second OR gate OR2 is connected to the sequence processing circuit S31, and the input end of the second OR gate OR2 is used to receive at least one logic signal lg <j>; The output end of the second OR gate OR2 is respectively connected to the input end of the third delay unit DLY3 and the second input end of the second NAND gate NAND2; the output end of the third delay unit DLY3 is connected to the first input end of the second NAND gate NAND2; the output end of the second NAND gate NAND2 serves as the output end of the flag signal generating circuit S3, which is used to output the flip flag signal flag.

[0121] like Figure 5 As shown, the second OR gate OR2 is composed of a NOR gate and a NOT gate in series.

[0122] It should be noted that the sequence processing circuit S31 can generate S logic signals according to the initial pseudo-random sequence Q<5:0>, S is an integer greater than 0, then j=1, 2...S, when the initial pseudo-random sequence Q<5:0> is in a preset level state, each logic signal lg <j>The level state of each logic signal lg is the second level state (taking logic 0 as an example), then the second OR gate OR2 <j>After processing, the signal output by the second OR gate OR2 is also 0, and then the signal output by the second OR gate OR2 is delayed by the third delay unit DLY3, and then the signal output by the second OR gate OR2 is logically processed by the second NAND gate NAND2, so that when the initial pseudo-random sequence Q<5:0> is in a preset level state, a flip flag signal flag in an enabled state (taking logic 1 as an example) can be output.

[0123] It should also be noted that the second OR gate OR2 can be replaced by a NOR gate, and the second NAND gate NAND2 can be replaced by an AND gate to achieve AND gate. Figure 5 The same functions as the circuit shown are not repeated here.

[0124] Specifically, Figure 5 As shown, the sequence processing circuit S31 includes a third NAND gate NAND3 and a fourth NAND gate NAND4, the third NAND gate NAND3 includes M input terminals, the fourth NAND gate NAND4 includes (NM) input terminals, M is less than N, wherein:

[0125] The input ends of the third NAND gate NAND3 and the fourth NAND gate NAND4 are used to receive N-bit initial data, or to receive a part of the N-bit initial data and an inverted signal of another part of the initial data;

[0126] The output end of the third NAND gate NAND3 is connected to the first input end of the second OR gate OR2, and the output end of the third NAND gate NAND3 is used to output the first logic signal lg <1> ;

[0127] The output end of the fourth NAND gate NAND4 is connected to the second input end of the second OR gate OR2, and the output end of the fourth NAND gate NAND4 is used to output the second logic signal lg <2> .

[0128] It should be noted that the sequence processing circuit S31 may be composed of a plurality of NAND gates, and the NAND gates receive the initial data or the inverted signal of the initial data, which is related to the preset level state. Figure 5 Taking the two NAND gates (the third NAND gate NAND3 and the fourth NAND gate NAND4) shown in the figure as an example, the preset level state is Q<5:0>=000011, then the three input terminals of the third NAND gate NAND3 receive the initial data Q <5> The inverted signal QN <5> , initial data Q <4> The inverted signal QN <4> , initial data Q <3> The inverted signal QN <3> The three input terminals of the fourth NAND gate NNAD4 receive the initial data Q <2> The inverted signal QN <2> , initial data Q <1> , initial data Q <0> .

[0129] For another example, taking the preset level state as Q<5:0>=111111 as an example, the third NAND gate NAND3 and the fourth NAND gate NAND3 can directly receive the initial data (as shown in FIG. Figure 5 As shown, each receives three, but one may receive two initial data and the other may receive four initial data, etc.).

[0130] In the case where the inverted signal of the initial data needs to be received, such as Figure 5 As shown, the sequence processing circuit may further include a sequence inversion circuit S32 for respectively converting each initial data Q The inversion process is the corresponding inverted signal QN Here, the sequence inversion circuit S32 may include N NOT gates, which perform inversion processing on each initial data respectively, and then send the inversion signal of the required initial data to the corresponding input end of the corresponding third NAND gate NAND3 or the fourth NAND gate NAND4. In addition, the sequence inversion circuit S32 may also be a part of the initial sequence generation circuit 21, which is not specifically limited here.

[0131] Figure 7 For the corresponding Figure 5 FIG. 1 is a schematic diagram showing the timing of each signal in the flag signal generating circuit S3. Figure 7 As shown, Q<5:0> represents the level value of the initial pseudo-random sequence at different times. Due to the length limitation of the attached figure, each initial data cannot be fully displayed. The initial data not shown is represented by *. net03 represents the signal output by the second OR gate OR2, net05 represents the signal output by the third delay unit DLY3, and flag represents the flip flag signal.

[0132] It should be noted that the generated initial pseudo-random sequence is cyclic, and the 6-stage LFSR can generate 2 6 -1 initial pseudo-random sequence with different level states, that is, it cycles once every 63 sequences, Figure 5 The function of the flag signal generating circuit S3 shown is to generate a pulse (flip the flag signal flag) when Q<5:0> is 000011, indicating that a cycle has been completed. Here, it is not limited to 000011, and any one of the 63 initial pseudo-random sequences can also be selected.

[0133] like Figure 7 As shown, each time the LFSR generates 000011, the net03 signal is 0, which means that another round of repeated polling starts from here, and the flip flag signal flag becomes 1. Figure 5 The flag signal generating circuit S2 in the circuit is a classic structure for generating pulses, generating one pulse per polling.

[0134] like Figure 5 As shown, the flip control circuit S4 can be implemented by a master-slave JK flip-flop, where:

[0135] The clock terminal CLK of the master-slave JK flip-flop is used to receive the flip flag signal flag, the J terminal of the master-slave JK flip-flop is used to receive the set signal J, the K terminal of the JK flip-flop is used to receive the reset signal K, and the output terminal Q of the master-slave JK flip-flop is used to output the periodic cycle signal cir. In addition, the inverting output terminal QN of the master-slave JK flip-flop is used to output the inverted signal cirN of the periodic cycle signal.

[0136] It should be noted that see Figure 8 , which shows a detailed structural diagram of a master-slave JK trigger provided by an embodiment of the present disclosure. Figure 8 As shown, the master-slave JK flip-flop is composed of a NAND gate NAND81, a NAND gate NAND82, a first latch LAC1, a NAND gate NAND83, a NAND gate NAND84, a second latch LAC2, and an invertor INV81. The first latch LAC1 specifically includes a NAND gate NAND85 and a NAND gate NAND86, and the second latch LAC2 specifically includes a NAND gate NAND87 and a NAND gate NAND88.

[0137] Among them, one input end of the NAND gate NAND81 serves as the J end of the master-slave JK trigger, for receiving the set signal J; one input end of the NAND gate NAND82 serves as the K end of the master-slave JK trigger, for receiving the set signal K; one input end of the NAND gate NAND81, one input end of the NAND gate NAND82 and the input end of the invertor INV81 are connected as the clock end of the master-slave JK trigger, for receiving the clock signal CLK, which can be the aforementioned preset clock signal Ck; the in-phase output end of the second latch LAC2 serves as the output end Q of the master-slave JK trigger, and the inverting output end of the second latch LAC2 serves as the inverting output end QN of the master-slave JK trigger. The connection method of each logic gate is as follows: Figure 8 shown.

[0138] Fig. 9 For the corresponding Figure 8 The timing diagram of each signal in the master-slave JK flip-flop. The operation rules of the master-slave JK flip-flop are shown in Table 1:

[0139] Table 1

[0140] J(set) K(reset) action Q <![CDATA[Q next ]]> 0 0 Keep X X 0 1 Reset X 0 1 0 Set X 1 1 1 Invert (inv) 1(0) 0(1)

[0141] Wherein, Q represents the signal output from the Q terminal when there is neither a set nor a reset, Qnext represents the signal output from the Q terminal after a set operation, a reset operation or other operations are performed, and X represents 0 or 1.

[0142] Combination Fig. 9 As shown in Table 1, the initial value of Q is X. When the set signal J and the reset signal K are both 0, it means that neither the set operation nor the reset operation is performed, and Qnext is consistent with Q and is also X; when the set signal J is 0 and the reset signal K is 1, the reset operation is performed and Qnext is reset to 0; when the set signal J is 1 and the reset signal K is 0, the set operation is performed and Qnext is set to 1; when the set signal J and the reset signal K are both 1, the inversion operation is performed, if Q is 1, Qnext is 0, and if Q is 0, Qnext is 1. At the same time, each operation can be triggered at the rising edge of the clock signal CLK.

[0143] It can be understood that in order to achieve a level flip in the periodic cycle signal cir when the flip flag signal flag is in the enabled state, both the set signal J and the reset signal K need to be 1 (enabled state), so that the master-slave JK trigger can flip the level state of the signal received by its clock terminal CLK and output it.

[0144] Fig.10 For the corresponding Figure 5 The timing diagram of the sequence cycle circuit 222 is shown in FIG. Fig.10 As shown, initially J=0, K=1, referring to the truth table shown in Table 1, the initial value of the periodic cycle signal cir is 0, and it can be seen that the periodic cycle signal cir is inverted once each time the LFSR cycles (that is, each time the flip flag signal flag starts a pulse). Alternatively, J=1 and K=0 can be given initially, so that the initial value of the periodic cycle signal cir is 1, and as long as J=1 and K=1 are continuously inverted in the subsequent operation, it can be done.

[0145] For the clock selection circuit 223, if Figure 5 As shown, the clock selection circuit 223 may include a third AND gate AND3, a fourth AND gate AND4, a first NOT gate NOT1, a second NOT gate NOT2, and a third OR gate OR3, wherein:

[0146] The first input terminal of the third AND gate AND3 and the input terminal of the first NOT gate NOT1 are connected as the first input terminal of the clock selection circuit 223 for receiving the periodic cycle signal cir; the output terminal of the first NOT gate NOT1 is connected to the first input terminal of the third OR gate OR3;

[0147] The second input end of the third AND gate AND3 and the input end of the second NOT gate NOT2 are connected as the second input end of the clock selection circuit 223 for receiving the initial clock signal rand; the output end of the second NOT gate NOT2 is connected to the second input end of the second OR gate OR3;

[0148] The output terminal of the third OR gate OR3 is used as the output terminal of the clock selection circuit 223 to output the target clock signal rand_com.

[0149] It should be noted that Figure 5 The circuit shown is only one circuit implementation of the clock selection circuit. Any logic gate combination can be used as long as it can realize that the target clock signal rand_com is the same as the initial clock signal rand when the periodic cycle signal cir is in the first level state, and that the target clock signal rand_com is opposite to the initial clock signal rand when the periodic cycle signal cir is in the second level state.

[0150] Fig.11 For the corresponding Figure 5 The timing diagram of the flip flag signal flag, the periodic cycle signal cir, the initial clock signal rand, and the target clock signal rand_com. It can be clearly seen that every time the flip flag signal flag starts a pulse (1), the level state of the periodic cycle cir will flip once (it can be understood that there will be a certain delay between the signals), thereby controlling the level state of the target clock signal rand_com to be the same as or opposite to the initial clock signal rand.

[0151] Specifically, Fig.11 As shown, in the t1 time period after the first pulse of the flip flag signal flag, the periodic cycle signal cir is 1, during which the target clock signal rand_com and the initial clock signal rand have the same level state; in the t2 time period after the second pulse of the flip flag signal flag, the periodic cycle signal cir is 0, during which the target clock signal rand_com and the initial clock signal rand have opposite level states.

[0152] It should be noted that the initial clock signal rand with unequal pulse width is not suitable for direct sampling, because it will make it impossible to traverse all 63 different initial pseudo-random sequences. In order to solve this problem, taking high-level sampling as an example, it is only necessary to invert the initial clock signal rand in the next cycle, so as to use the target clock signal rand_com to traverse all the initial pseudo-random sequences. The target clock signal rand_com and the initial clock signal rand alternately have the same logic and opposite logic in each LFSR cycle.

[0153] That is to say, in this embodiment, the design purpose of the flag signal generating circuit S3, the flip control circuit S4, and the clock selecting circuit 223 (also denoted as S5) is that the initial clock signal rand with unequal pulses generated previously is not suitable for direct use because it is based on Q <5> , Q <4> It is generated, so it also cycles once every 63 sequences. Therefore, the initial pseudo-random sequence that cannot be sampled in this cycle will never be sampled. Therefore, it needs to be inverted all the time to ensure that all different initial pseudo-random sequences are traversed. The inverted period is the preset cycle period of 63 sequences.

[0154] For the target sequence generating circuit 23, see Fig.12 , which shows a schematic diagram of the structure of a target sequence generation circuit provided by an embodiment of the present disclosure Figure 1 .like Fig.12 As shown, in a specific implementation, the target sequence generation circuit 23 includes a latch circuit 231, wherein:

[0155] The latch circuit 231 is used to receive the initial pseudo-random sequence Q<5:0> and the target clock signal rand_com, and to sample the initial pseudo-random sequence Q<5:0> according to the target clock signal rand_com or the inverted signal rand_comN of the target clock signal to generate a target pseudo-random sequence sample<5:0>.

[0156] It should be noted that when the initial pseudo-random sequence Q<5:0> is sampled, the initial pseudo-random sequence Q<5:0> may be sampled using the high level or low level of the target clock signal rand_com or the inverted signal rand_comN of the target clock signal, and this is not specifically limited.

[0157] like Fig.12 As shown, the latch circuit 231 may specifically include a third NOT gate NOT3 and a latch 2311, wherein the input end of the third NOT gate NOT3 and the clock end Lat of the latch 2311 are connected as the input end of the latch circuit 231 for receiving the target clock signal rand_com; the output end of the third NOT gate NOT3 is connected to the inverted clock end of the latch 2311, and the inverted signal rand_comN of the target clock signal is sent to the latch 2311, and the input end D of the latch 2311 receives the initial pseudo-random sequence Q<5:0>, and the initial pseudo-random sequence Q<5:0> is sampled using the target clock signal rand_com or the inverted signal rand_comN of the target clock signal, and the target pseudo-random sequence sample<5:0> is output from the output end Q.

[0158] It should also be noted that the latch circuit 231 may specifically include N latches 2311, and an input terminal D of each latch 2311 receives an initial data Q , for the initial data Q Perform sampling processing to obtain a target data sample , N target data samples Combined into the target pseudo-random sequence sample <n-1:0>, no specific limitation is given here.

[0159] In addition, the latch 2311 further includes a reset terminal RN for receiving a reset signal R. When the reset signal R is enabled, the signal output by the latch 2311 is reset.

[0160] In this way, by sampling the initial pseudo-random sequence using the target clock signal rand_com with different pulse widths, a target pseudo-random sequence with a higher degree of randomness can be obtained.

[0161] Furthermore, in order to achieve synchronous sampling with the initial pseudo-random sequence and improve the problem that the latch sampling interval will continue to jump with the output and input, Fig.12 Based on Fig.13 , which shows a schematic diagram of the structure of a target sequence generation circuit provided by an embodiment of the present disclosure Figure 2 .like Fig.13 As shown, in some embodiments, the target sequence generation circuit 23 includes a latch circuit 231 and a first sampling circuit 232, and the first sampling circuit 232 is connected to the latch circuit 231; wherein:

[0162] The latch circuit 231 is used to receive the initial pseudo-random sequence Q<5:0> and the target clock signal rand_com, and to sample the initial pseudo-random sequence Q<5:0> according to the target clock signal rand_com or the inverted signal rand_comN of the target clock signal to generate a first target pseudo-random sequence sample<5:0>;

[0163] The first sampling circuit 2321 is used to receive the preset clock signal Ck and the first target pseudo-random sequence sample<5:0>, and sample the first target pseudo-random sequence sample<5:0> according to the preset clock signal Ck or the inverted signal CkN of the preset clock signal to generate a target pseudo-random sequence sam<5:0>.

[0164] It should be noted that Fig.13 The latch circuit 231 in Fig.12 The latch circuit 231 shown is completely the same, except that the signal output by the latch circuit 231 is recorded as the first target pseudo-random sequence sample<5:0>, and its working method is not repeated here.

[0165] It should also be noted that when sampling the first target pseudo-random sequence sample<5:0>, the first target pseudo-random sequence sample<5:0> can be sampled using the level flip edge (such as the rising edge or the falling edge, the rising edge is taken as an example in this embodiment) of the preset clock signal Ck or the inverted signal CkN of the preset clock signal, and there is no specific limitation on this.

[0166] like Fig.13 As shown, the first sampling circuit 232 may specifically include a fourth NOT gate NOT4 and a trigger 2321 (FF), wherein the trigger 2321 may be a D trigger, etc., wherein the input end of the fourth NOT gate NOT4 and the clock end Ck of the trigger 2321 are connected as the input end of the first sampling circuit 232, for receiving the preset clock signal Ck; the output end of the fourth NOT gate NOT4 is connected to the inverted clock end CkN of the trigger 2321, and the inverted signal CkN of the preset clock signal is sent to the trigger 2321, the input end D of the trigger 2321 receives the first target pseudo-random sequence sample<5:0>, and the first target pseudo-random sequence sample<5:0> is sampled and processed using the preset clock signal Ck or the inverted signal CkN of the preset clock signal, and the target pseudo-random sequence sam<5:0> is output from its output end Q.

[0167] It should also be noted that the first sampling circuit 232 may specifically include N triggers 2321, and the input terminal D of each trigger 2321 is connected to the output terminal Q of the corresponding latch 2311 to receive a first data sample (the first target pseudo-random sequence includes N first data), for the first data sample Perform sampling processing to obtain a target data sam , N target data sam Combined into the target pseudo-random sequence sam <n-1:0>, no specific limitation is given here.

[0168] In this way, Fig.12 Based on Fig.13 The target sequence generating circuit 23 shown in the embodiment of the present disclosure further adds a trigger to sample sample<5:0>, thereby capturing one data each time Ck jumps and improving the randomness of the sequence.

[0169] Fig.14 For the corresponding Fig.12 or Fig.13 Timing diagram of Fig.14 As shown, only the first three lines are Fig.12 The corresponding timing diagram, looking at the overall 5 rows, is Fig.13 Corresponding timing diagram. It can be seen that the latch circuit 231 (also denoted as S6) is used to latch and sample the initial pseudo-random sequence Q<5:0> using the target clock signal rand_com to disrupt the order; what is shown here is a low-level latch, and swapping Lat and LatN will become a high-level latch without affecting the result; and in order to ensure that the final output target pseudo-random sequence sam<5:0> is synchronized with the preset clock signal Ck, a first sampling circuit 231 (also denoted as S7) is added, which includes a trigger triggered by the rising edge of the global clock Ck (i.e., the preset clock signal).

[0170] It should be noted that the embodiments of the present disclosure and subsequent embodiments involve multiple set signals and reset signals, wherein the multiple set signals can be the same signal, or a set signal can be allocated separately to each device. The same applies to the reset signal, which is specifically combined with the circuit setting and is not specifically limited here.

[0171] In short, the embodiments of the present disclosure provide a circuit and method capable of improving the randomness of a pseudo-random sequence, which is used to optimize the randomness of a pseudo-random sequence, and relates to a pseudo-random sequence. The method can be applied to a noise generator for measuring the performance of a communication system, a sampling circuit in an RHR, etc. by using an LFSR and a newly added circuit. Since the pseudo-random sequence generated by the LFSR is regular as a whole, the randomness can be improved by taking pseudo-random sequence data with unequal intervals to form a new sequence. The key point of this solution is to generate a target clock signal with unequal pulse widths.

[0172] Combination Figures 5 to 14 The specific implementation process is briefly described as follows:

[0173] In the clock generation subcircuit S1, a periodic pulse signal squ is generated by Ck, and its randomness is affected by the period of squ and the delay time of the first delay unit DLY1. Here, Ck and squ are not independent, which can reduce the deviation of rand.

[0174] In the pulse adjustment circuit S2, the combination of squ and the initial data in the initial pseudo-random sequence is used for logic processing to generate a signal rand with different pulse widths. rand is a square wave signal. rand is generated based on the initial pseudo-random sequence, so the cycle period of rand = Q<5:0> cycle period.

[0175] In the flag signal generating circuit S3, flag generates a pulse, which represents one cycle of the LFSR output.

[0176] In the flip control circuit S4, cir is generated by the master-slave JK flip-flop. When the LFSR output cycles once, cir is inverted once.

[0177] In the clock selection circuit 223 (S5), in order to make the extracted sequence traverse all addresses, rand_com is improved on the basis of rand: rand_com = cir·rand+cir! ·rand!, where cir! represents the inverted signal of cir, and rand! represents the inverted signal of rand. This formula represents Figure 5 The logic function of the clock selection circuit 223 is: cir and rand are operated with an AND logic operation, cir! and rand! are operated with an AND logic operation, and the operation results are operated with an OR logic operation, so as to ensure that within the preset cycle time of twice the initial pseudo-random sequence, the time of 1 and 0 in rand_com each accounts for half.

[0178] The latch circuit 231 (S6) uses rand_com to sample Q<5:0> to obtain sample<5:0>, which can traverse all (2 6 -1) sequences, so that when the LFSR levels are equal, the randomness of sample<5:0> is higher than that of Q<5:0>. Due to the improved randomness, the cycle period of Sample<5:0> is twice that of Q<5:0>.

[0179] Further optimization, in order to achieve synchronous sampling with the initial pseudo-random sequence and improve the problem that the latch sampling interval will constantly jump with the output and input, the first sampling circuit 232 (S7) uses Ck to sample sample<5:0> to obtain sam<5:0> as the final output signal. In this way, adding FF to sample sample<5:0> achieves the capture of one data each time Ck jumps and improves the randomness of the sequence.

[0180] In another embodiment of the present disclosure, see Fig.15 , which shows a schematic diagram of the composition structure of an address sampling circuit provided by an embodiment of the present disclosure. Fig.15 As shown, the address sampling circuit 30 includes:

[0181] A pseudo-random sequence generating circuit 301 is used to generate a target pseudo-random sequence;

[0182] The counting circuit 302 is used to count the command signal and generate a counting sequence signal;

[0183] A comparison circuit 303, used for comparing the counting sequence signal with the target pseudo-random sequence to generate a comparison signal;

[0184] The second sampling circuit 304 is used to sample the address signal according to the comparison signal to generate a target address signal.

[0185] It should be noted that the address sampling circuit 30 can be used as a circuit for preventing row hammering. In the circuit for preventing row hammering, LFSR is usually used to implement probability sampling. Using the average activation times sampling algorithm, such as Fig.15 As shown, when the pseudo-random sequence generating circuit 301 is LFSR, Figure 1 Taking the 6-level LFSR shown as an example, the initial value assigned to the LFSR is recorded as the seed. The seed is randomly assigned. The random seed is the first output sequence, which can be understood as which sequence to start the cycle from. For example, the first seed is 000001, then the 6-level LFSR will generate 63 different sequences at a time. After generating these 63 sequences, the seed will be updated once, and the next time it will no longer start the cycle from 000001.

[0186] For a 5-stage LFSR, the seed is updated after every 31 samples (after all the pseudo-random numbers represented by the 31 pseudo-random sequences generated by a seed are matched). For a 6-stage LFSR, the seed is updated after each seed is matched 63 times. Table 2 shows the relationship between the number of bits of the initial pseudo-random sequence generated by the LFSR (i.e., the number of LFSR stages) and the randomness of the sequence:

[0187] Table 2

[0188]

[0189] The random range is calculated using the following formula:

[0190] For example, if N=4, then

[0191] like Figure 1 As shown, when applied to row hammer protection, the command signal can be specifically an activation command (ACT), and the counting circuit 302 counts the ACT to generate a counting sequence signal, which is used to characterize the number of ACTs. The counting circuit 302 can be a counter, such as a synchronous counter or an asynchronous counter. The counting sequence signal is also an N-bit signal, including N-bit counting data. The comparison circuit 303 compares the counting sequence signal with the sequence generated by the pseudo-random sequence generation circuit 301. If the two are the same, a comparison signal in an enabled state is generated, and the comparison signal will generate a pulse. Among them, the comparison circuit 303 can be an XOR gate or an XOR gate.

[0192] The second sampling circuit 304 can be FF, such as DFF, whose clock terminal CK is connected to the comparison circuit 303 for receiving the comparison signal, and its input terminal D receives the address signal. It can be understood that the address signal corresponds to ACT. Specifically, the address signal is a row address signal, which can be recorded as ACT_RA. When the comparison signal is enabled, the first sampling circuit 304 samples the address signal to obtain the target address signal (RA).

[0193] like Fig.15 As shown, the counting circuit 302 also receives a reset signal. After each sampling, the reset signal is enabled to clear the output of the counting circuit to zero and restart counting from the beginning.

[0194] If the current sequence of the LFSR is 000001, and an ACT command arrives, the count value corresponding to the count sequence signal changes from 0 to 1, so that the match is successful, and the comparison signal starts a pulse for sampling of the first sampling circuit 304. Among them, the comparison signal also serves as the clock of the LFSR, and the LFSR is updated to the next sequence 000011. In addition, the comparison signal can also be used as a reset signal for the counting circuit 302. After each sampling, the counting circuit 302 starts counting again from 0, that is, the next sampling is the row address of the third activation. Then by analogy, for a 6-stage LFSR, an average of 63 samples can be sampled for every 2016 activation commands in one cycle (refer to Table 2).

[0195] It can be seen that when LFSR is used as a pseudo-random sequence generation circuit, there are the following defects: it can only average 4, 8, 16, 32, 64... samples, and cannot achieve an average of 10 times or more selections; Figure 1 As can be seen from the relevant description, the next sequence can be easily inferred from the previous known sequence, so that sampling can be bypassed, which increases the failure rate of the row hammer circuit protection.

[0196] In the disclosed embodiment, the pseudo-random sequence generating circuit 301 is not an LFSR, but the pseudo-random sequence generating circuit 20 in the aforementioned embodiment. According to the aforementioned pseudo-random sequence generating circuit 20, simulation is performed. From the previous description and simulation results, it can be known that the target pseudo-random sequence output by the pseudo-random sequence generating circuit 20 also has a cycle period, and its cycle period is twice the cycle period of the initial pseudo-random sequence output by the initial LFSR. The sequence within a cycle period is intercepted for statistics, and the specific values ​​of the pseudo-random sequence Q<5:0> and the target pseudo-random sequence sam<5:0> are as follows: Fig.16 As shown, statistics and analysis are performed on a cycle of the target pseudo-random sequence sam<5:0>, and the statistical results are shown in Table 3:

[0197] Table 3

[0198]

[0199] Among them, √ represents that the corresponding value of sam<5:0> appears in a cycle, and the number behind it represents the number of times it appears. It can be seen that for the pseudo-random sequence generation circuit 20, the optimized target pseudo-random sequence sam<5:0> has a higher randomness in the cycle than the initial pseudo-random sequence Q<5:0>.

[0200] The target pseudo-random sequence sam<5:0> can still traverse all (2 6 -1) sequences, the addresses that need to be measured multiple times can be decoded into different intervals according to the performance of the system. In the example of Table 3, sam<5:0> has the following rules: when sam<5:3> is 000, 001, 010, half of the sequences will be repeated twice; when sam<5:3> is 011, 100, 101, all sequences will be repeated twice; when sam<5:3> is 110, 111, all sequences will not be repeated and will be sampled only once.

[0201] Convert sam<5:0> from binary to decimal and find that there are 99 sequences output in one cycle, and the sum is 3015 (randomness). Taking the 6-level LFSR optimization as an example, it can achieve an average of 30 activation commands to sample a row address.

[0202] In this way, since the randomness of the target pseudo-random sequence is significantly improved compared with the randomness of the initial pseudo-random sequence, it is beneficial to test the system performance; the target pseudo-random sequence can traverse all (2 N -1) addresses, so that the decoding can be controlled according to the repeated sequence so that the addresses that need to be tested repeatedly do not need to wait for a longer time.

[0203] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0204] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0205] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0206] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0207] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0208] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0209] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims. < / j> < / j> < / j> < / j> < / j>

Claims

1. A pseudo-random sequence generating circuit, characterized in that: It includes an initial sequence generating circuit, a clock generating circuit and a target sequence generating circuit, wherein the initial sequence generating circuit and the clock generating circuit are both connected to the target sequence generating circuit; wherein: The initial sequence generating circuit is used to generate an initial pseudo-random sequence; The clock generating circuit is used to generate a target clock signal, and the pulse widths of different pulses in the target clock signal are different; The target sequence generating circuit is used to receive the initial pseudo-random sequence and the target clock signal, and perform sampling processing on the initial pseudo-random sequence according to the target clock signal to generate a target pseudo-random sequence; The initial pseudo-random sequence includes N bits of initial data, the target pseudo-random sequence includes N bits of target data, and N is an integer greater than 1.

2. The pseudo-random sequence generating circuit according to claim 1, characterized in that: The clock generation circuit comprises an initial clock generation circuit, a sequence cycle circuit and a clock selection circuit; wherein: The initial clock generating circuit is used to receive a preset clock signal and at least one bit of initial data among the N bits of initial data, and to perform logic processing according to the preset clock signal and the at least one bit of initial data to generate an initial clock signal; wherein the pulse widths of different pulses in the preset clock signal are the same, and the pulse widths of different pulses in the initial clock signal are different; The sequence cycle circuit is used to perform logic processing according to the initial pseudo-random sequence to generate a periodic cycle signal; wherein, when the level state of each initial data in the initial pseudo-random sequence is a preset level state, the level state of the periodic cycle signal is flipped; The clock selection circuit is used to receive the initial clock signal and the periodic cycle signal, perform logic processing according to the initial clock signal and the periodic cycle signal, and generate the target clock signal; wherein, when the periodic cycle signal is in a first level state, the level state of the target clock signal is the same as that of the initial clock signal, and when the periodic cycle signal is in a second level state, the level state of the target clock signal is opposite to that of the initial clock signal.

3. The pseudo-random sequence generating circuit according to claim 2, characterized in that: The initial clock generation circuit includes a clock generation subcircuit and a pulse adjustment circuit, the clock generation subcircuit is connected to the pulse adjustment circuit, and the at least one bit of initial data includes first initial data and second initial data, wherein: The clock generation subcircuit is used to receive the preset clock signal, perform delay processing on the preset clock signal to generate a delayed clock signal; perform a logical AND-NOT processing on the preset clock signal and the delayed clock signal to generate a preset square wave signal; The pulse adjustment circuit is used to receive the preset square wave signal, the first initial data and the second initial data, perform delay processing on the preset square wave signal to generate a delayed square wave signal; and perform AND logic processing on the first initial data and the preset square wave signal to generate a first clock signal, and perform AND logic processing on the second initial data and the delayed square wave signal to generate a second clock signal; and perform OR logic processing on the first clock signal and the second clock signal to generate the initial clock signal.

4. The pseudo-random sequence generating circuit according to claim 2, characterized in that: The sequence cycle circuit includes a flag signal generating circuit and a flip control circuit, wherein: The flag signal generating circuit is used to generate a flip flag signal according to the initial pseudo-random sequence; wherein, when the level state of each initial data in the initial pseudo-random sequence is the preset level state, the flip flag signal is in an enabled state; The flip control circuit is used to receive the flip flag signal and generate the periodic cycle signal according to the flip flag signal; wherein, when the flip flag signal is in an enabled state, the level state of the periodic cycle signal is flipped.

5. The pseudo-random sequence generating circuit according to claim 4, characterized in that: The flag signal generating circuit comprises a sequence processing circuit, a second OR gate, a third delay unit and a second NAND gate, wherein: The sequence processing circuit is used to generate at least one logic signal according to the initial pseudo-random sequence; wherein, when the level state of each initial data in the initial pseudo-random sequence is the preset level state, the level state of the at least one logic signal is the second level state; The second OR gate is connected to the sequence processing circuit, and the input end of the second OR gate is used to receive the at least one logic signal; the output end of the second OR gate is respectively connected to the input end of the third delay unit and the second input end of the second NAND gate; the output end of the third delay unit is connected to the first input end of the second NAND gate; the output end of the second NAND gate is used to output the flip flag signal.

6. The pseudo-random sequence generating circuit according to claim 4, characterized in that: The flip control circuit includes a master-slave JK flip-flop, wherein: The clock end of the master-slave JK trigger is used to receive the flip flag signal, the J end of the master-slave JK trigger is used to receive the set signal, the K end of the master-slave JK trigger is used to receive the reset signal, and the output end of the master-slave JK trigger is used to output the periodic cycle signal.

7. The pseudo-random sequence generating circuit according to claim 1, characterized in that: The target sequence generation circuit comprises a latch circuit, wherein: The latch circuit is used to receive the initial pseudo-random sequence and the target clock signal, and to perform sampling processing on the initial pseudo-random sequence according to the target clock signal or an inverted signal of the target clock signal to generate the target pseudo-random sequence.

8. The pseudo-random sequence generating circuit according to claim 1, characterized in that: The target sequence generation circuit comprises a latch circuit and a first sampling circuit, wherein the first sampling circuit is connected to the latch circuit; wherein: The latch circuit is used to receive the initial pseudo-random sequence and the target clock signal, and perform sampling processing on the initial pseudo-random sequence according to the target clock signal or the inverted signal of the target clock signal to generate a first target pseudo-random sequence; The first sampling circuit is used to receive a preset clock signal and the first target pseudo-random sequence, and to perform sampling processing on the first target pseudo-random sequence according to the preset clock signal or an inverted signal of the preset clock signal to generate the target pseudo-random sequence.

9. The pseudo-random sequence generating circuit according to any one of claims 1 to 8, characterized in that: The initial sequence generation circuit comprises an N-stage linear feedback shift register; wherein, at each preset cycle interval, the level state of each initial data in the initial pseudo-random sequence output by the N-stage linear feedback shift register is a preset level state.

10. An address sampling circuit, characterized in that: The method comprises a pseudo-random sequence generating circuit, a counting circuit, a comparing circuit and a second sampling circuit as claimed in any one of claims 1 to 9, wherein: The pseudo-random sequence generating circuit is used to generate the target pseudo-random sequence; The counting circuit is used to count the command signal and generate a counting sequence signal; The comparison circuit is used to compare the counting sequence signal with the target pseudo-random sequence to generate a comparison signal; The second sampling circuit is used to sample the address signal according to the comparison signal to generate a target address signal.

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