Cache and operation method, processor core, instruction processing method, equipment and medium

Abstract

The embodiment of the invention relates to a cache and an operation method thereof, a microinstruction cache, a processor core, an instruction processing method, electronic equipment and a computer readable storage medium. The cache comprises a plurality of cache entries, each cache entry is configured to store information related to one microinstruction group, and each cache entry comprises an address field corresponding to the corresponding microinstruction group; and in response to the condition that the object microinstruction group is filled in the microinstruction cache, storing address information of a microinstruction address of the object microinstruction group in the microinstruction cache in an address field of a cache entry corresponding to the object microinstruction group. By setting the address field in the cache entry included in the cache and storing the address information of the microinstruction group, the address information of the microinstruction group can be utilized to perform operations such as parallel reading of subsequent microinstruction groups and the like.

Description

Technical Field

[0001] The present disclosure relates to a cache and an operation method thereof, a microinstruction cache, a processor core, an instruction processing method, an electronic device and a computer-readable storage medium. Background Art

[0002] A processor core (or simply "CPU core") is a core that can independently complete the operation steps of a central processing unit (CPU). For example, a CPU may include at least one CPU core. Depending on the number of CPU cores included, the CPU may be a single-core processor (CPU) or a multi-core processor (CPU). Usually each CPU core contains a three-level cache (if there is a three-level cache).

[0003] The processor core translates each architectural instruction (instruction, referred to as "instruction") into one or more micro-instructions (micro-op, uop) within the microarchitecture. Each microinstruction only performs a limited number of operations. This ensures that each pipeline stage is very short to increase the operating frequency of the processor core. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a cache, comprising multiple cache entries, wherein each cache entry is configured to store information related to a microinstruction group, and each cache entry includes an address field corresponding to the corresponding microinstruction group; in response to an object microinstruction group being filled in the microinstruction cache, address information of a microinstruction address of the object microinstruction group in the microinstruction cache is stored in the address field of the cache entry corresponding to the object microinstruction group.

[0005] At least one embodiment of the present disclosure provides a microinstruction cache, comprising: a first sub-cache, configured to provide a microinstruction group storage space; and a second sub-cache, comprising a plurality of cache entries, each cache entry being configured to store information related to a microinstruction group, each cache entry comprising an address field corresponding to a corresponding microinstruction group; in response to an object microinstruction group being filled in the microinstruction cache, address information of a microinstruction address of the object microinstruction group in the microinstruction cache is stored in the address field of the cache entry corresponding to the object microinstruction group.

[0006] At least one embodiment of the present disclosure provides a processor core, comprising: a first sub-cache, configured to provide a microinstruction group storage space; a second sub-cache, comprising a plurality of cache entries, each cache entry being configured to store information related to a microinstruction group, each cache entry comprising an address field corresponding to a corresponding microinstruction group; and a cache operation module, configured to: in response to an object microinstruction group being filled in the first sub-cache, obtain a microinstruction address of the object microinstruction group in the first sub-cache; and store the address information of the microinstruction address in the address field of the cache entry corresponding to the object microinstruction group in the second sub-cache.

[0007] At least one embodiment of the present disclosure provides a cache operation method, comprising: in response to an object microinstruction group being filled in a microinstruction cache, selecting a target cache entry from a plurality of cache entries included in the cache; and storing address information of a microinstruction address of the object microinstruction group in the microinstruction cache in an address field included in the target cache entry.

[0008] At least one embodiment of the present disclosure provides an instruction processing method, comprising: in response to an object microinstruction group being filled in a first sub-cache, obtaining a microinstruction address of the object microinstruction group in the first sub-cache; and storing address information of the microinstruction address in an address field of a cache entry corresponding to the object microinstruction group in a second sub-cache.

[0009] At least one embodiment of the present disclosure provides an electronic device, including: a processor; and a memory, including one or more computer program instructions; wherein the one or more computer program instructions, when executed by the processor, execute the method provided by at least one embodiment of the present disclosure.

[0010] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the method provided by at least one embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0012] Figure 1 A schematic diagram of a pipeline of a processor core is shown;

[0013] Figure 2 A schematic diagram showing the basic structural division of a processor is shown;

[0014] Figure 3 A schematic diagram showing an example of a front-end structure of a CPU core;

[0015] Figure 4 A schematic diagram of a branch prediction module is shown;

[0016] Figure 5 A schematic diagram showing the operation of decoding instructions in a processor core;

[0017] Figure 6 A schematic diagram showing the operation of accessing the microinstruction cache to obtain corresponding microinstruction group data;

[0018] Figure 7 A schematic diagram showing the alignment relationship between microinstruction groups and cache blocks is shown;

[0019] Figure 8 A schematic diagram showing a cache according to at least one embodiment of the present disclosure is shown;

[0020] Fig. 9 A schematic flow chart showing a method for operating a cache according to at least one embodiment of the present disclosure is shown;

[0021] Fig.10 A schematic diagram showing a cache according to at least another embodiment of the present disclosure is shown;

[0022] Fig.11 A schematic diagram showing a cache according to at least another embodiment of the present disclosure is shown;

[0023] Fig.12 A schematic diagram showing a microinstruction cache according to at least one embodiment of the present disclosure is shown;

[0024] Fig.13 A schematic diagram showing the structure of a processor core according to at least one embodiment of the present disclosure is shown;

[0025] Fig.14 A schematic flow chart showing an instruction processing method according to at least one embodiment of the present disclosure;

[0026] Fig.15 A schematic flow chart showing an instruction processing method according to at least another embodiment of the present disclosure;

[0027] Fig.16 A schematic diagram showing the principle of storing address information in an address field included in a cache entry;

[0028] Fig.17 A schematic diagram showing the principle of reading multiple microinstruction groups in parallel according to at least one embodiment of the present disclosure is shown;

[0029] Fig.18 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0030] Fig.19A schematic diagram showing the structure of a computer-readable storage medium according to at least one embodiment of the present disclosure; and

[0031] Fig. 20 A schematic block diagram of an electronic device according to at least another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] The processor core (CPU core) of a single-core processor or a multi-core processor improves the efficiency of instruction execution through pipeline technology. Pipeline technology divides the complete operation steps of the CPU core into multiple sub-steps and executes these sub-steps in the form of pipeline to improve efficiency.

[0035] Figure 1 FIG. 1 shows an exemplary scalar central processing unit (CPU) instruction pipeline, which includes a five-stage pipeline. Figure 1As shown, each instruction can be issued in each clock cycle and executed within a fixed time (for example, 5 clock cycles). The execution of each instruction is divided into 5 steps: instruction fetch (IF) stage 1001, decode (ID) stage 1002, execute (EX) stage 1003, memory access (MEM) stage 1004 and write back (WB) stage 1005. In the IF stage 1001, the specified instruction is taken out from the instruction cache. A part of the specified instruction taken out is used to specify the source register that can be used to execute the instruction. In the ID stage 1002, the control logic is decoded and generated to take out the content of the specified source register. According to the control logic, an arithmetic or logical operation is performed in the EX stage 1003 using the taken out content. In the MEM stage 1004, the execution instruction can read / write the memory in the data cache. Finally, in the WB stage 1005, the value obtained by executing the instruction can be written back to a register.

[0036] Usually, the earlier pipeline steps in the CPU are classified as the front end. For example, taking the five-stage pipeline as an example, the modules used for the instruction fetch stage and the decoding stage are classified as the CPU front end. Correspondingly, the later pipeline steps in the CPU are classified as the back end. For example, taking the five-stage pipeline as an example, the modules used for the execution stage, memory access stage and write back stage are classified as the CPU back end.

[0037] In order to support high operating frequencies, each pipeline stage may contain multiple (sub) pipeline stages (clock cycles). Although each pipeline stage performs limited operations, each clock can be kept to a minimum, thereby improving the performance of the CPU core by increasing the operating frequency of the CPU. Each pipeline stage can also further improve the performance of the processor core by accommodating more instructions (i.e., superscalar technology). Superscalar refers to a method of executing multiple instructions in parallel within one cycle. A processor with increased instruction-level parallelism that can process multiple instructions within one cycle is called a superscalar processor. For example, a superscalar processor can further support out-of-order execution. Out-of-order execution refers to the technology used by the CPU to allow multiple instructions to be sent separately to the corresponding circuit units for processing in a non-programmed order.

[0038] The processor core translates each architectural instruction (instruction, referred to as "instruction") into one or more microinstructions within the microarchitecture. Each microinstruction only performs limited operations, which can ensure that each pipeline stage is very short to increase the operating frequency of the processor core. For example, a memory read instruction (load) can be translated into an address generation microinstruction and a memory read microinstruction. The second microinstruction will depend on the result of the first microinstruction, so the second microinstruction will only start to execute after the first microinstruction is executed. Microinstructions contain multiple microarchitecture-related fields, which are used to pass relevant information between pipeline stages.

[0039] Speculative execution is another technique to improve processor performance. This technique executes the instructions following an instruction before it has finished executing. One technique for speculative execution is branch prediction. As mentioned above, the instruction fetch unit is responsible for providing the processor with the instruction to be executed next. In the instruction fetch stage, in addition to fetching multiple instructions, it is also necessary to determine the instruction fetch address for the next cycle. Therefore, at this stage, it is determined whether there is a conditional branch instruction, if there is a branch, whether to jump (direction) and the target address. The instruction fetch unit includes a branch prediction unit (branch predictor) to perform branch prediction. The branch prediction unit (branch predictor) at the front end of the processor core predicts the jump direction of the conditional branch instruction, pre-fetches, and executes the instructions in that direction. Another technique for speculative execution is to execute a memory read instruction before the addresses of all previous memory write instructions are obtained.

[0040] Predictive execution further improves the parallelism between instructions, thereby greatly improving the performance of the processor core. When a predictive execution error occurs, such as a branch prediction error, or a write instruction before a memory read instruction rewrites the same address, all instructions in the pipeline following the erroneous instruction need to be flushed (or "cleared"), and then the program jumps to the error point and re-executes to ensure the correctness of program execution.

[0041] Figure 2 A schematic diagram of the basic structural division of a processor is shown. The processor 200 includes at least one CPU core (processor core) and at least one level of cache, for example, the CPU core includes a front end 201 and a back end 202, for example, the at least one level of cache includes a level one cache (not shown) arranged in the CPU core and a level two cache 203 outside the CPU core, where the level two cache 203 is a separate structure.

[0042] Figure 3A schematic diagram of an example of the front-end structure of a CPU core is shown. The front-end 201 of the CPU core includes an instruction fetch unit, a decoding unit and a transmitting unit. The instruction fetch unit includes a branch prediction 301 and a selection logic 302; the decoding unit includes an instruction cache 303, an instruction decoding 304, a microinstruction cache 305 and a microinstruction queue 306; and the transmitting unit 307 is connected to the microinstruction queue 306. The CPU core has both an instruction cache and a microinstruction cache, so it has microarchitecture optimization. The instruction address obtained by the instruction fetch unit (which can be a program counter address, referred to as a PC address) is predicted through a branch prediction 301 to obtain the instruction address to be executed next. At the same time, the instruction address passes through the selection logic 302 to determine whether the instruction corresponding to the instruction address needs to be decoded. If "yes", then go to step 1. Figure 3 The left path in the middle needs to decode the instruction; if "no", then go to Figure 3 The path on the right does not need to decode the instruction, but accesses the microinstruction cache to obtain the corresponding microinstruction group data.

[0043] Figure 4 FIG. 1 shows a schematic diagram of a branch prediction module. Figure 3 , the instruction address enters the branch prediction (301) module, and accesses the branch predictor 401 and other functional modules 402 respectively. The branch predictor 301 is accessed to determine whether there is a branch instruction within an interval starting from the instruction address (for example, the range from the instruction address to the first subsequent alignment address, for example, the processor alignment address can be 64 bytes), the branch direction and jump address when there is a branch instruction. The purpose of accessing other functional modules is to obtain some key information to facilitate access to subsequent modules. Among them, other functional modules may include, for example, a micro-label cache of microinstructions and a micro-label cache of instructions. If a branch that can be jumped is predicted, the next instruction address is the jump address of the branch. If no branch that can be jumped is predicted, the next instruction address is the starting address of the next alignment address.

[0044] Figure 5 FIG. 1 is a schematic diagram showing the operation of decoding instructions in a processor core. Figure 3According to the instruction address A, the instruction cache 303 is queried to obtain the undecoded instruction data (e.g., one or more instructions) corresponding to the instruction address A, and then the instruction data is decoded into multiple microinstructions (these microinstructions can be called microinstruction groups, such as microinstruction 1, microinstruction 2, microinstruction 3, etc.) through the instruction decoding 304. The obtained microinstruction group is sent to the microinstruction queue 306 on the one hand, waiting for the emission unit 307 to allocate and emit it to the corresponding execution unit in the back end of the CPU core for execution. On the other hand, if certain conditions are met (for example, the microinstruction group is a commonly used group of microinstructions), it is saved in the microinstruction cache 305, waiting for possible access again later.

[0045] In one embodiment, the processor core may update the micro-tag cache of the micro-instructions in other functional modules 402 while saving the micro-instruction group to the micro-instruction cache 305 .

[0046] Figure 6 A schematic diagram showing the operation of accessing the microinstruction cache to obtain the corresponding microinstruction group data. Figure 3 According to the instruction address, the microinstruction cache 305 is accessed to obtain the corresponding microinstruction group data (for example, including microinstruction 1, microinstruction 2, and microinstruction 3), and the obtained microinstruction group data is directly sent to the microinstruction queue 306 to wait for the launch unit 307 to allocate and launch it to the corresponding execution unit in the back end of the CPU core for execution. Since the delay of accessing the microinstruction cache is low and the power consumption caused by decoding is reduced, the selection logic 302 will choose to access the microinstruction cache 305 as much as possible.

[0047] Usually, the capacity of the cache is very small, and the content stored in the cache is only a subset of the main memory content. The data exchange between the cache and the main memory is in blocks, and the memory block of the main memory is the same size as the cache line or cacheblock of the cache. In order to cache the data in the main memory into the cache, a certain function must be applied to locate the main memory address to the cache, which is called address mapping. After the instruction data in the main memory is cached into the cache (instruction cache) according to this mapping relationship, when the CPU core executes the program, it will transform the main memory address in the program's instructions into the cache address. The address mapping methods of the cache usually include direct mapping, fully associative mapping, and set associative mapping.

[0048] Each cache item includes a cache block, that is, it corresponds to a cache block; each cache item also includes a valid bit (Valid), a tag (Tag) field and a data field, etc., wherein the data field includes a cache block for storing cached data (such as instruction data or operated data), and the tag field stores the tag part of the memory address of the cached data.

[0049] For fully associative mapping, all cache items in the cache are organized into multiple groups (sets). When the processor core uses the memory address to access the cache, it needs to use the tag and compare it with the tag in the cache item one by one. When a hit occurs, the offset is used to locate the corresponding byte in the cache block. For direct mapping, all cache items in the cache are organized into multiple groups, but there is only one cache item in each group, that is, there is only one "way". When the processor core uses the memory address to access the cache, it first finds the corresponding "group" through the index part (index) of the memory address, and then uses the tag and compares it with the tag in the cache item in the group. When a hit occurs, the offset is used to locate the corresponding byte in the cache block. For set-associative mapping, all cache items in the cache are organized into multiple groups, each group includes multiple cache items, and each cache item in the group occupies a "way", that is, there are multiple ways. When the processor core uses the memory address to access the cache, it first finds the corresponding "group" through the index part of the memory address, and then in the "group", uses the tag to compare with the tag in the cache item stored in each "way". If the same tag is found in a certain way, the cache query hits, otherwise, the cache query misses, and when it hits, the offset is used to locate the corresponding byte in the cache block.

[0050] As described above, in the case of fully associative mapping, the memory address includes two parts, a tag and an offset, but does not include an index; in the case of direct mapping and set associative mapping, the memory address includes three parts, a tag, an index, and an offset.

[0051] Figure 7 FIG. 1 shows a schematic diagram of the alignment relationship between the microinstruction group and the cache block. Figure 7 As shown, a certain cache block 700 is a cache block whose head and tail addresses are aligned with the memory block of the main memory. The head address of the cache block 700 is set to be the microinstruction starting address of a microinstruction group, and the tail address is the microinstruction ending address of a microinstruction group. The cache block 700 can at least store a microinstruction group 711 and a microinstruction group 712. It is understandable that, according to actual conditions, a cache block can also store only one microinstruction group, or two or more microinstruction groups.

[0052] If at least two microinstruction groups are stored in a cache block, under the X86 architecture, the multiple microinstruction groups are serially read by serially accessing the microinstruction cache. For example, it is necessary to first read a microinstruction group based on the instruction address. Then, based on the obtained microinstruction end address of the microinstruction group, the microinstruction start address of the next microinstruction group can be obtained. Since it is necessary to serially read multiple microinstruction groups stored in a cache block, the read bandwidth of the microinstruction cache is low.

[0053] At least one embodiment of the present disclosure provides a cache and a corresponding operation method. The cache provided by at least one embodiment can be used as a micro-tag cache of a microinstruction, or as a sub-cache in a microinstruction cache, and the embodiments of the present disclosure do not limit this. The cache sets an address field corresponding to a microinstruction group and stores the address information of the microinstruction group in the microinstruction cache. For example, before reading the microinstruction group from the microinstruction cache, the address information of the microinstruction group can be obtained in advance, for example, it can facilitate the operation of determining the address of at least one subsequent microinstruction group based on the address information.

[0054] The following will be combined Figure 8~Figure 11 The cache and its operation method provided by at least one embodiment of the present disclosure are described in detail.

[0055] Figure 8 A schematic diagram of a cache according to at least one embodiment of the present disclosure is shown.

[0056] like Figure 8 As shown, the cache 800 of this embodiment includes a plurality of cache entries, each cache entry corresponds to a microinstruction group and is configured to store information related to a microinstruction group. Figure 8 The description is made by taking the example that each row corresponds to one cache entry, and the embodiments of the present disclosure are not limited to this.

[0057] Each cache entry includes an address field 801 corresponding to a corresponding microinstruction group, and the address field 801 is used to store address information of a microinstruction address of the corresponding microinstruction group in the microinstruction cache.

[0058] For example, the microinstruction address of the corresponding microinstruction group in the microinstruction cache can be stored in address field 801, or the microinstruction end address of the corresponding microinstruction group in the microinstruction cache can be stored in address field 801, or the microinstruction starting address and address offset of the corresponding microinstruction group in the microinstruction cache can be stored in address field 801. The microinstruction end address of the microinstruction group can be the address of the last microinstruction in the microinstruction group. The microinstruction starting address of the microinstruction group can be the address of the first microinstruction in the microinstruction group. The address offset of the microinstruction group can be the offset of the microinstruction receiving address relative to the microinstruction starting address.

[0059] For example, if the microinstruction group includes five microinstructions, the addresses of the five microinstructions in the microinstruction cache are: 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, then the microinstruction start address is 0x1000, the microinstruction end address is 0x1004, and the address offset is 4.

[0060] In at least one embodiment of the present disclosure, the address information of the microinstruction address of the microinstruction group in the microinstruction cache may be, for example, any information that can indicate the end address of the microinstruction, and the present disclosure does not limit this. For example, if the processor alignment address is 64 bytes (for example, the system bus width is 64 bytes), the last 6 bits of the microinstruction address of the microinstruction group in the microinstruction cache may be used as the address information.

[0061] At least one embodiment of the present disclosure can store the address information of the microinstruction address of the object microinstruction group in the microinstruction cache in the address field of the cache entry corresponding to the object microinstruction group when the acquired instruction is decoded (decoded) by a decoding unit to obtain the object microinstruction group and the object microinstruction group is filled in the microinstruction cache.

[0062] At least one embodiment of the present disclosure sets an address field in a cache and stores address information in the address field. For example, the address information of a microinstruction group can be obtained before the microinstruction group is read from the microinstruction cache, so as to improve the efficiency of obtaining the address information in a scenario where the address information needs to be obtained.

[0063] For example, in at least one application scenario, before reading a designated microinstruction group according to a received instruction fetch address, address information can be first obtained from a cache entry corresponding to the designated microinstruction group in the cache, and the instruction fetch address of the next microinstruction group of the designated microinstruction group can be derived according to the address information. Subsequently, the designated microinstruction group and the next microinstruction group can be read in parallel based on the received instruction fetch address and the derived instruction fetch address, thereby improving the read bandwidth of the microinstruction cache and improving the microinstruction reading efficiency.

[0064] Based on the cache provided by at least one embodiment of the present disclosure, the present disclosure also provides an operation method of the cache. Fig. 9 Describe in detail.

[0065] Fig. 9 A schematic flow chart of a cache operation method according to at least one embodiment of the present disclosure is shown.

[0066] In at least one embodiment of the present disclosure, Fig. 9 As shown, a cache operation method 900 provided in at least one embodiment of the present disclosure may include operations S910 to S920.

[0067] In operation S910 , in response to a target microinstruction group being filled in a microinstruction cache, a target cache entry is selected from a plurality of cache entries included in the cache.

[0068] In operation S920, address information of a microinstruction address of a target microinstruction group in a microinstruction cache is stored in an address field included in a target cache entry.

[0069] For example, if the cache already includes a cache entry corresponding to the target microinstruction group, the corresponding cache entry can be used as the target cache entry. If the cache does not include a cache entry corresponding to the target microinstruction group, for example, a cache entry can be selected from cache entries that do not correspond to the microinstruction group as the target cache entry, or a cache entry can be determined as the target cache entry according to a cache replacement algorithm.

[0070] For example, it is possible to locate whether the cache includes a cache entry corresponding to the object microinstruction group according to the label of the object microinstruction group. Alternatively, it is possible to locate whether the cache includes a cache entry corresponding to the object microinstruction group according to the microlabel of the object microinstruction group. Wherein, the label of the microinstruction group can be obtained based on the address of the first microinstruction in the microinstruction group, for example, the label of the microinstruction group can be composed of other parts of the address of the first microinstruction except the index part. The microlabel of the microinstruction group can be a part of the label of the microinstruction group or the information obtained by compressing the label of the microinstruction group.

[0071] After the target cache entry is determined, the address information of the microinstruction address of the target microinstruction group in the microinstruction cache may be stored in the address field included in the target cache entry, ie, the address information may be written to the address field.

[0072] For example, the operation method may be executed by an instruction fetch unit in a processor core, or may be executed by a decoding unit in a processor core, or may be executed by other functional units with processing functions in the processor core, and the embodiments of the present disclosure are not limited to this.

[0073] In at least one embodiment of the present disclosure, the address information of the microinstruction group stored in the address field may include a microinstruction end address. For example, the microinstruction end address may be operated to conveniently obtain the starting address of the next microinstruction group of the object microinstruction group. In this way, the next microinstruction group may be read based on the obtained starting address without having to read the object microinstruction group before reading the next microinstruction group. In one embodiment, the next microinstruction group may be read in parallel with the object microinstruction group.

[0074] Fig.10 A schematic diagram of a cache according to at least another embodiment of the present disclosure is shown.

[0075] In at least one embodiment of the present disclosure, Fig.10 As shown, each cache entry of the plurality of cache entries included in the cache 1000 may further include a micro-tag field 1002 in addition to the address field 1001 , for example, and the micro-tag field 1002 stores the micro-tag of the corresponding micro-instruction group.

[0076] For example, the microtag may be determined based on the microinstruction start address of the microinstruction group in the microinstruction cache. For example, the microtag may be a portion of the microinstruction start address, or may be information obtained by compressing the microinstruction start address. Based on the microtag, the target cache entry may be selected quickly.

[0077] Exemplarily, when performing the aforementioned operation of selecting a target cache entry, the microtag of the target microinstruction group may be first determined according to the microinstruction start address of the target microinstruction group in the microinstruction cache. Subsequently, the determined microtag may be compared with the microtag stored in the microtag field included in each cache entry in the cache 1000. If there is a cache entry whose stored microtag is consistent with the determined microtag, the cache entry is determined as the target cache entry.

[0078] In at least one embodiment of the present disclosure, Fig.10 As shown, each cache entry included in the cache 1000 may also include a valid bit 1003, in which validity information of the corresponding microinstruction group is stored to indicate whether the corresponding microinstruction group is valid. Based on the valid bit, for example, it is convenient to select a target cache entry.

[0079] For example, the information stored in the valid bit 1003 can be a binary number. If the value of the stored binary number is 0, it indicates that the corresponding microinstruction group is invalid. If the value of the stored binary number is 1, it indicates that the corresponding microinstruction group is valid.

[0080] Exemplarily, when performing the aforementioned operation of selecting a target cache entry, the microtag of the target microinstruction group may be first determined according to the microinstruction start address of the target microinstruction group in the microinstruction cache. Subsequently, the determined microtag may be compared with the microtag stored in the microtag field included in each cache entry in the cache 1000. If there is no cache entry whose stored microtag is consistent with the determined microtag, a cache entry whose valid bit stores validity information indicating invalidity may be selected from the cache as the target cache entry.

[0081] In one embodiment, the address field can be added to the micro-tag cache of the micro-instruction provided with the micro-tag field and the valid bit to obtain the following: Fig.10 Cache 1000 is shown.

[0082] Fig.11 A schematic diagram of a cache according to at least another embodiment of the present disclosure is shown.

[0083] In at least one embodiment of the present disclosure, Fig.11As shown, the address field 1101 included in each cache entry in the cache 1100 may include, for example, at least two address subfields, for example, two address subfields, namely, the address subfield 1111 and the address subfield 1121. It should be noted that, Fig.11 The embodiment in which the address field includes two address subfields is described only as an example to facilitate understanding of the present disclosure. According to actual needs, the address field may also include three or more address subfields, which is not limited in the embodiments of the present disclosure.

[0084] Exemplarily, the number of address subfields included in the address field can be determined according to the number of microinstruction groups that can be stored in a cache block in the microinstruction cache. For example, if a cache block can store N microinstruction groups, the number of address subfields included in the address field in each cache entry can be N-1, where N is an integer greater than or equal to 2.

[0085] Exemplarily, the at least two address subfields included in the address field in each cache entry can sequentially store the address information of the microinstruction addresses of the target microinstruction group and the subsequent microinstruction group of the target microinstruction group in the microinstruction cache. For example, the subsequent microinstruction group of the target microinstruction group can be a microinstruction group stored in the same cache block as the target microinstruction group and stored in the microinstruction cache after the target microinstruction group.

[0086] For example, in response to the next microinstruction group immediately adjacent to the target microinstruction group being filled in the microinstruction cache and being in the same cache block as the target microinstruction, the address information of the microinstruction address of the next microinstruction in the microinstruction cache can be stored in the address subfield of the cache entry corresponding to the target microinstruction group. For example, the next microinstruction group can be understood as the first microinstruction group decoded by the decoding unit after the target microinstruction group is decoded.

[0087] For example, the order in which at least two address subfields included in the address field of each cache entry store at least two address information may correspond to the order in which the microinstruction groups corresponding to the at least two address information are stored in the microinstruction cache. For example, if microinstruction group 1, microinstruction group 2, and microinstruction group 3 are stored in sequence in the cache block, then in the two subfields included in the cache entry corresponding to microinstruction group 1, the address information of the microinstruction address of microinstruction group 1 in the microinstruction cache and the address information of the microinstruction address of microinstruction group 2 in the microinstruction cache are stored in sequence.

[0088] For example, at least two address subfields obtained in time sequence may be written into the at least two address subfields according to the front-to-back sequence of the at least two address subfields in the cache.

[0089] By setting at least two address subfields in the cache entry and storing the address information of the corresponding microinstruction group and the subsequent microinstruction group stored in the same cache block as the microinstruction group, it is convenient to derive the value addresses of the subsequent at least two microinstruction groups based on the stored at least two address information and the value address of the target microinstruction group. It is further convenient to read the target microinstruction group and the subsequent at least two microinstruction groups in parallel from the microinstruction cache based on the value address of the target microinstruction group and the derived value addresses of the subsequent at least two microinstruction groups.

[0090] Based on the cache provided by at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a microinstruction cache. Fig.12 The microinstruction cache is described in detail.

[0091] Fig.12 A schematic diagram of a microinstruction cache according to at least one embodiment of the present disclosure is shown.

[0092] like Fig.12 As shown, the microinstruction cache 1200 of this embodiment includes a first sub-cache 1201 and a second sub-cache 1202 .

[0093] The first sub-cache 1201 is configured to provide a microinstruction group storage space. For example, the first sub-cache 1201 stores microinstructions (microinstruction groups) in blocks. Each cache block can store one microinstruction group, or two or more microinstruction groups.

[0094] The second sub-cache 1202 may include a plurality of cache entries, each cache entry storing information associated with a microinstruction group, and each cache entry including an address field corresponding to a corresponding microinstruction group.

[0095] For example, in response to the target microinstruction group being filled in the first sub-cache 1201 , the address information of the microinstruction address of the target microinstruction group in the first sub-cache 1201 may be stored in the address field of the cache entry corresponding to the target microinstruction group included in the second sub-cache 1202 .

[0096] For example, the cache entries included in the second sub-cache 1202 are similar to the cache entries included in the cache in at least one embodiment described above, and are not described in detail here.

[0097] In at least one embodiment of the present disclosure, for example, a portion of the storage space in the existing microinstruction cache can be divided into multiple cache entries to store information related to the microinstruction group, and the remaining storage space except the multiple cache entries is used as the microinstruction group storage space to obtain the following Fig.12The microinstruction cache. Through the microinstruction cache of at least one embodiment of the present disclosure, the address information of the microinstruction address of the microinstruction group in the microinstruction cache can be stored without additionally setting up a cache. In a specific application scenario, the read bandwidth of the microinstruction cache can be increased without increasing the hardware cost.

[0098] Based on the cache provided by at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a processor core. Figure 13~Figure 17 A processor core and a method for processing instructions thereof provided by at least one embodiment of the present disclosure are described in detail.

[0099] Fig.13 A schematic diagram of the structure of a processor core according to at least one embodiment of the present disclosure is shown.

[0100] like Fig.13 As shown, the processor core 1300 of this embodiment includes a first sub-cache 1301, a second sub-cache 1302, and a cache operation module 1303. The cache operation module 1303 can be connected to the first sub-cache 1301 and the second sub-cache 1302. For example, the cache operation module 1303 can at least access the second sub-cache 1302 to perform read and write operations on the second sub-cache 1302.

[0101] The first sub-cache 1301 is configured to provide a microinstruction group storage space. For example, the first sub-cache 1301 may be a microinstruction cache, or may be combined with the second sub-cache 1302 as two parts of a microinstruction cache to form a microinstruction cache.

[0102] The second sub-cache 1302 includes a plurality of cache entries, each of which is configured to store information related to a microinstruction group, and each of which includes an address field corresponding to the corresponding microinstruction group. For example, the second sub-cache 1302 may be a cache provided by any of the foregoing embodiments of the present disclosure, or may be combined with the first sub-cache 1301 as two parts of a microinstruction cache to form a microinstruction cache.

[0103] The cache operation module 1303 is configured to obtain the microinstruction address of the target microinstruction group in the first sub-cache in response to the target microinstruction group being filled in the first sub-cache 1301. Then, the address information of the microinstruction address is stored in the address field of the cache entry corresponding to the target microinstruction group in the second sub-cache 1302. For example, the cache operation module 1303 can adopt the aforementioned instruction fetch unit or decoding unit, or any unit with processing function in the processor core, which is not limited by the present disclosure.

[0104] In at least one embodiment of the present disclosure, the cache operation module 1302 may write the acquired microinstruction address as address information into the address field of the cache entry corresponding to the object microinstruction group, or may write the microinstruction end address of the object microinstruction group included in the microinstruction address as address information into the address field of the cache entry corresponding to the object microinstruction group, or may write the microinstruction start address of the object microinstruction group included in the microinstruction address and the address offset determined based on the microinstruction start address and the microinstruction end address as address information into the address field of the cache entry corresponding to the object microinstruction group.

[0105] For example, the address information written by the cache operation module 1302 in the address field of the cache entry corresponding to the target microinstruction group may be any information that can indicate the microinstruction end address of the target microinstruction group, and the present disclosure does not limit this.

[0106] Based on the processor core of at least one embodiment, at least one embodiment of the present disclosure further provides an instruction processing method. Fig.14 A schematic flow chart of an instruction processing method according to at least one embodiment of the present disclosure is shown.

[0107] like Fig.14 As shown, the instruction processing method 1400 of this embodiment includes operations S1410 to S1420. The instruction processing method can be executed by, for example, a cache operation module in a processor core provided by at least one of the aforementioned embodiments.

[0108] In operation S1410 , in response to a target microinstruction group being filled in a first sub-cache, a microinstruction address of the target microinstruction group in the first sub-cache is obtained.

[0109] In operation S1420, address information of the microinstruction address is stored in an address field of a cache entry corresponding to the target microinstruction group in the second sub-cache.

[0110] It can be understood that the implementation principle of each operation in the instruction processing method is similar to the implementation principle of the operation performed after the cache operation module in the processor core provided in at least one embodiment described above is configured, and will not be repeated here.

[0111] In at least one embodiment of the present disclosure, in a specific application scenario, the processor core provided by at least one embodiment of the present disclosure can derive the instruction fetch address of the microinstruction group corresponding to the current instruction fetch address stored in the same cache block and adjacent to the microinstruction group corresponding to the current instruction fetch address based on the address information stored in the address field of the cache entry corresponding to the microinstruction group, and read at least two microinstruction groups stored in the same cache block in parallel based on the current instruction fetch address and the derived instruction fetch address. In this way, the read bandwidth of the microinstruction cache is improved, and the microinstruction reading efficiency is improved.

[0112] For example, the cache operation module in the processor core provided by at least one embodiment of the present disclosure is also configured to obtain the first instruction fetch address of the object microinstruction group in response to receiving an instruction fetch request for the object microinstruction group. The cache operation module is also configured to obtain the address information stored in the address field in the cache entry corresponding to the object microinstruction group from the second sub-cache while obtaining the first instruction fetch address or at any time after receiving the instruction fetch request. After obtaining the address information, the cache operation module is also configured to obtain the second instruction fetch address of the first microinstruction group based on the obtained address information. After obtaining the first instruction fetch address and the second instruction fetch address, the cache operation module is also configured to read the object microinstruction group and the first microinstruction group in parallel from the first sub-cache based on the first instruction fetch address and the second instruction fetch address. For example, the first microinstruction group and the object microinstruction group are stored in the same cache block of the first sub-cache, and the first microinstruction group is stored in the first sub-cache immediately after the object microinstruction group.

[0113] Accordingly, the instruction processing method provided by at least one embodiment of the present disclosure includes, in addition to the stage of storing address information through the aforementioned operations S1410 to S1420, a stage of reading address information and reading microinstruction groups in parallel. Fig.15 An instruction processing method provided by at least another embodiment of the present disclosure is described in detail to further describe the operations that the cache operation module is configured to perform.

[0114] Fig.15 A schematic flow chart of an instruction processing method according to at least another embodiment of the present disclosure is shown.

[0115] like Fig.15 As shown, the instruction processing method 1500 of this embodiment includes at least operations S1530 to S1560. For example, the instruction processing method 1500 may also include the aforementioned operations S1410 to S1420. For the same microinstruction group, operations S1530 to S1560 should be executed after operations S1410 to S1420. For different microinstruction groups, operations S1530 to S1560 and operations S1410 to S1420 may be executed in parallel or in any execution order, and the embodiments of the present disclosure do not limit this.

[0116] Operation S1530 , in response to receiving an instruction fetch request for the target microinstruction group, obtaining a first instruction fetch address of the target microinstruction group.

[0117] In operation S1540, address information stored in an address field in a cache entry corresponding to the target microinstruction group is obtained from the second sub-cache.

[0118] Operation S1550: acquiring a second instruction fetch address of the first microinstruction group based on the acquired address information.

[0119] In operation S1560 , based on the first instruction fetch address and the second instruction fetch address, the target microinstruction group and the first microinstruction group are read in parallel from the first sub-cache.

[0120] For example, the instruction fetch unit at the front end of the processor core obtains the instruction address according to the program counter (PC), and then saves the instruction fetch address to the instruction fetch queue to generate an instruction fetch request. If the current processor core is in the microinstruction fetch mode, and the instruction fetch address hits the microinstruction cache (which can be the first sub-cache included in the processor core in at least one of the aforementioned embodiments), the cache operation module can parse the instruction fetch request to obtain the instruction fetch address, and use the instruction fetch address as the first instruction fetch address.

[0121] It is understandable that the target microinstruction group is any microinstruction group stored in the microinstruction cache, and the embodiments of the present disclosure are not limited to this.

[0122] In at least one embodiment of the present disclosure, after obtaining the first instruction fetch address, the cache entry corresponding to the object microinstruction group in the second sub-cache can be determined according to the first instruction fetch address. For example, the cache entry corresponding to the object microinstruction group in the second sub-cache can be determined by matching a tag or micro-tag, or the cache entry corresponding to the object microinstruction group can be determined by an index or the like. Tags, micro-tags, indexes, etc. are associated with, for example, the instruction fetch address of the microinstruction group. After the corresponding cache entry is determined, the address information stored in the address field in the corresponding cache entry is obtained.

[0123] In at least one embodiment of the present disclosure, after obtaining the address information, the second instruction fetch address of the first microinstruction group can be calculated based on the address information. For example, if the address information is the end address of the microinstruction, the second instruction fetch address can be obtained by adding 1 to the end address of the microinstruction. For example, if the address information is the start address and address offset of the microinstruction, the second instruction fetch address can be obtained by adding the address offset to the start address of the microinstruction and then adding 1. For example, if the address information is the microinstruction address, the end address in the microinstruction address can be added by 1 to obtain the second instruction fetch address. For example, if the address information is the last few bytes (for example, 6 bytes) of the microinstruction address of the last microinstruction in the microinstruction group, the second instruction fetch address can be obtained by adding the high-order address of the first instruction fetch address to the address information and then adding 1. It can be understood that the above-mentioned calculation method for obtaining the second instruction fetch address is only used as an example to facilitate understanding of the present disclosure, and the embodiments of the present disclosure are not limited to this.

[0124] Through the processor core of at least one embodiment of the present disclosure and the instruction processing method of at least one embodiment, parallel reading of two microinstruction groups in the same cache block can be achieved, the reading bandwidth of the microinstruction cache can be improved, and the reading efficiency of the microinstruction group can be improved.

[0125] In at least one embodiment of the present disclosure, the first sub-cache included in the processor core may include at least two read ports, and the cache operation module may read the target microinstruction group and the first microinstruction group in parallel through two read ports corresponding to the target microinstruction group and the first microinstruction group among the at least two read ports. This embodiment provides hardware conditions for parallel reading of microinstruction groups.

[0126] For example, compared to a solution of serially reading a microinstruction cache using a single microinstruction cache read port, at least one embodiment of the present disclosure can read at least two microinstruction groups in parallel by adding at least one microinstruction cache read port.

[0127] In at least one embodiment of the present disclosure, the processor core may include a microinstruction queue in addition to the first sub-cache, the second sub-cache and the cache operation module. Figure 3 The described microinstruction queue is similar and is used to store the microinstruction groups read from the microinstruction cache and the parsed microinstruction groups.

[0128] For example, the microinstruction queue includes a write port. Figure 3 In the described embodiment, in at least one embodiment of the present disclosure, the write port of the microinstruction queue can be expanded at least twice to write at least two microinstruction groups read in parallel to the microinstruction queue in parallel. For example, the write port can write the object microinstruction group and the first microinstruction group read in parallel to the microinstruction queue in parallel. Through this embodiment, the instruction fetching efficiency of the processor core front end can be improved.

[0129] In at least one embodiment of the present disclosure, after reading the object microinstruction group and the first microinstruction group in parallel, the cache operation module can also compare whether the address information determined based on the read object microinstruction group is consistent with the address information obtained from the address field in the cache entry corresponding to the object microinstruction group in the second sub-cache. If the two are inconsistent, the first microinstruction group read in parallel with the object microinstruction group is abandoned.

[0130] For example, considering that the microtag is a part of the tag of the microinstruction group or is obtained by compressing the tag of the microinstruction group, in the embodiment of determining the cache entry corresponding to the object microinstruction group based on the microtag, there may be a situation where the cache entry corresponding to the object microinstruction group is erroneously determined. In this case, the address information of the object microinstruction group read from the microinstruction cache may be inconsistent with the address information stored in the address field included in the cache entry in the erroneously determined second sub-cache. If inconsistent, the first microinstruction group can be abandoned to facilitate ensuring the execution accuracy of the microinstructions.

[0131] For example, even if the cache entry corresponding to the target microinstruction group is determined in a more accurate manner, as a fallback strategy, the address information determined based on the read target microinstruction group can be compared with the address information obtained from the address field in the cache entry corresponding to the target microinstruction group in the second sub-cache to determine whether the two are consistent. In this way, the execution accuracy of the microinstructions can be effectively guaranteed.

[0132] Fig.16 A schematic diagram showing the principle of storing address information in an address field included in a cache entry.

[0133] In at least one embodiment of the present disclosure, the address field included in each cache entry may include at least two address subfields. At least one embodiment of the present disclosure may store at least two address information in the at least two address subfields to correspond to at least the first (N-1) microinstruction groups in the N microinstruction groups stored in the same cache block in the microinstruction cache (for example, it may also be the first sub-cache). For example, based on the at least two address information and the instruction fetch address of the first microinstruction group in the N microinstruction groups, the instruction fetch address of each microinstruction group in the N microinstruction groups can be derived. In this way, it is convenient to read the N microinstruction groups stored in the same cache block in parallel, further improve the read bandwidth of the microinstruction cache, and improve the read efficiency of the microinstruction group.

[0134] For example, the cache operation module can store the address information of the microinstruction address of the first microinstruction group in the first sub-cache in the address subfield of the cache entry corresponding to the object microinstruction group in response to the first microinstruction group adjacent to the object microinstruction group being filled in the first sub-cache and stored in the same cache block as the object microinstruction group. The cache operation module can also store the address information of the microinstruction address of the second microinstruction group in the first sub-cache in the address subfield of the cache entry corresponding to the object microinstruction group in response to the second microinstruction group adjacent to the first microinstruction group also being filled in the first sub-cache and stored in the same cache block as the object microinstruction group. And so on, until at least two address subfields included in the address field in the cache entry corresponding to the object microinstruction group store address information.

[0135] In at least one embodiment of the present disclosure, the index of the microinstruction group corresponding to the cache entry last updated in the second sub-cache can be recorded as the target index, and information indicating whether the address subfield in the cache entry last updated is fully stored is recorded. This embodiment can use the target index as a determination condition for whether the next microinstruction group and the microinstruction group corresponding to the cache entry last updated are stored in the same cache block. This is because under normal circumstances, the indexes of different microinstruction groups stored in the same cache block are the same.

[0136] In at least one embodiment of the present disclosure, in addition to recording the target index and the information indicating whether the address subfield is full, the micro tag of the microinstruction group corresponding to the cache entry last updated in the second sub-cache can also be recorded as the target tag, so as to quickly locate the cache entry last updated based on the target tag.

[0137] Exemplarily, the target microinstruction group is set to be the first microinstruction group filled in a cache block, such as Fig.16 As shown, after the address information of the object microinstruction group is stored in the address field of the corresponding cache entry, when the third microinstruction group adjacent to the object microinstruction group is filled in the first sub-cache, the address information of the microinstruction address of the third microinstruction group in the microinstruction cache can be stored in the second sub-cache by the logic described by operation S1612~operation S1662. It should be noted that, in this embodiment, it can be assumed that it is not determined in advance whether the third microinstruction group is stored in a cache block with the object microinstruction group. The object microinstruction group and the third microinstruction group can be understood as two microinstruction groups arranged in close proximity among the multiple microinstruction groups decoded by the decoding unit.

[0138] Operation S1612: Obtain an index of the third microinstruction group based on the microinstruction address of the third microinstruction group. For example, the index included in the microinstruction address of the first microinstruction in the third microinstruction group may be used as the index of the third microinstruction group.

[0139] Operation S1622 determines whether the index of the third microinstruction group is the same as the target index. It is understandable that, since the third microinstruction group is the microinstruction group next to the object microinstruction group, the target index is the index of the microinstruction group corresponding to the cache entry storing the address information of the object microinstruction group, for example, it can be the index obtained based on the microinstruction address of the object microinstruction group. If the two indexes are the same, operation S1632 is performed, otherwise it is determined that the third microinstruction group and the object microinstruction group are stored in different cache blocks of the first sub-cache, and operation S1652 is performed.

[0140] Operation S1632, determining whether the address subfield of the target cache entry is full. For example, the target cache entry is a cache entry that stores the address information of the target microinstruction group, for example, it can be a cache entry corresponding to the target microinstruction group. It can be determined whether all address subfields included in the target cache entry store address information. If all address information is stored, it is determined that the address subfield of the target cache entry is full. If not, operation S1642 is performed, otherwise operation S1662 is performed.

[0141] Operation S1642 , store address information of a microinstruction address of the third microinstruction group in the first sub-cache in an address subfield of the target cache entry where address information is not stored.

[0142] Operation S1652: Update the target index. For example, the target index may be updated to the index of the third microinstruction group.

[0143] Operation S1662: Select other cache entries except the target cache entry, and store address information of the microinstruction address of the third microinstruction group in the first sub-cache in the address field of the selected cache entry.

[0144] In operation S1672, the target cache entry is updated. For example, the target cache entry may be updated to the selected cache entry.

[0145] In at least one embodiment of the present disclosure, operation S1662 may select any cache entry that does not store information other than the target cache entry, or may select any cache entry whose valid bit information indicates invalidity, or may select a cache entry from cache entries other than the target cache entry based on a least recently used (Least Recently Used, LRU) strategy, a random replacement strategy, or a first in first out (First In First Out) strategy, etc., and the present disclosure is not limited to this.

[0146] According to at least one embodiment of the present disclosure, when the cache entry also includes a microtag field, the embodiment can also obtain the microtag of the third microinstruction group based on the microinstruction start address included in the microinstruction address of the third microinstruction group in the first sub-cache in the logic of storing address information, and after selecting to obtain the cache entry through operation S1662, the microtag of the third microinstruction group can be stored in the microtag field included in the selected cache entry. For example, the microtag can be obtained by compressing the tag part in the microinstruction start address (for example, a hash operation can be performed), and a part of the tag can be intercepted from the tag part in the microinstruction start address as the microtag.

[0147] According to an embodiment of the present disclosure, in the case where the address field includes at least two address subfields, the address information obtained by the aforementioned operation S1540 may be at least two. This embodiment, for example, can obtain at least two instruction fetch addresses based on the at least two address information obtained, and based on the first instruction fetch address of the object microinstruction group and the at least two instruction fetch addresses obtained, read the object microinstruction group and at least two microinstruction groups corresponding to the at least two instruction fetch addresses in parallel. It is understandable that the principle of obtaining at least two instruction fetch addresses is similar to the principle of obtaining the second instruction fetch address in the aforementioned operation S1550, and will not be repeated here.

[0148] The following will be combined Fig.17 , taking the address field including two address subfields (i.e. the aforementioned N value is 3) as an example, the principle of reading multiple microinstruction groups in parallel in at least one embodiment of the present disclosure is described in detail. It can be understood that when N takes a value greater than 3, the principle of reading multiple microinstruction groups in parallel can be derived based on the principle of reading multiple microinstruction groups in parallel when N is 3.

[0149] Fig.17 A schematic diagram showing the principle of reading multiple microinstruction groups in parallel according to at least one embodiment of the present disclosure is shown.

[0150] like Fig.17 As shown, in at least one embodiment of the present disclosure, when reading a microinstruction group, in response to receiving an instruction fetch request for an object microinstruction group, a first instruction fetch address of the object microinstruction group can be first obtained. The first instruction fetch address can be, for example, an instruction address obtained according to a program counter. After obtaining the first instruction fetch address, the first instruction fetch address can be placed in an instruction fetch queue. After traversing to the first instruction fetch address in the instruction fetch queue, operation S1701 can be performed.

[0151] Operation S1701, based on the first instruction fetch address, determines whether the microinstruction cache (for example, the first sub-cache) is hit. If the microinstruction cache is hit, S1702 is executed. If the microinstruction cache is not hit, the instruction cache is accessed based on the first instruction fetch address, and the read instruction is decoded to obtain the microinstruction. After obtaining the microinstruction, the microinstruction can be written into the microinstruction queue to wait for the aforementioned emission unit to allocate and emit it to the corresponding execution unit in the back end of the CPU core for execution.

[0152] For example, after obtaining the first instruction fetch address, the corresponding address information can be obtained from the second sub-cache based on the first instruction fetch address. Alternatively, after determining that the microinstruction cache is hit by operation S1701, the corresponding address information can be obtained from the second sub-cache based on the first instruction fetch address. For example, the address information stored in the address subfield in the cache entry corresponding to the target microinstruction group can be obtained from the second sub-cache.

[0153] Operation S1702, determine whether there is first address information. For example, the operation S1702 can determine whether an address information is obtained based on the first instruction fetch address. If obtained, any address information obtained can be used as the first address information. For example, the operation S1702 can also determine whether the address information stored in the first address subfield in the cache entry corresponding to the object microinstruction group is obtained from the second sub-cache based on the first instruction fetch address. If obtained, the address information stored in the first address subfield is used as the first address information. If there is first address information, perform operation S1703. If there is no first address information, access the first sub-cache based on the first instruction fetch address to read the object microinstruction group from the first sub-cache.

[0154] Operation S1703, calculating a second instruction fetch address based on the first address information and the first instruction fetch address. For example, the principle of obtaining the second instruction fetch address in operation S1703 is similar to the principle of obtaining the second instruction fetch address in operation S1550, which will not be repeated here.

[0155] In operation S1704, determine whether there is second address information. For example, the operation S1704 can determine whether two address information are obtained based on the first instruction fetch address. If two address information are obtained, the other address information other than the first address information can be used as the second address information. For example, the operation S1704 can also determine whether the address information stored in the second address subfield in the cache entry corresponding to the object microinstruction group is obtained from the second sub-cache based on the first instruction fetch address. If it is obtained, the address information stored in the second address subfield is used as the second address information. If there is second address information, perform operation S1706. If there is no second address information, perform operation S1705.

[0156] Operation S1705: Access the second sub-cache based on the first instruction fetch address and the second instruction fetch address to read the target microinstruction group and the microinstruction group corresponding to the second instruction fetch address in parallel. After operation S1705, operation S1707 is performed.

[0157] Operation S1706, calculating a third instruction fetch address based on the first instruction fetch address and the second address information, and accessing the second sub-cache based on the first instruction fetch address, the second instruction fetch address and the third instruction fetch address to read three microinstruction groups in parallel. After operation S1706, operation S1707 is performed.

[0158] For example, if the address information stored in the address subfield is the end address of the microinstruction, the second address information can be added by 1 to obtain the third instruction fetch address. If the address information stored in the address subfield is the last few bytes of the microinstruction address of the last microinstruction in the microinstruction group, the high-order address of the first instruction fetch address can be added to the second address information, and then added by 1 to obtain the third instruction fetch address. It can be understood that the above calculation method for obtaining the second instruction fetch address is only used as an example to facilitate understanding of the present disclosure, and the embodiments of the present disclosure are not limited to this.

[0159] Operation S1707, determining whether the address information of the microinstruction group read based on the first instruction fetch address is consistent with the first address information. If consistent, operation S1709 is executed, and if inconsistent, operation S1708 is executed.

[0160] In operation S1708, the microinstruction group read based on the second instruction fetch address and the third instruction fetch address is abandoned. After operation S1708, operation S1712 is performed.

[0161] Operation S1709, determining whether there is a third instruction fetch address, if yes, executing operation S1710, if no, executing operation S1712.

[0162] Operation S1710, whether the address information of the microinstruction group read based on the second instruction fetch address is consistent with the second address information. If consistent, operation S1712 is executed, and if inconsistent, operation S1711 is executed.

[0163] In operation S1711, the microinstruction group read based on the third instruction fetch address is abandoned. After operation S1711, operation S1712 is performed.

[0164] Operation S1712, write the read microinstruction group into the microinstruction queue. Operation S1712 writes the unabandoned microinstruction group among the three read microinstruction groups into the microinstruction queue in parallel through the write port of the microinstruction queue, waiting for the aforementioned emission unit to distribute and emit it to the corresponding execution unit in the back end of the CPU core for execution.

[0165] Through the technical solution of at least one embodiment of the present disclosure, parallel reading of at least two microinstruction groups can be achieved, the reading bandwidth of the microinstruction cache can be improved, and the reading efficiency of the microinstruction group can be improved.

[0166] Based on the cache operation method provided by at least one embodiment of the present disclosure and the instruction processing method provided by at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides an electronic device. Fig.18 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0167] For example, Fig.18As shown, the electronic device 1800 includes a processor 1810 and a memory 1820. The memory 1820 is used to store non-temporary computer-readable instructions (e.g., one or more computer program modules). The processor 1810 is used to run the computer program instructions, and the computer program instructions are executed by the processor 1810 to perform the cache operation method and / or instruction processing method provided by any embodiment of the present disclosure. The memory 1820 and the processor 1810 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0168] The processor 1810 may be a device with data processing capability and / or program execution capability, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), and may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. For example, the central processing unit (CPU) may be an X86 or ARM architecture, etc. The processor 1810 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 1800 to perform desired functions.

[0169] For example, the memory 1820 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 1810 may run one or more computer program modules to implement various functions of the electronic device 1800. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0170] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 1800 can refer to the above description of the cache operation method and / or instruction processing method, which will not be repeated here.

[0171] At least some embodiments of the present disclosure also provide a non-transitory storage medium. Fig.19 A schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure. Fig.19As shown, the storage medium 1900 non-temporarily stores computer executable instructions 1901. When the non-temporary computer executable instructions 1901 are executed by a computer (including a processor), the cache operation method and / or instruction processing method provided by any embodiment of the present disclosure can be executed.

[0172] For example, one or more computer instructions may be stored on the storage medium 1900. Some of the computer instructions stored on the storage medium 1900 may be, for example, instructions for implementing one or more steps in the above-mentioned cache operation method and / or instruction processing method.

[0173] For example, the storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media. For example, the storage medium 1900 may include the memory 1920 in the aforementioned electronic device 1900.

[0174] The technical effects of the storage medium provided by the embodiments of the present disclosure can be referred to the corresponding descriptions of the cache operation method and / or instruction processing method in the above embodiments, which will not be repeated here.

[0175] Fig. 20 A schematic block diagram of an electronic device according to at least another embodiment of the present disclosure is shown.

[0176] At least some embodiments of the present disclosure also provide an electronic device, which includes the processor core of any of the above embodiments. The electronic device in the embodiments of the present disclosure may include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig. 20 The electronic device 2000 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0177] For example, Fig. 20As shown, in some examples, the electronic device 2000 includes a processing device (such as a central processing unit, a graphics processor, etc.) 2001, which can include a processor core of any of the above embodiments, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 2002 or a program loaded from a storage device 2008 to a random access memory (RAM) 2003. In RAM 2003, various programs and data required for the operation of the computer system are also stored. The processor 2001, ROM 2002, and RAM 2003 are connected to each other through a bus 2004. An input / output (I / O) interface 2005 is also connected to the bus 2004.

[0178] For example, the following components may be connected to the I / O interface 2005: an input device 2006 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 2007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 2008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 2009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 2009 may allow the electronic device 2000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 2010 is also connected to the I / O interface 2005 as needed. A removable medium 2011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 2010 as needed, so that a computer program read therefrom is installed into the storage device 2008 as needed.

[0179] Although Fig. 20 The electronic device 2000 including various devices is shown, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0180] For example, the electronic device 2000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 2009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0181] For example, the electronic device 2000 may include any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or may be a combination of any data processing device and hardware, which is not limited by the embodiments of the present disclosure.

[0182] There are a few points to note about this disclosure:

[0183] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0184] (2) Unless there is a conflict, the features of the same embodiment or different embodiments of the present disclosure may be combined with each other.

[0185] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A cache, including multiple cache entries, in, Each of the cache entries is configured to store information associated with a microinstruction group, and each of the cache entries includes an address field corresponding to the corresponding microinstruction group; In response to the target microinstruction group being filled in the microinstruction cache, address information of the microinstruction address of the target microinstruction group in the microinstruction cache is stored in an address field of a cache entry corresponding to the target microinstruction group.

2. The cache according to claim 1, wherein: The address information includes a microinstruction end address.

3. The cache according to claim 1 or 2, wherein: Each of the cache entries also includes a micro-tag field and a valid bit, The microtag field stores a microtag of the corresponding microinstruction group; the microtag is determined based on the microinstruction start address of the microinstruction group in the microinstruction cache; The validity information of the corresponding microinstruction group is stored in the valid bit.

4. The cache according to claim 1 or 2, wherein: The address field includes at least two address subfields; each of the address subfields is used to store address information of a microinstruction address; In response to the next microinstruction group immediately following the target microinstruction group being filled in the microinstruction cache and in the same cache block as the target microinstruction, address information of a microinstruction address of the next microinstruction in the microinstruction cache is stored in an address subfield of a cache entry corresponding to the target microinstruction group.

5. A microinstruction cache comprising: A first sub-cache is configured to provide a microinstruction group storage space; as well as A second sub-cache includes multiple cache entries, wherein each of the cache entries is configured to store information related to a microinstruction group, each of the cache entries includes an address field corresponding to the corresponding microinstruction group, and in response to an object microinstruction group being filled in the first sub-cache, address information of the microinstruction address of the object microinstruction group in the first sub-cache is stored in the address field of the cache entry corresponding to the object microinstruction group.

6. A processor core, comprising: A first sub-cache is configured to provide a microinstruction group storage space; A second sub-cache, comprising a plurality of cache entries, each of the cache entries being configured to store information associated with a microinstruction group, each of the cache entries comprising an address field corresponding to the corresponding microinstruction group; as well as The cache operation module is configured as follows: In response to the target microinstruction group being filled in the first sub-cache, obtaining a microinstruction address of the target microinstruction group in the first sub-cache; and The address information of the microinstruction address is stored in the address field of the cache entry corresponding to the target microinstruction group in the second sub-cache.

7. The processor core according to claim 6, wherein: The address information includes a microinstruction end address.

8. The processor core according to claim 6 or 7, wherein: The cache operation module is further configured to: In response to receiving an instruction fetch request for the target microinstruction group, obtaining a first instruction fetch address of the target microinstruction group; Acquire, from the second sub-cache, address information stored in an address field in a cache entry corresponding to the target microinstruction group; Acquire a second instruction fetch address of a first microinstruction group based on the acquired address information, wherein the first microinstruction group and the target microinstruction group are stored in the same cache block of the first sub-cache and are immediately after the target microinstruction group; as well as Based on the first instruction fetch address and the second instruction fetch address, the target microinstruction group and the first microinstruction group are read from the first sub-cache in parallel.

9. The processor core according to claim 8, wherein: The first sub-cache includes at least two read ports; The cache operation module is further configured to: Based on the first instruction fetch address and the second instruction fetch address, the target microinstruction group and the first microinstruction group are read in parallel through the at least two read ports.

10. The processor core according to claim 8, wherein: The address field includes at least two address subfields, each of which is used to store address information of a microinstruction address; The cache operation module is further configured to: Acquire a third instruction fetch address of a second microinstruction group based on the acquired address information, wherein the second microinstruction group and the target microinstruction group are stored in the same cache block of the microinstruction cache and are immediately after the first microinstruction group; and Based on the third instruction fetch address, the second microinstruction group is read in parallel with the target microinstruction group and the first microinstruction group.

11. The processor core according to claim 8, wherein the cache operation module is further configured to: In response to the address information of the microinstruction address of the target microinstruction group in the first sub-cache determined based on the target microinstruction group being different from the address information obtained from the address field in the cache entry corresponding to the target microinstruction group in the second sub-cache, the read first microinstruction group is abandoned.

12. The processor core according to claim 8, further comprising a microinstruction queue, wherein the microinstruction queue comprises a write port; wherein: The write port is configured to write the target microinstruction group and the first microinstruction group to the microinstruction queue in parallel.

13. The processor core according to claim 6, wherein: The address field includes at least two address subfields; each of the address subfields is used to store address information of a microinstruction address; The cache operation module is further configured to: In response to a first microinstruction group adjacent to the object microinstruction group being filled in the first sub-cache and in the same cache block as the object microinstruction group, address information of a microinstruction address of the first microinstruction group in the first sub-cache is stored in an address subfield of a cache entry corresponding to the object microinstruction group.

14. The processor core according to claim 13, wherein: The cache operation module is further configured to: In response to the third microinstruction group being filled in the first sub-cache, obtaining an index of the third microinstruction group based on a microinstruction address of the third microinstruction group; and In response to the index of the third microinstruction group being the same as the target index and the address subfield of the target cache entry being not fully stored, storing address information of the microinstruction address of the third microinstruction group in the first sub-cache in the address subfield where the address information is not stored, The target index is the index of the microinstruction group corresponding to the cache entry updated last time, and the target cache entry is the cache entry updated last time.

15. The processor core according to claim 14, wherein: The cache operation module is further configured to: In response to the index of the third microinstruction group being the same as the target index and the address subfield of the target cache entry being full, selecting a first cache entry other than the target cache entry, and storing address information of a microinstruction address of the third microinstruction group in the first sub-cache in the address field of the first cache entry; and The target cache entry is updated to the first cache entry.

16. The processor core according to claim 15, wherein: Each of the cache entries also includes a micro-tag field; The cache operation module is further configured to: Acquire the microtag of the second microinstruction group based on the microinstruction start address of the third microinstruction group; as well as In response to storing address information of a microinstruction address of the third microinstruction group in the first sub-cache in the address field of the first cache entry, a microtag of the third microinstruction group is stored in the microtag field of the first cache entry.

17. The processor core according to claim 14, wherein: The cache operation module is further configured to: In response to the index of the third microinstruction group being different from the target index, selecting a second cache entry other than the target cache entry, and storing address information of a microinstruction address of the third microinstruction group in the first sub-cache in an address field of the second cache entry; as well as The target index is updated to the index of the third microinstruction group, and the target cache entry is updated to the second cache entry.

18. The processor core according to claim 17, wherein: Each of the cache entries also includes a micro-tag field; The cache operation module is further configured to: Acquire the micro tag of the third microinstruction group based on the microinstruction starting address of the third microinstruction group; as well as In response to storing address information of a microinstruction address of the third microinstruction group in the first sub-cache in the address field of the second cache entry, a microtag of the third microinstruction group is stored in the microtag field of the second cache entry.

19. A cache operation method, comprising: In response to the target microinstruction group being populated in the microinstruction cache, selecting a target cache entry among a plurality of cache entries included in the cache; as well as The address field included in the target cache entry stores address information of the microinstruction address of the target microinstruction group in the microinstruction cache.

20. A method for processing an instruction, comprising: In response to the target microinstruction group being filled in the first sub-cache, obtaining a microinstruction address of the target microinstruction group in the first sub-cache; as well as The address information of the microinstruction address is stored in the address field of the cache entry corresponding to the target microinstruction group in the second sub-cache.

21. The method according to claim 20, further comprising: In response to receiving an instruction fetch request for the target microinstruction group, obtaining a first instruction fetch address of the target microinstruction group; Acquire, from the second sub-cache, address information stored in an address field in a cache entry corresponding to the target microinstruction group; Acquire a second instruction fetch address of a first microinstruction group based on the acquired address information, wherein the first microinstruction group and the target microinstruction group are stored in the same cache block of the first sub-cache and are immediately after the target microinstruction group; as well as Based on the first instruction fetch address and the second instruction fetch address, the target microinstruction group and the first microinstruction group are read from the first sub-cache in parallel.

22. An electronic device comprising: processor; as well as a memory including one or more computer program instructions; Wherein, the one or more computer program instructions are executed by the processor to execute the method according to any one of claims 19 to 21.

23. A computer-readable storage medium that non-transitorily stores computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the method described in any one of claims 19 to 21 is implemented.

Images