Instruction optimization method and device, processor, electronic device and storage medium

Abstract

An instruction optimization method and device, a processor, an electronic device and a storage medium. The instruction optimization method comprises: obtaining a compilation file, wherein in the compilation file, each of the multiple instructions included in the compilation file has an instruction information register fully configured before execution; based on the compilation file, optimizing the multiple instructions one by one according to the instruction order of the multiple instructions in the compilation file to determine the optimization information of each instruction, wherein the optimization information includes whether the instruction is optimized and the optimization is performed in response to the instruction, and the optimization information also includes the instruction information register to be eliminated corresponding to the instruction; optimizing the compilation file according to the optimization information to obtain an optimized compilation file, wherein in the optimized compilation file, the configuration of the instruction information register with repeated configuration of at least part of the instructions is eliminated.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an instruction optimization method, a processor, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Instructions in a processor are the basic units of operation, used to direct the processor to perform specific tasks or operations. Instructions usually consist of two parts: opcodes and operands. The opcodes specify the type of operation to be performed, such as addition, subtraction, logical operations, etc., while the operands are the data or addresses of the data required for the operation, which can be registers, memory addresses, etc.

[0003] The instruction execution process includes the following steps:

[0004] 1. Instruction fetch operation: According to the value in the program counter, the instruction to be executed is read from the program memory (or memory), and the read instruction is sent to the instruction register for temporary storage; at the same time, the program counter is incremented by 1 as the address of the next instruction to be executed.

[0005] 2. Decoding operation: Take out the operation code and address code of the instruction from the instruction register, decode the operation code, and determine the type of operation to be performed by the instruction; find the address of the required data or operand based on the address code.

[0006] 3. Execute instructions: According to the result of instruction decoding, the controller sends a series of corresponding control signals. For example, these control signals are used to control the various components inside the CPU (central processing unit) (such as arithmetic logic unit ALU, register group, etc.) to perform corresponding operations.

[0007] 4. Write back: The process of writing the calculation result back to the register or memory after the instruction is executed. Summary of the invention

[0008] At least one embodiment of the present disclosure provides an instruction optimization method, comprising: obtaining a compilation file, wherein in the compilation file, each of a plurality of instructions included in the compilation file has an instruction information register fully configured before execution, the instruction information register being configured to cache the instruction configuration information or input parameters required by the instruction in the execution instruction stage of each instruction, and the fully configured instruction information register comprises writing corresponding input parameters to at least one instruction information register used by the instruction in the execution instruction stage; based on the compilation file, performing optimization operations on the plurality of instructions one by one according to the instruction sequence of the plurality of instructions in the compilation file to determine optimization information of each instruction, wherein the optimization information comprises whether the instruction is optimized, and whether the instruction is optimized in response to the instruction, and the optimization information further comprises an instruction information register to be eliminated corresponding to the instruction, the instruction information register to be eliminated is a repeatedly configured instruction information register, and the repeated configuration comprises repeatedly writing the same parameter into the same instruction information register; optimizing the compilation file according to the optimization information to obtain an optimized compilation file, wherein in the optimized compilation file, the configuration of the repeatedly configured instruction information register of at least part of the instructions is eliminated.

[0009] For example, in the instruction optimization method provided by at least one embodiment of the present disclosure, for any one of the multiple instructions, based on the compilation file, the optimization operation for any one of the multiple instructions includes: determining whether any one of the instructions has a corresponding first instruction, wherein the first instruction at least satisfies a first preset condition, the first preset condition including being located before any one of the instructions according to the instruction sequence, sharing an instruction information register configuration with any one of the instructions, and being the closest to any one of the instructions in the compilation file that share an instruction information register configuration with any one of the instructions according to the instruction sequence, and the shared instruction information register configuration including using the same instruction information register; in response to any one of the instructions having a corresponding first instruction, performing a checking operation on the first instruction and any one of the instructions to determine the optimization information of any one of the instructions; in response to any one of the instructions not having a corresponding first instruction, determining that any one of the instructions does not need to be optimized.

[0010] For example, in the instruction optimization method provided by at least one embodiment of the present disclosure, determining whether any one of the instructions has a corresponding first instruction includes: in response to any one of the instructions satisfying a second preset condition, determining that any one of the instructions does not have a corresponding first instruction; in response to any one of the instructions not satisfying the second preset condition, searching the compiled file for an instruction satisfying the first preset condition as the second instruction; and determining whether to use the second instruction as the first instruction based on the position of the second instruction, wherein the second preset condition includes that any one of the instructions is the first instruction of a non-inline function, the first instruction in a loop that cannot be expanded, or the first instruction in a branch that cannot be expanded.

[0011] For example, in the instruction optimization method provided by at least one embodiment of the present disclosure, searching the compiled file for an instruction that meets the first preset condition as the second instruction includes: searching the compiled file forward in accordance with the instruction sequence for the nearest instruction that shares an instruction information register configuration with any of the instructions as the second instruction.

[0012] For example, in the instruction optimization method provided by at least one embodiment of the present disclosure, determining whether to use the second instruction as the first instruction based on the position of the second instruction includes: in response to the second instruction not being located in any branch or loop, determining that any one of the instructions has a corresponding first instruction and using the second instruction as the first instruction; in response to the second instruction being located in a branch or loop, and the branch or the loop being able to be expanded, determining that any one of the instructions has a corresponding first instruction and using the second instruction as the first instruction; in response to the second instruction being located in a branch or loop that cannot be expanded, determining that any one of the instructions does not have a corresponding first instruction.

[0013] For example, in the instruction optimization method provided by at least one embodiment of the present disclosure, a checking operation is performed on the first instruction and any one of the instructions, including: checking the configuration of each instruction register of the first instruction and any one of the instructions, and determining whether there are instruction information registers with the same configuration in the first instruction and any one of the instructions; in response to the existence of instruction information registers with the same configuration in the first instruction and any one of the instructions, determining that any one of the instructions needs to be optimized, and determining that the optimization information includes the instruction information registers with the same configuration; in response to the absence of instruction information registers with the same configuration in the first instruction and any one of the instructions, determining that any one of the instructions does not need to be optimized, wherein the same configuration includes writing the same parameters into the same instruction information registers.

[0014] For example, in the instruction optimization method provided by at least one embodiment of the present disclosure, checking the configuration of each instruction register of the first instruction and any one of the instructions includes: checking the configuration of the multiple instruction information registers, and for the i-th instruction information register among the multiple instruction information registers, checking the i-th instruction information register includes performing the following operations: comparing whether the i-th instruction information register of the first instruction and the i-th instruction information register of any one of the instructions are configured to write the same parameters; in response to the i-th instruction information register of the first instruction and the i-th instruction information register of any one of the instructions writing the same parameters, determining that there are instruction information registers with the same configuration in the first instruction and any one of the instructions, and setting the i-th instruction information register as the repeatedly configured instruction information register; in response to the i-th instruction information register of the first instruction and the i-th instruction information register of any one of the instructions not writing the same parameters, determining that there are no instruction information registers with the same configuration in the first instruction and any one of the instructions.

[0015] At least one embodiment of the present disclosure provides an instruction optimization device, comprising: an acquisition module, configured to acquire a compilation file, wherein in the compilation file, each of the multiple instructions included in the compilation file is fully configured with an instruction information register before execution, and the instruction information register is configured to cache the instruction configuration information or input parameters required by the instruction in the execution instruction stage of each instruction, and the complete configuration of the instruction information register includes writing corresponding input parameters to at least one instruction information register used by the instruction in the execution instruction stage; a first optimization module, configured to, based on the compilation file, optimize the multiple instructions according to the multiple instructions in the compilation file; The instructions in the compiled file are optimized one by one in sequence to determine the optimization information of each instruction, wherein the optimization information includes whether the instruction is optimized and whether the optimization is performed in response to the instruction, and the optimization information also includes the instruction information register to be eliminated corresponding to the instruction, the instruction information register to be eliminated is a repeatedly configured instruction information register, and the repeated configuration includes repeatedly writing the same parameter to the same instruction information register; a second optimization module is configured to optimize the compiled file according to the optimization information to obtain an optimized compiled file, wherein in the optimized compiled file, the configuration of the repeatedly configured instruction information register of at least part of the instructions is eliminated.

[0016] At least one embodiment of the present disclosure provides an electronic device, comprising: a memory, which non-transitorily stores computer-executable instructions; and a processor, which is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the instruction optimization method according to any embodiment of the present disclosure.

[0017] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the instruction optimization method according to any embodiment of the present disclosure is implemented.

[0018] In the instruction optimization method provided in at least one embodiment of the present disclosure, a compilation file is first obtained, and then based on the compilation file, multiple instructions are optimized one by one according to the instruction order of the multiple instructions in the compilation file to determine the optimization information of each instruction, wherein the optimization information includes whether the instruction is optimized, and the optimization is performed in response to the instruction, and the optimization information also includes the instruction information register to be eliminated corresponding to the instruction, the instruction information register to be eliminated is a repeatedly configured instruction information register, and the repeated configuration includes repeatedly writing the same parameter to the same instruction information register; the compilation file is optimized according to the optimization information to obtain an optimized compilation file, wherein in the optimized compilation file, the configuration of the repeatedly configured instruction information register of at least part of the instructions is eliminated. The instruction optimization method can still configure the complete information of the interface from the user's perspective, ensure the readability of the code, reduce the difficulty of programming, and there is no need to design the interface against the instruction, avoiding the risk of exposing the instruction set and hardware design; and the instruction optimization method can take into account performance and compatibility, reuse the parameters cached by some instruction information registers, avoid multiple loading of repeated parameters, and improve system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0020] Figure 1 A schematic structural diagram of a general-purpose graphics processing unit (GPGPU);

[0021] Figure 2A It is the instruction execution flow with instruction information register;

[0022] Figure 2B for the update process of the register with instruction information;

[0023] Figure 3 A schematic flow chart of an instruction optimization method provided for at least one embodiment of the present disclosure;

[0024] Figure 4 A schematic flow chart of an optimization operation provided in accordance with an embodiment of the present disclosure;

[0025] Figure 5A schematic diagram of an instruction optimization process provided for at least one embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of a process of checking operation provided for at least one embodiment of the present disclosure;

[0027] Figure 7 A schematic block diagram of an instruction optimization device provided for at least one embodiment of the present disclosure;

[0028] Figure 8 A schematic block diagram of an electronic device provided in accordance with an embodiment of the present disclosure;

[0029] Fig. 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components.

[0032] Figure 1 A schematic structural diagram of a general-purpose graphics processing unit (GPGPU).

[0033] like Figure 1As shown, the general-purpose graphics processor is actually an array of programmable multiprocessors. For example, the programmable multiprocessor can be a streaming processor cluster (SPC), for example, including Figure 1 The stream processor clusters 1, ..., and stream processor cluster M are shown, where M is a positive integer greater than 1. In a general-purpose graphics processor, one stream processor cluster processes one computing task, or multiple stream processor clusters process one computing task. Multiple stream processor clusters share data through a global cache or a global memory.

[0034] like Figure 1 As shown, taking stream processor cluster 1 as an example, one stream processor cluster includes multiple computing units, such as Figure 1 In the figure, there are computing units 1, 2, ..., N, where N is a positive integer. Each computing unit (CU) is used to perform arithmetic and logical operations, such as accumulation, reduction, conventional addition, subtraction, multiplication, and division. A computing unit includes multiple cores (also called computing cores or computing cores), each of which includes an arithmetic logic unit (ALU), a floating-point computing unit, etc. The computing core is used to perform specific computing tasks. In addition, the computing unit also includes registers (e.g. Figure 1 The register file in the computing unit and the shared memory are used to hierarchically store source data and destination data related to computing tasks. The shared memory in a computing unit is used to share data between the cores of the computing unit.

[0035] In parallel computing, computing tasks are generally performed by multiple threads. These threads are divided into multiple thread blocks before being executed in a general-purpose graphics processor (or parallel computing processor), and then distributed through the thread block distribution module ( Figure 1 The CPU (not shown) distributes multiple thread blocks to each computing unit. All threads in a thread block must be assigned to the same computing unit for execution. At the same time, the thread block is split into minimum execution thread bundles (or simply thread bundles, warps), each of which contains a fixed number of threads (or less than this fixed number), for example, 32 threads. Multiple thread blocks can be executed in the same computing unit or in different computing units.

[0036] In each compute unit, the warp scheduling / dispatching module ( Figure 1The thread warps are scheduled and allocated (not shown) so that multiple computing cores of the computing unit can run the thread warps. Depending on the number of computing cores in the computing unit, multiple thread warps in a thread block can be executed simultaneously or in time-sharing. Multiple threads in each thread warp will execute the same instruction. The memory execution instruction will be emitted to the shared memory in the computing unit or further emitted to the intermediate level cache or global cache or global memory for read and write operations, etc.

[0037] A processor (such as a general-purpose graphics processor, a central processing unit, etc.) can design an instruction information register for an instruction to cache instruction configuration information or data during the execution of the instruction. For example, the instruction configuration information may include the instruction type (such as arithmetic instructions, logic instructions, data transfer instructions, control instructions, etc.), addressing mode (such as direct addressing, indirect addressing, register addressing, base address displacement addressing, etc.), instruction behavior (the operation specified by the opcode, and instructions of the same type may also have different instruction behaviors), instruction synchronization or timing control, and other configuration information related to the instruction. The present disclosure does not limit the specific content of the instruction configuration information. Data is, for example, the input parameters of the instruction, such as the operands of the instruction, which describe the action object of the instruction.

[0038] For example, multiple instruction information registers can be provided, and these instruction information registers can cache the input parameters or configuration information of each instruction when the instruction is executed. Subsequent instructions can continue to use the information cached in the instruction information register when they are executed, or they can update the information in the instruction information register according to actual needs for use by the instruction currently to be executed.

[0039] Figure 2A It is the instruction execution flow with instruction information register.

[0040] like Figure 2A As shown, the instruction execution process includes instruction fetching, decoding, executing instructions and writing back.

[0041] like Figure 2A As shown, when executing instructions, n instruction information registers are configured for the process of executing instructions ( Figure 2ARegister 1, register 2, ..., register n-1, register n in the instruction information register, where n is a positive integer greater than 1), is used to cache instruction configuration information or data of each instruction when it is executed. For example, for a Load instruction, when executing the Load instruction, information such as the data dimension used by the Load instruction may be stored in the instruction information register; when executing the Store instruction, information such as the data dimension used by the Store instruction may be stored in the instruction information register; or, if information such as the data dimension of the Load instruction corresponding to the Store instruction is also stored in the instruction information register, the data dimension may also reuse information such as the data dimension stored by the corresponding Load instruction.

[0042] Currently, there are usually two ways to configure the instruction information register.

[0043] In one approach, each instruction independently configures the instruction information registers that need to be updated for the instruction. For example, before instruction 0 is executed, registers 1 to n are configured, and the configuration here includes writing corresponding input parameters to registers 1 to n. Before instruction 1 is executed, assuming that it is determined that only the values ​​of instruction information register 1 and instruction information register n need to be updated when instruction 1 is executed, and the values ​​of other instruction information registers may remain unchanged, then only instruction information register 1 and instruction information register n are configured before instruction 1 is executed. Before instruction 2 is executed, assuming that it is determined that only the values ​​of instruction information register 2 and instruction information register n-1 need to be updated when instruction 2 is executed, then only instruction information register 2 and instruction information register n-1 are configured before instruction 2 is executed. Before instruction 3 is executed, assuming that it is determined that the values ​​of all instruction information registers do not need to be changed, then no instruction information register may be configured before instruction 3 is executed.

[0044] Figure 2B This is the update process of the register with instruction information.

[0045] like Figure 2B As shown, when instruction 0 is executed, all n instruction information registers are updated. When instruction 1 is executed, instruction information register 1 is updated, instruction information register n is updated, and other instruction information registers do not need to be updated; when instruction 2 is executed, instruction information register 2 is updated, instruction information register n-1 is updated, and other instruction information registers do not need to be updated; when instruction 3 is executed, all instruction information registers are not updated.

[0046] This method requires direct use of instructions for programming and designing interfaces based on instructions, which consumes manpower and is difficult to program. In addition, the function of hardware inheriting instructions cannot be used. The interface needs to configure the instruction information register of the instruction separately each time, exposing the instruction set design and hardware design, increasing risks. In addition, since each instruction needs to trace back to the last configuration when it is not configured to determine the current value of the instruction information register, the code readability is poor and the programming difficulty is increased.

[0047] In another method, all instruction information registers are configured for each instruction. For example, n instruction information registers are configured before each instruction is executed. This method will lead to a significant performance degradation. For example, in the case of Store and Load instructions, information such as data dimensions will be used multiple times. This method will cause the data dimensions and other information to be reloaded each time the Store and Load instructions are executed, resulting in performance degradation.

[0048] At least one embodiment of the present disclosure provides an instruction optimization method, a processor, an electronic device, and a non-transitory computer-readable storage medium. The instruction optimization method includes: obtaining a compiled file, wherein in the compiled file, each instruction is fully configured with all instruction information registers before execution, and each instruction information register is configured to cache the instruction configuration information or input parameters required by the instruction in the execution instruction stage of each instruction; based on the compiled file, optimizing multiple instructions in the compiled file one by one according to the instruction order of the multiple instructions in the compiled file to determine the optimization information of each instruction, wherein the optimization information includes whether the instruction is optimized, and register information of the instruction information register to be eliminated in response to the instruction being optimized, the instruction information register to be eliminated is a repeatedly configured instruction information register, and the repeated configuration includes repeatedly writing the same parameters into the same instruction information register; optimizing the compiled file according to the optimization information to obtain an optimized compiled file, wherein in the optimized compiled file, the configuration of the repeatedly configured instruction information register of at least part of the instructions is eliminated.

[0049] In at least one embodiment, the instruction optimization method can still configure complete information for the interface from the user's perspective, ensuring code readability and reducing programming difficulty, and there is no need to design the interface against instructions, thus avoiding the risk of exposing the instruction set and hardware design; and the instruction optimization method can take into account both performance and compatibility, reuse parameters cached by some instruction information registers, avoid multiple loading of repeated parameters, and improve system performance.

[0050] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0051] Figure 3 A schematic flow chart of an instruction optimization method provided for at least one embodiment of the present disclosure.

[0052] like Figure 3 As shown, the instruction optimization method provided by at least one embodiment of the present disclosure includes steps S10-S30.

[0053] In step S10, a compiled file is obtained.

[0054] For example, in a compiled file, each of the multiple instructions included in the compiled file fully configures the instruction information register before execution. As mentioned above, the instruction information register is configured to cache the instruction configuration information or input parameters required by the instruction in the execution instruction stage of each instruction.

[0055] For example, the multiple instructions here refer to instructions that use the instruction information register. Of course, the compiled file may also include instructions that do not use the instruction information register, and the present disclosure does not make any specific limitations on this.

[0056] For example, before executing the instruction, the instruction information register is fully configured. For example, fully configuring the instruction information register includes writing corresponding parameters to at least one instruction information register, where the at least one instruction information register is the instruction information register that the instruction will use during the instruction execution phase, for example, writing corresponding input parameters to all instruction information registers used by the instruction during the instruction execution phase, and the at least one instruction information register may obtain relevant information in advance through instruction design or hardware design.

[0057] For example, for each instruction that needs to use the instruction information register, the instruction information register is fully configured before execution, for example, according to the needs of the instruction, the required input parameters are written to each instruction information register used by the instruction. For example, this process can be implemented through a template function.

[0058] For example, the input parameters of the instruction information registers used by each of the above instructions can be fully configured in the software interface, and then compiled using a compiler to obtain a compiled file, so that each instruction using the instruction information register in the compiled file will fully configure the instruction information register.

[0059] In step S20, based on the compilation file, optimization operations are performed on the multiple instructions one by one according to the instruction sequence of the multiple instructions in the compilation file to determine optimization information of each instruction.

[0060] For example, the optimization information includes whether the instruction is optimized and whether the optimization is performed in response to the instruction. The optimization information also includes the instruction information register to be eliminated corresponding to the instruction. The instruction information register to be eliminated is a repeatedly configured instruction information register. The repeated configuration includes repeatedly writing the same parameters into the same instruction information register.

[0061] For example, the instruction sequence in the compilation file is the arrangement order of the instructions in the source code during the compilation process. The optimization operation is performed on multiple instructions in sequence according to the instruction sequence to determine the optimization information of each instruction.

[0062] For example, if it is determined that a certain instruction needs to be optimized, the optimization information includes the instruction information registers with duplicate configurations that need to be eliminated for the instruction, for example, these duplicated instruction information registers repeatedly write the same parameters to the same instruction information registers. For example, in the compilation file, before instruction 0 is executed, it is configured to write input parameter r0 to instruction information register 0 and output parameter r1 to instruction information register 1, and before instruction 1 is executed, it is configured to write input parameter r0 to instruction information register 0 and output parameter r1 to instruction information register 1. Therefore, instruction information register 0 and instruction information register 1 in instruction 1 are instruction information registers with duplicate configurations, because the same input parameters are repeatedly written to instruction information register 0 and instruction information register 1.

[0063] Figure 4 A schematic flowchart of an optimization operation provided for an embodiment of the present disclosure.

[0064] like Figure 4 As shown, the optimization operation for any instruction includes steps S201-S203.

[0065] In step S201, it is determined whether any instruction has a corresponding first instruction.

[0066] For example, the first instruction satisfies at least a first preset condition, the first preset condition includes being executed before any instruction, sharing an instruction information register with any instruction, and being the closest to any instruction in the instruction order among all instructions in the compilation file that share an instruction information register with any instruction, and the shared instruction information register includes the same instruction information register used.

[0067] In step S202, in response to any one instruction having a corresponding first instruction, a checking operation is performed on the first instruction and any one instruction to determine optimization information of any one instruction.

[0068] In step S203, in response to any instruction not having a corresponding first instruction, it is determined that any instruction does not need to be optimized.

[0069] For example, the first preset condition includes the following three conditions.

[0070] Condition 1: It is located before any instruction according to the instruction sequence. For example, in a compiled file, it is located before any instruction according to the instruction sequence.

[0071] Condition 2: Sharing the instruction information register with any other instruction. Sharing here means using the same instruction information register. For example, the first instruction uses instruction information register 1 and instruction information register 2, and any other instruction also uses instruction information register 1 and instruction information register 2.

[0072] Condition 3: Among all the instructions in the compilation file that share the instruction information register configuration with any instruction, the one that is closest to any instruction in the instruction sequence is the closest. For example, if there are multiple instructions in the compilation file that specify the use of instruction information register 1, instruction information register 2, and instruction information register 3, condition 3 requires that among all the instructions that use instruction information register 1, instruction information register 2, and instruction information register 3, the one that is located before any instruction in the instruction sequence is the closest to any instruction.

[0073] For example, the first instruction needs to at least meet the first preset condition, and the first instruction needs to meet other requirements as needed, such as the first instruction is not located in any branch or loop, or the first instruction is located in an expandable branch or loop.

[0074] For example, in some embodiments, step S201 may include: in response to any instruction satisfying a second preset condition, determining that any instruction does not have a corresponding first instruction; in response to any instruction not satisfying the second preset condition, searching for an instruction satisfying the first preset condition from a compiled file as a second instruction; and determining whether to use the second instruction as the first instruction based on the position of the second instruction, wherein the second preset condition includes that any instruction is the first instruction of a non-inline function, the first instruction in a loop that cannot be expanded, or the first instruction in a branch that cannot be expanded.

[0075] For example, if any instruction is the first instruction of a non-inline function, the first instruction in a loop that cannot be expanded, or the first instruction in a branch that cannot be expanded, it means that any instruction is a new start and cannot be optimized. At this time, it is considered that any instruction does not have a corresponding first instruction, and any instruction does not need to be optimized, and the optimization operation continues on the next instruction.

[0076] If any instruction does not meet the second preset condition, the nearest instruction that shares the instruction information register configuration with any instruction is searched forward from the compiled file in the instruction sequence as the second instruction, and whether to use the second instruction as the first instruction is determined based on the position of the second instruction.

[0077] For example, in some embodiments, determining whether to use the second instruction as the first instruction based on the position of the second instruction may include: in response to the second instruction not being located in any branch or loop, determining that any instruction has a corresponding first instruction and using the second instruction as the first instruction; in response to the second instruction being located in a branch or loop, and the branch or loop being able to be expanded, determining that any instruction has a corresponding first instruction and using the second instruction as the first instruction; in response to the second instruction being located in a branch or loop that cannot be expanded, determining that any instruction does not have a corresponding first instruction, and the any instruction does not need to be optimized, and continuing to perform optimization operations on the next instruction.

[0078] For example, if the second instruction itself is not in a branch or a loop, it can be directly determined that the second instruction can be used as the first instruction for subsequent checking operations.

[0079] If the second instruction is located in a branch or loop, it is necessary to further determine whether the branch or loop can be expanded. For example, if the branch or loop can be expanded, it can be determined that the second instruction is indeed the instruction closest to any instruction, and the second instruction can be used as the first instruction for subsequent inspection operations.

[0080] If the branch or loop cannot be expanded, it is impossible to determine whether the second instruction is indeed the instruction closest to any instruction. For example, in a loop, it is impossible to determine whether the second instruction belongs to the last operation executed in the loop. Therefore, it is determined that any instruction does not have a corresponding first instruction, and any instruction does not need to be optimized, and the optimization operation continues to the next instruction.

[0081] For example, in some embodiments, step S202 may include: checking the configuration of each instruction register of the first instruction and any instruction, and determining whether there are instruction information registers with the same configuration in the first instruction and any instruction; in response to the existence of instruction information registers with the same configuration in the first instruction and any instruction, determining that any instruction needs to be optimized, and determining that the optimization information includes instruction information registers with the same configuration; in response to the absence of instruction information registers with duplicate configuration in the first instruction and any instruction, determining that any instruction does not need to be optimized, wherein the same configuration includes writing the same parameters into the same instruction information registers.

[0082] For example, checking the configuration of each instruction register of the first instruction and any one instruction includes: checking the configuration of multiple instruction information registers, for the i-th instruction information register among the multiple instruction information registers, checking the i-th instruction information register includes performing the following operations: comparing whether the i-th instruction information register of the first instruction and the i-th instruction information register of any one instruction are configured to write the same parameters; in response to the i-th instruction information register of the first instruction and the i-th instruction information register of any one instruction writing the same parameters, determining that there are instruction information registers with the same configuration in the first instruction and any one instruction, and treating the i-th instruction information register as a repeatedly configured instruction information register; in response to the i-th instruction information register of the first instruction and the i-th instruction information register of any one instruction not writing the same parameters, determining that there are no instruction information registers with the same configuration in the first instruction and any one instruction.

[0083] For example, in one example, it is assumed that it is determined that the first instruction uses instruction information register 0, instruction information register 1, and instruction information register 2, and any instruction currently performing the optimization operation (hereinafter referred to as instruction 0) uses instruction information register 0, instruction information register 1, and instruction information register 2. According to the instruction sequence, the first instruction is before instruction 0 and is closest to instruction 0 relative to other instructions that use instruction information register 0, instruction information register 1, and instruction information register 2. The process of obtaining the first instruction is as described in step S201, and will not be repeated here.

[0084] For example, after determining the first instruction, compare whether the instruction information register 0 of instruction 0 and the instruction information register 0 of the first instruction are configured to write the same parameters. If the instruction information register 0 of instruction 0 and the instruction information register 0 of the first instruction are configured to write the same input parameters, it is determined that the instruction information register 0 is a repeatedly configured register, the optimization information of instruction 0 includes that instruction 0 needs to be optimized, and the instruction information register to be eliminated includes instruction information register 0. If the instruction information register 0 of instruction 0 and the instruction information register 0 of the first instruction are configured to write different input parameters, continue to check instruction information register 1.

[0085] Compare whether the instruction information register 1 of instruction 0 and the instruction information register 1 of the first instruction are configured to write the same parameters. If the instruction information register 1 of instruction 0 and the instruction information register 1 of the first instruction are configured to write the same input parameters, it is determined that the instruction information register is a duplicately configured register, the optimization information of instruction 0 includes that instruction 0 needs to be optimized, and the instruction information register to be eliminated includes instruction information register 1. If the instruction information register 1 of instruction 0 and the instruction information register 1 of the first instruction are configured to write different input parameters, continue to check instruction information register 2.

[0086] Compare whether the instruction information register 2 of instruction 0 and the instruction information register 2 of the first instruction are configured to write the same parameters. If the instruction information register 2 of instruction 0 and the instruction information register 2 of the first instruction are configured to write the same input parameters, it is determined that the instruction information register 2 is a repeatedly configured register, the optimization information of instruction 0 includes that instruction 0 needs to be optimized, and the instruction information register to be eliminated includes instruction information register 2. If the instruction information register 2 of instruction 0 and the instruction information register 2 of the first instruction are configured to write different input parameters, the check operation on instruction 0 is terminated. If the three instruction information registers of instruction 0 and the three instruction information registers of the first instruction are all configured to write different input parameters, it is determined that instruction 0 does not need to be optimized.

[0087] Figure 5 A schematic diagram of the instruction optimization process provided by at least one embodiment of the present disclosure. Figure 5 , specifically describes the instruction optimization execution process.

[0088] like Figure 5 As shown, first, a compiled file is obtained. The specific process of obtaining the compiled file can refer to the related description of the aforementioned step S10, which will not be repeated here.

[0089] After that, determine whether to enable optimization. If not, exit the optimization mode directly and use the Debug mode to debug the compiled file.

[0090] If it is determined to enable optimization, multiple instructions using the instruction information register in the compiled file are traversed and optimization operations are performed on them one by one.

[0091] Specifically, if Figure 5 As shown, for the current instruction currently being optimized, it is determined whether it meets the second preset condition, that is, whether the instruction is the first instruction of a non-inline function, the first instruction in a loop that cannot be expanded, or the first instruction in a branch that cannot be expanded. If the instruction meets the second preset condition, that is, the instruction is the first instruction of a non-inline function, the first instruction in a loop that cannot be expanded, or the first instruction in a branch that cannot be expanded, then the optimization operation on the instruction is exited and the optimization operation on the next instruction is continued.

[0092] If the instruction does not meet the second preset condition, a second instruction of the instruction is determined. For example, the nearest instruction that shares the instruction information register configuration with the instruction is searched forward in the compiled file according to the instruction sequence as the second instruction. If the second instruction cannot be found, the optimization operation of the instruction is exited and the optimization operation of the next instruction is continued.

[0093] Afterwards, if Figure 5As shown, it is determined whether the second instruction is located in a branch or a loop. If the second instruction is not located in a branch or a loop, the second instruction is used as the first instruction for subsequent checking operations. If it is located in a branch or a loop, if the second instruction is located in an expandable branch or loop, the second instruction is used as the first instruction for subsequent checking operations. If the second instruction is located in a non-expandable branch or loop, the optimization operation of the instruction is exited and the optimization operation of the next instruction is continued.

[0094] The above process is executed repeatedly until multiple instructions are traversed, the optimization process is ended, and the optimization information is obtained.

[0095] Figure 6 A process diagram of an inspection operation provided for at least one embodiment of the present disclosure.

[0096] like Figure 6 As shown, first, the instruction information register configuration of the first instruction is obtained.

[0097] Then, the configurations of the respective instruction registers of the first instruction and the instruction currently undergoing the optimization operation are checked.

[0098] For example, assuming that the instruction information register configuration shared by the first instruction and the current instruction includes n instruction information registers, the first instruction information register to the nth instruction information register are checked cyclically.

[0099] For example, first i=1, check the first instruction information register of the first instruction and the first instruction information register of the current instruction to compare whether they are configured to write the same parameters; if the same parameters are written, it is considered that the first instruction information register of the first instruction and the first instruction information register of the current instruction are configured the same, and the first instruction information register of the first instruction is used as a repeatedly configured instruction information register, and then execute i+1 to check the second instruction information register of the first instruction and the second instruction information register of the current instruction; if different parameters are written, it is considered that the first instruction information register of the first instruction and the first instruction information register of the current instruction are configured differently, execute i+1, and continue to check the second instruction information register of the first instruction and the second instruction information register of the current instruction.

[0100] When i=2, check the second instruction information register of the first instruction and the second instruction information register of the current instruction to compare whether they are configured to write the same parameters; if the same parameters are written, it is considered that the second instruction information register of the first instruction and the second instruction information register of the current instruction are configured the same, and the second instruction information register of the first instruction is used as a repeated instruction information register, and then execute i+1 to continue checking the third instruction information register of the first instruction and the third instruction information register of the current instruction; if different parameters are written, it is considered that the second instruction information register of the first instruction and the second instruction information register of the current instruction are configured differently, and execute i+1 to check the third instruction information register of the first instruction and the third instruction information register of the current instruction.

[0101] Repeat the above process until n instruction information registers are checked, the optimization information of the current instruction is obtained, and the checking operation of the current instruction is terminated. For example, if the checking process finds that there are repeated instruction information registers, the optimization information includes optimizing the instruction and the optimization information includes these instruction information registers. If the checking process does not find repeated instruction information registers, the optimization information includes not optimizing the first instruction.

[0102] Afterwards, in step S30, the compiled file is optimized according to the optimization information to obtain an optimized compiled file.

[0103] For example, in the optimized compiled file, the configuration of the instruction information register of the repeated configuration of at least part of the instructions is eliminated.

[0104] For example, in step S20, the optimization information of each instruction can be recorded, such as processing the instruction information register to be eliminated through a mask operation. In step S30, the compiler can automatically generate an optimized compiled file based on the optimization information obtained in step S20, and the configuration of the repeatedly configured instruction information register is eliminated in the optimized compiled file, thereby avoiding and reducing the repeated configuration of the same input parameters of the same register, and improving system performance.

[0105] In the above embodiment, when first obtaining the compiled file, the user does not need to pay attention to the underlying hardware design and instruction set, and configures the instruction information register for each instruction according to the requirements of the instruction itself. For example, the instruction information register can be configured in the form of a template function, which is simple to program, has good code readability, and reduces the manpower consumption of programming; then, when the optimization is selected to be turned on, each instruction is automatically optimized, the optimization information is determined, and then the compiled file is optimized according to the optimization information to obtain the optimized compiled file. The optimized compiled file eliminates the instruction information registers with repeated configurations, reduces and avoids the loading of repeated instruction information registers, improves performance, and avoids the exposure of instruction sets and hardware design interfaces.

[0106] At least one embodiment of the present disclosure also provides an instruction optimization device. Figure 7 A schematic block diagram of an instruction optimization device provided for at least one embodiment of the present disclosure.

[0107] like Figure 7 As shown, the instruction optimization device 100 includes an acquisition module 101 , a first optimization module 102 and a second optimization module 103 .

[0108] The acquisition module 101 is configured to acquire a compilation file, wherein, in the compilation file, each instruction of the multiple instructions included in the compilation file has an instruction information register fully configured before execution, and the instruction information register is configured to cache the instruction configuration information or input parameters required by the instruction in the execution instruction stage during the execution instruction stage of each instruction, and the complete configuration of the instruction information register includes writing corresponding input parameters to at least one instruction information register used by the instruction in the execution instruction stage.

[0109] The first optimization module 102 is configured to perform optimization operations on multiple instructions one by one according to the instruction order of the multiple instructions in the compilation file based on the compilation file to determine the optimization information of each instruction, wherein the optimization information includes whether the instruction is optimized and whether the optimization is performed in response to the instruction, and the optimization information also includes the instruction information register to be eliminated corresponding to the instruction, the instruction information register to be eliminated is a repeatedly configured instruction information register, and the repeated configuration includes repeatedly writing the same parameters into the same instruction information register.

[0110] The second optimization module 103 is configured to optimize the compiled file according to the optimization information to obtain an optimized compiled file, wherein in the optimized compiled file, the configuration of the instruction information register of the repeated configuration of at least part of the instructions is eliminated.

[0111] For example, the acquisition module 101, the first optimization module 102, and the second optimization module 103 include codes and programs stored in the memory. The acquisition module 101, the first optimization module 102, and the second optimization module 103 are implemented as a central processing unit (CPU) or other forms of processing units with instruction optimization capability and / or instruction execution capability. The processing unit can be a general-purpose processor, and can also be a single-chip microcomputer, a microprocessor, a digital signal processor, a dedicated image processing chip, or a field programmable logic array, etc. The acquisition module 101, the first optimization module 102, and the second optimization module 103 execute the code and program to implement some or all of the functions of the acquisition module 101, the first optimization module 102, and the second optimization module 103 as described above. For example, the acquisition module 101, the first optimization module 102, and the second optimization module 103 can be a circuit board or a combination of multiple circuit boards for implementing the functions as described above. In the embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) firmware stored in the memory that can be executed by the processor.

[0112] It should be noted that the acquisition module 101 can be used to implement Figure 3 Step S10 shown; the first optimization module 102 can be used to implement Figure 3 Step S20 shown; the second optimization module 103 can be used to implement Figure 3 Step S30 shown. Therefore, for the specific description of the functions that can be implemented by the acquisition module 101, reference can be made to the relevant description of step S10 in the embodiment of the above-mentioned instruction optimization method. For the specific description of the functions that can be implemented by the first optimization module 102, reference can be made to the relevant description of step S20 in the embodiment of the above-mentioned instruction optimization method. For the specific description of the functions that can be implemented by the second optimization module 103, reference can be made to the relevant description of step S30 in the embodiment of the above-mentioned instruction optimization method. The repeated parts will not be repeated here. In addition, the instruction optimization device 100 can achieve technical effects similar to those of the aforementioned instruction optimization method, which will not be repeated here.

[0113] It should be noted that in at least one embodiment of the present disclosure, the instruction optimization device 100 may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or in other applicable ways.

[0114] For example, the instruction optimization device 100 may be implemented in hardware, software, or a combination of hardware and software, and the present disclosure does not impose any specific limitations on this.

[0115] The instruction optimization method provided by at least one embodiment of the present disclosure can achieve similar technical effects as the instruction optimization method described above, and will not be described in detail here.

[0116] The instruction optimization method and instruction optimization device provided in at least one embodiment of the present disclosure can be applied to different systems or devices, such as Figure 8 The electronic device 300 shown. The electronic device 300 can be a terminal, such as a mobile phone terminal, a tablet computer, a laptop computer, an AR device, a VR device, a vehicle terminal, etc., and can also be a server, etc. The instruction optimization method provided in at least one embodiment of the present disclosure can be applied to electronic devices 300 involving CPU, high performance computing (High Performance Computing, HPC for short) and artificial intelligence (Artificial Intelligence, AI) and other scenarios. Of course, the present disclosure is not limited to this, and any scenario, device, device, etc. involving instructions can adopt the instruction optimization method or instruction optimization device provided in at least one embodiment of the present disclosure.

[0117] In some embodiments, the instruction optimization device provided in at least one embodiment of the present disclosure may be a chip, for example, the chip is a system-on-a-chip (SoC). The system-on-a-chip includes a processor, which may be a single-core processor or a multi-core processor, a memory, an I / O interface, etc.

[0118] Figure 8 The following is a schematic block diagram of an electronic device provided by an embodiment of the present disclosure. Figure 8 As shown, the electronic device 300 is suitable for implementing the instruction optimization method provided by the embodiment of the present disclosure. It should be noted that Figure 8 The components of the electronic device 300 shown are merely exemplary and non-limiting. The electronic device 300 may also have other components according to actual application requirements.

[0119] like Figure 8 As shown, the electronic device 300 may include a processing device 301 (eg, a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to non-transitory computer-readable instructions stored in a memory to implement various functions.

[0120] For example, when the computer readable instruction is executed by the processing device 301, one or more steps in the instruction optimization method described in any of the above embodiments may be executed. It should be noted that for a detailed description of the processing process of the instruction optimization method, reference may be made to the relevant description in the above-mentioned instruction optimization method embodiment.

[0121] For example, the memory may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) 303 and / or cache memory (cache), etc. For example, computer-readable instructions may be loaded from storage device 308 into random access memory (RAM) 303 to run computer-readable instructions. Non-volatile memory may include, for example, read-only memory (ROM) 302, hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. Various applications and various data, such as style images, and various data used and / or generated by applications, etc., may also be stored in the computer-readable storage medium.

[0122] For example, the processing device 301, the read only memory (ROM) 302, and the random access memory (RAM) 303 are connected to each other through a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0123] Typically, the following devices may be connected to the input / output (I / O) interface 305: input devices 306 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 308 including, for example, a magnetic tape, a hard disk, a flash memory, etc.; and communication devices 309. The communication devices 309 may allow the electronic device 300 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 7 An electronic device 300 having various devices is shown, but it should be understood that it is not required to implement or have all the devices shown, and the electronic device 300 may alternatively implement or have more or fewer devices. For example, the processing device 301 can control other components in the electronic device 300 to perform the desired functions. The processing device 301 can be a device with instruction optimization capability and / or program execution capability such as a central processing unit (CPU), a tensor processing unit (TPU) or a graphics processing unit GPU. The central processing unit (CPU) can be an X86, ARM, RISC-V architecture, etc. The GPU can be directly integrated into the SOC, directly integrated into the motherboard, or built into the north bridge chip of the motherboard.

[0124] Fig. 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Fig. 9As shown, the storage medium 400 may be a non-transitory computer-readable storage medium, and one or more computer-readable instructions 401 may be non-transitory stored on the storage medium 400. For example, when the computer-readable instructions 401 are executed by a processor, one or more steps in the instruction optimization method described above may be executed.

[0125] For example, the storage medium 400 may be applied in the electronic device 300 . For example, the storage medium 400 may include the storage device 308 in the electronic device 300 .

[0126] For example, the storage device may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and the processor may run the computer-readable instructions to implement various functions of the processor. Various applications and various data may also be stored in the storage medium.

[0127] For example, the storage medium may include a memory card of a smart phone, a cache component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other applicable storage media.

[0128] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0129] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0130] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0131] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0132] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0133] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0134] There are a few points to note about this disclosure:

[0135] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to the general design.

[0136] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0137] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An instruction optimization method, comprising: Obtaining a compilation file, wherein, in the compilation file, each of the multiple instructions included in the compilation file fully configures an instruction information register before execution, and the instruction information register is configured to cache instruction configuration information or input parameters required by the instruction in the execution instruction stage during the execution instruction stage of each instruction, and the fully configuring the instruction information register includes writing corresponding parameters to at least one instruction information register used by the instruction in the execution instruction stage; Based on the compilation file, the plurality of instructions are optimized one by one according to the instruction order of the plurality of instructions in the compilation file to determine optimization information of each instruction, wherein the optimization information includes whether the instruction is optimized, and in response to determining that the instruction is optimized, the optimization information also includes an instruction information register to be eliminated corresponding to the instruction, the instruction information register to be eliminated is a repeatedly configured instruction information register, and the repeated configuration includes repeatedly writing the same parameter into the same instruction information register; The compiled file is optimized according to the optimization information to obtain an optimized compiled file, wherein in the optimized compiled file, configurations of instruction information registers of repeated configurations of at least part of the instructions are eliminated.

2. The instruction optimization method according to claim 1, wherein: For any one of the multiple instructions, based on the compilation file, the optimization operation for the any one of the instructions includes: Determine whether any of the instructions has a corresponding first instruction, wherein the first instruction satisfies at least a first preset condition, the first preset condition including being located before any of the instructions according to the instruction sequence, sharing an instruction information register configuration with any of the instructions, and being the instruction in the compiled file that shares an instruction information register configuration with any of the instructions, being closest to any of the instructions according to the instruction sequence, and the shared instruction information register configuration including using the same instruction information register; In response to any one of the instructions having a corresponding first instruction, performing a checking operation on the first instruction and the any one of the instructions to determine optimization information of the any one of the instructions; In response to any one of the instructions not having a corresponding first instruction, it is determined that any one of the instructions does not need to be optimized.

3. The instruction optimization method according to claim 2, wherein: Determining whether any of the instructions has a corresponding first instruction includes: In response to any one of the instructions satisfying a second preset condition, determining that any one of the instructions does not have a corresponding first instruction, In response to any one of the instructions not satisfying the second preset condition, searching the compiled file for an instruction satisfying the first preset condition as the second instruction, and determining whether to use the second instruction as the first instruction based on the position of the second instruction, The second preset condition includes that any one of the instructions is the first instruction of a non-inline function, the first instruction in a loop that cannot be expanded, or the first instruction in a branch that cannot be expanded.

4. The instruction optimization method according to claim 3, wherein: Searching the compiled file for an instruction that satisfies the first preset condition as the second instruction includes: In the compiled file, the nearest instruction that shares the instruction information register configuration with any one of the instructions is searched forward according to the instruction sequence as the second instruction.

5. The instruction optimization method according to claim 3, wherein: Determining whether to use the second instruction as the first instruction based on the position of the second instruction includes: In response to the second instruction not being located in any branch or loop, determining that any one of the instructions has a corresponding first instruction and using the second instruction as the first instruction; In response to the second instruction being located in a branch or a loop, and the branch or the loop being able to be unrolled, determining that any one of the instructions has a corresponding first instruction and using the second instruction as the first instruction; In response to the second instruction being located in a branch or loop that cannot be expanded, it is determined that any one of the instructions does not have a corresponding first instruction.

6. The instruction optimization method according to claim 2, wherein: Performing a check operation on the first instruction and any one of the instructions includes: Checking the configuration of each instruction register of the first instruction and any one of the instructions to determine whether there are instruction information registers with the same configuration in the first instruction and any one of the instructions; In response to the existence of instruction information registers with the same configuration in the first instruction and the any one instruction, determining that the any one instruction needs to be optimized, and determining that the instruction information register to be eliminated included in the optimization information is the instruction information register with the same configuration; In response to the absence of instruction information registers with the same configuration in the first instruction and the any one instruction, determining that the any one instruction does not need to be optimized, The same configuration includes writing the same parameters into the same instruction information register.

7. The instruction optimization method according to claim 6, wherein: Checking the configuration of each instruction register of the first instruction and any one of the instructions includes: Checking the configuration of the plurality of instruction information registers, for an i-th instruction information register among the plurality of instruction information registers, checking the configuration of the i-th instruction information register comprises performing the following operations: Comparing whether the i-th instruction information register of the first instruction and the i-th instruction information register of any one of the instructions are configured to write the same parameters; In response to the i-th instruction information register of the first instruction and the i-th instruction information register of any one of the instructions being configured to write the same parameter, determining that there are instruction information registers with the same configuration in the first instruction and the any one of the instructions, and using the i-th instruction information register as the instruction information register to be eliminated; In response to the i-th instruction information register of the first instruction and the i-th instruction information register of any one of the instructions not having the same parameter written therein, it is determined that the first instruction and any one of the instructions do not have instruction information registers with the same configuration.

8. An instruction optimization device, comprising: an acquisition module configured to acquire a compilation file, wherein, in the compilation file, each of the multiple instructions included in the compilation file fully configures an instruction information register before execution, and the instruction information register is configured to cache instruction configuration information or input parameters required by the instruction in the execution instruction stage during the execution instruction stage of each instruction, and the fully configuring the instruction information register includes writing corresponding parameters to at least one instruction information register used by the instruction in the execution instruction stage; A first optimization module is configured to perform optimization operations on the multiple instructions one by one according to the instruction order of the multiple instructions in the compilation file based on the compilation file, so as to determine optimization information of each instruction, wherein the optimization information includes whether the instruction is optimized, and in response to determining that the instruction is optimized, the optimization information also includes an instruction information register to be eliminated corresponding to the instruction, the instruction information register to be eliminated is a repeatedly configured instruction information register, and the repeated configuration includes repeatedly writing the same parameter into the same instruction information register; The second optimization module is configured to optimize the compiled file according to the optimization information to obtain an optimized compiled file, wherein in the optimized compiled file, the configuration of the instruction information register of the repeated configuration of at least part of the instructions is eliminated.

9. An electronic device, comprising: A memory non-transitorily stores computer executable instructions; a processor configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the processor, the instruction optimization method according to any one of claims 1-7 is implemented.

10. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, When the computer executable instructions are executed by a processor, the instruction optimization method according to any one of claims 1 to 7 is implemented.

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