Processor crash recovery method, device, electronic device and storage medium

Abstract

The present application provides a method, device, electronic device and storage medium for recovering a processor crash, and relates to the field of communication technology. The method includes: when the processor crashes, the watchdog in the programmable logic device sends a reset signal to the processor to instruct the processor to execute a restart process; when the processor receives the reset signal, the first target value in the startup flag register is read; the first target value and the target preset value are bitwise XORed to obtain a first result value; the first target bit number of the bit value 1 in the first result value is determined; according to the first target bit number, whether the restart process is a reset abnormal startup process is determined; when the restart process is determined to be a reset abnormal startup process, fixed parameters are directly obtained from the processor program and process data are read from the target memory to complete the recovery operation. The technical solution provided by the present application is implemented to achieve the effect of reducing costs and misjudgment.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method, device, electronic device and storage medium for recovering a processor crash. Background Art

[0002] In communication or computer systems, the stable operation of the processor is crucial to the performance of the entire system. Especially in some critical applications, such as aerospace, military equipment and other fields, once the processor crashes, it will not only affect the normal operation of the system, but may also cause serious safety problems. Therefore, how to quickly and effectively restore the normal operation of the processor has become one of the research focuses.

[0003] A common method in the related art is to save the state before the abnormal shutdown by writing key data to the non-volatile storage system. The long writing time will lead to the problem of slow system response speed. This method requires a special non-volatile memory, which will increase the hardware design cost. In addition, in the processor recovery method of the related art, when judging whether it is a normal startup or a reset abnormal startup, it is usually judged according to a fixed value. In actual application scenarios, under the space radiation environment, a single particle flip may occur in the processor program execution area, and the fixed value judgment method is easy to cause misjudgment, which may cause the problem of not being able to quickly recover from a freeze. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a method, device, electronic device and storage medium for recovering a processor crash.

[0005] In a first aspect, the present application provides a method for recovering a processor crash, comprising: when the processor crashes, a watchdog in a programmable logic device sends a reset signal to the processor to instruct the processor to execute a restart process; when the processor receives the reset signal, the processor reads a first target value in a startup flag register, wherein the startup flag register is configured in the programmable logic device; the first target value is bitwise XORed with a target preset value to obtain a first result value, wherein the first target value has the same number of bits as the target preset value; a first target number of bits of the first result value is determined, wherein the first target number of bits is used to represent the number of bit values ​​1 in the first result value; judging whether the restart process is a reset abnormal startup process based on the first target number of bits; when it is judged that the restart process is a reset abnormal startup process, the processor directly obtains fixed parameters from the processor program and reads process data from a target memory to complete the recovery operation, wherein the target memory is configured in the programmable logic device.

[0006] By adopting the above technical solution, when the processor crashes, the watchdog in the programmable logic device (PLD) will automatically send a reset signal to the processor, which can trigger the restart process of the processor in time to avoid long-term unresponsiveness and cause system failure. After receiving the reset signal, the processor reads the first target value in the startup flag register and performs a bitwise XOR operation with the target preset value, and then judges whether it is a reset abnormal startup based on the number of first target bits in the first result value. Compared with the traditional fixed value judgment method, this method is more flexible and reliable, and effectively reduces the probability of misjudgment caused by factors such as single particle flips. If it is determined to be a reset abnormal startup, the processor can directly obtain the necessary fixed parameters from its own program and read the process data from the target memory in the pre-configured programmable logic device for recovery processing. This method not only improves the recovery efficiency, but also does not need to rely on external non-volatile storage devices, reduces the hardware design cost and speeds up the system's response speed.

[0007] Optionally, judging whether the restart process is a reset abnormal startup process according to the first target bit number includes: when the first target bit number is less than or equal to a preset number, judging that the restart process is a reset abnormal startup process.

[0008] By adopting the above technical solution, it is possible to quickly and accurately determine whether a reset abnormality is initiated when the processor freezes. Specifically, when the number of the first target bits is less than or equal to the preset number, it can effectively avoid misjudgment caused by a single particle upset, thereby ensuring that the processor can quickly enter the correct recovery process under abnormal circumstances, thereby improving the reliability and security of the system.

[0009] Optionally, the method further includes: when the device starts to power on, starting the programmable logic device and setting the reset pin of the processor to a reset state, wherein the device includes a programmable logic device and a processor; after the programmable logic device completes the initialization operation, the programmable logic device releases a reset signal to start the processor; the processor obtains a second target value in a startup flag register, wherein the programmable logic device sets the startup flag register to 0 when performing the initialization operation; performing a bitwise XOR operation on the second target value and a target preset value to obtain a second result value, wherein the second target value has the same number of bits as the target preset value; determining a second target number of bits of the second result value, wherein the second target number of bits is used to represent the number of bit values ​​of 1 in the second result value; judging whether the processor executes a normal startup process based on the second target number of bits; when judging that the processor executes a normal startup process, the processor executes a preset startup operation, wherein the preset startup operation includes the following operations: setting the startup flag register to the target preset value, enabling the watchdog, initializing peripheral devices, and writing process data to the target memory.

[0010] By adopting the above technical solution, the programmable logic device is started when the device starts to power on, and the processor is in a reset state. After the programmable logic device performs the initialization operation, the reset signal is released, so that the processor can start smoothly; the processor obtains the second target value in the startup flag register, and performs a bitwise XOR operation on it and the target preset value to generate a second result value. This process is used to detect the startup type; the number of second target bits of the second result value is determined, so as to judge whether the processor executes a normal startup process, thereby improving the accuracy of the startup judgment; if it is judged to be a normal startup process, the processor executes a series of preset startup operations, including setting the startup flag register to the target preset value, enabling the watchdog, initializing peripheral devices, and writing process data to the target memory, so as to ensure that the system enters a stable operation state; these measures effectively avoid the problem of misjudgment caused by fixed value judgment, and improve the reliability and stability of the processor in various environments.

[0011] Optionally, judging whether the processor executes a normal startup process according to the second target bit number includes: when the second target bit number is greater than a preset number, judging that the processor executes a normal startup process.

[0012] By adopting the above technical solution, it is possible to accurately determine whether the processor is in the normal startup process at the initial stage of device power-on. Specifically, by performing a bitwise XOR operation on the second target value and the target preset value in the startup flag register, and determining the number of bit values ​​1 in the second result value (i.e., the second target bit number), if the number is greater than the preset number, it can be reliably determined that the processor is executing the normal startup process, which ensures that the system can correctly identify the normal startup state when powered on, thereby avoiding unnecessary resets or other erroneous operations caused by misjudgment, and improving the stability and reliability of the system.

[0013] Optionally, the above method also includes: when it is determined that the restart process is a reset abnormal startup process, setting the startup flag to a first value and enabling the watchdog, wherein the first value is used to indicate a reset startup; when it is determined that the processor executes a normal startup process, setting the startup flag to a second value and enabling the watchdog, wherein the second value is used to indicate a normal startup.

[0014] By adopting the above technical solution, when it is determined that the restart process is a reset abnormal startup process, the startup flag is set to the first value and the watchdog is enabled, which helps to clarify the current reset abnormal startup state in subsequent operations, so as to take corresponding recovery measures; when it is determined that the processor executes a normal startup process, the startup flag is set to the second value and the watchdog is enabled, which ensures that during the normal startup process, the system can correctly identify and execute the preset startup operation, while maintaining the effectiveness of the watchdog function to prevent the future crash. In this way, the reset abnormal startup and normal startup of the processor can be effectively distinguished.

[0015] Optionally, the target memory performs a triple-module redundancy design for the written process data.

[0016] By adopting the above technical solution, the target memory in the programmable logic device performs a triple-module redundancy design for the written process data, thereby improving the reliability and fault tolerance of the data. When the processor crashes and needs to be restored, even if part of the data is damaged, the process data can be correctly restored through the redundancy mechanism, ensuring that the processor can quickly and accurately resume normal operation.

[0017] Optionally, when the processor crashes, the watchdog in the programmable logic device sends a reset signal to the processor, including: when the watchdog does not receive a dog feeding signal sent by the processor within a preset time period, sending a reset signal to the processor.

[0018] By adopting the above technical solution, when the processor crashes, the watchdog in the programmable logic device can send a reset signal to the processor in time if it does not receive a feeding signal within a preset time, thereby quickly triggering the restart process of the processor. This mechanism can effectively prevent the system from falling into a stagnant state due to long-term non-response, improve the reliability and stability of the system, and significantly reduce the safety risks caused by processor crashes, especially in critical applications.

[0019] In a second aspect of the present application, a processor crash recovery device is also provided, including: a sending module, used for, when the processor crashes, a watchdog in a programmable logic device sends a reset signal to the processor to instruct the processor to execute a restart process; a reading module, used for the processor to read a first target value in a startup flag register when receiving the reset signal, wherein the startup flag register is configured in the programmable logic device; an operation module, used for performing a bitwise XOR operation on the first target value and a target preset value to obtain a first result value, wherein the first target value and the target preset value have the same number of bits; a determination module, used for determining a first target number of bits of the first result value, wherein the first target number of bits is used to represent the number of bit values ​​of 1 in the first result value; a judgment module, used for judging whether the restart process is a reset abnormal startup process based on the first target number of bits; a processing module, used for, when it is judged that the restart process is a reset abnormal startup process, the processor directly obtains fixed parameters from the processor program and reads process data from the target memory to complete the recovery operation, wherein the target memory is configured in the programmable logic device.

[0020] In a third aspect of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the program, any of the above method steps is implemented.

[0021] In a fourth aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores instructions, and when the instructions are executed, any of the above method steps is performed.

[0022] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages:

[0023] 1. Compared with the traditional fixed value judgment method, it is more flexible and reliable, and effectively reduces the probability of misjudgment caused by factors such as single particle upset;

[0024] 2. If it is determined that the reset is abnormally started, the processor can directly obtain the necessary fixed parameters from its own program and read the process data from the target memory in the pre-configured programmable logic device to perform recovery processing. This method not only improves the recovery efficiency, but also does not need to rely on external non-volatile storage devices, reduces the hardware design cost and speeds up the system's response speed;

[0025] 3. By performing a bitwise XOR operation on the second target value and the target preset value in the startup flag register, and determining the number of bits with a value of 1 in the second result value (i.e., the second target bit number), if the number is greater than the preset number, it can be reliably determined that the processor is executing a normal startup process, which ensures that the system can correctly identify the normal startup state when powered on, thereby avoiding unnecessary resets or other erroneous operations caused by misjudgment, and improving the stability and reliability of the system;

[0026] 4. The target memory in the programmable logic device uses a triple-mode redundant design for the written process data, which improves the reliability and fault tolerance of the data. When the processor crashes and needs to be restored, even if part of the data is damaged, the process data can be correctly restored through the redundant mechanism, ensuring that the processor can quickly and accurately resume normal operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a flow chart of a method for recovering a processor crash provided by an embodiment of the present application;

[0028] Figure 2 It is a flowchart of a method for quickly recovering a processor crash provided by an embodiment of the present application;

[0029] Figure 3 It is a structural block diagram of a processor crash recovery device provided by an embodiment of the present application;

[0030] Figure 4 It is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application.

[0031] Description of reference numerals: 400 - electronic device; 401 - processor; 402 - communication bus; 403 - user interface; 404 - network interface; 405 - memory. DETAILED DESCRIPTION

[0032] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0033] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0034] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0035] The following is combined with Figure 1-Figure 4 The embodiments of the present application are described.

[0036] This application provides a method for recovering a processor crash. Figure 1 , Figure 1 : is a flow chart of a method for recovering a processor crash provided by an embodiment of the present application, the method comprising:

[0037] Step S101, when the processor freezes, the watchdog in the programmable logic device sends a reset signal to the processor to instruct the processor to execute a restart process;

[0038] Step S102, when the processor receives a reset signal, reads a first target value in a startup flag register, wherein the startup flag register is configured in the programmable logic device;

[0039] Step S103, performing a bitwise XOR operation on the first target value and the target preset value to obtain a first result value, wherein the first target value and the target preset value have the same number of bits;

[0040] Step S104, determining a first target number of bits of the first result value, wherein the first target number of bits is used to represent the number of bits of the first result value that are 1;

[0041] Step S105, judging whether the restart process is a reset abnormal startup process according to the first target bit quantity;

[0042] Step S106, when it is determined that the restart process is a reset abnormal startup process, the processor directly obtains fixed parameters from the processor program and reads process data from the target memory to complete the recovery operation, wherein the programmable logic device is configured with a target memory.

[0043] Through the above steps, when the processor crashes, the watchdog in the programmable logic device (PLD) will automatically send a reset signal to the processor, which can trigger the restart process of the processor in time to avoid long-term unresponsiveness and cause system failure. After receiving the reset signal, the processor reads the first target value in the startup flag register and performs a bitwise XOR operation with the target preset value, and then judges whether it is a reset abnormal startup based on the number of first target bits in the first result value. Compared with the traditional fixed value judgment method, this method is more flexible and reliable, and effectively reduces the probability of misjudgment caused by factors such as single particle flips. If it is determined to be a reset abnormal startup, the processor can directly obtain the necessary fixed parameters from its own program and read the process data from the target memory in the pre-configured programmable logic device for recovery processing. This method not only improves the recovery efficiency, but also does not need to rely on external non-volatile storage devices, reduces the hardware design cost and speeds up the system's response speed.

[0044] When the processor crashes, the watchdog in the programmable logic device will send a reset signal to the processor, instructing it to execute the restart process; after receiving the reset signal, the processor will read the first target value in the startup flag register configured in the PLD, and perform a bitwise XOR operation on this first target value and a preset target preset value to obtain a result value; by calculating the number of bit values ​​​​of 1 in the XOR result value, that is, the number of first target bits, the processor can determine whether this startup is a normal startup or a reset abnormal startup. In the related art, whether it is a reset abnormal start is determined only by whether the result of the XOR operation is equal to a fixed value. However, in actual applications, due to the space radiation environment, the processor program execution area may have a single particle flip, such as the value in the startup flag register may have a single particle flip. The method in the related art is easy to cause misjudgment, and the method of the present application can avoid this problem, because the present application provides a more flexible and reliable judgment mechanism through bitwise XOR operation and bit value 1 bit number judgment, reducing the possibility of misjudgment; that is, for the single particle flip problem in extreme environments such as space radiation, the use of bitwise XOR operation and bit counting can more accurately determine whether it is an abnormal reset, thereby reducing the possibility of misjudgment. When it is determined that it is a reset abnormal start, the processor will directly obtain fixed parameters from its program and read process data from the target memory (also configured in the PLD) to complete the recovery operation. The method of saving the state by writing into the non-volatile storage system in the related art not only takes a long time to write, affects the system response speed, but also increases the hardware design cost. The method of the embodiment of the present application avoids this problem because the startup flag register and the target memory are both configured in the PLD, and no additional non-volatile memory is required. The present embodiment reduces the time required for system recovery, improves the stability and reliability of the system, avoids the use of additional non-volatile memory, and reduces the hardware design cost by quickly judging the startup type and directly performing the recovery operation. In complex environments such as space radiation, the present method provides a more reliable startup type judgment mechanism and enhances the system's adaptability to abnormal situations.

[0045] In an optional embodiment, judging whether the restart process is a reset abnormal startup process according to the first target bit number includes: when the first target bit number is less than or equal to a preset number, judging that the restart process is a reset abnormal startup process.

[0046] In the above embodiment, it is possible to quickly and accurately determine whether a reset abnormality is initiated when the processor freezes. Specifically, when the number of first target bits is less than or equal to the preset number, it is possible to effectively avoid misjudgment caused by a single particle upset, thereby ensuring that the processor can quickly enter the correct recovery process under abnormal circumstances, thereby improving the reliability and security of the system.

[0047] In this embodiment, after receiving the reset signal, the processor performs a series of operations, such as reading the first target value in the startup flag register, performing a bitwise XOR operation with the target preset value, obtaining a first result value, and determining the number of bit values ​​1 in the first result value, that is, the first target bit number, and then the processor compares the first target bit number with a preset number (such as 5, or 6, or other values); if the first target bit number is less than or equal to the preset number, the processor determines that the current restart process is a reset abnormal start (such as an abnormal start caused by a single particle upset). Based on this judgment, the processor will take specific recovery measures, such as directly obtaining fixed parameters from the processor program and reading process data from the target memory to complete the recovery operation. By introducing a preset number as a judgment threshold and combining the XOR operation and the bit number judgment, the method can more accurately identify whether the processor should perform a reset abnormal start, which helps to reduce misjudgment and improve the reliability of crash recovery. The introduction of the preset number allows the judgment standard to be adjusted according to the actual situation, thereby improving the flexibility and applicability of the method. For example, under different environmental conditions or for different processor states, different preset numbers can be set to adapt to changes. By accurately identifying abnormal reset startup and taking timely recovery measures, this method helps to improve the stability and reliability of the entire system, which is particularly important for key applications (such as aerospace, military equipment and other fields) because these applications have extremely high requirements for system stability and reliability. The preset number here is a pre-set value, which is used to distinguish the key standard between normal startup and abnormal startup. In the normal startup process, the value in the startup flag register should match the target preset value, so the number of bit values ​​1 in the first result value obtained after the bitwise XOR operation should be 0, but if an abnormal situation caused by a single particle flip occurs, then this first result value may not be equal to 0, and the relevant technology cannot accurately judge. Therefore, by comparing the first target bit number with the preset number, it can be effectively determined whether it is a reset abnormal startup.

[0048] Usually, the target preset value is a value containing multiple bit values ​​1. After the first power-on startup and the PLD releases the reset signal, the processor will set the value in the startup flag register (such as the first target value mentioned above) to the same value as the target preset value. If a crash and restart occurs in subsequent operation, it can be confirmed based on the result of the XOR operation.

[0049] In an optional embodiment, the above method also includes: when the device starts to power on, starting the programmable logic device and setting the reset pin of the processor to a reset state, wherein the device includes a programmable logic device and a processor; after the programmable logic device completes the initialization operation, the programmable logic device releases a reset signal to start the processor; the processor obtains a second target value in the startup flag register, wherein the programmable logic device sets the startup flag register to 0 when performing the initialization operation; performing a bitwise XOR operation on the second target value and the target preset value to obtain a second result value, wherein the second target value and the target preset value have the same number of bits; determining a second target number of bits of the second result value, wherein the second target number of bits is used to represent the number of bit values ​​1 in the second result value; judging whether the processor executes a normal startup process based on the second target number of bits; when it is judged that the processor executes a normal startup process, the processor executes a preset startup operation, wherein the preset startup operation includes the following operations: setting the startup flag register to the target preset value, enabling the watchdog, initializing peripheral devices, and writing process data to the target memory.

[0050] In the above embodiment, the programmable logic device is started when the device starts to power on, and the processor is in a reset state. After the programmable logic device performs the initialization operation, the reset signal is released, so that the processor can start smoothly; the processor obtains the second target value in the startup flag register, and performs a bitwise XOR operation on it and the target preset value to generate a second result value. This process is used to detect the startup type; the number of second target bits of the second result value is determined, so as to judge whether the processor executes a normal startup process, thereby improving the accuracy of the startup judgment; if it is judged to be a normal startup process, the processor executes a series of preset startup operations, including setting the startup flag register to the target preset value, enabling the watchdog, initializing peripheral devices, and writing process data to the target memory, so as to ensure that the system enters a stable operation state; these measures effectively avoid the problem of misjudgment caused by fixed value judgment, and improve the reliability and stability of the processor in various environments.

[0051] When the device starts to power on, the PLD is first started and the reset pin of the processor is placed in a reset state. Subsequently, the PLD performs initialization operations, including setting the startup flag register to 0, etc. After the PLD completes initialization, it releases the reset signal to start the processor. The processor then reads the second target value in the startup flag register, which should be 0 at this time because the PLD sets it to 0 during initialization. The processor performs a bitwise XOR operation on the read second target value and a preset target preset value to obtain a second result value. Then, the processor calculates the number of bits in this result value that are 1, that is, the second target bit number. Under normal circumstances, that is, when no single particle upset occurs, the second result is The result value should be equal to the target preset value, for example, the number of bit values ​​1 in the target preset value is 14 bits (or 13 bits, or other). The method in the related art will only judge it as a normal startup when the second result value is equal to the target preset value. In the space radiation environment, a single particle flip may occur. The embodiment of the present application can more accurately judge whether it is a normal startup by judging the count of bit values ​​1 in the second result value, thereby reducing the possibility of misjudgment. According to the second target bit number and the preset logical judgment rule (for example, compared with a certain threshold), the processor can determine whether the current startup process is a normal startup. For example, the second target bit number is 8 (or 5, or other values). If it is judged to be a normal startup, the processor will perform a series of preset startup operations, including setting the startup flag register to the target preset value, enabling the watchdog, initializing peripheral devices, and writing process data to the target memory. That is, once it is confirmed to be a normal startup, the system can immediately execute the corresponding initialization steps, thereby shortening the startup time and laying the foundation for rapid recovery in the event of a possible crash. In this embodiment, by introducing mechanisms such as bitwise XOR operation and bit number judgment with bit value 1, the method can more accurately judge whether the startup process of the processor is a normal startup process. The method makes full use of hardware resources such as PLD to realize the control of the processor reset pin and the initialization of the startup flag register, thereby optimizing the initialization and reset mechanism of the processor; through accurate startup process judgment and perfect initialization and reset mechanism, the method helps to improve the stability and reliability of the entire system, which is particularly important for application scenarios that require high reliability and stability (such as aerospace, military equipment and other fields). The method optimizes the startup and recovery process of the processor by making full use of hardware resources such as PLD, thereby improving the utilization rate of hardware resources and the overall performance of the system.

[0052] In an optional embodiment, judging whether the processor executes a normal startup process according to the second target bit number includes: judging that the processor executes a normal startup process when the second target bit number is greater than a preset number.

[0053] In the above embodiment, it is possible to accurately determine whether the processor is in a normal startup process at the initial stage of device power-on. Specifically, by performing a bitwise XOR operation on the second target value and the target preset value in the startup flag register, and determining the number of bit values ​​1 in the second result value (i.e., the second target bit number), if the number is greater than the preset number, it can be reliably determined that the processor is executing a normal startup process, which ensures that the system can correctly identify the normal startup state when powered on, thereby avoiding unnecessary resets or other erroneous operations caused by misjudgment, and improving the stability and reliability of the system.

[0054] When the number of bits with a value of 1 in the calculated second result value (i.e., the second target bit number) is greater than a preset threshold (preset number), the system determines that the current startup is a normal startup process; in the case of normal startup, since the startup flag register is set to 0 when the PLD is initialized, if the second target value read at the time of processor startup is bitwise XORed with the target preset value, the second result value is equal to the target preset value. Usually, the number of bit values ​​1 in the target preset value is large, such as 14 bits (or 13 bits, or other). If a single particle flip occurs, the number of bit values ​​1 in the second result value should also be large, such as 12 to 16 bits, which can be considered as a normal startup behavior. By comparing the second target bit number and the preset number through this method, it is possible to more accurately determine whether the startup process of the processor is a normal startup process, which helps to reduce misjudgment and missed judgment and improve the stability and reliability of the system. It should be noted that the preset number (assuming the first preset number) when performing the normal startup process judgment in this embodiment and the preset number (assuming the second preset number) when performing the reset abnormal startup process judgment in the aforementioned embodiment may be the same or different, and the first preset number is greater than the second preset number. For example, the first preset number is 8 and the second preset number is 3.

[0055] In actual applications, when the hardware device is just powered on, the first power-on detection flag defaults to 0. If the second target number is less than or equal to the preset number, the processor will further detect whether the first power-on detection flag is 0, indicating that there is an abnormality in the XOR result and it is necessary to wait for restart. At this time, the processor should stop feeding the dog; if it is detected that the first power-on detection flag is not 0, it means that it is not a normal startup process, and it may be a reset abnormal startup process.

[0056] In an optional embodiment, the above method also includes: when it is determined that the restart process is a reset abnormal startup process, setting the startup flag to a first value and enabling the watchdog, wherein the first value is used to indicate a reset startup; when it is determined that the processor executes a normal startup process, setting the startup flag to a second value and enabling the watchdog, wherein the second value is used to indicate a normal startup.

[0057] In the above embodiment, when it is determined that the restart process is a reset abnormal startup process, the startup flag is set to the first value and the watchdog is enabled, which helps to clarify the current reset abnormal startup state in subsequent operations, so as to take corresponding recovery measures; when it is determined that the processor executes a normal startup process, the startup flag is set to the second value and the watchdog is enabled, which ensures that during the normal startup process, the system can correctly identify and execute the preset startup operation, while maintaining the effectiveness of the watchdog function to prevent the future crash. In this way, the reset abnormal startup and normal startup of the processor can be effectively distinguished.

[0058] When the processor restart process is judged as a reset abnormal startup process, the startup flag is set to the first value, which is used to clearly indicate that the startup state of the current processor is reset startup, that is, the processor is restored from a dead state, and the watchdog function is enabled at the same time, so as to continuously monitor the state of the processor in subsequent operation to prevent the dead state from occurring again, and ensure that the processor can run stably. When the processor executes a normal startup process, the startup flag is set to the second value. The second value is used to indicate that the startup state of the current processor is normal startup, that is, the processor is started from the initial state after the device is powered on, and the watchdog function is also enabled to achieve continuous monitoring and protection of the processor and improve the stability of the system. By clearly indicating the startup state and uniformly enabling the watchdog function, the abnormal situation of the processor can be discovered and handled in time, and the occurrence of problems such as deadlock can be prevented, thereby improving the stability and reliability of the system and ensuring the continuous normal operation of key application scenarios; the system can adopt targeted optimization strategies and operations according to the clear startup state indication, such as quickly entering the working state during normal startup, and performing necessary recovery operations during reset abnormal startup, thereby improving the operation efficiency and response speed of the system and meeting the needs of different application scenarios. The watchdog is enabled regardless of whether the processor is started by a reset exception or a normal startup. This helps ensure that the system can run stably after startup and reset in time when an exception is detected. By unifying the configuration strategy of the watchdog, the reliability and stability of the system are enhanced. By setting the startup flag bit to different values ​​to clearly indicate the startup type of the processor (reset exception startup or normal startup), the system can respond appropriately according to different startup types. This helps improve the flexibility and maintainability of the system.

[0059] In an optional embodiment, the target memory performs a triple-module redundancy design for the written process data.

[0060] In the above embodiment, the target memory in the programmable logic device performs a triple-module redundancy design for the written process data, which improves the reliability and fault tolerance of the data. When the processor crashes and needs to be restored, even if part of the data is damaged, the process data can be correctly restored through the redundancy mechanism, ensuring that the processor can quickly and accurately resume normal operation.

[0061] This embodiment uses a triple-module redundancy design for the written process data. For example, in the target memory, the process data is stored in three independent storage units. When reading data, the data in these three storage units are read at the same time and compared. If the data in two of the storage units are consistent, and the data in the third storage unit is different, it is considered that the data in the third storage unit is erroneous, and it is corrected to be consistent with the other two. Through the triple-module redundancy design, this embodiment can effectively detect and correct data errors in the memory, ensure the accuracy and integrity of the data, and provide a solid data foundation for the stable operation of the processor and the normal operation of the system; enhance the fault tolerance of the system, so that the system can operate more stably in the face of various abnormal situations, reduce problems such as system restart or crash caused by data errors, and improve the overall stability of the system.

[0062] In an optional embodiment, when the processor crashes, the watchdog in the programmable logic device sends a reset signal to the processor, including: when the watchdog does not receive a dog feeding signal sent by the processor within a preset time period, sending a reset signal to the processor.

[0063] In the above embodiment, when the processor crashes, the watchdog in the programmable logic device can send a reset signal to the processor in a timely manner when it does not receive a feeding signal within a preset time, thereby quickly triggering the restart process of the processor. This mechanism can effectively prevent the system from falling into a stagnant state due to long-term non-response, improve the reliability and stability of the system, and especially in critical application scenarios, can significantly reduce the safety risks caused by processor crashes.

[0064] The watchdog is used to detect whether the processor is operating normally. The principle is that during normal operation, the processor will periodically send a pulse or signal called a "feeding signal" to the watchdog to indicate that it is still operating normally. If the watchdog does not receive the feeding signal from the processor within a preset time period (called "timeout" or "feeding cycle"), it is considered that the processor may have crashed or fallen into an abnormal state. At this time, the watchdog will trigger a reset signal to restart the processor. Through the watchdog mechanism, the processor can be detected in time when it crashes. If the watchdog does not receive the feeding signal within the preset time, it will immediately send a reset signal to the processor to quickly restore the normal operation of the system. The watchdog mechanism helps to reduce system crashes and data loss caused by processor crashes, and improves the overall reliability of the system, which is especially important for systems that need to run stably for a long time. Through the timely detection and reset mechanism of the watchdog, the processor can be effectively prevented from being in a dead state for a long time, ensuring that the system can quickly resume normal operation, improving the stability and reliability of the system, and reducing the risk of system failure caused by processor crashes.

[0065] In an optional embodiment, the target preset value is a 32-bit value, the number of bits with a bit value of 1 in the target preset value is 14, and the preset number is 5.

[0066] In the above embodiment, the target preset value is a 32-bit value, of which 14 bits are 1. This design makes the result of the bitwise XOR operation have high randomness and discrimination, further reducing the possibility of misjudgment. The preset number is set to 5. The selection of this threshold value not only ensures sufficient sensitivity, but also effectively filters out accidental interference, thereby more accurately identifying the reset abnormal startup process and improving the robustness of the system. Using specific target preset values ​​and preset numbers can simplify the startup judgment logic and avoid unnecessary complexity. For example, it is only necessary to compare the relationship between the calculated target bit number and the preset number to make a quick judgment, reducing processing time and resource consumption. It ensures that even in extreme environments (such as space radiation), normal startup and abnormal reset can be accurately distinguished, enhancing the reliability and security of the system.

[0067] Assuming that the reset pin is valid at a low level, in the above embodiment, the watchdog sends a reset signal to the processor including first sending a low level and then a high level to the reset pin of the processor, that is, setting the reset pin low first and then high.

[0068] Obviously, the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below in conjunction with specific embodiments.

[0069] In a space radiation environment, a single particle flip may occur in the processor program execution area, which may cause the processor to crash. The embodiment of the present application provides a method for quickly recovering from a processor crash caused by a single particle flip in a space radiation environment. The method reasonably divides existing resources and uses programmable logic devices to design a watchdog function. After the hardware is powered on, when the programmable logic device detects that the processor has crashed for a certain period of time, the processor program is reloaded without powering off the hardware, and the processor restarts and inherits the running state before the crash, quickly recovering to normal operation.

[0070] The specific steps include:

[0071] After the hardware is powered on, the programmable logic device starts up, and the processor reset pin is set to the reset state by default. The processor does not start up. The programmable logic configures internal registers, RAM, watchdog and other functions, and sets the processor startup register flag to 0 by default. The watchdog function is set to disabled by default. After the programmable logic device is initialized and started up, the processor reset signal is released and related functions are executed, among which the watchdog function is judged. If enabled, it is periodically determined whether the processor feeds the dog. If the processor does not feed the dog within a fixed time, it indicates that the processor is running abnormally and the processor needs to be reset.

[0072] After receiving the reset signal released by the programmable logic device, the processor reset pin starts to execute the software process normally. First, the 32-bit value in the programmable logic device startup flag register (corresponding to the aforementioned target preset value) is read back and recorded as A. When powered on for the first time, the value in the register is 0. When A and 0x21AA5A5A are bitwise XORed, the value is 0x21AA5A5A. The conventional judgment process is that if the value is equal to 0x21AA5A5A, it is judged as a normal startup. However, if a single particle upset occurs, for example, the value in the register becomes 1, when A and 0x21AA5A5A are bitwise XORed After the operation, the value is 0x21AA5A5B. If it is judged conventionally that 0x21AA5A5B is not equal to 0x21AA5A5A, it is judged as a reset restart, but the actual situation is a normal startup, which will lead to misjudgment; since the number of bits with a value of 1 in the 32-bit XOR result is 14, and a single particle flip exceeding 2 bits will cause a restart, the number of bits with a value of 1 in a normal startup under a single particle flip ranges from 12 to 16. As long as the program design determines that the number of bits with a value of 1 in the 32-bit value is greater than 5 (corresponding to the aforementioned preset number), it is considered to be a normal power-on startup. At the same time, the value in the programmable logic device startup flag register is changed to 0x21AA5A5A, and then the watchdog function is enabled, and the value is written to the programmable logic device watchdog feeding register regularly to perform the dog feeding operation.

[0073] In the normal startup process, the processor needs to configure the corresponding parameters according to different design requirements. The parameters of the configuration process (corresponding to the aforementioned process data) are synchronously written into the programmable logic device RAM. After receiving the data written by the processor, the programmable logic device performs a triple-module redundancy design on the data. The triple-module redundancy system is referred to as TMR (Triple Modular Redundancy). It is a fault-tolerant technology for single-particle flips. Three modules perform the same operation at the same time, and the majority of the same outputs are used as the correct output of the voting system, usually called three out of two. As long as two identical errors do not occur at the same time in the three modules, the fault error can be masked. Since the three modules are independent of each other, the probability of errors in two modules at the same time is extremely low, so it has extremely high simplicity and reliability, ensuring the reliability of data transmission. At this point, the processor enters the normal operation process.

[0074] In a space radiation environment, when the processor crashes due to a single particle upset, it will stop feeding the dog. If the programmable logic device does not detect the dog feeding signal within the set time, it will reset the processor. After receiving the reset signal, the processor will restart the startup process and read back the startup flag A in the programmable logic device. Since the processor sets the register to 0x21AA5A5A after normal startup, when A and 0x21AA5A5A are bitwise XORed, the value is 0. The conventional judgment process is that if the value is equal to 0, it is judged as a reset and restart. However, if a single particle upset occurs, such as register The value in becomes 0x21AA5A5B. After A and 0x21AA5A5A are bitwise XORed, the value is 1. According to conventional judgment, 1 is not equal to 0, that is, it is judged as a normal startup. However, the actual situation is a reset restart, which will lead to misjudgment. Since the number of bits with a value of 1 in the 32-bit XOR result is 0, and a single-particle flip exceeding 2 bits will cause a restart, the number of bits with a value of 1 in the reset abnormal startup in the case of a single-particle flip ranges from 0 to 2. As long as the program design determines that the number of bits with a value of 1 in the 32-bit value is less than or equal to 5, it is considered to be a reset abnormal startup.

[0075] After the reset exception is started, the processor no longer operates on other requirements, but directly obtains fixed parameters from the processor program, and the real-time data in the process (corresponding to the aforementioned process data) is directly read back from the programmable logic device RAM. Since the programmable logic device has a triple-module redundant design for RAM, the correctness of the read-back data can be ensured. At this point, the processor returns to normal.

[0076] Figure 2 1 is a flow chart of a method for quickly recovering a processor crash provided by an embodiment of the present application, the flow chart comprising:

[0077] S201, the hardware device is powered on, the programmable logic device (PLD) is started, and the PLD begins to initialize, including: setting the startup flag register to 0, setting the watchdog state to off, setting the processor reset level to low, initializing the on-chip RAM, and setting the first power-on detection flag to 0;

[0078] S202, the processor reset level is set high;

[0079] S203, the processor starts. Since the processor reset pin is set to a reset state when the power is just turned on, the processor is not working when the power is just turned on. When the processor reset level is set high, the processor starts to start;

[0080] S204, read back the start flag register value A;

[0081] S205, the XOR value of A and 0x21AA5A5A is B;

[0082] S206, determine whether the single bit value of B is 1 and is greater than 5;

[0083] S207, when the judgment result of step S206 is yes, the start flag register is set to 0x21AA5A5A;

[0084] When the judgment result of step S206 is no, proceeds to step S215;

[0085] S208, enable the watchdog and feed the watchdog regularly;

[0086] S209, determining whether the watchdog is working properly;

[0087] S210, when the determination result of step S209 is yes, continue to determine whether a dog feeding signal is received within a fixed time period;

[0088] When the determination result of step S209 is no, continue to determine whether the watchdog is working normally;

[0089] S211, when the judgment result of the above step S210 is yes, that is, the dog is not fed within a fixed time, the processor reset level is first low and then high, that is, a reset signal is sent to the processor, and the process goes to step S203. For example, in the case of a crash, the process goes to S203 to reset and restart;

[0090] When the judgment result of the above step S210 is no, continue to monitor the watchdog;

[0091] S212, the first power-on detection flag is set to 0xAA;

[0092] S213, initializing peripheral devices;

[0093] S214, the intermediate data (or process data) is written into the RAM of the programmable logic device; if no abnormality or crash occurs, then the subsequent process is entered, that is, step S222;

[0094] It should be noted that the above steps S209-S211 are not steps that must be performed after step S208. After the above step S208, the process can be directly entered into S212. Step S208 is to provide an enable signal to the watchdog, and the watchdog will subsequently monitor whether the processor is operating normally.

[0095] S215, determining whether the first power-on detection flag is 0;

[0096] S216, when the judgment result of the above step S215 is yes, the start flag register is set to 0;

[0097] S217, enable the watchdog and stop feeding the watchdog;

[0098] S218, the first power-on is abnormal and waiting for reset and restart; this situation indicates an abnormality;

[0099] S219, when the judgment result of the above step S215 is no, that is, the number of single bit values ​​1 in B is less than or equal to 5, the watchdog is enabled and the watchdog is fed regularly;

[0100] S220, the processor reads back the real-time data from the RAM of the programmable logic device;

[0101] S221, the fixed data is stored in the processor program and can be obtained at any time; then the subsequent process is entered, that is, step S222;

[0102] The above steps S207-S214 correspond to the normal startup process, and the above steps S219-S221 correspond to the reset abnormal startup process.

[0103] The embodiment of the present application can be used to enable the processor to quickly resume normal operation without power failure in the hardware system, thereby reducing hardware power failure and improving efficiency. The unchanged parameters are stored in the processor software code in advance. For example, the unchanged parameters of the peripheral device initialization are allocated in an array in the software code, unsigned char adrv9026Init{0x80, 0x36, 0x55, ..., 0x38}. The parameters are compiled together with the software code and do not need to be obtained through the peripheral interface. The process parameters are stored in the RAM allocated by the programmable logic device. For example, the application parameter beam weight needs to be changed from time to time. The parameter is stored in the RAM allocated by the programmable logic device. There is no need to design an independent non-volatile memory to store the above parameters, which is low in cost. The program does not need to operate the non-volatile memory and has high operating efficiency. The process parameters are all stored in the register or RAM allocated by the programmable logic device, and the data is comprehensive and the status is reliable. In addition, the status query at startup is changed from determining a fixed value to determining a range, which improves the correctness of status transmission. At the same time, the programmable logic device performs a triple-module redundant design on the RAM, and data transmission is more reliable.

[0104] The embodiments of the present application have at least the following technical effects: 1) Rationally utilizing the resources of programmable logic devices to open up RAM, storing process data in the RAM saves hardware costs and improves system operation efficiency. At the same time, 3-mode processing is performed on the RAM in the programmable logic unit to improve the reliability of data reading and writing; 2) Fixed data in system operation is embedded in the processor program in advance, avoiding anomalies caused by fixed parameter transmission and improving the efficiency of program operation; 3) The system normal startup and abnormal restart register identifiers are designed to be 32 bits. By performing a bitwise XOR operation with 0x21AA5A5A, the range of bit numbers that are 1 in the 32-bit result is determined instead of a specific value, thereby improving the fault tolerance of the system identification and avoiding misjudgment of the system startup identifier due to individual bit anomalies caused by single-particle flips.

[0105] The present application also provides a processor crash recovery device, such as Figure 3 As shown, Figure 3 : is a structural block diagram of a processor crash recovery device provided in an embodiment of the present application, the device comprising:

[0106] The sending module 301 is used for, when the processor freezes, the watchdog in the programmable logic device sends a reset signal to the processor to instruct the processor to execute a restart process;

[0107] A reading module 302, configured for the processor to read a first target value in a startup flag register when receiving a reset signal, wherein the startup flag register is configured in the programmable logic device;

[0108] An operation module 303 is used to perform a bitwise XOR operation on the first target value and the target preset value to obtain a first result value, wherein the first target value and the target preset value have the same number of bits;

[0109] A determination module 304 is configured to determine a first target number of bits of the first result value, wherein the first target number of bits is used to represent the number of bits of 1 in the first result value;

[0110] A judging module 305, configured to judge whether the restart process is a reset abnormality start process according to the first target bit quantity;

[0111] The processing module 306 is used for, when it is determined that the restart process is a reset abnormal startup process, the processor directly obtains fixed parameters from the processor program and reads process data from the target memory to complete the recovery operation, wherein the target memory is configured in the programmable logic device.

[0112] It should be noted that: when the device provided in the above embodiment realizes its function, only the division of the above functional modules is used as an example. In actual application, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0113] The present application also provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed, any one of the method steps described above is executed.

[0114] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0115] The present application also discloses an electronic device. Figure 4 As shown, Figure 4 The electronic device 400 may include: at least one processor 401 , at least one communication bus 402 , a user interface 403 , at least one network interface 404 , and a memory 405 .

[0116] The communication bus 402 is used to realize the connection and communication between these components.

[0117] The user interface 403 may include a display screen (Display) and a camera (Camera). Optionally, the user interface 403 may also include a standard wired interface and a wireless interface.

[0118] The network interface 404 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0119] Among them, the processor 401 may include one or more processing cores. The processor 401 uses various interfaces and lines to connect various parts of the entire electronic device (such as a server), and executes various functions of the server and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 405, and calling data stored in the memory 405. Optionally, the processor 401 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 401 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 401, and it can be implemented separately through a chip.

[0120] Among them, the memory 405 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 405 includes a non-transitory computer-readable storage medium. The memory 405 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 405 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 405 may optionally also be at least one storage device located away from the aforementioned processor 401. Refer to Figure 4 , the memory 405 as a computer storage medium may include an operating system, a network communication module, a user interface module and an application program of a method for recovering a processor crash.

[0121] exist Figure 4 In the electronic device 400 shown, the user interface 403 is mainly used to provide an input interface for the user and obtain the data input by the user; and the processor 401 can be used to call an application program of a processor crash recovery method stored in the memory 405, and when executed by one or more processors 401, the electronic device 400 executes one or more of the methods described in the above embodiments. It should be noted that for the aforementioned method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required for the present application.

[0122] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] In the several implementation modes provided in this application, it should be understood that the disclosed device or system can be implemented in other ways. For example, the device or system embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0124] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0126] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: various media that can store program codes, such as USB flash drives, mobile hard drives, magnetic disks or optical disks.

[0127] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification, those skilled in the art will easily think of other embodiments of the present disclosure.

[0128] This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not recorded in the present disclosure.

Claims

1. A method for recovering a processor crash, characterized in that: include: When the processor crashes, the watchdog in the programmable logic device sends a reset signal to the processor to instruct the processor to execute a restart process; The processor reads a first target value in a startup flag register when receiving the reset signal, wherein the startup flag register is configured in the programmable logic device; Performing a bitwise XOR operation on the first target value and the target preset value to obtain a first result value, wherein the first target value and the target preset value have the same number of bits; Determine a first target number of bits of the first result value, wherein the first target number of bits is used to represent the number of bits with a value of 1 in the first result value; Determining whether the restart process is a reset abnormal startup process according to the first target bit quantity; When it is determined that the restart process is the reset abnormal startup process, the processor directly obtains fixed parameters from the processor program and reads process data from the target memory to complete the recovery operation, wherein the target memory is configured in the programmable logic device.

2. The method according to claim 1, characterized in that: Judging whether the restart process is a reset abnormal startup process according to the first target bit quantity includes: When the first target bit quantity is less than or equal to the preset quantity, it is determined that the restart process is the reset abnormality startup process.

3. The method according to claim 1, characterized in that The method further comprises: When the device starts to be powered on, the programmable logic device is started, and a reset pin of the processor is set to a reset state, wherein the device includes the programmable logic device and the processor; After the programmable logic device completes the initialization operation, the programmable logic device releases a reset signal to start the processor; The processor obtains a second target value in the startup flag register, wherein the programmable logic device sets the startup flag register to 0 when performing the initialization operation; Performing a bitwise XOR operation on the second target value and the target preset value to obtain a second result value, wherein the second target value and the target preset value have the same number of bits; Determine a second target number of bits of the second result value, wherein the second target number of bits is used to represent the number of bits with a value of 1 in the second result value; Determining whether the processor executes a normal startup process according to the second target bit quantity; When it is determined that the processor executes the normal startup process, the processor executes a preset startup operation, wherein the preset startup operation includes the following operations: setting the startup flag register to the target preset value, enabling the watchdog, initializing peripheral devices, and writing the process data to the target memory.

4. The method according to claim 3, characterized in that Determining whether the processor executes a normal startup process according to the second target bit quantity includes: When the second target bit quantity is greater than a preset quantity, it is determined that the processor executes the normal startup process.

5. The method according to claim 3, characterized in that: The method further comprises: In the case where it is determined that the restart process is the reset abnormal startup process, setting the startup flag bit to a first value and enabling the watchdog, wherein the first value is used to indicate a reset startup; When it is determined that the processor executes the normal startup process, the startup flag is set to a second value and the watchdog is enabled, wherein the second value is used to indicate a normal startup.

6. The method according to claim 1, characterized in that The target memory performs a triple-module redundancy design for the process data to be written.

7. The method according to claim 1, characterized in that When the processor crashes, the watchdog in the programmable logic device sends a reset signal to the processor, including: When the watchdog does not receive the dog feeding signal sent by the processor within a preset time period, the reset signal is sent to the processor.

8. A processor crash recovery device, characterized in that: include: A sending module, used for, when the processor freezes, the watchdog in the programmable logic device sends a reset signal to the processor to instruct the processor to execute a restart process; a reading module, configured for the processor to read a first target value in a startup flag register when receiving the reset signal, wherein the startup flag register is configured in the programmable logic device; an operation module, configured to perform a bitwise exclusive OR operation on the first target value and a target preset value to obtain a first result value, wherein the first target value and the target preset value have the same number of bits; A determination module, configured to determine a first target number of bits of the first result value, wherein the first target number of bits is used to represent the number of bits with a value of 1 in the first result value; A judging module, configured to judge whether the restart process is a reset abnormality starting process according to the first target bit quantity; A processing module is used for, when it is determined that the restart process is the reset abnormal startup process, the processor directly obtains fixed parameters from the processor program and reads process data from the target memory to complete the recovery operation, wherein the target memory is configured in the programmable logic device.

9. An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed, the method according to any one of claims 1 to 7 is performed.

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