Chip self-checking method and device, chip and storage medium
By adjusting the pointer pointer of the main stack, the CPU avoids entering the interrupt processing stage many times, solving the problem of CPU locking and self-testing cannot be judged, and realizing the effectiveness and reliability of chip self-test.
Patent Information
- Application Number
- CN202411618105.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-03-18
AI Technical Summary
In the prior art, when the CPU detects ECC errors in RAM, it enters the interrupt processing stage many times, causing the CPU to enter a locked state, unable to work normally, and it is impossible to judge whether the self-test has passed.
By pointing the pointer of the main stack in the first storage module to the second storage module, the control error injection module injects error information into the first channel, performs a self-test operation, and re-points the pointer of the main stack to the first storage module after the self-test is completed, so as to avoid the CPU entering the interrupt processing stage multiple times.
It effectively avoids the CPU entering the locked state, ensures that the microcontroller unit (MCU) works normally, and can determine whether the self-test passes.
Smart Images
Figure CN119645742A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of software self-checking, and more specifically, to a chip self-checking method, device, chip and storage medium. Background Art
[0002] The multi-bit error detection in the current random access memory (RAM) instruction error checking and correcting (ECC) technology is to intercept the read data bus, check bit bus and address bus of the specified RAM through a hardware error injection unit, and flip the transmission value of the selected bit on these three buses to inject ECC errors.
[0003] When the central processing unit (CPU) reads data from the RAM space through the corresponding bus, an ECC error is detected, and then a bus error occurs. The CPU enters the interrupt processing stage and performs a stack push operation to maintain the system context. After the CPU interrupt processing stage, a stack pop operation is performed to restore the context before the exception so that the program can continue to execute. However, in this process, the CPU will enter the interrupt processing stage multiple times, causing the CPU to enter a locked state, which in turn causes the microcontroller unit (MCU) to fail to work properly and it is impossible to determine whether the self-test has passed. Summary of the invention
[0004] In view of the above problems, the present application proposes a chip self-test method, device, chip and storage medium, which can prevent the CPU from entering the interrupt processing stage multiple times, thereby preventing the CPU from entering a locked state, so that it can be determined whether the self-test has passed.
[0005] In a first aspect, an embodiment of the present application provides a chip self-test method, which is applied to a chip, wherein the chip includes a first storage module, a second storage module and an error injection module, the first storage module interacts with the chip through a first channel, and the second storage module interacts with the chip through a second channel. The chip self-test method includes: pointing a pointer of a main stack in the first storage module to the second storage module; the main stack is an operation stack after an error occurs in the first channel; controlling the error injection module to inject error information into the first channel; performing a self-test operation; after the self-test operation is completed, re-pointing the pointer of the main stack to the first storage module.
[0006] In the second aspect, an embodiment of the present application also provides a chip self-test device, which is applied to a chip, wherein the chip includes a first storage module, a second storage module and an error injection module, the first storage module interacts with the chip through a first channel, and the second storage module interacts with the chip through a second channel, the chip self-test device includes: a first execution module, used to point the pointer of the main stack in the first storage module to the second storage module; the main stack is an operation stack after an error occurs in the first channel; a second execution module, used to control the error injection module to inject error information into the first channel; the second execution module, used to perform a self-test operation; and a fourth execution module, used to re-point the pointer of the main stack to the first storage module after the self-test operation is completed.
[0007] In a third aspect, an embodiment of the present application further provides a chip, comprising a processor, a memory, and one or more applications; the one or more applications are stored in the memory and configured to be executed by the processor to implement the above-mentioned chip self-test method.
[0008] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, in which a program code is stored, wherein the above-mentioned chip self-test method is executed when the program code is run by a processor.
[0009] In a fifth aspect, an embodiment of the present application further provides a computer program product, including a computer program or instructions, characterized in that when the computer program or instructions are executed by a processor, the steps of the above-mentioned chip self-test method are implemented.
[0010] The technical solution provided by the present application is applied to a chip, wherein the chip includes a first storage module, a second storage module and an error injection module. The first storage module interacts with the chip through a first channel, and the second storage module interacts with the chip through a second channel. The chip self-check method includes: pointing the pointer of the main stack in the first storage module to the second storage module; the main stack is the operation stack after an error occurs in the first channel; controlling the error injection module to inject error information into the first channel; performing a self-check operation; after the self-check operation is completed, re-pointing the pointer of the main stack to the first storage module. Thus, by adjusting the dimming module to an opaque state, the image light beam in the optical waveguide is effectively reduced from propagating to the external environment through the dimming module, thereby effectively and simply reducing the light leakage phenomenon of the AR device, thereby reducing the occurrence of information leakage and effectively improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments and drawings obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0012] Figure 1 A schematic structural diagram of a chip provided in an embodiment of the present application is shown.
[0013] Figure 2 A schematic flow chart of a chip self-checking method provided in an embodiment of the present application is shown.
[0014] Figure 3 A schematic structural diagram of a chip self-test device provided in an embodiment of the present application is shown.
[0015] Figure 4 A schematic structural diagram of a chip provided in an embodiment of the present application is shown.
[0016] Figure 5 A schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0017] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.
[0018] In the following description, reference is made to "some embodiments", which describes a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. In the following description, reference is made to the term "multiple" to mean at least two.
[0019] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.
[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0021] The multi-bit error detection in the current random access memory (RAM) instruction error correction technology (Error Checking and Correcting, ECC) is to inject multi-bit ECC errors through the hardware error injection unit. That is, the ECC error injection mechanism of the hardware error injection unit is to inject ECC errors by intercepting the read data bus, check bit bus and address bus of the specified RAM, and flipping the transmission value of the selected bit on these three buses.
[0022] When the central processing unit (CPU) reads and accesses data in the corresponding RAM space through the corresponding bus, it will detect the ECC error corresponding to the RAM. After the error occurs, the error information is reported through the error reporting mechanism.
[0023] Since multi-bit errors can only be used to detect whether the RAM ECC module can work properly, it cannot correct the actual data in the RAM. This results in a bus error when the hardware error injection unit turns on the error injection mechanism, and the CPU reads the data in the RAM space through the corresponding bus, and enters the interrupt processing stage to perform a stack push operation. After the interrupt processing stage, a stack pop operation is performed to read out the data saved in the stack space by the stack push operation and restore it to the RAM, thereby ensuring that subsequent programs can be executed normally.
[0024] However, when executing the stack pop operation, the CPU will access the data in the RAM space through the corresponding bus again, and will detect the ECC error again, resulting in a bus error, and entering the interrupt processing stage again, causing the CPU to enter a locked state, making it impossible to execute subsequent programs, resulting in the microcontroller unit (MCU) not being able to work normally, and the software cannot determine whether the self-test has passed. It can only be restored through an external reset or a watchdog reset. After the reset, it is also impossible to determine whether the self-test has passed, which makes the software self-test impossible.
[0025] In order to improve the above-mentioned problems, the present application provides a chip self-test method, device, chip and storage medium, which are applied to a chip, wherein the chip includes a first storage module, a second storage module and an error injection module, the first storage module interacts with the chip through a first channel, and the second storage module interacts with the chip through a second channel. The chip self-test method includes: pointing the pointer of the main stack in the first storage module to the second storage module; the main stack is the operation stack after an error occurs in the first channel; controlling the error injection module to inject error information into the first channel; performing a self-test operation; after the self-test operation is completed, re-pointing the pointer of the main stack to the first storage module.
[0026] Therefore, by adjusting the pointer pointing to the main stack, the CPU is prevented from accessing the first storage module through the first channel multiple times, thereby preventing the CPU from entering a locked state, preventing the MCU from failing to work normally, and preventing the situation where it is impossible to determine whether the self-test has passed.
[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0028] See also Figure 1 , Figure 1 FIG. 1 shows a schematic diagram of the structure of a chip provided in an embodiment of the present application. Figure 1 As shown, the chip 100 includes a first storage module 101, a second storage module 102 and an error injection module 103, wherein the first storage module 101 interacts with the chip 100 through a first channel, and the second storage module 102 interacts with the chip 100 through a second channel.
[0029] In the embodiment of the present application, the first storage module 101 and the second storage module 102 may be random access memories (RAM).
[0030] It is understandable that the present application does not limit the number of storage modules (RAM) provided on the chip 100 , and the number of storage modules (RAM) can be flexibly determined according to actual conditions.
[0031] In the embodiment of the present application, the first channel may be an address bus, a data bus, and a check bit bus for information exchange between the first storage module 101 and a central processing unit (CPU) in the chip 100 .
[0032] In the embodiment of the present application, the second channel may be an address bus, a data bus, and a check bit bus for information exchange between the second storage module 102 and the central processing unit in the chip 100 .
[0033] In an embodiment of the present application, the error injection module 103 is used to inject a multi-bit error checking and correction (ECC) error into a specified RAM. In some embodiments, the error injection module 103 may be a hardware error injection module. The hardware error injection module injects ECC errors by intercepting a data bus, a check bit bus, and an address bus of a specified RAM and flipping the transmission value of a selected bit on the three buses.
[0034] In some embodiments, the chip 100 further includes an error detection module. The error detection module is used to collect fault information on the chip. The error detection module is connected to the CPU. In an embodiment of the present application, the error detection module is used to collect ECC errors on the first channel.
[0035] When the CPU accesses the specified RAM through the data bus, check bit bus and address bus corresponding to the specified RAM, the CPU will detect the ECC error, causing the CPU to enter the abnormal interrupt processing stage, which will trigger the storage of the data information of the registers on the CPU (for example, the value of the register, the program counter, etc.) to the location pointed to by the pointer of the main stack. The error detection module then performs a self-test result judgment based on the ECC error to determine whether the error detection module has the error detection function, so as to determine whether the chip has the detection capability of detecting ECC errors.
[0036] See also Figure 2 , Figure 2 FIG. 1 is a flow chart of a chip self-checking method provided in an embodiment of the present application. Figure 2 As shown, the chip self-checking method is applied to the above chip, and the chip self-checking method may include steps 210 to 240.
[0037] In step 210, a pointer of the main stack in the first storage module is pointed to the second storage module.
[0038] The main stack is the operation stack after the error occurs in the first channel. The main stack is the stack pointer required by the chip to run the program, which is an area in the RAM. The main stack is used for function calls and saving system context when the CPU is in the abnormal interrupt processing stage, so that the subsequent programs can still run normally after the CPU completes the abnormal interrupt processing.
[0039] Since the pointer of the main stack in the first storage module generally points to the first storage module, after the error injection module injects the ECC error into the first channel, when the CPU accesses the data in the first storage module through the first channel, the CPU will detect the ECC error and then abnormally interrupt the processing stage.
[0040] When the CPU is in the abnormal interrupt processing stage, the CPU will store the data of the register on the CPU to the location pointed by the main stack pointer (MSP) according to the main stack pointer. Then, after the CPU completes the abnormal interrupt processing stage, the data information of the register stored in the first storage module is restored to the register through the first channel according to the main stack pointer, thereby saving the system context and allowing the CPU to continue to run subsequent programs.
[0041] However, due to the ECC error in the first channel, the CPU will detect the ECC error again when restoring the stored data to the register through the first channel according to the main stack pointer, and the CPU will enter the abnormal interrupt processing stage again. At this time, the CPU will enter a locked state and will be unable to continue running subsequent programs.
[0042] Since the CPU cannot continue to run subsequent programs, the microcontroller unit (MCU) in the chip cannot work normally, and it is impossible to determine whether the error detection function of the chip has failed, that is, the software self-check cannot be implemented.
[0043] Before performing a self-check operation on the first storage module, the pointer of the main stack in the first storage module is pointed to the second storage module. In a subsequent step, after the error injection module injects an ECC error into the first channel, when the CPU accesses the first storage module through the first channel, the CPU detects the ECC error and enters the abnormal interrupt processing stage. The CPU stores the data information of the register in the second storage module through the pointer of the main stack pointing to the second storage module in the first storage module.
[0044] After the CPU completes the abnormal interrupt processing stage, the CPU restores the data information stored in the second storage module to the register through the pointer of the main stack of the second storage module in the first storage module, so as to avoid the CPU from being locked, resulting in the inability to determine whether the error detection module has the error detection function, so as to determine whether the chip has the detection capability of detecting ECC errors.
[0045] In step 220, the error injection module is controlled to inject error information into the first channel.
[0046] The error information is a multi-bit ECC error.
[0047] After the pointer of the main stack in the first storage module is pointed to the second storage module, the error injection module is started to inject ECC errors into the first channel, so that when the CPU accesses the first storage module through the first channel, the ECC error is obtained, and the chip self-test result is determined according to the ECC error.
[0048] Further, in some implementations, the step of controlling the error injection module to inject error information into the first channel includes the steps of: calling an error injection function, where the error injection function is used to enable the error injection module to inject error information into the first channel.
[0049] The error injection function is used to simulate the generation of errors. The error injection function may include a channel for simulating the generation of errors and parameters for simulating the generation of errors (such as the bit to be flipped on the bus). For example, the error injection function may include injecting an ECC error on the first channel.
[0050] The error injection function injects an ECC error into the first channel corresponding to the first storage module through the error injection module. After the ECC error is injected into the first channel corresponding to the first storage module, when the CPU accesses any data of the first storage module through the first channel, the ECC error will be detected, and the self-test result of the error detection module will be determined according to the ECC error to determine whether the chip has the detection capability of detecting the ECC error.
[0051] In step 230, a self-check operation is performed.
[0052] After the CPU calls the error injection function to make the error injection module inject error information into the first channel, when the CPU accesses any data in the first storage module through the first channel, an ECC error will be detected, and then the abnormal interrupt processing stage will be entered.
[0053] During the abnormal interrupt processing stage, the CPU will determine the self-test result of the chip according to the ECC error. Specifically, in some implementations, the self-test operation includes the following steps: (1) When error information is read on the first channel, the data information is stored in the second storage module through the second channel according to the pointer of the main stack.
[0054] (2) Determine the self-test result of the first storage module according to the error message and the error information.
[0055] (3) Restore the data information to the chip through the second channel according to the pointer of the main stack to complete the self-test operation.
[0056] The error information is error information read when the CPU accesses any data in the first storage module through the first channel.
[0057] When the CPU accesses any data in the first storage module through the first channel, after reading the error information on the first channel, the data information of the register is stored in the second storage module according to the pointer to the main stack of the second storage module. The error detection module determines whether the error information is consistent with the error information, and then determines the self-test result of the chip.
[0058] Wherein, the error detection module is an external module of the CPU, and the error detection module is used to collect fault information on the chip. In an embodiment of the present application, the error detection module is used to collect ECC errors on the first channel. In other embodiments, the error detection module can also be used to collect other error information on the chip.
[0059] After the error detection module determines the self-test result of the chip, the CPU restores the data information of the register to the register according to the pointer to the main stack of the second storage module to ensure the system context, so that the CPU continues to run subsequent programs, avoids the CPU entering a locked state, and avoids the MCU from failing to work, so as to ensure that it can be determined whether the error detection module has the error detection function.
[0060] Further, in some implementations, the step of determining the self-test result of the first storage module according to the error message and the error information includes the following steps: When the error reporting information is consistent with the error information, it is determined that the self-test result of the first storage module is in a normal state.
[0061] When the error message is consistent with the error message, it is determined that the error detection module can work normally, that is, it is determined that the error detection module has the detection function of detecting ECC errors. When the user uses the chip, if the chip has an ECC error, the error detection module can detect the ECC error autonomously, and then take corresponding actions to avoid safety accidents. For example, when the chip is used in a car, since the error detection module has the ability to detect ECC errors, when the car is driving, if an important module in the car has an ECC error, the error detection module can detect it, and then take remedial measures to avoid serious consequences.
[0062] Furthermore, in some implementations, the error information includes at least one or more of an error status bit and an error address.
[0063] In some implementations, the error information includes at least one or more of an error status bit and an error address.
[0064] In one embodiment, the error information includes an error status bit and an error address, and the error information includes an error status bit and an error address. When the CPU determines that the error status bit in the error information is consistent with the error status bit in the error information, and the error address in the error information is consistent with the error address in the error information, it is determined that the self-test result of the error detection module is in a normal state. That is, the error detection module has the ability to detect ECC errors.
[0065] After the error detection module determines that the error status bit in the error reporting information is consistent with the error status bit in the error information, and the error address in the error reporting information is consistent with the error address in the error information, the error injection module stops injecting error information into the first channel by calling the error injection function.
[0066] In step 240, after the self-check operation is completed, the pointer of the main stack is redirected to the first storage module.
[0067] Since the error injection module stops injecting error information into the first channel by calling the error injection function, when the CPU accesses the data in the first storage module through the first channel, it will not trigger the CPU to enter the abnormal interrupt processing stage, that is, the CPU can access the data in the first storage module normally. Therefore, after the self-check operation is completed, the pointer of the main stack is re-pointed to the first storage module.
[0068] Specifically, in some implementations, before the step of pointing the pointer of the main stack in the first storage module to the second storage module, the chip self-checking method further includes the following steps: The address pointed to by the pointer of the main stack in the first storage module is recorded, and the pointer of the main stack is redirected to the recorded address, thereby redirecting the pointer of the main stack corresponding to the first storage module to the first storage module.
[0069] See also Figure 3 , Figure 3 The structure diagram of a chip self-test device provided in an embodiment of the present application is shown, which is applied to the above chip. The chip self-test device 300 includes: a first execution module 310, a second execution module 320, a third execution module 330 and a fourth execution module 340. Specifically: The first execution module 310 is used to point the pointer of the main stack in the first storage module to the second storage module; the main stack is the operation stack after an error occurs in the first channel.
[0070] The second execution module 320 is used to control the error injection module to inject error information into the first channel.
[0071] The third execution module 330 is used to perform a self-check operation.
[0072] The fourth execution module 340 is used to redirect the pointer of the main stack to the first storage module after the self-check operation is completed.
[0073] In some implementations, the second execution module 320 includes a first execution unit, wherein: The first execution unit is used to call an error injection function, where the error injection function is used to enable the error injection module to inject error information into the first channel.
[0074] In some implementations, the third execution module 330 includes a second execution unit, a third execution unit, and a fourth execution unit, wherein: The second execution unit is used to store the data information in the second storage module through the second channel according to the pointer of the main stack when the error information is read on the first channel.
[0075] The third execution unit is used to determine the self-test result of the first storage module according to the error reporting information and the error information.
[0076] The fourth execution unit is used to restore the data information to the chip through the second channel according to the pointer of the main stack to complete the self-check operation.
[0077] In some embodiments, the third execution unit further includes a first execution subunit, wherein: The first execution subunit is used to determine that the self-test result of the first storage module is in a normal state when the error reporting information is consistent with the error information.
[0078] In some implementations, the error information in the third execution unit includes at least one or more of an error state bit and an error address.
[0079] In some implementations, the error information in the third execution unit includes at least one or more of an error state bit and an error address.
[0080] In some implementations, before the first execution module 310, the chip self-test device 300 further includes a fifth execution module, wherein: The fifth execution module is used to record the address pointed to by the pointer of the main stack in the first storage module.
[0081] In some implementations, the first execution module 310 includes a fifth execution unit, wherein: The fifth execution unit is used to redirect the pointer of the main stack to point to the recorded address.
[0082] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.
[0083] In several embodiments provided in the present application, the coupling or direct coupling or communication connection between the modules shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or modules, which may be electrical, mechanical or other forms.
[0084] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.
[0085] See also Figure 4 , Figure 4 A schematic diagram of the structure of a chip provided in an embodiment of the present application is shown. The terminal device 400 in the present application may include one or more of the following components: a processor 410, a memory 420, and one or more applications, wherein the one or more applications may be stored in the memory 420 and configured to be executed by one or more processors 410, and the one or more programs are configured to execute the anti-light leakage method as described in the aforementioned method embodiment.
[0086] The processor 410 may include one or more processing cores. The processor 410 uses various interfaces and lines to connect various parts of the entire terminal device 400, and executes various functions and processes data of the terminal device 400 by running or executing instructions, programs, code sets or instruction sets stored in the memory 420, and calling data stored in the memory 420. Optionally, the processor 410 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 410 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 410, but may be implemented separately through a communication chip.
[0087] The memory 420 may include a random access memory (RAM) or a read-only memory (ROM). The memory 420 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 420 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the following various method embodiments, etc. The data storage area may also store data created by the terminal device 400 during use.
[0088] See also Figure 5 , Figure 5 A schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present application is shown, wherein the computer-readable medium 500 stores program code, and the program code can be called by a processor to execute the cooking control method described in the above method embodiment.
[0089] The computer-readable storage medium 500 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk or a ROM. Optionally, the computer-readable storage medium 400 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 500 has storage space for program code 510 for executing any method steps in the above method. These program codes can be read from or written to one or more computer program devices. The program code 510 can be compressed, for example, in a suitable form.
[0090] The present invention also provides a computer program product, which includes a computer program. When the computer program product is executed by a processor, the steps of the chip self-test method described in any of the above embodiments are implemented.
[0091] The specific embodiments of the computer program product of the present invention are basically the same as the embodiments of the above-mentioned chip self-test method, and will not be described in detail here.
[0092] The technical solution provided by the present application is applied to a chip, wherein the chip includes a first storage module, a second storage module and an error injection module, wherein the first storage module interacts with the chip through a first channel, and the second storage module interacts with the chip through a second channel, and the chip self-test method includes: pointing the pointer of the main stack in the first storage module to the second storage module; the main stack is the operation stack after an error occurs in the first channel; controlling the error injection module to inject error information into the first channel; performing a self-test operation; after the self-test operation is completed, re-pointing the pointer of the main stack to the first storage module. Thus, by adjusting the pointer pointing of the main stack, the CPU is prevented from accessing the first storage module through the first channel multiple times, thereby preventing the CPU from entering a locked state, and preventing the MCU from being unable to work normally and being unable to determine whether the self-test has passed.
[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A chip self-test method, characterized in that: Applied to a chip, the chip includes a first storage module, a second storage module and an error injection module, the first storage module interacts with the chip through a first channel, the second storage module interacts with the chip through a second channel, and the method includes: Point the pointer of the main stack in the first storage module to the second storage module; the main stack is the operation stack after an error occurs in the first channel; Controlling the error injection module to inject error information into the first channel; Perform self-test operation; After the self-check operation is completed, the pointer of the main stack is redirected to point to the first storage module.
2. The chip self-checking method according to claim 1, characterized in that: The controlling the error injection module to inject error information into the first channel includes: An error injection function is called, where the error injection function is used to enable the error injection module to inject the error information into the first channel.
3. The chip self-checking method according to any one of claims 1-2, characterized in that: The self-checking operation includes: When error information is read on the first channel, the data information is stored in the second storage module through the second channel according to the pointer of the main stack; Determining a self-test result of the first storage module according to the error reporting information and the error information; The data information is restored to the chip through the second channel according to the pointer of the main stack to complete the self-test operation.
4. The chip self-checking method according to claim 3, characterized in that: The step of determining a self-test result of the first storage module according to the error information and the error information to complete the self-test operation includes: When the error reporting information is consistent with the error information, it is determined that the self-test result of the first storage module is in a normal state.
5. The chip self-checking method according to claim 3, characterized in that: The error information at least includes one or more of an error state bit and an error address; And / or, the error information includes at least one or more of an error status bit and an error address.
6. The chip self-checking method according to claim 1, characterized in that: Before pointing the pointer of the main stack in the first storage module to the second storage module, the method further includes: Recording the address pointed to by the pointer of the main stack in the first storage module; The step of pointing the pointer of the main stack in the first storage module to the second storage module comprises: The pointer of the main stack is redirected to point to the recorded address.
7. A chip self-test device, characterized in that: Applied to a chip, the chip includes a first storage module, a second storage module and an error injection module, the first storage module interacts with the chip through a first channel, the second storage module interacts with the chip through a second channel, and the device includes: A first execution module, configured to point a pointer of a main stack in the first storage module to a second storage module; the main stack is an operation stack after an error occurs in the first channel; A second execution module, used for controlling the error injection module to inject error information into the first channel; A third execution module is used to perform a self-check operation; The fourth execution module is used to redirect the pointer of the main stack to the first storage module after the self-check operation is completed.
8. A chip, characterized in that: include: one or more processors; Memory; One or more application programs, wherein the one or more application programs are stored in the memory and are configured to be executed by the one or more processors as the chip self-test method according to any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code can be called by a processor to execute the chip self-test method as described in any one of claims 1-6.
10. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the chip self-test method according to any one of claims 1 to 6 are implemented.