Configurable interface module and electronic equipment

Abstract

The embodiment of the invention provides a configurable interface module and electronic equipment. A configurable interface module comprises: a plurality of timers for outputting one or more clock signals; a plurality of pins for transmitting or receiving data based on the clock signal; the plurality of data processing units are used for processing the data received by the pins and / or outputting the processed data through the pins; the register module is used for receiving configuration information input by the peripheral bus, and the configuration information is at least used for configuring enabling and functions of part or all of the timers, enabling and functions of part or all of the pins and enabling and functions of part or all of the data processing units; therefore, the function of setting the configurable interface module is realized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic devices, and in particular to a configurable interface module and an electronic device. Background Art

[0002] Serial communication bus interfaces such as UART (Universal Asynchronous Receiver Transmitter) and SPI (Serial Peripheral Interface) are widely used in MCU (Micro Controller Unit) as a communication method between embedded devices. Currently, low-speed peripheral interfaces are mostly used as independent modules in engineering. In complex communication systems, these communication interface modules occupy hardware space, are costly and have low flexibility. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a configurable interface module and an electronic device.

[0004] On the one hand, an embodiment of the present application provides a configurable interface module, including:

[0005] A plurality of timers for outputting one or more clock signals;

[0006] A plurality of pins for sending data or receiving data based on the clock signal;

[0007] A plurality of data processing units, used for processing the data received by the pins and / or outputting the processed data through the pins;

[0008] A register module is used to receive configuration information input by the peripheral bus, and the configuration information is at least used to configure some or all of the timer enable and function of multiple timers, some or all of the pin enable and function of multiple pins, and some or all of the data processing unit enable and function of multiple data processing units, so as to realize the function of setting the configurable interface module. In some embodiments, the configurable interface module also includes:

[0009] A timer selection unit is used to enable one or more of the timers based on the configuration of the register module.

[0010] In some embodiments, the plurality of pins include: one or more input pins and one or more output pins;

[0011] The configurable interface module also includes:

[0012] An input selection unit, configured to enable one or more of the input pins based on the configuration of the register module;

[0013] An output selection unit is used to enable one or more of the output pins based on the configuration of the register module.

[0014] In some embodiments, the data processing unit includes:

[0015] Shift register, used to process received data and output;

[0016] The cache unit is used to cache the data to be processed and output the data to the shift register.

[0017] In some embodiments, the signal processing function includes at least one of the following:

[0018] Universal Asynchronous Receiver / Transmitter UART transmission function and / or UART reception function;

[0019] Serial peripheral interface SPI master mode function and / or SPI slave mode function;

[0020] Pulse Width Modulation Waveform Generator PWM function.

[0021] In some embodiments, when implementing the UART sending function and the UART receiving function, the register module configures the UART sending function and the UART receiving function to use different timers, different pins and different data processing units respectively.

[0022] In some embodiments, when the UART transmission function is implemented,

[0023] A first pin among the plurality of pins is configured for UART data transmission based on the register module;

[0024] A first timer among the plurality of timers is configured based on the register module to: indicate a start bit and / or a stop bit of the transmitted data through a timing signal;

[0025] The first processing unit in the data processing unit is configured to process the data to be sent based on the register module and transfer the data to the first pin; and output the start bit and / or the stop bit according to the timing signal.

[0026] In some embodiments, the start bit or the stop bit comprises one or more bits respectively;

[0027] The register module is specifically configured to insert the one or more stop bits into the data to be sent according to the configuration information.

[0028] In some embodiments, a second pin among the plurality of pins is configured to receive a clear-to-send (CTS) signal based on the register module.

[0029] In some embodiments, the register module is further used to configure sending an interrupt signal or an idle signal based on the configuration information;

[0030] The first processing unit sends the corresponding first preset data before sending the interrupt signal, or sends the corresponding second preset data before sending the idle signal according to the configuration of the register module.

[0031] In some embodiments, when the UART receiving function is implemented,

[0032] A third pin among the plurality of pins is configured as UART data reception based on the register module;

[0033] A second timer among the plurality of timers is configured based on the register module to: indicate a start bit and / or a stop bit of received data through a timing signal;

[0034] The second processing unit in the data processing unit is configured to cache the data received by the third pin based on the register module; and verify the start bit and / or the stop bit according to the indication of the timing signal.

[0035] In some embodiments, a fourth pin among the plurality of pins is configured to receive a request to send (RTS) signal based on the register module.

[0036] In some embodiments, a third timer among the plurality of timers is configured based on the register module to: filter glitch anomalies in the received data.

[0037] In some embodiments, a fourth timer among the plurality of timers is configured based on the register module to detect whether the duration of an idle character as a preset character meets a preset length, so as to determine whether the sleep mode of the configurable interface is awakened.

[0038] In some embodiments, when implementing the SPI master mode function and / or the SPI slave mode function, the register module configures the SPI master mode function and the SPI slave mode function to use different timers, different pins and different data processing units respectively.

[0039] In some embodiments, when the SPI master mode and / or the SPI slave mode functions are implemented, a fifth pin among the plurality of pins is configured as SPI data reception based on the register module, and three sixth pins are configured as SPI data transmission based on the register module;

[0040] A fifth timer among the plurality of timers is configured based on the register module to: output a clock signal indicating reception of the SPI data; a sixth timer among the plurality of timers is configured based on the register module to: output a clock signal indicating transmission of the SPI data;

[0041] A third processing unit among the multiple data processing units is configured based on the register module to: cache data received by the fifth pin; and a fourth processing unit among the multiple data processing units is configured based on the register module to process data to be sent and send it through the sixth pin.

[0042] In some embodiments, the register module is further configured to maintain assertion during the SPI data reception process; wherein the stop counting state flag of the fifth timer is used to indicate stopping the SPI data reception;

[0043] The data processing unit is configured to set a shift error flag in the register module if the received data has not been completely cached before receiving the assertion indication signal.

[0044] In some embodiments, when implementing the PWM function,

[0045] A seventh timer among the plurality of timers is configured to count respectively the high level and the low level of the PWM signal to be output based on the register module;

[0046] The seventh pin among the plurality of pins is configured based on the register module to output the high level and the low level in sequence based on the count of the seventh timer to output the PWM signal.

[0047] In some embodiments, the configurable interface module further includes: a direct memory access DMA signal transmitter;

[0048] The DMA signal sending end is configured to send the number of data to be transmitted to an external DMA controller; wherein the DMA controller is used to start data transmission and reception between the configurable interface module and other data transceiver devices.

[0049] In some embodiments, the configurable interface module further includes: an interrupt signal sending end;

[0050] The interrupt signal sending end is configured to send a required interrupt signal when the configurable interface module is used to implement a data transmission function.

[0051] On the other hand, an embodiment of the present application provides an electronic device, comprising: a processor and any one of the above-mentioned configurable interface modules;

[0052] The processor is connected to the configurable interface module via a peripheral bus;

[0053] The processor is used to configure a register module in the configurable interface module to configure a signal processing function implemented by the configurable interface module.

[0054] The embodiment of the present application can realize a variety of different data transmission functions by providing a configurable module with multiple timers, multiple pins and multiple data processing units. In addition, the configurable interface module determines the selected timer, pin and data processing unit through the configuration information in the register module, and determines the functions of the timer, pin and data processing unit, and then determines the function realized by the configurable interface module. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A structural block diagram of a configurable interface module provided in an embodiment of the present application;

[0056] Figure 2 A structural block diagram of another configurable interface module provided in an embodiment of the present application;

[0057] Figure 3 This is a structural block diagram of another configurable interface module provided in an embodiment of the present application;

[0058] Figure 4 A schematic diagram of a configurable interface module provided in an embodiment of the present application;

[0059] Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The following will be combined with the embodiments of the present application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0064] like Figure 1 As shown, the embodiment of the present application provides a configurable interface module 100, including:

[0065] A plurality of timers 110, configured to output one or more clock signals;

[0066] A plurality of pins 120 for sending data or receiving data based on a clock signal;

[0067] A plurality of data processing units 130, for processing data received by the pins 120 and / or outputting the processed data through the pins 120;

[0068] The register module 140 is used to receive configuration information input by the peripheral bus APB, and the configuration information is used to configure at least the enable and function of some or all of the multiple timers 110, the enable and function of some or all of the multiple pins 120, and the enable and function of some or all of the multiple data processing units 130, so as to realize the function of setting the configurable interface module 100.

[0069] In the embodiment of the present application, the configurable interface module 100 can realize various data communication or signal generation functions, such as UART data transceiver function, SPI interface and PWM signal generator, etc., through different combinations of pins, timers and data processing units, functions, connection methods or corresponding relationships. According to the specific requirements or protocols of the environment or system or device in which the configurable interface module 100 is located, the above components can be flexibly configured. For example, in a communication system, modules including UART, SPI and PWM also include the above configurable interface module 100. When a certain module of the communication system is occupied or damaged, the configurable interface module 100 can be configured as an additional module to supplement or replace it. For example, when the UART module is occupied by other buses and the current communication needs to use the UART module, the configurable interface module 100 is configured as a UART module to replace the original UART module to realize its data receiving or sending function. When the original UART module is released from occupation, the configurable interface module 100 can be reconfigured as a module with other functions, for example, it can be reconfigured as a PWM signal generator.

[0070] The register module 140 connected to the peripheral bus APB can be used to configure the correspondence between the timer 110, the pin 120 and the data processing unit 130 according to the configuration information input by the peripheral bus APB; wherein, the configurable interface module 100 can be used to implement different signal processing functions under different correspondences. For example, the timer can determine the transmission timing of the pin or the data processing timing of the data processing unit; for another example, the timer can be used to implement a specified data processing function or specified data transmitted by the pin, etc. Moreover, since the timing periods of different timers may be different, the input and output methods of the pins may be different, and the processing methods of the data processing unit may also be different, therefore, when implementing different functions, the connection relationship combination of the timer, pin and data processing unit can be switched through the configuration information, thereby realizing various different functions. Specifically:

[0071] The configurable interface module 100 in the embodiment of the present application can output clock signals of various frequencies through the timer 110, so as to provide the clock edge or timing required for data transmission. In addition, the timer can also provide various counting information required for data transmission, such as the start bit or stop bit of data transmission.

[0072] The plurality of pins 120 may include one or more input pins for data reception, or one or more output pins for data transmission.

[0073] The data processing unit 130 may be connected to the pin 120. For example, the data processing unit 130 may be connected between the input pin and the output pin, respectively, to process the received input data and output it through the output pin. For example, the data processing unit 130 may be a buffer or a shifter, etc., so as to adjust the timing of data transmission or the serial / parallel transmission mode, or insert bits of a specified format into the data to be transmitted according to a predetermined rule, realize the encapsulation of the data format, and parse the received data, etc.

[0074] The register module 140 is used to configure the selected timer 110, pin 120 and data processing unit 130, and enable the selected timer 110, pin 120 and data processing unit 130. For example, the register module 140 outputs enable or disable signals to different timers 110, pin 120 and data processing unit 130, or the register module 140 conducts or switches the connection of the timer 110, pin 120 and data processing unit 130 to enable the required units. The register module 140 is also used to configure the functions required to be implemented by the timer 110, pin 120 and data processing unit 130, for example, by adjusting the connection relationship, quantity and signal timing of the timer 110, pin 120 and data processing unit 130 to configure their functions. The register module 140 is connected to an external processor through the peripheral bus APB. The configuration in the register module 140 can be edited or rewritten by an external CPU or DMA, so as to flexibly set the function of the configurable interface module 100. In this way, the configurable interface module 100 can be used to implement interfaces of various communication modes in embedded devices.

[0075] In the embodiment of the present application, the configurable interface module 100 implements different functions, which may include simplex data transceiver functions such as UART, duplex data transceiver functions such as SPI, signal generator functions such as PWM, etc. The configurable interface module 100 can implement any function under the configuration of the register module 140, and change the function it implements when the configuration is changed. In other words, the configurable interface module 100 can change the configuration repeatedly to achieve different functions in different demand scenarios.

[0076] Specifically, the register module 140 can receive external input configuration information through APB to implement a configuration, thereby determining the specific functions of the current configuration. After the configuration is completed, APB can be disconnected from an external device, such as a computer device, or other devices with core components such as a CPU, or it can remain connected, but can stop receiving configuration information. At this time, the configurable interface module 100 is used to implement a function and is used as an independent functional module. Afterwards, the configuration information can be changed again through the APB interface so that the function of the configurable interface module 100 is changed, so that it can be used again as a new functional module. In other words, the function implemented by the configurable interface module 100 can be changed by changing the configuration information through APB, so that it can be used as a different functional module in different scenarios.

[0077] It should be noted that the timing for changing the configuration information of the configurable interface module 100 may be that the register module 140 receives a new configuration signal through APB and directly enters the configuration process; or it may be that the register module 140 receives a relevant indication signal of the APB interface bridging to the APB bus, or a relevant signal controlled by DMA, so that the register module 140 enters the configuration process, and then further changes the configuration through the configuration information received by APB, and ends the configuration process after the configuration is completed, enters the use mode, and implements specific module functions in the use mode.

[0078] In some embodiments, Figure 2 As shown, the configurable interface module 100 also includes:

[0079] The timer selection unit 150 is used to enable one or more timers based on the configuration of the register module 140 .

[0080] Exemplarily, the timer selection unit 150 may be implemented by a data selector, a switch or other components and combinations thereof. According to the configuration of the register module 140, the timer selection unit 150 may select a required timer to access and be used to implement a specific counting or clock function.

[0081] In some embodiments, the plurality of pins 120 include: one or more input pins 121 and one or more output pins 122;

[0082] The configurable interface module 100 further includes:

[0083] An input selection unit 160 for enabling one or more input pins 121 based on the configuration of the register module 150;

[0084] The output selection unit 170 is used to enable one or more output pins 122 based on the configuration of the register module 150 .

[0085] In one embodiment, a number of the plurality of pins 120 may be fixed as input pins 121, and the other part may be fixed as output pins 122. For example, the configurable interface module 100 may include 8 pins, 4 of which are input pins and the other 4 are output pins. The input selection unit 160 is connected to each input pin 121 and the register module 150, and selects the input pin 121 to be used according to the configuration information of the register module 150. The output selection unit 170 is connected to each output pin 122 and the register module 150, and selects the output pin 122 to be used according to the configuration information of the register module 150.

[0086] In another embodiment, the types of the plurality of pins 120 may not be fixed, and each pin may be used as an input pin 121 or an output pin 122 according to the configuration of the register module 150. In applications with different functions, the input and output types of the pins may be switched. In this case, the input selection unit 160 connects all the pins 120 and the output selection unit 170 connects all the pins 120, and selects the required pin 120 as the input pin 121 or the output pin 122 based on the configuration of the register module 150.

[0087] In some embodiments, Figure 2 As shown, the data processing unit 130 includes:

[0088] Shift register 131, used for processing received data and outputting it;

[0089] The buffer unit 132 is used to buffer the data to be processed and output the data to the shift register 131 .

[0090] In the embodiment of the present application, the shift register 131 can be used to implement data processing functions in various communication interfaces, thereby adjusting the timing or transmission mode of data transmission, for example, implementing functions such as serial-to-parallel conversion or parallel-to-serial conversion.

[0091] The cache unit 132 is used to cooperate with the shift register 131 to temporarily store data to be processed or temporarily store processed data to be output. Exemplarily, each shift register 131 can be connected to a cache unit 132. In one embodiment, each cache unit can have a cache space of a fixed size, which is individually connected to each shift register; in another embodiment, the cache unit can include a plurality of cache spaces that can be flexibly allocated and allocated to a plurality of different shift registers for use, so as to meet the requirements of different interface functions of the configurable interface module 100, and the division of the cache space can be flexibly configured by the register module 140.

[0092] In some embodiments, the signal processing function includes at least one of the following:

[0093] Universal Asynchronous Receiver Transmitter (UART) transmit function and / or UART receive function;

[0094] Serial Peripheral Interface (SPI) master mode functionality and / or SPI slave mode functionality;

[0095] Pulse-Width Modulation (PWM) waveform generator function.

[0096] UART is a popular and widely used peripheral interface device in the field of digital communication. It is a type of asynchronous serial communication protocol. UART can communicate in both directions and can achieve full-duplex transmission and reception.

[0097] SPI is a high-speed synchronous serial interface that can communicate with multiple slave devices. The SPI interface can be used for serial data transmission. The synchronous and high-speed serial transmission method makes it have a wide range of applications. For example, the SPI interface is often used to read the application program in FLASH.

[0098] PWM, as a pulse width modulation waveform generator, can generate sound based on stored sampled audio files, and can also be used to output high and low level signals with different duty cycles.

[0099] The functions of the configurable interface module 100 can be configured through the configuration of the register module 130 , and the above-mentioned different interface functions can be realized by adjusting the functions of the configured timer 110 , the pin 120 and the data processing unit 130 .

[0100] The following describes the functions for implementing different situations:

[0101] In some embodiments, when implementing the UART transmission function and the UART reception function, the register module configures the UART transmission function and the UART reception function to use different timers, different pins, and different data processing units, respectively.

[0102] The above-mentioned configurable interface module can realize the UART transmission function or the UART reception function alone, or can realize the UART transmission and reception functions at the same time. When realizing the UART transmission function and the UART reception function at the same time, different timers, pins and data processing units are used respectively. Therefore, the number of pins, the number of timers and the number of data processing units of the configurable interface module need to meet the total number required by the two functions.

[0103] In some embodiments, when the UART transmission function is implemented,

[0104] A first pin among the plurality of pins is configured for UART data transmission based on the register module;

[0105] A first timer among the plurality of timers is configured based on the register module to: indicate a start bit and / or a stop bit of the transmitted data through a timing signal;

[0106] The first processing unit in the data processing unit is configured to process the data to be sent based on the register module and transfer the data to the first pin; and output a start bit and / or a stop bit according to the timing signal.

[0107] It is understandable that the UART frame format includes: the start bit, data bit, check bit and stop bit of the data frame. The start bit is generally a fixed low level, used to mark the beginning of the data frame; the data bit contains the valid data to be transmitted, such as 5 to 9 bits of data; the check bit is optional, used for data verification, which can be odd check, even check or no check; the stop bit is a fixed high level of one or two bits, used to mark the end of the data frame.

[0108] Therefore, when the UART transmission function is realized by using the above-mentioned configurable interface module, a pin (referred to as the "first pin" here for ease of description) can be selected as the data transmission pin. Here, the first pin can be any pin. If the multiple pins of the configurable interface module are divided into fixed input pins and output pins, the first pin here can be any output pin. In addition, the function of identifying the start bit and / or stop bit in the UART data frame is realized by a timer (referred to as the "first timer" for ease of description). For example, if 8 bits of data are transmitted, the next clock pulse after 8 bits is transmitted as the identification of the stop bit through the counting of the timer, thereby determining the end of data transmission.

[0109] Since UART is a serial communication protocol, only one data processing unit (referred to as a "first processing unit" for ease of description) is needed to process the data that the UART needs to send.

[0110] In some embodiments, the start bit or the stop bit includes one or more bits respectively; the register module is specifically used to insert one or more stop bits into the data to be sent according to the configuration information.

[0111] By counting the first timer, two or more start bits or stop bits can be supported, and the number of start bits or stop bits can be set by configuring the register module. When data is sent, the data processing unit can insert corresponding stop bits into the data to be sent based on the count of the first timer and the set number of stop bits.

[0112] In some embodiments, a second pin of the plurality of pins is configured to receive a CTS signal based on a register module.

[0113] CTS is a signal used by the data receiving end to notify the sending end whether it is ready to receive data. The data sending end determines whether to send data to the receiving end module based on the received CTS signal. For example, the effective level of CTS is low, that is, when the CTS signal is low, it indicates that the module is ready to receive data. The CTS signal can be used to implement data flow control in serial communication to avoid data overflow.

[0114] In the embodiment of the present application, when the configurable interface unit is used as a UART transmission function, a CTS function can be supported. Another pin other than the first pin (herein referred to as the "second pin") is used to receive a CTS signal to determine the state of the data receiving end and allow data transmission to begin.

[0115] Thus, when the configurable interface unit is configured to implement the UART data transmission function, one or two pins, a timer and a data processing unit are required. If other control functions need to be implemented on this basis, the use of other pins, timers and data processing units can also be additionally set.

[0116] In some embodiments, the register module is further used to configure sending an interrupt signal or an idle signal based on the configuration information;

[0117] The first processing unit sends the corresponding first preset data before sending the interrupt signal, or sends the corresponding second preset data before sending the idle signal according to the configuration of the register module.

[0118] Before the first processing unit sends an interrupt signal or an idle signal, it may first send a specified set of data to indicate that the character to be sent next is an interrupt character or an idle character. For example, before sending an interrupt character or an idle character, data 0xFF or 0x00 is sent.

[0119] In some embodiments, when implementing the UART receiving function,

[0120] A third pin among the plurality of pins is configured as a UART data reception based on the register module;

[0121] A second timer among the plurality of timers is configured based on the register module to: indicate a start bit and / or a stop bit of received data through a timing signal;

[0122] The second processing unit in the data processing unit is configured to buffer the data received by the third pin based on the register module; and verify the start bit and / or the stop bit according to the instruction of the timing signal.

[0123] If the above-mentioned configurable interface module realizes the UART receiving function alone, the above-mentioned third pin can be any pin. If the multiple pins of the configurable interface module are divided into fixed input pins and output pins, the third pin here can be any input pin. If the configurable interface module realizes the UART receiving function and the sending function at the same time, the third pin and the first pin are two different pins, and the first pin can be any pin among the output pins, and the third pin can be any pin among the input pins.

[0124] Similar to the UART transmission function, a timer (called the "second timer") is used to configure the start bit and stop bit in the UART data frame. The corresponding data processing unit (called the "second processing unit") verifies the start bit and stop bit in the received data based on the timing of the timer.

[0125] In some embodiments, a fourth pin among the plurality of pins is configured to receive a request to send (RTS) signal based on the register module.

[0126] The RTS signal is a signal used by the data sending end to notify the receiving end that it is ready to send data, that is, it indicates a request to send data. When the data receiving end is ready to receive data, the data can be sent.

[0127] The RTS signal and the CTS signal are two signals used to control data transmission in serial communication. The RTS signal serves as a request signal for data transmission, and the CTS signal serves as a response to the RTS signal. The two work together on the sending and receiving ends of half-duplex communication to achieve data transmission between the two parties and prevent conflicts when sending and receiving data.

[0128] In the embodiment of the present application, when the configurable interface unit is used as a UART receiving function, the RTS function can be supported. Another pin other than the third pin (here referred to as the "fourth pin") is used to receive the RTS signal to determine the state of the data transmitting end and whether there is data to be received.

[0129] Thus, when the configurable interface unit is configured to realize the UART data receiving function, one or two pins, a timer and a data processing unit are required. If other control functions need to be realized on this basis, the use of other pins, timers and data processing units can also be set additionally.

[0130] It is understandable that if the configurable interface unit is configured to simultaneously implement the above-mentioned UART data transmission function and UART data reception function, two or four pins, two timers and two data processing units are required.

[0131] In some embodiments, a third timer among the plurality of timers is configured based on the register module to: filter glitch anomalies in the received data.

[0132] Here, when implementing the above-mentioned UART data transmission or data reception function, another timer can also be used as a fault filter. In digital circuits, switch bounce, electromagnetic interference or reflection on the signal transmission line may cause short (such as a few nanoseconds), undesirable signal jumps, which are called glitch anomalies. If the configurable interface module only samples once in the middle of each bit of data, data errors will occur if a glitch anomaly occurs during sampling. Therefore, the third timer is used here to set the input signal change to a certain time before it is considered as a correct output, thereby eliminating the burrs. Therefore, an additional timer can be used here as a fault filter to filter out the burrs.

[0133] In some embodiments, a fourth timer among the multiple timers is configured based on the register module to detect whether the duration of the idle character as a preset character meets the preset length, so as to determine whether the sleep mode of the configurable interface is awakened.

[0134] The idle character refers to a character in which the start bit, all data bits and stop bits are preset characters, for example, all are "1". The function of the idle character is to wake up the configurable interface module when it is set to a wake-up mode in sleep mode, i.e., the idle character. Whether to wake up is determined by using a fourth timer to check whether the length of the idle character remains 1 for a certain period of time. Exemplarily, the length of the idle character, i.e., the preset length, can be set to 10 bits (1 stop bit, 8 data bits, 1 start bit) or more.

[0135] It is understandable that if the configurable interface module can realize the UART data transmission function and the receiving function at the same time, the two above-mentioned "third timers" can be selected as the fault filters required for the data transmission function and the data receiving function, and the two "fourth timers" can be selected to realize the wake-up mode of the data transmission function and the data receiving function. In this case, the configurable interface module needs to have at least 2 or 4 pins, 6 timers and 2 data processing units. Therefore, it is understandable that if the configurable interface module is to be able to flexibly realize a variety of different functions, more pins, timers and data processing units can be set for backup.

[0136] In some embodiments, when implementing the SPI master mode function and / or the SPI slave mode function, the register module configures the SPI master mode function and the SPI slave mode function to use different timers, different pins, and different data processing units respectively.

[0137] The above configurable interface module can realize the SPI master mode function or the SPI slave mode function alone, or can realize the SPI master mode function and the SPI slave mode function at the same time. In the case of realizing the SPI master mode function and the SPI slave mode function at the same time, different timers, pins and data processing units are used respectively. Therefore, the number of pins, the number of timers and the number of data processing units of the configurable interface module need to meet the total number required by the two functions.

[0138] SPI master mode and slave mode are both SPI communication protocols, which stipulate that the communication between SPI devices needs to be controlled by the master device. The configurable interface unit is used as a master device to implement the SPI master mode and as a slave device to implement the SPI slave mode. The master device can control one or more slave devices by providing a clock signal and selecting the slave device.

[0139] The master device can generate corresponding clock pulses according to the exchanged data, and control when the two SPI devices exchange data and when to sample the received data through clock polarity (ClockPolarity, CPOL) and clock phase (ClockPhase, CPHA), ensuring that the data is transmitted synchronously between the two devices.

[0140] SPI supports full-duplex communication, that is, data can be transmitted in both directions at the same time. Both the master device and the slave device have serial shift registers. The master device initiates a transmission by writing a byte to its serial shift register.

[0141] In some embodiments, when the SPI master mode and / or SPI slave mode functions are implemented, a fifth pin among the plurality of pins is configured as SPI data reception based on the register module, and three sixth pins are configured as SPI data transmission based on the register module;

[0142] A fifth timer among the multiple timers is configured based on the register module to: output a clock signal indicating SPI data reception; a sixth timer among the multiple timers is configured based on the register module to: output a clock signal indicating SPI data transmission;

[0143] The third processing unit among the multiple data processing units is configured based on the register module to: cache data received by the fifth pin; the fourth processing unit among the multiple data processing units is configured based on the register module to process the data to be sent and send it through the sixth pin.

[0144] SPI master-slave mode data transmission requires three signals, including chip select signal, clock signal and signal for determining input and output relationship, specifically:

[0145] The three signals required for data transmission in SPI master mode are: 1. Chip Select / Slave Select (CS / SS), which is used to send to the specified slave device to activate the slave device for communication. For example, the master device can select the slave device by pulling the chip select signal low; 2. Clock signal (Serial Clock, SCLK), which is used to synchronize the data transmission between the master device and the slave device. The master device generates a clock signal to control the rate and timing of data transmission. The clock signal can be implemented by the fifth timer mentioned above; 3. Master Output Slave Input (MOSI) The master device sends data to the slave device through this line. Data is sent in bits, for example, it can be sent from the most significant bit (MSB). In addition, another signal is required for data reception in SPI master mode.

[0146] The three signals required for data transmission in SPI slave mode are: 1. CS / SS signal, a signal controlled by the master device, used to activate the slave device. When the master device pulls the CS / SS line low, the selected slave device is activated and ready to receive clock signals and data, as well as send data. 2. SCLK signal, generated by the master device, used to synchronize the sending and receiving of data. The slave device determines when to send data based on the SCLK signal. In other words, in SPI slave mode, the CS / SS signal and the SCLK signal are also sent by the master device, and the SPI slave device receives these two signals and sends data based on these two signals. 3. Master Input Slave Output (MISO), a signal line used by the slave device to send data to the master device. The slave device sends the data bits to the master device through the MISO line, and the direction of data transmission is from the slave device to the master device. In addition, similar to the master mode, data reception in SPI slave mode also requires an additional signal.

[0147] In summary, the configurable interface module needs four pins to implement the SPI master mode or slave mode, as the three signals required for sending data and one signal required for receiving data. In addition, a timer and a data processing unit are also required.

[0148] To implement the above SPI master mode and slave mode at the same time, 8 pins, two timers and two data processing units are required.

[0149] In some embodiments, the register module is further configured to maintain assertion during the SPI data reception process; wherein the stop counting state flag of the fifth timer is used to indicate the stop of SPI data reception;

[0150] The data processing unit is configured to set a shift error flag in the register module if the received data has not been completely cached before receiving the assertion indication signal.

[0151] Since the fifth timer is used as the clock signal for data reception in the SPI master mode and the slave mode, the signal is used to achieve synchronization between the data transmitter and the receiver. Therefore, the timing count of the fifth timer can also be used to indicate the start or stop of SPI data reception. Specifically, here, the SPI data reception is indicated by the stop count state flag of the fifth timer, and the stop count state flag can be a preset count value. The assertion indication signal can be realized by the predetermined data received by the data receiving end. If the received data is not cached before the data processing unit receives the assertion indication signal, it cannot be received normally, so the data reception error is indicated by setting the register, and the shift error flag is set so that the register can be read externally to confirm the data reception error.

[0152] In some embodiments, the configurable interface module further includes: a DMA signal sending end;

[0153] The DMA signal sending end is configured to send the number of data to be transmitted to an external DMA controller; wherein the DMA controller is used to start data transmission and reception between the configurable interface module and other data transceiver devices.

[0154] For the above-mentioned UART data sending function or data receiving function, and SPI function, multiple transmissions can be supported through DMA signals, for example, the number of multiple transmissions can be set through DMA.

[0155] DMA is a computer technology used to allow certain hardware subsystems (such as computer peripherals) to read and write system memory directly independent of the CPU. This technology can significantly improve data transfer efficiency and reduce the CPU burden, especially when processing large amounts of data transfer.

[0156] The configurable interface module can be used as a DMA controller to send DMA signals to coordinate data transmission and reception with the other end.

[0157] In some embodiments, the configurable interface module further includes: an interrupt signal sending end;

[0158] The interrupt signal sending end is configured to send a required interrupt signal when the configurable interface module is used to implement the data transmission function.

[0159] When the above configurable interface module implements the UART data receiving or data sending function and the SPI function, it may also be necessary to send an interrupt signal to notify the processor or the other end of the data receiving and sending that an event that needs to be processed immediately has occurred. Therefore, the configurable interface module may additionally include an interrupt signal sending end, which is used solely for sending an interrupt signal.

[0160] In some embodiments, when implementing the PWM function,

[0161] A seventh timer among the plurality of timers is configured to count respectively the high level and the low level of the PWM signal to be output based on the register module;

[0162] The seventh pin among the plurality of pins is configured based on the register module to output a high level and a low level in sequence based on the count of the seventh timer to output a PWM signal.

[0163] In the embodiment of the present application, in addition to realizing the data transmission function through the above-mentioned configurable interface module, it can also be used as a signal generator to realize the PWM function. PWM is a pulse width modulation signal generator, which can control the intensity or power of the output analog signal by changing the width of the pulse, and can be widely used in various electronic devices and systems.

[0164] PWM uses a digital signal (square wave) to simulate an analog signal, and controls the strength of the analog signal by adjusting the duty cycle of the square wave. The duty cycle refers to the ratio of the high level time in the PWM signal to the entire cycle time. The higher the duty cycle, the higher the average output voltage or power, and the lower the duty cycle, the lower the average output voltage or power.

[0165] In the embodiment of the present application, a timer (herein referred to as the "seventh timer") in the configurable interface module is used to count the high and low levels of the PWM signal, and the output pin outputs a high level according to the high level count value, and then outputs a low level according to the low level count value. By setting the count value through the register module, the duty cycle of the PWM can be changed, thereby realizing pulse width modulation.

[0166] It is understandable that the above-mentioned "Xth timer", "Xth pin" and "Xth data processing unit" are distinguished for the convenience of description and do not necessarily mean that they must be different. In actual applications, the configurable interface module can be configured to implement different functions in different situations. The same pin, timer or data processing unit can be called to implement different functions at different times. Whether it is called and what function it implements is only determined by the configuration of the current register module.

[0167] The present application also provides the following examples:

[0168] As a communication method between embedded devices, serial communication bus interfaces such as UART and SPI are widely used in MCU. Currently, low-speed peripheral interfaces are mostly used as independent modules in engineering.

[0169] UART is a popular and widely used peripheral interface device in the field of digital communication. It is a type of asynchronous serial communication protocol. UART can communicate in both directions and can achieve full-duplex transmission and reception.

[0170] SPI is a high-speed synchronous serial interface that can communicate with multiple slave devices. The SPI interface can be used for serial data transmission. The synchronous and high-speed serial transmission method makes it have a wide range of applications. For example, the SPI interface is often used to read the application program in FLASH.

[0171] PWM, as a pulse width modulation waveform generator, can generate sound based on stored sampled audio files, and can also be used to output high and low level signals with different duty cycles.

[0172] As one of the common modules in the subsystem, when the number of communication modules (such as UART) required is insufficient, this highly configurable module can imitate the communication behavior of UART according to the protocol and replace the required UART for communication. In addition, it can also act as a PWM to give the required waveform signal when an additional waveform generator is needed.

[0173] Regarding the current application of communication modules, there are mainly the following technical problems:

[0174] 1. For applications that require multiple communication protocols and an indefinite number, multiple separate UART, SPI, and PWM modules may be required, which will increase hardware cost and space occupation.

[0175] 2. If additional dedicated modules are needed in rare cases, each dedicated module usually occupies specific hardware resources, and these resources may be wasted if some modules are not used during a specific period.

[0176] 3. For smaller applications or systems with limited resources, using multiple dedicated modules may lead to unnecessary cost increases.

[0177] Based on this, an embodiment of the present application provides a configurable universal module interface (CUMI), which can provide multiple protocol formats, including: UART, SPI and PWM, etc.

[0178] like Figure 3As shown, the module consists of 4 shifters (shift0-shift3), 4 timers (timer0-timer3) and 8 pins (pin0-pin7), and includes the following interfaces:

[0179] 1. APB bus interface (APB_BUS), through which the register module (Registers) is read and written;

[0180] 2. 1 interrupt signal port (int);

[0181] 3. 16 input trigger signal ports (Trigger_in[15:0]);

[0182] 4. 4 output trigger signal ports (Trigger_out[3:0]);

[0183] 5. 8 pins (pin[7:0]);

[0184] 6. 4 DMA request signals (DMA_REQ[3:0]).

[0185] In addition, the eight pins are also connected via a pin selection unit (Pinmux). It should be noted that the above shifter is an example of an implementation of the "data processing unit" involved in any of the above embodiments.

[0186] The principle, specific structure and signal direction of the above configurable interface module are as follows: Figure 4 As shown, the register module (Registers) is connected to the outside through APB_Bus, and the external processor can set the specific functions of the configurable interface module by editing the configuration information in the register module.

[0187] The four timers (timer0-timer3) output the required clock signal through the external trigger signal, and the clock selection unit (Timer_sel) selects the clock signal currently required based on the configuration of the register.

[0188] The 8 pins can be divided into 4 input pins (pin_in[3:0]) and 4 output pins (pin_out[3:0]). The input pins are selected by the input selector (Input_sel) based on the configuration of the register, and the output pins are selected by the output selector (Output_sel) based on the configuration of the register. Multiple shifters (shifer[3:0]) are connected between the input selector and the output selector, and each shifter is also connected to a 32-bit buffer unit (Shifter_buf[3:0]).

[0189] The input trigger signal port (Trigger_in[15:0]) can be used to receive an external input control signal to control the data input of the configurable interface module. For example, it is used to provide a clock signal for the input signal, or to trigger the timing of the internal timer, as a clock signal for the input signal or to trigger other functions of the timer. Similarly, the output trigger signal port (Trigger_out[3:0]) is also used to receive an external input control signal to control the data output of the configurable interface module. For example, it is used to provide a clock signal for the output signal, or to trigger the timing of the internal timer, as a clock signal for the output signal or to trigger other functions of the timer. In other words, the timer in the configurable interface module provided in the embodiment of the present application can be configured through a register module, and can also be triggered and used by an external input trigger signal.

[0190] The following describes the configuration of the above configurable interface modules to implement different functions:

[0191] 1. UART sending function:

[0192] Uses a timer, a shifter and a pin (two pins if CTS is supported) to emulate UART transmission. Start and stop bit insertion is handled automatically, and multiple transfers are supported using DMA. The timer status flag can be used to indicate when the stop bit of each word is sent.

[0193] Break and idle characters require software intervention. Before sending a "break" or "idle" character, the data to be sent should be equal to 0xFF or 0x00. A second stop bit is supported. Software is required to insert the stop bit into the data stream (and increase the number of bits to be transmitted). Automatic insertion of parity bits is not supported.

[0194] 2. UART receiving function:

[0195] UART reception is simulated using one timer, one shifter, and one pin (two timers and two pins if RTS is supported). Start and stop bit verification is handled automatically, and multiple transfers can be supported using the DMA controller. The timer status flag can be used to indicate when the stop bit of each word has been received.

[0196] Oversampling of received data is not supported, data is sampled only once in the middle of each bit. Another timer can be used to implement a glitch filter on the incoming data, and another timer can also be used to detect idle characters of programmable length. Automatic verification of the parity bit is not supported.

[0197] 3. SPI master mode:

[0198] Uses two timers, two shifters, and four pins to emulate SPI master mode. Can support CPHA=0 or CPHA=1, and can use DMA controller to support transfers. For CPHA=1, the selection can remain asserted for multiple transfers, and the timer status flag can be used to indicate the end of the transfer.

[0199] The stop bit is used to ensure that there is at least one clock cycle from the invalid edge (rising or falling edge) of the clock to the next transfer. Writing to the transfer buffer by the CPU or DMA is used to start each transfer.

[0200] Due to synchronization delay, the setup time of input data is 1.5 clock cycles, so the cycle required to complete one bit of data transmission is actually 1.5*2+1, 1 is the time margin, that is, 4 cycles to complete one bit of transmission, so the maximum supported SPI rate is the clock frequency divided by 4.

[0201] 4. SPI slave mode:

[0202] Uses one timer, two shifters, and four pins to emulate SPI master mode. Can support CPHA=0 or CPHA=1, and can use DMA controller to support transfers. For CPHA=1, the selection can remain asserted for multiple transfers, and the timer status flag can be used to indicate the end of the transfer.

[0203] The transmit data must be written to the transmit buffer register before the external slave select is asserted, otherwise the shift error flag will be set.

[0204] Due to synchronization delay, the output valid time of the output data is 2.5 clock cycles. Therefore, the actual number of cycles required to complete the transmission of one bit of data is 2.5*2+1, where 1 is the time margin, that is, 6 cycles are required to complete the transmission of one bit. Therefore, the maximum baud rate supported is the clock frequency divided by 6.

[0205] 5. PWM function:

[0206] Using 1 timer and 1 pin can simulate PWM function and generate PWM signal.

[0207] In 8-bit PWM mode, the 16-bit counter is divided into two 8-bit counters. The lower 8 bits are used to configure the high period of the timer output, and the upper 8 bits are used to configure the low period of the timer output. The lower 8 bits are decremented when the output is high. When the lower 8 bits are equal to zero and decremented, the timer output is cleared and the lower 8 bits are reloaded from the compare register. When the output is low, the upper 8 bits are decremented. When the upper 8 bits are equal to zero and decremented, the timer output is set to 1 and the upper 8 bits are reloaded from the compare register. When the upper 8 bits are equal to zero and decremented, the timer compare event occurs. And the timer status flag is set to 1.

[0208] Based on the same inventive concept, the present application also provides an electronic device, such as Figure 5 As shown, the electronic device 200 includes: a processor 201 and any one of the above-mentioned configurable interface modules 100;

[0209] The processor 201 is connected to the configurable interface module 100 via a peripheral bus 202;

[0210] The processor 201 is used to configure the register module in the configurable interface module 100 to configure the signal processing function to be implemented by the configurable interface module 100 .

[0211] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0212] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium includes: a mobile storage device, ROM, a disk or an optical disk, and other media that can store program codes.

[0213] The various embodiments / implementations provided in this application can be combined with each other without causing any contradiction.

[0214] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A configurable interface module, characterized in that: include: A plurality of timers for outputting one or more clock signals; A plurality of pins for sending data or receiving data based on the clock signal; A plurality of data processing units, used for processing the data received by the pins and / or outputting the processed data through the pins; A register module is used to receive configuration information input by the peripheral bus, wherein the configuration information is at least used to configure the enabling and functions of some or all of the multiple timers, the enabling and functions of some or all of the multiple pins, and the enabling and functions of some or all of the multiple data processing units, so as to realize the function of setting the configurable interface module.

2. The configurable interface module according to claim 1, characterized in that: The configurable interface module also includes: A timer selection unit is used to enable one or more of the timers based on the configuration of the register module.

3. The configurable interface module according to claim 1, characterized in that: The plurality of pins include: one or more input pins and one or more output pins; The configurable interface module also includes: An input selection unit, configured to enable one or more of the input pins based on the configuration of the register module; An output selection unit is used to enable one or more of the output pins based on the configuration of the register module.

4. The configurable interface module according to claim 1, characterized in that: The data processing unit comprises: Shift register, used to process received data and output; The cache unit is used to cache the data to be processed and output the data to the shift register.

5. The configurable interface module according to any one of claims 1 to 4, characterized in that: The signal processing function includes at least one of the following: Universal Asynchronous Receiver / Transmitter UART transmission function and / or UART reception function; Serial peripheral interface SPI master mode function and / or SPI slave mode function; Pulse Width Modulation Waveform Generator PWM function.

6. The configurable interface module according to claim 5, characterized in that: In the case of implementing the UART sending function and the UART receiving function, the register module configures the UART sending function and the UART receiving function to use different timers, different pins and different data processing units respectively.

7. The configurable interface module according to claim 6, characterized in that: In the case of realizing the UART transmission function, A first pin among the plurality of pins is configured for UART data transmission based on the register module; A first timer among the plurality of timers is configured based on the register module to: indicate a start bit and / or a stop bit of the transmitted data through a timing signal; The first processing unit in the data processing unit is configured to process the data to be sent based on the register module and transfer the data to the first pin; and output the start bit and / or the stop bit according to the timing signal.

8. The configurable interface module according to claim 7, characterized in that: The start bit or the stop bit includes one or more bits respectively; The register module is specifically configured to insert the one or more stop bits into the data to be sent according to the configuration information.

9. The configurable interface module according to claim 7, characterized in that: A second pin among the plurality of pins is configured to receive a clear-to-send (CTS) signal based on the register module.

10. The configurable interface module according to claim 7, characterized in that: The register module is also used to configure the sending of an interrupt signal or an idle signal based on the configuration information; The first processing unit sends the corresponding first preset data before sending the interrupt signal, or sends the corresponding second preset data before sending the idle signal according to the configuration of the register module.

11. The configurable interface module according to claim 6, characterized in that: In the case of realizing the UART receiving function, A third pin among the plurality of pins is configured as UART data reception based on the register module; A second timer among the plurality of timers is configured based on the register module to: indicate a start bit and / or a stop bit of received data through a timing signal; The second processing unit in the data processing unit is configured to cache the data received by the third pin based on the register module; and verify the start bit and / or the stop bit according to the indication of the timing signal.

12. The configurable interface module according to claim 11, characterized in that: A fourth pin among the plurality of pins is configured to receive a request to send (RTS) signal based on the register module.

13. The configurable interface module according to claim 11, characterized in that: A third timer among the plurality of timers is configured based on the register module to filter glitch anomalies in the received data.

14. The configurable interface module according to claim 11, characterized in that: A fourth timer among the plurality of timers is configured based on the register module to detect whether the duration of an idle character as a preset character meets a preset length, so as to determine whether the sleep mode of the configurable interface is awakened.

15. The configurable interface module according to claim 5, characterized in that: In the case of implementing the SPI master mode function and / or the SPI slave mode function, the register module configures the SPI master mode function and the SPI slave mode function to use different timers, different pins and different data processing units respectively.

16. The configurable interface module according to claim 15, characterized in that: In the case of implementing the SPI master mode and / or the SPI slave mode functions, A fifth pin among the plurality of pins is configured as SPI data receiving based on the register module, and three sixth pins are configured as SPI data sending based on the register module; A fifth timer among the plurality of timers is configured based on the register module to: output a clock signal indicating reception of the SPI data; a sixth timer among the plurality of timers is configured based on the register module to: output a clock signal indicating transmission of the SPI data; A third processing unit among the multiple data processing units is configured based on the register module to: cache data received by the fifth pin; and a fourth processing unit among the multiple data processing units is configured based on the register module to process data to be sent and send it through the sixth pin.

17. The configurable interface module according to claim 16, characterized in that: The register module is also used to configure the assertion to be maintained during the SPI data reception process; wherein the stop counting state flag of the fifth timer is used to indicate the stop of the SPI data reception; The data processing unit is configured to set a shift error flag in the register module if the received data has not been completely cached before receiving the assertion indication signal.

18. The configurable interface module according to claim 5, characterized in that: In the case of realizing the PWM function, A seventh timer among the plurality of timers is configured to count respectively the high level and the low level of the PWM signal to be output based on the register module; The seventh pin among the plurality of pins is configured based on the register module to output the high level and the low level in sequence based on the count of the seventh timer to output the PWM signal.

19. The configurable interface module according to any one of claims 6 to 15, characterized in that: The configurable interface module also includes: a direct memory access DMA signal sending end; The DMA signal sending end is configured to send the number of data to be transmitted to an external DMA controller; wherein the DMA controller is used to start data transmission and reception between the configurable interface module and other data transceiver devices.

20. The configurable interface module according to any one of claims 6 to 15, characterized in that: The configurable interface module also includes: an interrupt signal sending end; The interrupt signal sending end is configured to send a required interrupt signal when the configurable interface module is used to implement a data transmission function.

21. An electronic device, characterized in that: include: A processor and a configurable interface module as described in any one of claims 1 to 20; The processor is connected to the configurable interface module via a peripheral bus; The processor is used to configure a register module in the configurable interface module to configure a signal processing function implemented by the configurable interface module.

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