Data processing method, electronic device, storage medium, and program product

Abstract

The present application discloses a data processing method, an electronic device, a storage medium, and a program product, which relate to the technical field of data processing. For data signals of different lengths, Fourier transform can be performed, solving the problem in the related art that different algorithms are required to process signal sequences of different lengths, resulting in low data processing efficiency, and improving the data processing efficiency.

Description

Technical Field

[0001] This application relates to the technical field of signal processing, and in particular, to a data processing method, an electronic device, a storage medium, and a program product. Background Art

[0002] In the field of signal processing, the Fourier transform, as a commonly used algorithm, can convert a time-domain signal into a frequency-domain signal and vice versa, so as to process the signal more efficiently.

[0003] In the related art, the signal to be processed can be sampled first to obtain a signal sequence. For signal sequences of different lengths, different algorithms need to be used for Fourier transform. For example, for a sequence with a length that is a power of 2, the time-domain radix-2 algorithm or the frequency-domain radix-2 algorithm can be used for Fourier transform; for a sequence with a prime number length, the Rader algorithm or the Bluestein algorithm can be used for Fourier transform; for sequences of other lengths, the Cooley-Tukey algorithm can be used for Fourier transform. In the above signal processing process, since different algorithms are required for signal sequences of different lengths, the efficiency of data processing is low. Summary of the Invention

[0004] This application provides a data processing method, an electronic device, a storage medium, and a program product to at least solve the problem of low efficiency in data processing in the related art.

[0005] This application provides a data processing method, including:

[0006] Obtain an input data signal, where the length of the input data signal is an initial length;

[0007] Determine a first data signal from a plurality of first preset signals according to the initial length, where the length of the first data signal is the initial length;

[0008] Generate a second data signal according to the input data signal and the first data signal;

[0009] Perform an expansion process on the second data signal to obtain a third data signal, where the length of the third data signal is a target length, and the target length is , where N is an integer greater than or equal to 1;

[0010] Process the third data signal to obtain an output data signal corresponding to the input data signal.

[0011] In a possible implementation manner, processing the third data signal to obtain an output data signal corresponding to the input data signal includes:

[0012] Determine a fourth data signal among multiple second preset signals according to the target length;

[0013] Perform Fourier transform processing on the third data signal to obtain a first processed signal, and perform Fourier transform processing on the fourth data signal to obtain a second processed signal;

[0014] Determine an output data signal according to the first processed signal and the second processed signal.

[0015] In a possible implementation manner, determining an output data signal according to the first processed signal and the second processed signal includes:

[0016] Perform calculation processing on the first processed signal and the second processed signal to obtain a third processed signal;

[0017] Perform Fourier transform processing on the third processed signal to obtain a fifth data signal;

[0018] Perform calculation processing on the fifth data signal and the first data signal to obtain an output data signal.

[0019] In a possible implementation manner, performing Fourier transform processing on the third data signal to obtain a first processed signal includes:

[0020] Perform preprocessing on the third data signal to obtain a first sequence;

[0021] Determine the number of butterfly calculations K according to the target length, where K is an integer greater than or equal to 1;

[0022] Perform the first butterfly calculation processing on the first sequence to obtain a first output sequence, and the length of the first output sequence is the same as the length of the first sequence;

[0023] Perform the (i + 1)-th butterfly calculation processing on the i-th output sequence to obtain the (i + 1)-th output sequence, where i successively takes 1, 2, 3,..., until when the K-th output sequence is obtained, determine the K-th output sequence as the second sequence;

[0024] Perform postprocessing on the second sequence to obtain a first processed signal.

[0025] In a possible implementation manner, performing the first butterfly calculation processing on the first sequence to obtain a first output sequence includes:

[0026] Perform grouping processing on the data in the first sequence to obtain multiple subsequences;

[0027] Determine the rotation factor corresponding to each subsequence;

[0028] For any subsequence, perform butterfly calculation on the subsequence according to the rotation factor corresponding to the subsequence to obtain the sub-calculation result corresponding to the subsequence;

[0029] Perform splicing processing on the multiple sub-calculation results corresponding to the multiple subsequences to obtain the first output sequence.

[0030] In a possible implementation manner, perform grouping processing on the data in the first sequence to obtain multiple subsequences, including:

[0031] Perform splitting processing on the first sequence to obtain x elements and the serial numbers corresponding to each element, where x is the quantity corresponding to the target length;

[0032] Perform grouping processing on the x elements to obtain multiple subsequences. The subsequence includes a first element and a second element. The serial number of the first element is less than the serial number of the second element. The serial number corresponding to the second element is the sum of the serial number corresponding to the first element and the first value, and the first value is the product of x and the preset number.

[0033] In a possible implementation manner, the subsequence includes a first element and a second element. Perform butterfly calculation on the subsequence according to the rotation factor corresponding to the subsequence to obtain the sub-calculation result corresponding to the subsequence, including:

[0034] Calculate the product of the value corresponding to the second element and the rotation factor;

[0035] Calculate the sum of the value corresponding to the first element and the product to obtain the first calculation data;

[0036] Calculate the difference between the value corresponding to the first element and the product to obtain the second calculation data;

[0037] Wherein, the sub-calculation result includes the first calculation data and the second calculation data.

[0038] In a possible implementation manner, perform preprocessing on the third data signal to obtain the first sequence, including:

[0039] Judge whether the signal type of the third data signal is a frequency domain signal type;

[0040] If so, perform splitting processing and signal conjugate processing on the third data signal to obtain the first sequence;

[0041] If not, perform splitting processing on the third data signal to obtain the first sequence.

[0042] In a possible implementation manner, perform postprocessing on the second sequence to obtain the first processing signal, including:

[0043] Judge whether the signal type of the third data signal is a frequency domain signal type;

[0044] If so, perform signal conjugate processing and splicing processing on the second sequence to obtain a first processed signal;

[0045] If not, perform splicing processing on the second sequence to obtain a first processed signal.

[0046] In a possible implementation manner, performing expansion processing on the second data signal to obtain a third data signal includes:

[0047] Determine the signal length of the second data signal;

[0048] Judge whether the signal length is , where N is any positive integer;

[0049] If so, determine the second data signal as the third data signal;

[0050] If not, obtain a first mapping relationship, and determine the third data signal according to the signal length and the first mapping relationship. The first mapping relationship includes multiple preset ranges and preset values corresponding to each preset range. The target length of the third data signal is the preset value corresponding to the target range among the multiple preset ranges.

[0051] In a possible implementation manner, after processing the third data signal to obtain an output data signal corresponding to the input data signal, the method further includes:

[0052] Obtain the signal identifier corresponding to the input data signal, where the signal identifier includes a frequency domain identifier and a time domain identifier;

[0053] If the signal identifier is a frequency domain identifier, perform sorting processing on the output data signal and output the sorted output data signal;

[0054] If the signal identifier is a time domain identifier, output the output data signal.

[0055] This application also provides a data processing device, including:

[0056] An acquisition module, configured to acquire an input data signal, and the length of the input data signal is an initial length;

[0057] A determination module, configured to determine a first data signal from multiple first preset signals according to the initial length, and the length of the first data signal is the initial length;

[0058] A generation module, configured to generate a second data signal according to the input data signal and the first data signal;

[0059] An expansion module, configured to perform expansion processing on the second data signal to obtain a third data signal, and the length of the third data signal is a target length, where the target length is , where N is an integer greater than or equal to 1;

[0060] A processing module, configured to process a third data signal to obtain an output data signal corresponding to the input data signal.

[0061] In a possible implementation, the processing module is specifically configured to:

[0062] Determine a fourth data signal from a plurality of second preset signals according to a target length;

[0063] Perform Fourier transform processing on the third data signal to obtain a first processed signal, and perform Fourier transform processing on the fourth data signal to obtain a second processed signal;

[0064] Determine the output data signal according to the first processed signal and the second processed signal.

[0065] In a possible implementation, the processing module is specifically configured to:

[0066] Perform calculation processing on the first processed signal and the second processed signal to obtain a third processed signal;

[0067] Perform Fourier transform processing on the third processed signal to obtain a fifth data signal;

[0068] Perform calculation processing on the fifth data signal and the first data signal to obtain the output data signal.

[0069] In a possible implementation, the processing module is specifically configured to:

[0070] Preprocess the third data signal to obtain a first sequence;

[0071] Determine the number of butterfly calculations K according to the target length, where K is an integer greater than or equal to 1;

[0072] Perform the first butterfly calculation processing on the first sequence to obtain a first output sequence, and the length of the first output sequence is the same as that of the first sequence;

[0073] Perform the (i + 1)-th butterfly calculation processing on the i-th output sequence to obtain the (i + 1)-th output sequence, where i sequentially takes 1, 2, 3,..., until when the K-th output sequence is obtained, the K-th output sequence is determined as the second sequence;

[0074] Post-process the second sequence to obtain the first processed signal.

[0075] In a possible implementation, the processing module is specifically configured to:

[0076] Group the data in the first sequence to obtain a plurality of subsequences;

[0077] Determine the rotation factor corresponding to each subsequence;

[0078] For any one subsequence, perform butterfly calculation on the subsequence according to the rotation factor corresponding to the subsequence to obtain the sub-calculation result corresponding to the subsequence;

[0079] Perform splicing processing on the multiple sub-calculation results corresponding to the multiple subsequences to obtain the first output sequence.

[0080] In a possible implementation manner, the processing module is specifically configured to:

[0081] Perform splitting processing on the first sequence to obtain x elements and the serial numbers corresponding to each element, where x is the quantity corresponding to the target length;

[0082] Perform grouping processing on the x elements to obtain multiple subsequences. The subsequence includes a first element and a second element. The serial number of the first element is less than the serial number of the second element, and the serial number corresponding to the second element is the sum of the serial number corresponding to the first element and a first numerical value. The first numerical value is the product of x and a preset number.

[0083] In a possible implementation manner, the subsequence includes a first element and a second element. The processing module is specifically configured to:

[0084] Calculate the product of the value corresponding to the second element and the rotation factor;

[0085] Calculate the sum of the value corresponding to the first element and the product to obtain the first calculation data;

[0086] Calculate the difference between the value corresponding to the first element and the product to obtain the second calculation data;

[0087] Wherein, the sub-calculation result includes the first calculation data and the second calculation data.

[0088] In a possible implementation manner, the processing module is specifically configured to:

[0089] Judge whether the signal type of the third data signal is a frequency domain signal type;

[0090] If so, perform splitting processing and signal conjugate processing on the third data signal to obtain the first sequence;

[0091] If not, perform splitting processing on the third data signal to obtain the first sequence.

[0092] In a possible implementation manner, the processing module is specifically configured to:

[0093] Judge whether the signal type of the third data signal is a frequency domain signal type;

[0094] If so, perform signal conjugate processing and splicing processing on the second sequence to obtain a first processed signal;

[0095] If not, perform splicing processing on the second sequence to obtain a first processed signal.

[0096] In a possible implementation manner, the expansion module is specifically configured to:

[0097] Determine the signal length of the second data signal;

[0098] Judge whether the signal length is , where N is any positive integer;

[0099] If so, determine the second data signal as the third data signal;

[0100] If not, obtain a first mapping relationship, and determine the third data signal according to the signal length and the first mapping relationship. The first mapping relationship includes multiple preset ranges and preset values corresponding to each preset range. The target length of the third data signal is the preset value corresponding to the target range among the multiple preset ranges.

[0101] In a possible implementation manner, the processing module is further configured to:

[0102] Obtain the signal identifier corresponding to the input data signal. The signal identifier includes a frequency domain identifier and a time domain identifier;

[0103] If the signal identifier is a frequency domain identifier, perform sorting processing on the output data signal and output the sorted output data signal;

[0104] If the signal identifier is a time domain identifier, output the output data signal.

[0105] This application also provides a data processor, including: an input port, a first preset memory, a complex multiplier, a Fourier transform calculator, a framing unit, and an output port;

[0106] Among them, the input port is connected to the complex multiplier, the first preset memory is connected to the complex multiplier, the complex multiplier is connected to the framing unit, the framing unit is connected to the Fourier transform calculator, and the complex multiplier is also connected to the output port;

[0107] The input port is used to obtain an input data signal, and the length of the input data signal is the initial length;

[0108] The first preset memory is used to determine a first data signal from multiple first preset signals according to the initial length, and the length of the first data signal is the initial length;

[0109] The complex multiplier is used to generate a second data signal according to the input data signal and the first data signal;

[0110] The framing unit is used to perform an expansion process on the second data signal to obtain a third data signal, and the length of the third data signal is the target length, where the target length is , and N is an integer greater than or equal to 1;

[0111] The Fourier transform calculator and the complex multiplier are used to process the third data signal to obtain the output data signal corresponding to the input data signal;

[0112] The output port is used to output the output data signal.

[0113] In a possible implementation, the data processor includes a second preset memory, and the second preset memory is connected to the Fourier transform calculator.

[0114] The second preset memory is used to determine a fourth data signal from multiple second preset signals according to the target length;

[0115] The Fourier transform calculator is specifically used to perform a Fourier transform process on the third data signal to obtain a first processed signal, and perform a Fourier transform process on the fourth data signal to obtain a second processed signal;

[0116] The complex multiplier and the Fourier transform calculator are specifically used to determine the output data signal according to the first processed signal and the second processed signal.

[0117] In a possible implementation, the complex multiplier is specifically used to perform a calculation process on the first processed signal and the second processed signal to obtain a third processed signal;

[0118] The Fourier transform calculator is further used to perform a Fourier transform process on the third processed signal to obtain a fifth data signal;

[0119] The complex multiplier is further used to perform a calculation process on the fifth data signal and the first data signal to obtain the output data signal.

[0120] In a possible implementation, the Fourier transform calculator is specifically used for:

[0121] Perform preprocessing on the third data signal to obtain a first sequence;

[0122] Determine the number of butterfly calculations K according to the target length, where K is an integer greater than or equal to 1;

[0123] Store the first sequence in the first memory, and perform a first butterfly calculation process on the first sequence in the first memory to obtain a first output sequence, and the length of the first output sequence is the same as the length of the first sequence;

[0124] Store the i-th output sequence in the M-th memory, perform the (i + 1)-th butterfly calculation process on the i-th output sequence in the M-th memory to obtain the (i + 1)-th output sequence, where i successively takes 1, 2, 3, ……, until when the K-th output sequence is obtained, determine the K-th output sequence as the second sequence, where when i is odd, M is 2, and when i is even, M is 1;

[0125] Perform post-processing on the second sequence to obtain a first processed signal.

[0126] In a possible implementation manner, the first memory includes a first real part sub-memory and a first imaginary part sub-memory, the second memory includes a second real part sub-memory and a second imaginary part sub-memory, the first sequence includes a first real part sequence and a first imaginary part sequence, the first real part sequence is stored in the first real part sub-memory, the first imaginary part sequence is stored in the first imaginary part sub-memory, the i-th output sequence includes an i-th output real part sequence and an i-th output imaginary part sequence, the i-th output real part sequence is stored in the M-th real part sub-memory of the M-th memory, and the i-th output imaginary part sequence is stored in the M-th imaginary part sub-memory of the M-th memory.

[0127] In a possible implementation manner, the framing unit is further connected to an output port;

[0128] The framing unit is further configured to obtain a signal identifier corresponding to the input data signal, where the signal identifier includes a frequency domain identifier and a time domain identifier; if the signal identifier is a frequency domain identifier, perform sorting processing on the output data signal to obtain a sorted output data signal.

[0129] This application further provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any one of the above data processing methods when executing the computer program.

[0130] This application further provides a computer-readable storage medium, in which a computer program is stored, where the computer program implements the steps of any one of the above data processing methods when executed by a processor.

[0131] This application further provides a computer program product, including a computer program, where the computer program implements the steps of any one of the above data processing methods when executed by a processor.

[0132] Through this application, for data signals of different lengths, the Fourier transform can be performed through this method. Therefore, it is possible to solve the problem in the related art that due to different algorithms being required for processing signal sequences of different lengths, the data processing efficiency is low, and the data processing efficiency is improved. Description of the Drawings

[0133] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0134] Figure 1 Schematic diagram of a data processing system provided by an embodiment of the present application;

[0135] Figure 2 Flow chart of a data processing method provided by an embodiment of the present application;

[0136] Figure 3 Flow chart of another data processing method provided by an embodiment of the present application;

[0137] Figure 4 Flow chart of yet another data processing method provided by an embodiment of the present application;

[0138] Figure 5 Schematic diagram of the structure of a data processor provided by an embodiment of the present application;

[0139] Figure 6 Schematic diagram of the structure of a Fourier transform calculator provided by an embodiment of the present application;

[0140] Figure 7 Schematic diagram of the structure of a butterfly calculation unit provided by an embodiment of the present application;

[0141] Figure 8 Schematic diagram of the structure of a data processing device provided by an embodiment of the present application;

[0142] Figure 9 Schematic diagram of the structure of an electronic device provided by the present application. Detailed implementation manners

[0143] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0144] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0145] In the field of signal processing, the Fourier transform, as a commonly used algorithm, can convert a time-domain signal to a frequency-domain signal and vice versa, so as to process the signal more efficiently.

[0146] In the related art, the signal to be processed can be sampled first to obtain a signal sequence. For signal sequences of different lengths, different algorithms are required for Fourier transform. For example, for a sequence of length that is a power of 2, the time-domain radix-2 algorithm or the frequency-domain radix-2 algorithm can be used for Fourier transform; for a sequence of prime length, the Rader algorithm or the Bluestein algorithm can be used for Fourier transform; for sequences of other lengths, the Cooley-Tukey algorithm can be used for Fourier transform. In the above signal processing process, since different algorithms are required for signal sequences of different lengths, the efficiency of data processing is low.

[0147] To solve the above technical problems, the embodiments of the present application provide a data processing method. By obtaining an input data signal, performing data processing and extension processing on the input data signal, a data signal with a target length of is obtained, where N is an integer greater than or equal to 1. Processing the data signal with a target length of yields an output data signal corresponding to the input data signal. In this way, for data signals of different lengths, Fourier transform can be performed through this method, improving the efficiency of data processing.

[0148] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0149] Next, in combination with Figure 1 , a data processing system corresponding to the data processing method will be illustrated by way of example.

[0150] Please refer to Figure 1 , Figure 1 which is a schematic diagram of a data processing system provided by an embodiment of the present application. Figure 1It may include a data processing system, which can be applied to a programmable logic chip. The data processing system may include multiple cross switches, multiple frame disassembling units, complex multipliers, multiple framing units, Fourier transform calculators, a first preset memory, a second preset memory, an address control unit, a sequence memory, an input port, and an output port.

[0151] Among them, the input port can be connected to the cross switch, the cross switch can be connected to the frame disassembling unit, the frame disassembling unit can be connected to the complex multiplier, the complex multiplier can be connected to the framing unit, the framing unit can be connected to the Fourier transform calculator, the Fourier transform calculator can be connected to the cross switch, the complex multiplier can also be connected to the sequence memory, the address control unit can be respectively connected to the first preset memory, the second preset memory, and the sequence memory, the first preset memory can be connected to the cross switch, the cross switch can be connected to the complex multiplier, the second preset memory can be connected to the framing unit, the framing unit can be connected to the Fourier transform calculator, the Fourier transform calculator can be connected to the frame disassembling unit, the frame disassembling unit can be connected to the cross switch, the sequence memory can be connected to the framing unit, and the framing unit can be connected to the output port.

[0152] The cross switch can be used for dynamic switching of different signals between different logic units to meet various design requirements. For example, the cross switch can allow the signal in the input port to be transmitted to the frame disassembling unit, or allow the signal in the Fourier transform calculator to be transmitted to the frame disassembling unit.

[0153] The frame disassembling unit can be used to split the data signal to obtain sequence data. The sequence data can be a set of discrete sequences in the time domain or a set of discrete sequences in the frequency domain.

[0154] The complex multiplier can be used to perform complex multiplication processing on the input data.

[0155] The framing unit can be used to combine the discrete data processed by the previous logic unit in a specific format and order to form a data signal.

[0156] The Fourier transform calculator can be used to perform Fourier transform processing on the signal. The Fourier transform processing can include the forward Fourier transform and the inverse Fourier transform. The forward Fourier transform can convert the time-domain signal into a frequency-domain signal to achieve the transformation of the signal from the time domain to the frequency domain. The inverse Fourier transform can convert the frequency-domain signal into a time-domain signal to achieve the transformation of the signal from the frequency domain to the time domain.

[0157] The first preset memory can be a read-only memory, and the first preset memory can store the first rotation factor. The first preset memory may include an output port ( Figure 1("Output" as shown in []) and an address. The first rotation factor can be used for complex multiplication with the input signal to achieve an efficient frequency-domain transformation. The first rotation factor can include multiple preset signals. The first preset memory can ensure that the first rotation factor is not rewritten during the operation of the system, guaranteeing the stability and consistency of the data and enabling continuous provision of accurate rotation factor data to the complex multiplier.

[0158] For example, the first rotation factor is , where N is the length corresponding to the input signal and W is the preset rotation factor, .

[0159] The second preset memory can be a read-only memory and can store the second rotation factor. The second preset memory can include an output port ( Figure 1 "Output" as shown in [] and an address. The second rotation factor can be used for complex multiplication with the input signal to achieve an efficient frequency-domain transformation. The second rotation factor can include multiple preset signals. The second preset memory can ensure that the second rotation factor is not rewritten during the operation of the system, guaranteeing the stability and consistency of the data and enabling continuous provision of accurate rotation factor data to the complex multiplier.

[0160] The address control unit can be used to provide address signals to the first preset memory, the second preset memory, and the sequence memory. When performing a data read operation on the memory, the address control unit can accurately generate the address corresponding to each storage unit according to the system requirements and the data processing flow, ensuring that the data can be correctly accessed.

[0161] The sequence memory can include an A-end input, a B-end output, and an A-end address corresponding to the A-end input and a B-end address corresponding to the B-end output. The A-end input can be used to input the processed signal sequence. The sequence memory can cache the processed signal sequence, and the B-end output can be used to output the processed signal sequence.

[0162] The input port can be used to input the data signal to be processed. The input port can include a high-performance scalable streaming interface. The input port can also input a ready signal, a valid signal, an end signal, etc., which are not limited here.

[0163] The output port can be used to output the processed data signal. The output port can include a high-performance scalable streaming interface.

[0164] Figure 2 FIG. [] is a schematic flow chart of a data processing method provided by an embodiment of the present application. The execution subject of the embodiment of the present application can be a processor. As Figure 2 shown, the method is as follows:

[0165] S201: Obtain the input data signal.

[0166] The length of the input data signal is the initial length.

[0167] The input data signal can be a data signal that needs to be Fourier-transformed.

[0168] The input data signal can be a data sequence, and each element in the data sequence can be a complex number composed of a real part and an imaginary part.

[0169] The bit width of the input data signal can be 64 bits, where the lower 32 bits represent the real part of the complex number and the upper 32 bits represent the imaginary part of the complex number.

[0170] The data format of the input data signal can be a 32-bit fixed-point number or a 32-bit floating-point number.

[0171] The input data signal can be a time-domain signal or a frequency-domain signal.

[0172] The input data signal can be obtained through the input port.

[0173] S202: Determine the first data signal among multiple first preset signals according to the initial length.

[0174] The length of the first data signal is the initial length.

[0175] The multiple first preset signals can be the multiple preset signals corresponding to the first rotation factor.

[0176] The first preset signal can be a parameter for performing complex multiplication operations.

[0177] The first data signal with the same length as the initial length can be determined among the multiple first preset signals in the memory.

[0178] S203: Generate a second data signal according to the input data signal and the first data signal.

[0179] The input data signal and the first data signal can be processed to obtain the second data signal.

[0180] Among them, the processing method can include complex multiplication processing, dot product processing, etc., which are not limited here.

[0181] S204: Perform expansion processing on the second data signal to obtain a third data signal.

[0182] The length of the third data signal is the target length, and the target length is , where N is an integer greater than or equal to 1.

[0183] Optionally, the second data signal can be processed in the following manner to obtain a third data signal: According to the signal length of the second data signal, determine, among a plurality of preset lengths, a target length that is adjacent to the signal length of the second data signal and greater than the signal length of the second data signal, and determine the third data signal according to the target length.

[0184] Optionally, the second data signal can be processed in the following manner to obtain a third data signal: Determine the signal length of the second data signal; determine whether the signal length is ; if so, determine the second data signal as the third data signal; if not, obtain a first mapping relationship, and determine the third data signal according to the signal length and the first mapping relationship.

[0185] where N is any positive integer, the first mapping relationship includes a plurality of preset ranges and preset values corresponding to each preset range, and the target length of the third data signal is the preset value corresponding to the target range among the plurality of preset ranges.

[0186] The target range can be determined among a plurality of preset ranges according to the signal length, the preset value corresponding to the target range can be determined, and the third data signal can be determined according to the preset value corresponding to the target range.

[0187] Among them, the third data signal can be determined in the following manner: At least one preset element can be added to the sequence corresponding to the second data signal so that the length of the corresponding sequence is the length corresponding to the preset value.

[0188] It should be noted that the third data signal can be determined according to any feasible implementation manner, and the embodiments of the present application do not limit this.

[0189] S205: Process the third data signal to obtain an output data signal corresponding to the input data signal.

[0190] Optionally, the fourth data signal can be determined among a plurality of second preset signals according to the target length; perform Fourier transform processing on the third data signal to obtain a first processed signal, perform Fourier transform processing on the fourth data signal to obtain a second processed signal; determine the output data signal according to the first processed signal and the second processed signal.

[0191] Optionally, perform Fourier transform processing on the third data signal to obtain a first processed signal, obtain a second processed signal from a second memory according to the target length, and determine the output data signal according to the first processed signal and the second processed signal.

[0192] Among them, the second memory can store the second processed signal, the second processed signal can be a signal after Fourier transform processing, and the second processed signal can be determined according to the target length.

[0193] It should be noted that the output data signal can be determined according to any feasible implementation manner, and the embodiments of the present application do not limit this.

[0194] Optionally, after processing the third data signal to obtain the output data signal corresponding to the input data signal, the method further includes: obtaining a signal identifier corresponding to the input data signal; if the signal identifier is a frequency domain identifier, performing a sorting process on the output data signal and outputting the sorted output data signal; if the signal identifier is a time domain identifier, outputting the output data signal.

[0195] Wherein, the signal identifier includes a frequency domain identifier and a time domain identifier.

[0196] The frequency domain identifier can indicate that the input data signal is a frequency domain signal for performing Fourier transform processing from the frequency domain to the time domain.

[0197] The time domain identifier can indicate that the input data signal is a time domain signal for performing Fourier transform processing from the time domain to the frequency domain.

[0198] Optionally, the output data signal can be sorted and the sorted output data signal can be output in the following manner: dividing each element in the output data signal by the value corresponding to the target length to obtain an intermediate data signal, sorting the intermediate data signal according to the following formula to obtain the sorted output data signal, and outputting the sorted output data signal:

[0199]

[0200] Wherein, and can represent the element corresponding to the sorted output data signal, and can represent the element corresponding to the output data signal, n represents the serial number of the element, and N represents the target length.

[0201] In the data processing method provided in this embodiment, by obtaining an input data signal, the length of the input data signal is the initial length; according to the initial length, a first data signal is determined among multiple first preset signals, and the length of the first data signal is the initial length; according to the input data signal and the first data signal, a second data signal is generated; the second data signal is subjected to an expansion process to obtain a third data signal, and the length of the third data signal is the target length, and the target length is , where N is an integer greater than or equal to 1; the third data signal is processed to obtain the output data signal corresponding to the input data signal. In this way, for data signals of different lengths, Fourier transform can be performed through this method, improving the efficiency of data processing.

[0202] Next, in conjunction with Figure 3 , the process of processing the third data signal to obtain the output data signal corresponding to the input data signal (S205) will be explained.

[0203] Figure 3 This is a schematic flowchart of another data processing method provided by an embodiment of the present application. Based on the above embodiment, reference can be made to Figure 3 for a detailed description of this method. The method includes:

[0204] S301: Determine a fourth data signal from multiple second preset signals according to the target length.

[0205] The length of the fourth data signal is the target length.

[0206] The multiple second preset signals may be multiple preset signals corresponding to a second rotation factor.

[0207] The second rotation factor may be stored in a second preset memory.

[0208] It is possible to determine a fourth data signal with the same target length from the multiple second preset signals in the memory.

[0209] S302: Perform Fourier transform processing on the third data signal to obtain a first processed signal, and perform Fourier transform processing on the fourth data signal to obtain a second processed signal.

[0210] It is possible to perform a forward Fourier transform process on the third data signal through a Fourier transform calculator to obtain a first processed signal, and perform a forward Fourier transform process on the fourth data signal through a Fourier transform calculator to obtain a second processed signal.

[0211] S303: Perform calculation processing on the first processed signal and the second processed signal to obtain a third processed signal.

[0212] It is possible to perform complex multiplication processing on the first processed signal and the second processed signal to obtain a third processed signal.

[0213] S304: Perform Fourier transform processing on the third processed signal to obtain a fifth data signal.

[0214] It is possible to perform an inverse Fourier transform process on the third processed signal through a Fourier transform calculator to obtain a fifth data signal.

[0215] S305: Perform calculation processing on the fifth data signal and the first data signal to obtain an output data signal.

[0216] It is possible to perform complex multiplication processing on the fifth data signal and the first data signal to obtain an output data signal.

[0217] The data processing method provided in this embodiment determines a fourth data signal among multiple second preset signals according to the target length, performs Fourier transform processing on the third data signal to obtain a first processed signal, performs Fourier transform processing on the fourth data signal to obtain a second processed signal, performs calculation processing on the first processed signal and the second processed signal to obtain a third processed signal, performs Fourier transform processing on the third processed signal to obtain a fifth data signal, and performs calculation processing on the fifth data signal and the first data signal to obtain an output data signal. In this way, for data signals of different lengths, Fourier transform can be performed through this method, improving the efficiency of data processing.

[0218] Next, in combination with Figure 4 , the process of performing Fourier transform processing on the third data signal to obtain the first processed signal (S302) will be explained.

[0219] Figure 4 FIG. is a schematic flowchart of another data processing method provided in an embodiment of the present application. On the basis of the above embodiment, reference can be made to Figure 4 for a detailed description of this method. This method is applied to a Fourier transform calculator, and this method includes:

[0220] S401: Preprocess the third data signal to obtain a first sequence.

[0221] The preprocessing may include splitting processing and signal conjugate processing.

[0222] The first sequence may include multiple elements.

[0223] The signal type of the third data signal can be obtained, and according to the signal type, the third data signal is preprocessed to obtain a first sequence.

[0224] Optionally, the third data signal can be preprocessed to obtain a first sequence in the following manner: Determine whether the signal type of the third data signal is a frequency domain signal type; if so, perform splitting processing and signal conjugate processing on the third data signal to obtain a first sequence; if not, perform splitting processing on the third data signal to obtain a first sequence.

[0225] The signal type may include a frequency domain signal type and a time domain signal type.

[0226] S402: Determine the number of butterfly calculations K according to the target length.

[0227] K is an integer greater than or equal to 1.

[0228] The logarithm value can be determined according to the target length, and this logarithm value is determined as the number of butterfly calculations K.

[0229] S403: Perform the first butterfly calculation process on the first sequence to obtain a first output sequence.

[0230] The length of the first output sequence is the same as that of the first sequence.

[0231] Optionally, a rotation factor can be obtained, and through the butterfly calculation unit, the first sequence in the first memory is subjected to the first butterfly calculation process according to the rotation factor to obtain a first output sequence.

[0232] Optionally, the data in the first sequence can be grouped to obtain multiple subsequences; determine the rotation factor corresponding to each subsequence; for any one subsequence, perform butterfly calculation on the subsequence according to the rotation factor corresponding to the subsequence to obtain a sub-calculation result corresponding to the subsequence; splice the multiple sub-calculation results corresponding to the multiple subsequences to obtain a first output sequence.

[0233] Among them, the grouping process can be to group the elements in the first sequence to obtain multiple subsequences, and each subsequence includes a first element and a second element to perform butterfly calculation on each subsequence.

[0234] Optionally, the data in the first sequence can be grouped to obtain multiple subsequences in the following manner: perform a splitting process on the first sequence to obtain x elements and the serial numbers corresponding to each element, where x is the quantity corresponding to the target length; group the x elements to obtain multiple subsequences, and the subsequence includes a first element and a second element, the serial number of the first element is less than the serial number of the second element, and the serial number corresponding to the second element is the sum of the serial number corresponding to the first element and a first value, and the first value is the product of x and a preset number.

[0235] For example, assume that the x elements are 8 elements, which are {x(0), x(1), x(2), x(3), x(4), x(5), x(6), x(7)}, where (0), (1), ……, (7) can represent the serial numbers corresponding to each element.

[0236] It can be divided into 4 subsequences, which are respectively:

[0237] Subsequence 1: {x(0), x(4)}

[0238] Subsequence 2: {x(1), x(5)}

[0239] Subsequence 3: {x(2), x(6)}

[0240] Subsequence 4: {x(3), x(7)}

[0241] Among them, the serial number of the first element is less than that of the second element, and the serial number corresponding to the second element is the sum of the serial number corresponding to the first element and the first value. The first value is the product of x and the preset number, and the preset number is one-half.

[0242] Optionally, the sub-sequence can be subjected to a butterfly calculation according to the rotation factor corresponding to the sub-sequence in the following manner to obtain a sub-calculation result corresponding to the sub-sequence: calculate the product of the value corresponding to the second element and the rotation factor; calculate the sum of the value corresponding to the first element and the product to obtain a first calculation data; calculate the difference between the value corresponding to the first element and the product to obtain a second calculation data; wherein, the sub-calculation result includes the first calculation data and the second calculation data.

[0243] Optionally, the splicing process can splice multiple sub-calculation results corresponding to multiple sub-sequences according to the serial numbers corresponding to each sub-sequence.

[0244] S404: Perform the (i + 1)-th butterfly calculation process on the i-th output sequence to obtain the (i + 1)-th output sequence.

[0245] Among them, i takes 1, 2, 3,... in sequence. When the K-th output sequence is obtained, the K-th output sequence is determined as the second sequence.

[0246] Optionally, the (i + 1)-th butterfly calculation process can be performed on the i-th output sequence in the following manner to obtain the (i + 1)-th output sequence: group the data in the i-th output sequence to obtain multiple sub-sequences; determine the rotation factor corresponding to each sub-sequence; for any one sub-sequence, perform the (i + 1)-th butterfly calculation on the sub-sequence according to the rotation factor corresponding to the sub-sequence to obtain a sub-calculation result corresponding to the sub-sequence; splice the multiple sub-calculation results corresponding to the multiple sub-sequences to obtain the (i + 1)-th output sequence.

[0247] Optionally, the data in the i-th output sequence can be grouped in the following manner to obtain multiple sub-sequences: perform a splitting process on the i-th output sequence to obtain x elements and the serial numbers corresponding to each element, where x is the quantity corresponding to the target length; group the x elements to obtain multiple sub-sequences. The sub-sequence includes a first element and a second element. The serial number of the first element is less than that of the second element, and the serial number corresponding to the second element is the sum of the serial number corresponding to the first element and the first value. The first value is the product of x and the preset number.

[0248] Among them, the preset number can be .

[0249] For example, when i is 1, the preset number is one-fourth for performing the 2nd butterfly calculation.

[0250] When i is 2, the preset number is one-eighth for the third butterfly calculation.

[0251] Among them, the process of performing the (i + 1)-th butterfly calculation on the i-th output sequence to obtain the (i + 1)-th output sequence is similar to the process of "performing the first butterfly calculation on the first sequence to obtain the first output sequence", which will not be elaborated here.

[0252] S405: Perform post-processing on the second sequence to obtain the first processed signal.

[0253] The post-processing may include splicing processing and signal conjugate processing.

[0254] Optionally, the signal type of the third data signal can be determined, and according to the signal type, post-processing is performed on the second sequence to obtain the first processed signal.

[0255] Optionally, it can be determined whether the signal type of the third data signal is a frequency-domain signal type; if so, signal conjugate processing and splicing processing are performed on the second sequence to obtain the first processed signal; if not, splicing processing is performed on the second sequence to obtain the first processed signal.

[0256] The data processing method provided in this embodiment preprocesses the third data signal to obtain the first sequence; determines the number of butterfly calculations K according to the target length, where K is an integer greater than or equal to 1; performs the first butterfly calculation on the first sequence to obtain the first output sequence, and the length of the first output sequence is the same as that of the first sequence; performs the (i + 1)-th butterfly calculation on the i-th output sequence to obtain the (i + 1)-th output sequence, where i takes 1, 2, 3,... in sequence until the K-th output sequence is obtained, and the K-th output sequence is determined as the second sequence; performs post-processing on the second sequence to obtain the first processed signal. In this way, for data signals of different lengths, Fourier transform can be performed through this method, improving the efficiency of data processing.

[0257] Among them, the Fourier transform processing in the embodiments of the present application can refer to the process of performing Fourier transform on the third data signal as described above, which will not be elaborated here.

[0258] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0259] Figure 5 It is a schematic structural diagram of a data processor provided in an embodiment of the present application. Please refer to Figure 5 , Figure 5Comprising a data processor, the data processor at least includes an input port, a first preset memory, a complex multiplier, a Fourier transform calculator, a framing unit, and an output port;

[0260] Wherein, the input port is connected to the complex multiplier, the first preset memory is connected to the complex multiplier, the complex multiplier is connected to the framing unit, the framing unit is connected to the Fourier transform calculator, and the complex multiplier is also connected to the output port;

[0261] The input port is used to obtain an input data signal, and the length of the input data signal is the initial length;

[0262] The first preset memory is used to determine a first data signal among a plurality of first preset signals according to the initial length, and the length of the first data signal is the initial length;

[0263] The complex multiplier is used to generate a second data signal according to the input data signal and the first data signal;

[0264] The framing unit is used to perform expansion processing on the second data signal to obtain a third data signal, and the length of the third data signal is the target length, and the target length is , where N is an integer greater than or equal to 1;

[0265] The Fourier transform calculator and the complex multiplier are used to process the third data signal to obtain an output data signal corresponding to the input data signal;

[0266] The output port is used to output the output data signal.

[0267] In a possible implementation manner, the data processor includes a second preset memory, and the second preset memory is connected to the Fourier transform calculator,

[0268] The second preset memory is used to determine a fourth data signal among a plurality of second preset signals according to the target length;

[0269] The Fourier transform calculator is specifically used to perform Fourier transform processing on the third data signal to obtain a first processed signal, and perform Fourier transform processing on the fourth data signal to obtain a second processed signal;

[0270] The complex multiplier and the Fourier transform calculator are specifically used to determine the output data signal according to the first processed signal and the second processed signal.

[0271] In a possible implementation manner, the complex multiplier is specifically used to perform calculation processing on the first processed signal and the second processed signal to obtain a third processed signal;

[0272] The Fourier transform calculator is further used to perform Fourier transform processing on the third processed signal to obtain a fifth data signal;

[0273] The complex multiplier is also used to perform computational processing on the fifth data signal and the first data signal to obtain an output data signal.

[0274] In a possible implementation, the framing unit is also connected to an output port;

[0275] The framing unit is also used to obtain a signal identifier corresponding to the input data signal. The signal identifier includes a frequency domain identifier and a time domain identifier; if the signal identifier is a frequency domain identifier, perform sorting processing on the output data signal to obtain a sorted output data signal.

[0276] In a possible implementation, the Fourier transform calculator is specifically used for:

[0277] Preprocess the third data signal to obtain a first sequence;

[0278] Determine the number of butterfly computations K according to the target length, where K is an integer greater than or equal to 1;

[0279] Store the first sequence in the first memory, and perform the first butterfly computation processing on the first sequence in the first memory to obtain a first output sequence, where the length of the first output sequence is the same as the length of the first sequence;

[0280] Store the i-th output sequence in the M-th memory, and perform the (i + 1)-th butterfly computation processing on the i-th output sequence in the M-th memory to obtain the (i + 1)-th output sequence, where i sequentially takes 1, 2, 3,... until the K-th output sequence is obtained, and determine the K-th output sequence as the second sequence. Among them, when i is odd, M is 2, and when i is even, M is 1;

[0281] Perform post-processing on the second sequence to obtain a first processed signal.

[0282] Among them, the first memory includes a first real part sub-memory and a first imaginary part sub-memory, the second memory includes a second real part sub-memory and a second imaginary part sub-memory, the first sequence includes a first real part sequence and a first imaginary part sequence, the first real part sequence is stored in the first real part sub-memory, the first imaginary part sequence is stored in the first imaginary part sub-memory, the i-th output sequence includes an i-th output real part sequence and an i-th output imaginary part sequence, the i-th output real part sequence is stored in the M-th real part sub-memory of the M-th memory, and the i-th output imaginary part sequence is stored in the M-th imaginary part sub-memory of the M-th memory. Among them, when i is odd, M is 2, and when i is even, M is 1.

[0283] A ping-pong storage structure is formed between the first memory and the second memory, that is, the first output sequence is stored in the second memory, the first output sequence in the second memory is subjected to the second butterfly calculation process to obtain the second output sequence, and the second output sequence is stored in the first memory, and so on, until the K-th output sequence is obtained, and the K-th output sequence is determined as the second sequence.

[0284] Among them, the process of subjecting the i-th output sequence in the M-th memory to the (i + 1)-th butterfly calculation process to obtain the (i + 1)-th output sequence is similar to the process of "subjecting the first sequence to the first butterfly calculation process to obtain the first output sequence".

[0285] Next, in combination with Figure 6 , the structure of the Fourier transform calculator will be explained.

[0286] Figure 6 This is a schematic structural diagram of a Fourier transform calculator provided by an embodiment of the present application. Please refer to Figure 6 , Figure 6 It includes a Fourier transform calculator, and the Fourier transform calculator at least includes a preprocessing module, a postprocessing module, a butterfly calculation unit, a plurality of cross switches, a first memory, a second memory, a rotation factor memory, and an address control unit. The first memory includes a first real part sub-memory and a first imaginary part sub-memory, the second memory includes a second real part sub-memory and a second imaginary part sub-memory, and the imaginary part sub-memory is used to store an imaginary part sequence, and the real part sub-memory is used to store a real part sequence.

[0287] Each sub-memory includes an A-end input, an A-end output, a B-end input, a B-end output, and storage addresses corresponding to a plurality of inputs and a plurality of outputs respectively.

[0288] The i-th output real part sequence is stored in the M-th real part sub-memory of the M-th memory, and the i-th output imaginary part sequence is stored in the M-th imaginary part sub-memory of the M-th memory, where when i is odd, M is 2, and when i is even, M is 1.

[0289] The rotation factor memory may include a rotation factor real part memory and a rotation factor imaginary part memory, and storage addresses corresponding to the rotation factor real part memory and the rotation factor imaginary part memory respectively.

[0290] Among them, a third data signal is input, and the third data signal is preprocessed by a preprocessing module to obtain a first sequence. The first sequence is stored in a first memory. A first butterfly calculation process is performed on the first sequence in the first memory to obtain a first output sequence. The first output sequence is stored in a second memory. A second butterfly calculation process is performed on the first output sequence in the second memory to obtain a second output sequence. The second output sequence is stored in the first memory. And so on, until a Kth output sequence is obtained, the Kth output sequence is determined as a second sequence. The second sequence is post-processed by a post-processing module to obtain a first processed signal, and the first processed signal is output.

[0291] The butterfly calculation unit may include a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a rotation factor input terminal. The first input terminal may include a real part of the first input terminal and an imaginary part of the first input terminal. The second input terminal may include a real part of the second input terminal and an imaginary part of the second input terminal. The first output terminal may include a real part of the first output terminal and an imaginary part of the first output terminal. The second output terminal may include a real part of the second output terminal and an imaginary part of the second output terminal. The rotation factor input terminal may include a real part of the rotation factor input terminal and an imaginary part of the rotation factor input terminal. The real part of the rotation factor in the real part memory of the rotation factor may be transmitted to the butterfly calculation unit through the real part of the rotation factor input terminal. The imaginary part of the rotation factor in the imaginary part memory of the rotation factor may be transmitted to the butterfly calculation unit through the imaginary part of the rotation factor input terminal.

[0292] Next, in combination with Figure 7 , the butterfly calculation process will be explained.

[0293] Figure 7 FIG. is a schematic structural diagram of a butterfly calculation unit provided by an embodiment of the present application. Please refer to Figure 7 , Figure 7 including a butterfly calculation unit. The butterfly calculation unit includes a first input terminal, a second input terminal, a rotation factor input terminal, a complex adder, a complex multiplier, a complex subtractor, a first output terminal, and a second output terminal.

[0294] The value corresponding to the second element can be input to the complex multiplier through the second input terminal, the rotation factor can be input to the complex multiplier through the rotation factor input terminal, the product between the value corresponding to the second element and the rotation factor is calculated by the complex multiplier, and the product is sent to the complex adder and the complex subtractor. The first element is input to the complex adder and the complex subtractor through the first input terminal. Through the complex adder, the sum of the value corresponding to the first element and the product is calculated to obtain a first calculation data; through the complex subtractor, the difference between the value corresponding to the first element and the product is calculated to obtain a second calculation data.

[0295] The implementation details of each step in the embodiments of the present application can be referred to the descriptions of the corresponding steps or operations in the above method embodiments, and the repeated content will not be elaborated.

[0296] Figure 8 It is a schematic structural diagram of a data processing device provided by an embodiment of the present application. Please refer to Figure 8 , the data processing device 800 includes an acquisition module 801, a determination module 802, a generation module 803, an expansion module 804, and a processing module 805, where

[0297] The acquisition module 801 is configured to acquire an input data signal, and the length of the input data signal is an initial length;

[0298] The determination module 802 is configured to determine a first data signal from a plurality of first preset signals according to the initial length, and the length of the first data signal is the initial length;

[0299] The generation module 803 is configured to generate a second data signal according to the input data signal and the first data signal;

[0300] The expansion module 804 is configured to perform expansion processing on the second data signal to obtain a third data signal, and the length of the third data signal is a target length, and the target length is , where N is an integer greater than or equal to 1;

[0301] The processing module 805 is configured to process the third data signal to obtain an output data signal corresponding to the input data signal.

[0302] In a possible implementation manner, the processing module 805 is specifically configured to:

[0303] Determine a fourth data signal from a plurality of second preset signals according to the target length;

[0304] Perform Fourier transform processing on the third data signal to obtain a first processing signal, and perform Fourier transform processing on the fourth data signal to obtain a second processing signal;

[0305] Determine the output data signal according to the first processing signal and the second processing signal.

[0306] In a possible implementation manner, the processing module 805 is specifically configured to:

[0307] Perform calculation processing on the first processing signal and the second processing signal to obtain a third processing signal;

[0308] Perform Fourier transform processing on the third processing signal to obtain a fifth data signal;

[0309] Perform calculation processing on the fifth data signal and the first data signal to obtain the output data signal.

[0310] In a possible implementation manner, the processing module 805 is specifically configured to:

[0311] Preprocess the third data signal to obtain a first sequence;

[0312] Determine the number of butterfly calculations K according to the target length, where K is an integer greater than or equal to 1;

[0313] Perform a first butterfly calculation process on the first sequence to obtain a first output sequence, and the length of the first output sequence is the same as that of the first sequence;

[0314] Perform an (i + 1)-th butterfly calculation process on the i-th output sequence to obtain an (i + 1)-th output sequence, where i successively takes 1, 2, 3,... until the K-th output sequence is obtained, and the K-th output sequence is determined as the second sequence;

[0315] Post-process the second sequence to obtain a first processed signal.

[0316] In a possible implementation manner, the processing module 805 is specifically configured to:

[0317] Group the data in the first sequence to obtain a plurality of subsequences;

[0318] Determine the rotation factor corresponding to each subsequence;

[0319] For any one of the subsequences, perform a butterfly calculation on the subsequence according to the rotation factor corresponding to the subsequence to obtain a sub-calculation result corresponding to the subsequence;

[0320] Perform a splicing process on the plurality of sub-calculation results corresponding to the plurality of subsequences to obtain a first output sequence.

[0321] In a possible implementation manner, the processing module 805 is specifically configured to:

[0322] Split the first sequence to obtain x elements and the sequence numbers corresponding to the respective elements, where x is the quantity corresponding to the target length;

[0323] Group the x elements to obtain a plurality of subsequences, where the subsequence includes a first element and a second element, the sequence number of the first element is less than that of the second element, and the sequence number corresponding to the second element is the sum of the sequence number corresponding to the first element and a first value, and the first value is the product of x and a preset number.

[0324] In a possible implementation manner, the subsequence includes a first element and a second element, and the processing module 805 is specifically configured to:

[0325] Calculate the product of the value corresponding to the second element and the rotation factor;

[0326] Calculate the sum of the values corresponding to the first element and the product to obtain the first calculation data;

[0327] Calculate the difference between the value corresponding to the first element and the product to obtain the second calculation data;

[0328] Among them, the sub-calculation results include the first calculation data and the second calculation data.

[0329] In a possible implementation manner, the processing module 805 is specifically configured to:

[0330] Determine whether the signal type of the third data signal is a frequency domain signal type;

[0331] If so, perform splitting processing and signal conjugate processing on the third data signal to obtain the first sequence;

[0332] If not, perform splitting processing on the third data signal to obtain the first sequence.

[0333] In a possible implementation manner, the processing module 805 is specifically configured to:

[0334] Determine whether the signal type of the third data signal is a frequency domain signal type;

[0335] If so, perform signal conjugate processing and splicing processing on the second sequence to obtain the first processed signal;

[0336] If not, perform splicing processing on the second sequence to obtain the first processed signal.

[0337] In a possible implementation manner, the expansion module 804 is specifically configured to:

[0338] Determine the signal length of the second data signal;

[0339] Determine whether the signal length is , where N is any positive integer;

[0340] If so, determine the second data signal as the third data signal;

[0341] If not, obtain the first mapping relationship, and determine the third data signal according to the signal length and the first mapping relationship. The first mapping relationship includes multiple preset ranges and the preset values corresponding to each preset range. The target length of the third data signal is the preset value corresponding to the target range among the multiple preset ranges.

[0342] In a possible implementation manner, the processing module 805 is further configured to:

[0343] Obtain the signal identifier corresponding to the input data signal, where the signal identifier includes a frequency domain identifier and a time domain identifier;

[0344] If the signal identifier is a frequency-domain identifier, perform sorting processing on the output data signal and output the sorted output data signal;

[0345] If the signal identifier is a time-domain identifier, output the output data signal.

[0346] For the description of the features in the embodiments corresponding to the data processing device, reference can be made to the relevant descriptions in the embodiments corresponding to the data processing method, which will not be elaborated here one by one.

[0347] Figure 9 This is a schematic structural diagram of the electronic device provided by this application. As Figure 9 shown, the electronic device 900 provided in this embodiment includes: at least one processor 901 and a memory 902. Optionally, the electronic device 900 further includes a communication component 903. Among them, the processor 901, the memory 902, and the communication component 903 are connected through a bus 904.

[0348] In a specific implementation process, at least one processor 901 executes the computer execution instructions stored in the memory 902, so that at least one processor 901 executes the above data processing method embodiment.

[0349] For the specific implementation process of the processor 901, reference can be made to the above method embodiment. The implementation principle and technical effects are similar, and will not be elaborated here in this embodiment.

[0350] In the above embodiments, it should be understood that the processor may be a central processing unit (Central Processing Unit, abbreviated as: CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, abbreviated as: DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as: ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

[0351] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0352] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the buses in the drawings of this application are not limited to only one bus or one type of bus.

[0353] An embodiment of this application also provides a computer-readable storage medium, in which a computer program is stored. Wherein, the computer program is configured to execute the steps in any one of the above-described data processing method embodiments when running.

[0354] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0355] An embodiment of this application also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above-described data processing method embodiments.

[0356] An embodiment of this application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above-described data processing method embodiments.

[0357] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0358] The above has introduced in detail a data processing method provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method of this application and its core idea. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of this application, several improvements and modifications can also be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data processing method, characterized in that, Including: Obtain an input data signal, where the length of the input data signal is an initial length; Determine a first data signal from a plurality of first preset signals according to the initial length, where the length of the first data signal is the initial length; Generate a second data signal according to the input data signal and the first data signal; Determine the signal length of the second data signal; Judge whether the signal length is 2^N, where N is any positive integer; If so, determine the second data signal as a third data signal; Otherwise, obtain the first mapping relationship. According to the signal length and the first mapping relationship, determine the third data signal. The first mapping relationship includes multiple preset ranges and the preset values corresponding to each preset range. The target length of the third data signal is the preset value corresponding to the target range among the multiple preset ranges. The length of the third data signal is the target length, and the target length is , where N is an integer greater than or equal to 1; Determine a fourth data signal with the same length as the target length from a plurality of second preset signals according to the target length; Perform Fourier transform processing on the third data signal to obtain a first processed signal, and perform Fourier transform processing on the fourth data signal to obtain a second processed signal; Determine an output data signal according to the first processed signal and the second processed signal.

2. The data processing method according to claim 1, wherein Determine the output data signal according to the first processed signal and the second processed signal, including: Perform calculation processing on the first processed signal and the second processed signal to obtain a third processed signal; Perform Fourier transform processing on the third processed signal to obtain a fifth data signal; Perform calculation processing on the fifth data signal and the first data signal to obtain the output data signal.

3. The data processing method according to claim 1, wherein Perform Fourier transform processing on the third data signal to obtain a first processed signal, including: Perform preprocessing on the third data signal to obtain a first sequence; Determine the number of butterfly calculations K according to the target length, where K is an integer greater than or equal to 1; Perform a first butterfly calculation process on the first sequence to obtain a first output sequence, where the length of the first output sequence is the same as the length of the first sequence; Perform an (i + 1)-th butterfly calculation process on the i-th output sequence to obtain an (i + 1)-th output sequence, where i sequentially takes 1, 2, 3, …… until the K-th output sequence is obtained, and determine the K-th output sequence as the second sequence; Perform postprocessing on the second sequence to obtain a first processed signal.

4. The data processing method according to claim 3, characterized in that, Perform a first butterfly calculation process on the first sequence to obtain a first output sequence, including: Perform grouping processing on the data in the first sequence to obtain a plurality of subsequences; Determine the rotation factor corresponding to each subsequence; For any one subsequence, perform butterfly calculation on the subsequence according to the rotation factor corresponding to the subsequence to obtain a sub-calculation result corresponding to the subsequence; Perform splicing processing on the plurality of sub-calculation results corresponding to the plurality of subsequences to obtain the first output sequence.

5. The data processing method according to claim 4, wherein Perform grouping processing on the data in the first sequence to obtain a plurality of subsequences, including: Perform splitting processing on the first sequence to obtain x elements and the serial numbers corresponding to each element, where x is the quantity corresponding to the target length; Group x elements to obtain multiple subsequences. Each subsequence includes a first element and a second element. The serial number of the first element is less than that of the second element, and the serial number corresponding to the second element is the sum of the serial number corresponding to the first element and a first value. The first value is the product of x and a preset number.

6. The data processing method according to claim 4, wherein Each subsequence includes a first element and a second element. Perform butterfly calculation on the subsequence according to the rotation factor corresponding to the subsequence to obtain a sub-calculation result corresponding to the subsequence, including: Calculate the product of the value corresponding to the second element and the rotation factor; Calculate the sum of the value corresponding to the first element and the product to obtain a first calculation data; Calculate the difference between the value corresponding to the first element and the product to obtain a second calculation data; Wherein, the sub-calculation result includes the first calculation data and the second calculation data.

7. The data processing method according to claim 3, wherein Preprocess the third data signal to obtain a first sequence, including: Judge whether the signal type of the third data signal is a frequency domain signal type; If so, perform splitting processing and signal conjugate processing on the third data signal to obtain a first sequence; If not, perform splitting processing on the third data signal to obtain a first sequence.

8. The data processing method according to claim 3, wherein Post-process the second sequence to obtain a first processed signal, including: Judge whether the signal type of the third data signal is a frequency domain signal type; If so, perform signal conjugate processing and splicing processing on the second sequence to obtain a first processed signal; If not, perform splicing processing on the second sequence to obtain a first processed signal.

9. The data processing method according to any one of claims 1-8, characterized in that, After processing the third data signal to obtain an output data signal corresponding to the input data signal, the method further includes: Obtain a signal identifier corresponding to the input data signal. The signal identifier includes a frequency domain identifier and a time domain identifier; If the signal identifier is a frequency domain identifier, perform sorting processing on the output data signal and output the sorted output data signal; If the signal identifier is a time domain identifier, output the output data signal.

10. A data processor, characterized in that, Including: An input port, a first preset memory, a complex multiplier, a Fourier transform calculator, a framing unit, and an output port; Wherein, the input port is connected to the complex multiplier, the first preset memory is connected to the complex multiplier, the complex multiplier is connected to the framing unit, the framing unit is connected to the Fourier transform calculator, and the complex multiplier is further connected to the output port; The input port is used to obtain an input data signal, and the length of the input data signal is an initial length; The first preset memory is used to determine a first data signal from multiple first preset signals according to the initial length, and the length of the first data signal is the initial length; The complex multiplier is used to generate a second data signal according to the input data signal and the first data signal; The framing unit is configured to perform an expansion process on the second data signal to obtain a third data signal, where the length of the third data signal is a target length, and the target length is , where N is an integer greater than or equal to 1; The Fourier transform calculator and the complex multiplier are used to process the third data signal to obtain an output data signal corresponding to the input data signal; The output port is used to output the output data signal; The data processor includes a second preset memory, and the second preset memory is connected to the Fourier transform calculator. The second preset memory is configured to determine a fourth data signal from multiple second preset signals according to the target length. The Fourier transform calculator is specifically configured to perform Fourier transform processing on the third data signal to obtain a first processed signal, and perform Fourier transform processing on the fourth data signal to obtain a second processed signal. The complex multiplier and the Fourier transform calculator are specifically configured to determine the output data signal according to the first processed signal and the second processed signal. The framing unit is specifically configured to determine the signal length of the second data signal; determine whether the signal length is 2^N, where N is any positive integer; if so, determine the second data signal as the third data signal; if not, obtain a first mapping relationship, and determine a third data signal according to the signal length and the first mapping relationship. The first mapping relationship includes multiple preset ranges and preset values corresponding to each preset range. The target length of the third data signal is the preset value corresponding to the target range in the multiple preset ranges.

11. The data processor according to claim 10, wherein The complex multiplier is specifically configured to perform calculation processing on the first processed signal and the second processed signal to obtain a third processed signal. The Fourier transform calculator is further configured to perform Fourier transform processing on the third processed signal to obtain a fifth data signal. The complex multiplier is further configured to perform calculation processing on the fifth data signal and the first data signal to obtain the output data signal.

12. The data processor according to claim 10, wherein The Fourier transform calculator is specifically configured to: Perform preprocessing on the third data signal to obtain a first sequence. Determine the number of butterfly calculations K according to the target length, where K is an integer greater than or equal to 1. Store the first sequence in a first memory, and perform first butterfly calculation processing on the first sequence in the first memory to obtain a first output sequence, and the length of the first output sequence is the same as the length of the first sequence. Store the i-th output sequence in the M-th memory, and perform the (i + 1)-th butterfly calculation processing on the i-th output sequence in the M-th memory to obtain the (i + 1)-th output sequence, where i sequentially takes 1, 2, 3,..., until the K-th output sequence is obtained, and the K-th output sequence is determined as the second sequence. When i is odd, M is 2, and when i is even, M is 1. Perform postprocessing on the second sequence to obtain a first processed signal.

13. The data processor according to claim 12, characterized in that, Wherein The first memory includes a first real sub-memory and a first imaginary sub-memory, the second memory includes a second real sub-memory and a second imaginary sub-memory, the first sequence includes a first real sequence and a first imaginary sequence, the first real sequence is stored in the first real sub-memory, the first imaginary sequence is stored in the first imaginary sub-memory, the i-th output sequence includes an i-th output real sequence and an i-th output imaginary sequence, the i-th output real sequence is stored in the i-th real sub-memory of the M-th memory, and the i-th output imaginary sequence is stored in the i-th imaginary sub-memory of the M-th memory.

14. The data processor according to any one of claims 10-13, characterized in that, The framing unit is also connected to the output port; The framing unit is further configured to obtain a signal identifier corresponding to the input data signal, where the signal identifier includes a frequency-domain identifier and a time-domain identifier; if the signal identifier is a frequency-domain identifier, perform sorting processing on the output data signal to obtain a sorted output data signal.

15. An electronic device, characterized in that, Comprising: A memory and a processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the data processing method according to any one of claims 1 to 9.

16. A computer-readable storage medium, characterized in that, Computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, they are used to implement the data processing method according to any one of claims 1 to 9.

17. A computer program product, comprising a computer program, which when executed by a processor implements the data processing method according to any one of claims 1 to 9.

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