SRAM Compiler Design Method and Device Against Single-Event Latchup

Abstract

The present application relates to a design method and device for an SRAM compiler against single-event latch-up effect. The method includes: performing device-level single-event latch-up effect simulation on the underlying sub-modules of the SRAM compiler; formulating reinforcement design rules for the underlying sub-modules according to the simulation results; optimizing and improving the underlying sub-modules according to the reinforcement design rules and making them into an anti-latch-up reinforcement database; obtaining the splicing rules of the anti-latch-up reinforcement database in memories with different capacities and describing the splicing rules using a high-level programming language; and using the high-level programming language to call the underlying sub-modules of the anti-latch-up reinforcement database, thereby generating memories with different capacities. This method performs anti-single-event latch-up reinforcement on the underlying sub-modules at the initial stage of SRAM compiler design, which not only ensures the characteristics of low cost, short cycle, high efficiency and flexible configuration of the SRAM compiler, but also enables the memories generated by the SRAM compiler to have the performance of anti-single-event latch-up effect.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit chip design, and particularly to a design method and device for an SRAM compiler resistant to single-event latch-up effect. Background Art

[0002] When an SRAM memory operates in harsh environments such as electromagnetic fields and outer space, the memory may experience single-event latch-up effect, resulting in phenomena such as increased local current and data errors in the memory. Therefore, when designing SRAM memories applied to these harsh environments, it is necessary to perform anti-single-event latch-up design on such memories.

[0003] There are two types of SRAM memory design methods: one is the full-custom design method, but this method has a long design cycle and high cost; the other is the design method of automatically generating a memory by an SRAM compiler. This method has low cost, short cycle, high efficiency, and flexible configuration, and has become the best custom design method for embedded memories. The SRAM compiler design method is as follows: First, design the underlying sub-modules of the compiler and make them into a basic database; then study the splicing rules of the basic database in memories of different capacities, and describe these splicing rules using a high-level programming language; finally, use the high-level programming language to call the underlying sub-modules of the basic database to generate memories of different capacities.

[0004] The single-event latch-up effect is caused by high-energy particles incident on the internally parasitic PNPN structure in a CMOS integrated circuit, and its effect mechanism is well-known in the field. Document 1 (document with publication number CN103886158A) discloses a design method for a standard cell resistant to single-event latch-up effect, and through certain reasonable reinforcement measures, the anti-single-event latch-up effect reinforcement design of the standard cell is realized. Similar to the CMOS standard cell circuit, there is also a parasitic PNPN structure in the underlying sub-modules of the SRAM compiler. If reasonable reinforcement measures are not adopted, the memories generated by the SRAM compiler will also have the risk of single-event latch-up effect. Summary of the Invention

[0005] Based on this, it is necessary to provide a design method and device for an SRAM compiler resistant to single-event latch-up effect in view of the above technical problems.

[0006] A design method for an SRAM compiler resistant to single-event latch-up effect, the method comprising:

[0007] Performing device-level single-event latch-up effect simulation on the underlying sub-modules of the SRAM compiler.

[0008] Formulating reinforcement design rules for the underlying sub-modules according to the simulation results.

[0009] Optimize and improve the underlying sub-module according to the reinforcement design rules, and make it into an anti-latch-up reinforcement database.

[0010] Obtain the splicing rules of the anti-latch-up reinforcement database in memories with different capacities, and describe the splicing rules using a high-level programming language.

[0011] Use a high-level programming language to call the underlying sub-module of the anti-latch-up reinforcement database to generate an anti-latch-up reinforcement SRAM memory with the corresponding capacity.

[0012] In one embodiment, perform device-level single-event latch-up effect simulation on the underlying sub-module of the SRAM compiler, including:

[0013] Obtain the process parameter information of the MOS transistors used in the underlying sub-module of the SRAM compiler.

[0014] According to the process parameter information, perform device-level modeling on the MOS transistors used in the underlying sub-module to obtain a MOS transistor model.

[0015] Determine the first distance between the MOS transistor and the adjacent well contact and the second distance between the MOS transistor and the adjacent well according to the MOS transistor model.

[0016] Adjust the first distance and the second distance, and perform device-level single-event latch-up effect simulation on the MOS transistor model.

[0017] Obtain the maximum critical distance and the minimum critical distance at which the MOS transistor model has a single-event latch-up effect.

[0018] In one embodiment, the maximum value of the first distance between the MOS transistor and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS transistor and the adjacent well is the minimum critical distance.

[0019] In one embodiment, the splicing rules include: the names, call times, and call positions of different underlying sub-modules under different-capacity memories.

[0020] An SRAM compiler design device for anti-single-event latch-up effect, the device includes:

[0021] A device-level single-event latch-up effect simulation module, used to perform device-level single-event latch-up effect simulation on the underlying sub-module of the SRAM compiler.

[0022] A reinforcement design rule determination module, used to formulate reinforcement design rules for the underlying sub-module according to the simulation results.

[0023] The anti-latch-up reinforcement database production module is used to optimize and improve the underlying sub-modules according to the reinforcement design rules and produce an anti-latch-up reinforcement database; obtain the splicing rules of the anti-latch-up reinforcement database in memories with different capacities, and describe the splicing rules using a high-level programming language.

[0024] The anti-latch-up reinforcement SRAM memory design module is used to call the underlying sub-modules of the anti-latch-up reinforcement database using a high-level programming language to generate an anti-latch-up reinforcement SRAM memory with a corresponding capacity.

[0025] In one embodiment, the device-level single-event latch-up effect simulation module is further used to obtain the process parameter information of the MOS transistors used in the underlying sub-modules of the SRAM compiler; perform device-level modeling on the MOS transistors used in the underlying sub-modules according to the process parameter information to obtain a MOS transistor model; determine the first distance between the MOS transistor and the adjacent well contact and the second distance between the MOS transistor and the adjacent well according to the MOS transistor model; adjust the first distance and the second distance to perform device-level single-event latch-up effect simulation on the MOS transistor model; obtain the maximum critical distance and the minimum critical distance at which the MOS transistor model has or does not have a single-event latch-up effect.

[0026] In one embodiment, the maximum value of the first distance between the MOS transistor and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS transistor and the adjacent well is the minimum critical distance.

[0027] In one embodiment, the splicing rules in the anti-latch-up reinforcement database production module include: the names, call times, and call positions of different underlying sub-modules under memories with different capacities.

[0028] The above SRAM compiler design method and device for anti-single-event latch-up effect, the method includes: performing device-level single-event latch-up effect simulation on the underlying sub-modules of the SRAM compiler; formulating reinforcement design rules for the underlying sub-modules according to the simulation results; optimizing and improving the underlying sub-modules according to the reinforcement design rules and producing an anti-latch-up reinforcement database; obtaining the splicing rules of the anti-latch-up reinforcement database in memories with different capacities and describing the splicing rules using a high-level programming language; using a high-level programming language to call the underlying sub-modules of the anti-latch-up reinforcement database, thereby generating memories with different capacities. This method performs anti-single-event latch-up reinforcement on the underlying sub-modules at the initial stage of SRAM compiler design, which not only ensures the characteristics of low cost, short cycle, high efficiency, and flexible configuration of the SRAM compiler, but also enables the memories generated by the SRAM compiler to have the performance of anti-single-event latch-up effect. Description of the Drawings

[0029] Figure 1Application scenario diagram of the SRAM compiler design method for anti-single event latch-up effect in one embodiment;

[0030] Figure 2 Schematic diagram of the composition of module C under different capacities in another embodiment;

[0031] Figure 3 Schematic diagram of the MOS transistor model in another embodiment;

[0032] Figure 4 Structural block diagram of the SRAM compiler design device for anti-single event latch-up effect in one embodiment. Detailed implementation manners

[0033] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] In one embodiment, as Figure 1 shown, a design method for an SRAM compiler for anti-single event latch-up effect is provided, and the method includes the following steps:

[0035] Step 100: Perform device-level single event latch-up effect simulation on the underlying sub-modules of the SRAM compiler.

[0036] Specifically, perform device-level single event latch-up effect simulation on the underlying sub-modules of the SRAM compiler to obtain the minimum requirements for avoiding single event latch-up effect in the sub-modules.

[0037] Step 102: Formulate reinforcement design rules for the underlying sub-modules according to the simulation results.

[0038] Specifically, formulate anti-latch-up reinforcement design rules for the underlying sub-modules according to the simulation results, and the reinforcement design rules are described as: the maximum distance between the MOS transistor and the adjacent well contact is the critical distance L1 max and the minimum distance between the MOS transistor and the adjacent well is the critical distance L2 min .

[0039] Step 104: Optimize and improve the underlying sub-modules according to the reinforcement design rules and make them into an anti-latch-up reinforcement database.

[0040] Specifically, optimize and improve the underlying sub-modules one by one until all MOS transistors in all underlying sub-modules meet the above reinforcement design rules.

[0041] In a specific embodiment, if the distance between MOS transistor A and the adjacent well is less than the critical distance L2 min, then the MOS transistor A needs to be translated as a whole in a direction away from the adjacent well, so that the distance between the MOS transistor A and the adjacent well is greater than or equal to the critical distance L2 min .

[0042] If the distance of MOS transistor B is L1 max and there is no well contact within it, then at least one well contact needs to be added within the distance L1 of MOS transistor B max .

[0043] Step 106: Obtain the splicing rules of the anti-latch-up reinforcement database in memories with different capacities, and describe the splicing rules using a high-level programming language.

[0044] Specifically, memories with different capacities are spliced by different types and numbers of modules, but memories with a specific capacity must be spliced by specific types and specific numbers of modules. The anti-latch-up reinforcement database needs to contain the underlying sub-modules that can be spliced into memories of all capacities. The anti-latch-up underlying sub-modules are spliced into the sub-underlying modules, and the lower-level modules are gradually spliced into the upper-level modules until the top-level module, which is the anti-latch-up memory. And the specific splicing rules are described by a high-level programming language.

[0045] As Figure 2 shown, in a specific embodiment, the C module with a memory capacity of S1 is spliced by module A and module B; the C module with a memory capacity of S2 is spliced by module A, module A, and module B; the C module with a memory capacity of S3 is spliced by module A, module A, module A, and module B.

[0046] In the high-level programming language, the following contents need to be defined:

[0047] When the capacity of the memory is S2, the memory is spliced by modules step by step. Among them, the C module calls module A and module B. The coordinates of the first module A are (xa 1 , ya 1 ), the coordinates of the second module A are (xa 2 , ya 2 ), and the coordinates of module B are (xb 1 , yb 1 ). Similarly, except for the anti-latch-up underlying sub-modules, each module of memories with different capacities needs to be defined in this way.

[0048] Step 108: Use the high-level programming language to call the underlying sub-modules of the anti-latch-up reinforcement database to generate the anti-latch-up reinforcement SRAM memory corresponding to the capacity.

[0049] Specifically, when it is necessary to generate a latch-up resistant SRAM memory with a capacity of S2, the high-level programming language will call the lower-level modules step by step according to the above splicing rules. The lowest-level module is the underlying sub-module of the latch-up resistant database, thereby generating a latch-up resistant memory with the corresponding capacity.

[0050] In a specific embodiment, for ease of understanding, assume that different types of underlying sub-modules are different types of "building block parts", and the latch-up resistant SRAM memory is a "building block house". Then, the latch-up resistant database is all types of "building block parts", the high-level programming language is the "rule description" for assembling the building block parts into a building block house, and the latch-up resistant SRAM memories with different capacities are "building block houses of different sizes".

[0051] The latch-up resistant SRAM compiler designed by this method can generate latch-up resistant SRAM memories with different capacities, greatly reducing the R & D cost of latch-up resistant memories. This design method has low cost, is easy to implement, can generate latch-up resistant SRAM memories with different capacities, and greatly reduces the R & D cost of latch-up resistant memories.

[0052] In the above SRAM compiler design method for anti-single event latch-up effect, the method includes: performing device-level single event latch-up effect simulation on the underlying sub-modules of the SRAM compiler; formulating reinforcement design rules for the underlying sub-modules according to the simulation results; optimizing and improving the underlying sub-modules according to the reinforcement design rules and making them into a latch-up resistant database; obtaining the splicing rules of the latch-up resistant database in memories with different capacities and describing the splicing rules using a high-level programming language; using the high-level programming language to call the underlying sub-modules of the latch-up resistant database, thereby generating memories with different capacities. This method performs anti-single event latch-up reinforcement on the underlying sub-modules at the initial stage of SRAM compiler design, which not only ensures the characteristics of low cost, short cycle, high efficiency, and flexible configuration of the SRAM compiler, but also enables the memories generated by the SRAM compiler to have the performance of anti-single event latch-up effect.

[0053] In one of the embodiments, step 100 includes: obtaining the process parameter information of the MOS transistors used in the underlying sub-modules of the SRAM compiler; performing device-level modeling on the MOS transistors used in the underlying sub-modules according to the process parameter information to obtain a MOS transistor model; determining a first distance between the MOS transistor and the adjacent well contact and a second distance between the MOS transistor and the adjacent well according to the MOS transistor model; adjusting the first distance and the second distance to perform device-level single event latch-up effect simulation on the MOS transistor model; obtaining the maximum critical distance and the minimum critical distance at which the MOS transistor model has or has not occurred single event latch-up effect.

[0054] Specifically, obtain the process parameter information of the MOS transistors used in the underlying sub-module (the process parameter information of the MOS transistors includes parameters such as model flag parameters, general model parameters, and DC parameters. The model flag parameters define parameters such as the minimum and maximum values of the MOS transistor gate length, the general model parameters define parameters such as the gate oxide layer thickness, and the DC parameters define parameters such as the polysilicon doping concentration and junction depth of the gate). According to this process parameter information, perform device-level modeling on the MOS transistors used in the underlying sub-module. The schematic diagram of the MOS model is shown in Figure 3 as shown, Figure 3 also shows the distance L1 between the MOS transistor (PMOS transistor or NMOS transistor) and the adjacent well contact, and the distance L2 between the MOS transistor and the adjacent well. According to relevant literature, the single-event latch-up effect can be reduced by reducing the distance L1 and increasing the distance L2, etc. Adjust the distances L1 and L2 between the MOS transistor and the adjacent well contact, and perform device-level single-event latch-up effect simulation on the established model.

[0055] Obtain the critical distance L1 at which the single-event latch-up effect occurs in the MOS transistor model max and the critical distance L2 min .

[0056] In one embodiment, the maximum value of the first distance between the MOS transistor and the adjacent well contact is the maximum value of the critical distance, and the minimum value of the distance between the MOS transistor and the adjacent well is the minimum value of the critical distance.

[0057] In one embodiment, the splicing rule includes: the names, call times, and call locations of different underlying sub-modules under different capacity memories.

[0058] It should be understood that although Figure 1 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 1 at least a part of the steps in

[0059] In one embodiment, as shown in Figure 4As shown, a device for designing an SRAM compiler against single-event latch-up effect is provided, including: a device-level single-event latch-up effect simulation module, a reinforcement design rule determination module, an anti-latch-up reinforcement database production module, and an anti-latch-up reinforcement SRAM memory design module, where:

[0060] The device-level single-event latch-up effect simulation module is used to perform device-level single-event latch-up effect simulation on the underlying sub-modules of the SRAM compiler.

[0061] The reinforcement design rule determination module is used to formulate the reinforcement design rules for the underlying sub-modules according to the simulation results.

[0062] The anti-latch-up reinforcement database production module is used to optimize and improve the underlying sub-modules according to the reinforcement design rules, and produce them into an anti-latch-up reinforcement database; obtain the splicing rules of the anti-latch-up reinforcement databases in memories with different capacities, and describe the splicing rules using a high-level programming language.

[0063] The anti-latch-up reinforcement SRAM memory design module is used to call the underlying sub-modules of the anti-latch-up reinforcement database using a high-level programming language to generate an anti-latch-up reinforcement SRAM memory with the corresponding capacity.

[0064] In one embodiment, the device-level single-event latch-up effect simulation module is further used to obtain the process parameter information of the MOS transistors used in the underlying sub-modules of the SRAM compiler; perform device-level modeling on the MOS transistors used in the underlying sub-modules according to the process parameter information to obtain a MOS transistor model; determine the first distance between the MOS transistor and the adjacent well contact and the second distance between the MOS transistor and the adjacent well according to the MOS transistor model; adjust the first distance and the second distance, and perform device-level single-event latch-up effect simulation on the MOS transistor model; obtain the maximum critical distance and the minimum critical distance at which the MOS transistor model has or has not occurred single-event latch-up effect.

[0065] In one embodiment, the maximum value of the first distance between the MOS transistor and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS transistor and the adjacent well is the minimum critical distance.

[0066] In one embodiment, the splicing rules in the anti-latch-up reinforcement database production module include: the names, call times, and call positions of different underlying sub-modules under different-capacity memories.

[0067] For the specific limitations of the SRAM compiler design device against single-event latch-up, reference can be made to the limitations of the SRAM compiler design method against single-event latch-up in the above text, which will not be elaborated here. Each module in the above SRAM compiler design device against single-event latch-up can be implemented in whole or in part by software, hardware, or a combination thereof. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to each of the above modules.

[0068] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0069] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for designing an SRAM compiler resistant to single event latch-up effect, characterized in that: The method comprises: Perform device-level single-event latch-up simulation on the underlying submodules of the SRAM compiler; Formulate reinforcement design rules for underlying submodules based on simulation results; Optimizing and improving the bottom layer submodules according to the reinforcement design rules and making them into an anti-latch reinforcement database; Obtaining the splicing rules of the anti-latch reinforcement database in the storage devices of different capacities, and describing the splicing rules in a high-level programming language; the splicing rules include: the names, call times and call locations of different bottom-level submodules in the storage devices of different capacities; Using a high-level programming language to call the bottom submodule of the anti-latch hardening database to generate an anti-latch hardening SRAM memory of corresponding capacity; Among them, the device-level single-particle latch-up effect simulation is performed on the underlying submodules of the SRAM compiler, including: Get the process parameter information of the MOS tube used by the bottom submodule of the SRAM compiler; According to the process parameter information, device-level modeling is performed on the MOS tube used by the bottom submodule to obtain a MOS tube model; Determine a first distance between the MOS tube and the adjacent well contact and a second distance between the MOS tube and the adjacent well according to the MOS tube model; Adjusting the first distance and the second distance to perform device-level single-particle latch effect simulation on the MOS tube model; The maximum value and the minimum value of the critical distance for determining whether the single-particle latch effect occurs in the MOS tube model are obtained.

2. The method for designing a SRAM compiler resistant to single event latch-up effect according to claim 1, characterized in that: The maximum value of the first distance between the MOS tube and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS tube and the adjacent well is the minimum critical distance.

3. A SRAM compiler design device resistant to single-particle latch effect, characterized in that: The device comprises: Device-level single-particle latch-up effect simulation module, used to perform device-level single-particle latch-up effect simulation on the underlying submodules of the SRAM compiler; A reinforcement design rule determination module is used to formulate reinforcement design rules for underlying submodules based on simulation results; an anti-latching reinforcement database making module, used for optimizing and improving the bottom-level submodules according to the reinforcement design rules, and making them into an anti-latching reinforcement database; obtaining the splicing rules of the anti-latching reinforcement databases in memories of different capacities, and describing the splicing rules in a high-level programming language; the splicing rules include: the names, call times and call locations of different bottom-level submodules in memories of different capacities; An anti-latch reinforcement SRAM memory design module is used to call the bottom submodule of the anti-latch reinforcement database using a high-level programming language to generate an anti-latch reinforcement SRAM memory of corresponding capacity; Among them, the device-level single-particle latch-up effect simulation module is also used to obtain process parameter information of the MOS tube used by the bottom sub-module of the SRAM compiler; according to the process parameter information, device-level modeling is performed on the MOS tube used by the bottom sub-module to obtain a MOS tube model; according to the MOS tube model, a first distance between the MOS tube and the adjacent well contact and a second distance between the MOS tube and the adjacent well are determined; the first distance and the second distance are adjusted to perform device-level single-particle latch-up effect simulation on the MOS tube model; and a critical distance maximum value and a critical distance minimum value for whether the MOS tube model has a single-particle latch-up effect are obtained.

4. The SRAM compiler design device for resisting single event latch-up effect according to claim 3, characterized in that: The maximum value of the first distance between the MOS tube and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS tube and the adjacent well is the minimum critical distance.

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