Integrated design method and system for gene sequencing chip

Abstract

The present invention relates to the field of chip integrated design, and in particular to an integrated design method and system for a gene sequencing chip. The method comprises the following steps: obtaining an initial design drawing of a gene sequencing chip; performing a multi-level chip framework design on the initial design drawing, thereby constructing a multi-level chip simulation framework; performing a multi-parameter design of a probe array arrangement and a feasibility adjustment of a channel distribution based on the gene sequencing chip design drawing, thereby obtaining multiple chip space arrangement schemes; extracting an optimal chip space arrangement scheme based on multiple chip space arrangement schemes; and optimizing the space arrangement of the multi-level chip simulation framework to obtain a space optimization simulation framework; performing a full-cycle gene sequencing simulation based on the space optimization simulation framework, collecting gene sequencing simulation data, and performing a noise suppression circuit design, thereby obtaining a noise suppression circuit strategy. The present invention improves the accuracy and reliability of chip integrated design by optimizing the layout in chip design.

Description

Technical Field

[0001] The present invention relates to the field of chip integration design, and in particular to an integrated design method and system for a gene sequencing chip. Background Art

[0002] With the rapid development of life sciences and genomics, gene sequencing technology has been widely used in medicine, agriculture, environmental monitoring and other fields. As the core component of this technology, gene sequencing chips undertake the important task of high-throughput and accurate analysis of genetic information. Traditional gene sequencing chip design methods mainly rely on laboratory experiments and manual design, and have problems such as long design cycle, high cost, and limited accuracy. With the rapid growth of genomic data and the improvement of sequencing accuracy requirements, traditional methods can no longer meet the needs of efficient, accurate, and personalized gene sequencing.

[0003] At the same time, the design of gene sequencing chips faces multiple challenges, including layout optimization of probe arrays, suppression of signal noise, distribution of chip channels, and coordination of fluid dynamics. Especially under the influence of multiple complex factors, how to accurately predict and optimize these influencing factors during the design phase has become the key to improving the performance of gene sequencing chips. Traditional gene sequencing chip design methods often rely on manual adjustments and local optimizations, lacking a systematic and integrated simulation design platform, making it easy to ignore potential design defects during the chip design process, and even unable to promptly discover and solve performance bottlenecks caused by unreasonable chip structures. Summary of the invention

[0004] In order to solve the above technical problems, the present invention proposes an integrated design method and system for a gene sequencing chip to solve at least one of the above technical problems.

[0005] To achieve the above object, the present invention provides an integrated design method for a gene sequencing chip, comprising the following steps:

[0006] Step S1: obtaining an initial design drawing of a gene sequencing chip; performing a multi-level chip framework design on the initial design drawing, thereby constructing a multi-level chip simulation framework;

[0007] Step S2: Based on the gene sequencing chip design drawings, multi-parameter design of probe array layout and feasibility adjustment of channel distribution are performed to obtain multiple chip space layout schemes;

[0008] Step S3: extracting the optimal chip space layout scheme based on multiple chip space layout schemes; and optimizing the space layout of the multi-level chip simulation framework to obtain a space optimization simulation framework;

[0009] Step S4: performing full-cycle gene sequencing simulation based on the spatial optimization simulation framework, collecting gene sequencing simulation data, and performing noise suppression circuit design to obtain a noise suppression circuit strategy;

[0010] Step S5: performing microfluidic response imbalance mining on gene sequencing simulation data and performing response imbalance compensation calculation to generate chip response imbalance compensation parameters;

[0011] Step S6: fine-tuning the final chip parameters based on the noise suppression circuit strategy and chip response imbalance compensation parameters, thereby obtaining the final chip framework.

[0012] The present invention obtains the initial design drawings and performs multi-level framework design to manage the chip in layers, ensuring that the design of each layer can cooperate with other layers to avoid design conflicts. This method allows the complexity of the gene sequencing chip to be clearly presented, facilitating subsequent optimization and modification. The multi-level framework design can provide an independent simulation path for each layer, ensuring that the characteristics of each layer can be evaluated separately while maintaining the coordination of the overall design. Through this hierarchical design, the complexity is effectively reduced and the simulation efficiency is improved. The arrangement of the probe array is crucial to the sequencing quality and speed of the gene sequencing chip. Through multi-parameter design, it can be flexibly adjusted according to different design requirements (such as the density, size, and distribution of the probe), thereby Optimize sequencing results and improve probe utilization. By adjusting channel distribution, we can make full use of chip space and improve chip sequencing throughput. At the same time, we can ensure the effective layout of probes and avoid redundancy or waste of space, thereby improving overall performance. Extracting the best solution from multiple solutions can ensure that the chip design selects the most performant and efficient configuration among multiple potential solutions, avoid repeated trial and error in design, and reduce development cycle and cost. By optimizing the space of the multi-level chip simulation framework, we can not only ensure the reasonable layout of the chip's functional modules, but also further improve the chip's stability and operating efficiency. The optimized simulation framework helps to discover potential design problems in advance and achieve more efficient resource allocation. Full-cycle simulation helps to optimize the overall Evaluate each link in the gene sequencing process to ensure that the design can adapt to different usage scenarios, identify potential problems in advance, and avoid mistakes in the experimental stage. Noise is a common source of interference in the gene sequencing process, which will affect the accuracy of the data. By designing noise suppression circuits, the impact of noise generated by the external environment or the system itself can be reduced to ensure the accuracy and reliability of sequencing data. This strategy makes simulation design more practical in high-precision sequencing applications. The microfluidic system in the gene sequencing chip has response imbalance, which will affect the consistency of sample processing and the sequencing efficiency of the chip. By mining the imbalance of simulation data, the unstable factors in the microfluidic system can be accurately located, fluid dynamics problems can be prevented in advance, and response imbalance can be addressed. Compensation calculations can optimize the chip's microfluidic system and ensure the consistency of liquid flow and sample processing. The response compensation strategy can improve the chip's sequencing accuracy, reduce errors, and ensure the consistency and reliability of experimental results. Fine-tuning based on noise suppression circuit strategies and response imbalance compensation parameters ensures that every technical detail of the chip design is optimal. The final fine-tuned chip framework can meet the highest standards in performance, stability, and reliability, ensuring the accuracy and efficiency of gene sequencing experiments. Through comprehensive optimization of noise and response imbalance problems, the final chip can not only provide higher sequencing accuracy, but also adapt to a wider range of experimental needs in practical applications, thereby enhancing the market competitiveness and applicability of the chip.

[0013] In this specification, an integrated design system for a gene sequencing chip is provided, which is used to execute the integrated design method for the gene sequencing chip as described above, including:

[0014] A multi-level framework is used to obtain the initial design drawings of the gene sequencing chip; a multi-level chip framework is designed for the initial design drawings, thereby constructing a multi-level chip simulation framework;

[0015] A multi-parameter design module is used to perform multi-parameter design of probe array layout and feasibility adjustment of channel distribution based on the gene sequencing chip design drawings, thereby obtaining multiple chip space layout schemes;

[0016] A space layout optimization module is used to extract the optimal chip space layout scheme based on multiple chip space layout schemes; and optimize the space layout of the multi-level chip simulation framework to obtain a space optimization simulation framework;

[0017] The noise suppression module is used to perform full-cycle gene sequencing simulation based on the spatial optimization simulation framework, collect gene sequencing simulation data, and perform noise suppression circuit design to obtain a noise suppression circuit strategy;

[0018] The response imbalance compensation module is used to mine the microfluidic response imbalance of gene sequencing simulation data and perform response imbalance compensation calculations to generate chip response imbalance compensation parameters;

[0019] The parameter fine-tuning module is used to fine-tune the final chip parameters based on the noise suppression circuit strategy and the chip response imbalance compensation parameters, so as to obtain the final chip framework.

[0020] The present invention lays the foundation for the entire design process by obtaining the initial design drawings of the gene sequencing chip. By analyzing the initial design drawings, the preliminary design structure of the chip can be fully understood, and potential design defects or bottlenecks can be identified. The multi-level chip framework design combines the electrical, fluid, thermal and other dimensional behaviors of the chip for comprehensive analysis. The topological structure of the circuit, the flow conditions of the microfluidic channel, the distribution of the probes, etc., each layer is independently simulated, thereby improving the design accuracy, discovering problems in advance and adjusting the design. The layout of the probe array directly affects the efficiency and accuracy of gene sequencing. The array layout is optimized through multi-parameter design (such as probe spacing, arrangement density, etc.), which significantly improves the accuracy of the sequencing results and avoids interference and overlapping signals. The distribution and design of microfluidic channels can achieve more efficient fluid control and optimize the flow path and reaction efficiency of liquid samples. This optimization not only affects the sequencing speed, but is also directly related to the stability and reliability of the chip. By adjusting the feasibility of different design schemes, various configuration schemes can be evaluated in the early stages of design to avoid unfeasible or costly schemes in the later design process and reduce the investment in ineffective designs. By comparing multiple design schemes, the design scheme with the highest space utilization and the best performance can be extracted to ensure that the design density and function of the chip are maximized and to avoid wasting precious space resources. The spatial layout of the multi-level simulation framework can be further optimized to better integrate different functional modules such as circuits, microfluidic channels, and probe arrays. Reduce the interference between modules and improve the overall efficiency of the system. By optimizing the spatial layout, reduce the mechanical or fluid problems caused by unreasonable design, reduce the failure rate in chip production, and conduct full-cycle gene sequencing simulation, it can simulate the entire working process of the chip and identify the performance bottlenecks that appear at different stages, such as probe signal distortion and fluid dynamics inequality. Noise is an important factor affecting sequencing accuracy in the gene sequencing process. By specially designing noise suppression circuits, it can effectively reduce the impact of external noise, signal interference, etc. on sequencing results, ensuring that the signal is more accurate and clear. The effectiveness of the noise suppression circuit design directly improves the signal-to-noise ratio (SNR) in the gene sequencing process, thereby improving the accuracy and reliability of the final sequencing results and improving the overall Performance, response imbalance problems in fluid dynamics are common in microfluidic systems, resulting in uneven fluid flow, uneven sample distribution, etc. By exploring the response imbalance problem, these problems can be effectively identified and solved to ensure that the fluid response of the chip is accurate and balanced. By generating response imbalance compensation parameters, the microfluidic system of the chip can be accurately adjusted to ensure consistent responses of each channel, avoid errors or deviations in the sequencing process due to local imbalance, timely detect and compensate for response imbalance, improve the stability of the chip under long-term and high-load use, reduce the probability of errors in the sequencing process, and optimize the reliability of sequencing. By optimizing the two aspects of noise suppression and response imbalance compensation, the chip design is finally fine-tuned to ensure that the chip performance reaches the best state.These fine-tunings improve the adaptability and stability of the chip in different working environments. By comprehensively considering the optimization of noise control, response balance, spatial layout and other aspects, the final chip framework will have higher gene sequencing accuracy, faster response speed and lower error rate. The finely optimized chip design can reduce the defective rate in production, improve mass production efficiency, and better cope with complex conditions in actual applications, ensuring the commercialization and market application of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the steps of an integrated design method for a gene sequencing chip according to the present invention;

[0022] Figure 2 Detailed implementation flow chart of step S1;

[0023] Figure 3 Detailed implementation flow chart of step S2;

[0024] Figure 4 Detailed implementation flow chart of step S3. DETAILED DESCRIPTION

[0025] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0026] The present application example provides an integrated design method and system for a gene sequencing chip. The execution subjects of the integrated design method and system for the gene sequencing chip include but are not limited to: mechanical equipment, data processing platform, cloud server node, network upload device, etc. equipped with the system can be regarded as the general computing node of the present application, and the data processing platform includes but is not limited to: at least one of an audio image management system, an information management system, and a cloud data management system.

[0027] See also Figures 1 to 4 The present invention provides an integrated design method for a gene sequencing chip, and the integrated design method for a gene sequencing chip comprises the following steps:

[0028] Step S1: obtaining an initial design drawing of a gene sequencing chip; performing a multi-level chip framework design on the initial design drawing, thereby constructing a multi-level chip simulation framework;

[0029] Step S2: Based on the gene sequencing chip design drawings, multi-parameter design of probe array layout and feasibility adjustment of channel distribution are performed to obtain multiple chip space layout schemes;

[0030] Step S3: extracting the optimal chip space layout scheme based on multiple chip space layout schemes; and optimizing the space layout of the multi-level chip simulation framework to obtain a space optimization simulation framework;

[0031] Step S4: performing full-cycle gene sequencing simulation based on the spatial optimization simulation framework, collecting gene sequencing simulation data, and performing noise suppression circuit design to obtain a noise suppression circuit strategy;

[0032] Step S5: performing microfluidic response imbalance mining on gene sequencing simulation data and performing response imbalance compensation calculation to generate chip response imbalance compensation parameters;

[0033] Step S6: fine-tuning the final chip parameters based on the noise suppression circuit strategy and chip response imbalance compensation parameters, thereby obtaining the final chip framework.

[0034] The present invention obtains the initial design drawings and performs multi-level framework design to manage the chip in layers, ensuring that the design of each layer can cooperate with other layers to avoid design conflicts. This method allows the complexity of the gene sequencing chip to be clearly presented, facilitating subsequent optimization and modification. The multi-level framework design can provide an independent simulation path for each layer, ensuring that the characteristics of each layer can be evaluated separately while maintaining the coordination of the overall design. Through this hierarchical design, the complexity is effectively reduced and the simulation efficiency is improved. The arrangement of the probe array is crucial to the sequencing quality and speed of the gene sequencing chip. Through multi-parameter design, it can be flexibly adjusted according to different design requirements (such as the density, size, and distribution of the probe), thereby Optimize sequencing results and improve probe utilization. By adjusting channel distribution, we can make full use of chip space and improve chip sequencing throughput. At the same time, we can ensure the effective layout of probes and avoid redundancy or waste of space, thereby improving overall performance. Extracting the best solution from multiple solutions can ensure that the chip design selects the most performant and efficient configuration among multiple potential solutions, avoid repeated trial and error in design, and reduce development cycle and cost. By optimizing the space of the multi-level chip simulation framework, we can not only ensure the reasonable layout of the chip's functional modules, but also further improve the chip's stability and operating efficiency. The optimized simulation framework helps to discover potential design problems in advance and achieve more efficient resource allocation. Full-cycle simulation helps to optimize the overall Evaluate each link in the gene sequencing process to ensure that the design can adapt to different usage scenarios, identify potential problems in advance, and avoid mistakes in the experimental stage. Noise is a common source of interference in the gene sequencing process, which will affect the accuracy of the data. By designing noise suppression circuits, the impact of noise generated by the external environment or the system itself can be reduced to ensure the accuracy and reliability of sequencing data. This strategy makes simulation design more practical in high-precision sequencing applications. The microfluidic system in the gene sequencing chip has response imbalance, which will affect the consistency of sample processing and the sequencing efficiency of the chip. By mining the imbalance of simulation data, the unstable factors in the microfluidic system can be accurately located, fluid dynamics problems can be prevented in advance, and response imbalance can be addressed. Compensation calculations can optimize the chip's microfluidic system and ensure the consistency of liquid flow and sample processing. The response compensation strategy can improve the chip's sequencing accuracy, reduce errors, and ensure the consistency and reliability of experimental results. Fine-tuning based on noise suppression circuit strategies and response imbalance compensation parameters ensures that every technical detail of the chip design is optimal. The final fine-tuned chip framework can meet the highest standards in performance, stability, and reliability, ensuring the accuracy and efficiency of gene sequencing experiments. Through comprehensive optimization of noise and response imbalance problems, the final chip can not only provide higher sequencing accuracy, but also adapt to a wider range of experimental needs in practical applications, thereby enhancing the market competitiveness and applicability of the chip.

[0035] In the embodiment of the present invention, refer to Figure 1 , is a schematic flow chart of the steps of an integrated design method for a gene sequencing chip of the present invention. In this example, the steps of the integrated design method for a gene sequencing chip include:

[0036] Step S1: obtaining an initial design drawing of a gene sequencing chip; performing a multi-level chip framework design on the initial design drawing, thereby constructing a multi-level chip simulation framework;

[0037] In this embodiment, the initial design drawings of the gene sequencing chip are obtained from relevant databases or research institutions. The design drawings should contain information such as the circuit design of the chip, the layout of the fluid channel, and the material specifications. The obtained design drawings are reviewed in detail to ensure their completeness and accuracy. Check the identification of each component in the drawing to confirm whether the parameters of all electrical and fluid channels, such as voltage, current, flow rate, temperature, etc., meet the experimental requirements. According to the experimental requirements, record the key design parameters, including the size of the chip, the diameter and length of the channel, the conductivity of the material, etc. These parameters will provide a basis for subsequent design optimization. Convert the initial design drawings into a format that can be processed by computer-aided design (CAD) (such as DXF or SVG format) for subsequent design work. Use professional software (such as AutoCAD or SolidWorks) for format conversion. During the conversion process, ensure that all key parameters (such as electrical characteristics, the geometry of the fluid channel, etc.) can be reflected in the new drawings. If necessary, redesign the drawings to ensure that they meet the requirements of the new experimental plan. Integrate the converted design drawings with other relevant data (such as laboratory standards, sequencing requirements, etc.) to form a complete design database. Use data management tools (such as Excel or database management systems) to integrate data and ensure the traceability of information. Perform a preliminary analysis of the integrated data to ensure the rationality and feasibility of all parameters. Analyze whether the design of the fluid channel can meet the required flow rate and pressure requirements, and whether the circuit design can support the operating voltage and power of the chip. Determine the design requirements of the multi-layer chip framework, including the layout of fluid channels, electronic components, sensors, and other functional modules. Set design goals, such as improving the integration of the chip, optimizing the fluid flow path, and reducing noise interference. Combined with experimental parameters, formulate design standards, including requirements such as fluid flow rate, reaction time, and thermal management. These standards will guide the subsequent design process. Use computer-aided design (CAD) software (such as COMSOL Multiphysics or Ansys) to start building a multi-layer chip simulation framework. According to the initial design drawings, add fluid channels, electronic components, and other modules layer by layer. During the design process, consider the functions and relationships of each layer. The fluid channel layer should be designed to facilitate fluid flow, while the electrical layer should ensure the stability of signal transmission. Record the design parameters of each layer and ensure that they are consistent with the experimental requirements. Conduct preliminary simulation tests on the constructed multi-layer chip simulation framework to evaluate its performance. Use CFD (computational fluid dynamics) and electrical simulation tools to simulate the fluid flow, heat conduction and electrical characteristics of the chip. During the simulation process, record key performance indicators such as flow rate, pressure, temperature and current to ensure that these indicators meet the design standards. If unqualified items are found, make necessary adjustments and optimizations to ensure that the design of each level can meet the overall functional requirements.

[0038] Step S2: Based on the gene sequencing chip design drawings, multi-parameter design of probe array layout and feasibility adjustment of channel distribution are performed to obtain multiple chip space layout schemes;

[0039] In this embodiment, according to the application requirements of the gene sequencing chip, the design goals of the probe array are determined, including the type, quantity, layout density and functional characteristics of the probes. The target genome size, sequencing depth and coverage of the sequencing need to be considered. The performance parameters of each probe, such as sensitivity, specificity and reaction time, are determined. These parameters will affect the selection and arrangement of the probes.

[0040] Collect experimental parameters related to probe array design, including probe spacing, effective detection area, signal strength, and background noise. Ensure that these parameters are consistent with actual experimental conditions. Set design criteria, such as probe spacing should be less than a certain threshold to ensure adequate coverage and detection sensitivity. Use computer-aided design (CAD) software (such as AutoCAD or SolidWorks) to build a preliminary probe array layout. According to the design drawings, specify the size and position of each probe to ensure that it meets the experimental requirements. Consider the arrangement of probes, such as matrix, linear, or random layout. Each layout has its advantages and disadvantages. Choose the layout that best suits the current sequencing needs. Perform simulation tests on the preliminary design to evaluate the performance of the probe array under different conditions. Use software (such as COMSOL Multiphysics) to simulate optical, fluid, and electrical properties to ensure that the response time and signal strength of the probes meet the standards. Based on the simulation results, adjust the position and spacing of the probes to optimize the probe layout. Record the performance changes after each adjustment to compare the advantages and disadvantages of different design schemes. Generate multiple probe array layout schemes based on different parameter combinations to ensure that each scheme meets the design criteria. Create probe arrays with different densities and different arrangements to select the best scheme later. Conduct a feasibility assessment for each solution, taking into account cost, manufacturing difficulty, and practical application to ensure that the final solution selected is of practical significance. Determine the design requirements of the microfluidic channel, including fluid flow rate, channel diameter, length, and material. Set channel design standards to ensure that it can support the functional requirements of the probe array. Consider factors such as flow resistance, temperature changes, and chemical reactions in the channel to ensure that the channel design can meet the stability and reliability requirements. Draw the channel layout in CAD software and combine the location of the probe array to ensure that the channel can effectively supply fluid and will not affect the function of the probe. The design should ensure uniform fluid flow and avoid dead zones and stagnation. Use fluid dynamics simulation software (such as ANSYS Fluent) to simulate the channel flow and evaluate the flow velocity distribution and pressure changes. Ensure that the channel design can support the required flow rate and flow velocity. During the simulation process, adjust the shape and size of the channel according to the results of the fluid dynamics analysis to optimize the design to improve flow efficiency and reduce energy loss. Adjust the width and height of the channel to achieve better fluid distribution. Record the results of each adjustment to ensure that the final channel design can support the efficient operation of the probe and meet the actual needs of the experiment.

[0041] Step S3: extracting the optimal chip space layout scheme based on multiple chip space layout schemes; and optimizing the space layout of the multi-level chip simulation framework to obtain a space optimization simulation framework;

[0042] In this embodiment, all generated probe array layouts and channel design schemes are collected. These schemes should contain detailed parameters of each design, including the number of probes, positions, channel dimensions, flow characteristics, etc. A comprehensive table is made to summarize the key parameters of all schemes for subsequent analysis and comparison. Ensure that the information of each scheme is complete and easy to retrieve. A preliminary evaluation is performed on each spatial arrangement scheme, considering its feasibility and effectiveness under experimental conditions. Evaluation indicators include probe coverage, fluid flow uniformity, signal strength, manufacturing difficulty, and cost. A scoring system is used to quantitatively evaluate each scheme, giving different weights to reflect the importance of each indicator. This ensures that the evaluation results can fully reflect the practical application value of the scheme. According to the results of the preliminary evaluation, each scheme is comprehensively scored, and the scheme with the highest score is selected as the optimal scheme. The scores of each evaluation index are comprehensively calculated using the weighted average method. Analyze the schemes with lower scores, identify the key factors affecting their performance, and record this information so that it can be improved in future designs. The selected optimal scheme is further verified. The scheme is simulated and tested in detail using fluid dynamics simulation software (such as COMSOL Multiphysics) to evaluate its actual performance, including flow velocity distribution, temperature change, and signal response. Ensure that the optimal scheme performs well in the simulation and meets all design criteria and experimental requirements. If necessary, adjust certain parameters to optimize performance and re-evaluate. After confirming the optimal chip spatial layout scheme, analyze the spatial configuration of the multi-layer chip simulation framework to identify areas with inefficient space utilization or poor fluid channels. Set optimization goals, including improving space utilization, optimizing fluid flow paths, and enhancing signal transmission efficiency. The analysis at this stage will provide direction for subsequent optimization. Use CAD software (such as SolidWorks or AutoCAD) to optimize the spatial layout of the multi-layer chip simulation framework. According to the parameters of the optimal scheme, redesign the hierarchical structure of the chip to ensure coordination between the various components. In this process, pay special attention to the relative position of the probe array and the fluid channel to ensure that the fluid channel can effectively support the function of the probe and avoid dead zones and stagnation. Simulate and test the optimized multi-layer chip simulation framework. Use CFD (computational fluid dynamics) and electrical performance simulation tools to evaluate the performance of the new layout in actual applications. Record key performance indicators, such as flow velocity, pressure distribution, temperature change, and signal output, to ensure that these indicators meet the expected design goals. If necessary, make adjustments and re-simulate to ensure that the final design achieves optimal performance. Record the optimized spatial layout plan and its performance indicators in the design document, ensuring that each design modification and adjustment is recorded in detail. This will provide a reference for subsequent manufacturing and testing. Generate a comprehensive report that summarizes the selection process of the optimal solution, the design ideas for spatial optimization, and its simulation results. This report will provide a basis for the next steps of the project.

[0043] Step S4: performing full-cycle gene sequencing simulation based on the spatial optimization simulation framework, collecting gene sequencing simulation data, and performing noise suppression circuit design to obtain a noise suppression circuit strategy;

[0044] In this embodiment, in a spatially optimized chip simulation framework, a simulation environment suitable for full-cycle gene sequencing is configured. Use simulation software (such as COMSOL Multiphysics or Ansys) to set simulation conditions, including fluid properties, temperature, pressure, and electrical properties. Determine the key parameters required in the simulation process, such as sample concentration, flow rate, sequencing time, and probe sensitivity. Ensure that these parameters can accurately reflect the actual gene sequencing scenario. According to the optimized chip design, a full-cycle gene sequencing simulation model is constructed. The model should include all key components such as probe arrays, fluid channels, and noise sources to ensure consistency with actual applications. Set initial conditions and boundary conditions in the model to ensure that they meet experimental requirements. Set the inlet velocity and concentration of the fluid, as well as the input characteristics of the electrical signal. Run the full-cycle gene sequencing simulation and monitor the key parameters in the simulation process in real time, including fluid flow, probe response, and signal changes. The simulation time should cover the entire sequencing cycle to ensure the integrity of the data. Use appropriate simulation tools to record data during the sequencing process, such as electrical signal intensity, probe binding, and reaction time. These data will be used for subsequent analysis and optimization. After the simulation is completed, extract and organize the sequencing data, including the response signal, background noise, and signal strength of each probe. Ensure that the data is saved in a usable format (such as .csv or .txt) for subsequent analysis. Perform a preliminary analysis of the collected data and calculate key performance indicators such as signal-to-noise ratio, sequencing accuracy, and response time to evaluate the effectiveness of the simulation results. Based on the simulation data, identify the main noise sources generated during the gene sequencing process, including electronic noise, noise caused by fluid flow, and background interference. Record the characteristics and impact of each noise. Analyze the impact of noise on the sequencing signal and quantify the ratio of noise to signal (noise factor) to provide a basis for subsequent circuit design. Design the corresponding noise suppression circuit based on the identified noise source. Select a suitable circuit topology, such as a low-pass filter, band-pass filter, or differential amplifier, to effectively suppress noise in a specific frequency range. Use circuit design software (such as LTspice or Multisim) to perform circuit simulation and evaluate the noise suppression effect of the design. Ensure that parameters such as the operating voltage, power consumption, and frequency response of the actual circuit are taken into account in the design. Optimize the designed noise suppression circuit to ensure that it works well with other parts of the gene sequencing chip. Adjust circuit parameters, such as gain, cutoff frequency, etc., to achieve the best noise suppression effect. Integrate the noise suppression circuit with the overall design of the chip to ensure that the circuit can operate effectively in actual applications. Record the key parameters and performance indicators of the circuit design for subsequent testing and verification. Record the gene sequencing data, noise characteristics and noise suppression circuit design results obtained by simulation in detail to form a comprehensive report. The report should include data analysis, noise source characteristics, suppression circuit design scheme and its performance evaluation.By comparing the signal quality before and after noise suppression, the effectiveness of the noise suppression circuit in the actual sequencing process is analyzed to provide a basis for subsequent optimization.

[0045] Step S5: performing microfluidic response imbalance mining on gene sequencing simulation data and performing response imbalance compensation calculation to generate chip response imbalance compensation parameters;

[0046] In this embodiment, relevant data including fluid flow characteristics, probe response signals and sequencing results are extracted from the gene sequencing simulation results. Ensure the integrity and accuracy of the data and store them in a format that is easy to process (such as CSV or Excel). Preprocess the extracted data to remove noise and outliers to ensure the reliability of the analysis results. Use data cleaning tools (such as Python Pandas) for data processing to ensure data consistency. Statistical analysis methods and data mining techniques are applied to identify the response imbalance characteristics in the simulation data. This includes analyzing the changes in the response time, signal intensity and fluid flow velocity of different probes. Use visualization tools (such as Matplotlib or Seaborn) to draw a relationship between the response signal and the flow velocity to observe whether there is a systematic deviation or imbalance. This process will help identify the source of response imbalance. The identified imbalance features are quantitatively analyzed to calculate the response differences of different probes. Statistical indicators such as standard deviation and mean deviation are used to evaluate the degree of response imbalance. Record the performance parameters of each probe, including reaction time, signal intensity and fluid flow rate, to ensure that the necessary data support can be provided for subsequent compensation calculations. A compensation model is established based on the identified microfluidic response imbalance features. The model should consider the fluid dynamics, probe response characteristics and their interactions. Use mathematical modeling tools (such as MATLAB or Python SciPy) to establish equations to describe the relationship between noise, flow rate and probe response. Ensure that the model can accurately reflect the physical characteristics of the system. Use the established compensation model to calculate the compensation of the response imbalance. Find the optimal compensation parameter combination by adjusting the fluid flow rate, the activation time of the probe and the signal processing parameters. Use optimization algorithms (such as genetic algorithms or particle swarm optimization algorithms) to find the best compensation parameters to minimize the response imbalance of the system. Ensure that the optimal solution is found through multiple iterative calculations. Apply the calculated compensation parameters to the simulation model to perform verification tests on the response imbalance compensation. Record the probe response before and after compensation to evaluate the compensation effect. Use statistical analysis methods (such as t-test or variance analysis) to compare the results before and after compensation to verify the effectiveness of the compensation strategy. Ensure that the response imbalance is significantly improved after compensation. Organize the calculated chip response imbalance compensation parameters into a table, including the specific value of each compensation parameter and its corresponding influencing factors. Ensure that the parameters are operational and repeatable. Record the calculation process and verification results of the compensation parameters to form detailed technical documents. This will provide a reference for subsequent chip design and manufacturing.

[0047] Step S6: fine-tuning the final chip parameters based on the noise suppression circuit strategy and chip response imbalance compensation parameters, thereby obtaining the final chip framework.

[0048] In this embodiment, relevant data on noise suppression circuit strategies and chip response imbalance compensation parameters are collected and organized, including noise source characteristics, compensation parameter values, and noise suppression circuit design documents, and the final chip parameter fine-tuning goals are determined, including improving chip performance, reducing noise interference, and optimizing response balance. This step ensures that the direction of fine-tuning is clear, and the existing chip design is evaluated to analyze the problems existing in the existing design, whether the sensitivity, signal strength, and response time of the probe meet the experimental requirements, and use statistical analysis tools (such as SPSS or R) to analyze previous experimental data, evaluate whether the performance indicators of the current design meet the expected results, find out where improvements are needed, and integrate the designed noise suppression circuit scheme into the chip design, including the layout, connection, and interaction of the circuit with other components, using circuit design software (such as LTspice or Altium Designer) to simulate the working condition of the noise suppression circuit in the chip to ensure that the circuit can effectively reduce noise, perform performance tests on the circuit, evaluate the effect of the noise suppression circuit in the actual chip, record the voltage, current and signal output of the circuit when it is working to ensure that it meets the design requirements, and fine-tune the circuit parameters such as gain, filter frequency and cutoff frequency according to the test results to optimize the noise suppression effect, integrate the response imbalance compensation parameters calculated previously into the chip design, ensure that each compensation parameter is coordinated with the functional module of the chip, record the specific application location and function of each compensation parameter to verify its effect later, and use multi-physics simulation software (such as COMSOL Multiphysics) is used to simulate the performance of the chip with integrated compensation parameters, evaluate the performance of the chip under various working conditions, focus on key performance indicators such as signal strength, response time and fluid flow characteristics, ensure that these indicators meet the expected goals, formulate the final chip parameter fine-tuning strategy according to the effect of the noise suppression circuit and the application effect of the compensation parameters, which includes adjusting the probe position, fluid channel size and circuit parameters, determine the priority of each adjustment, sort them according to the impact on performance, ensure that the fine-tuning process is efficient and effective, implement the fine-tuning strategy, gradually adjust the various parameters of the chip, perform performance tests after each adjustment, record the changes, ensure that each step of the adjustment has clear goals and effects, collect feedback data, analyze the gap between the results after fine-tuning and the expected goals, make further adjustments when necessary, integrate the fine-tuned parameters into the final chip design, generate the final chip framework, ensure that the function and position of each component in the framework are verified and optimized, and conduct comprehensive verification tests, including electrical performance, fluid dynamics characteristics and response speed, to ensure that the final design meets all experimental requirements.

[0049] In this embodiment, refer to Figure 2, is a flowchart of detailed implementation steps of step S1. In this embodiment, the detailed implementation steps of step S1 include:

[0050] Step S11: obtaining an initial design drawing of a gene sequencing chip; performing visual identification of chip interfaces on the initial design drawing, and marking multiple chip interfaces;

[0051] Step S12: Performing physical connection circuit analysis on the initial design drawing to extract all connection circuits of the chip;

[0052] Step S13: performing circuit topology analysis on all the connection circuits of the chip, thereby generating circuit topology data inside the chip;

[0053] Step S14: performing microfluidic channel identification on the initial design drawing to extract multiple microfluidic channels;

[0054] Step S15: performing channel spatial distribution analysis on a plurality of microfluidic channels to obtain microfluidic channel spatial distribution characteristics;

[0055] Step S16: Design a multi-level chip framework for multiple chip interfaces, chip internal circuit topology data, and microfluidic channel spatial distribution characteristics, thereby constructing a multi-level chip simulation framework.

[0056] In this embodiment, the initial design drawings of the gene sequencing chip are obtained from the chip design team or related databases. The drawings should be in high-resolution electronic file formats, such as PDF, DWG, or DXF, to facilitate subsequent processing. Ensure that the drawings contain all necessary details, including chip size, interface location, microfluidic channel layout, and circuit connection, etc. Use graphics processing software (such as Adobe Illustrator or AutoCAD) to pre-process the obtained drawings, clean up unnecessary details, highlight important parts such as interfaces and channels, convert the drawings into a standard format to facilitate subsequent visual recognition processing, set visual recognition parameters, such as recognition accuracy and threshold, to ensure that multiple chip interfaces can be accurately marked in subsequent steps, prepare the required tools and software, such as OpenCV or TensorFlow, implement the visual recognition algorithm, and use circuit analysis software (such as Altium The software should support the import and editing of circuit diagrams for subsequent analysis. Ensure that the software contains the necessary circuit component library to identify the electrical connections in the drawings. The software should automatically identify all connecting lines and electrical components in the design drawings and generate a preliminary circuit connection diagram. Use algorithms to analyze the circuit layout, identify the connection relationships between connection points and components, ensure that all circuit connections can be accurately identified, extract all circuit connection data, including the type, position and connection relationship of circuit components, form a circuit connection database, record circuit parameters (such as resistance, capacitance, etc.), and provide basic data for subsequent analysis. Based on the extracted circuit connection data, define the topological structure of the circuit, including nodes (components) and edges (connections), determine the input and output of each node, and form a mathematical model of the circuit diagram. Use graph theory methods (such as adjacency matrix or adjacency list) to represent the topological structure of the circuit for subsequent analysis. Apply topological analysis tools (such as MATLAB or Py thon) to analyze the circuit, identify important features in the circuit, such as loops, branches, and critical paths, generate circuit topology data, including the number of nodes, number of connections, and topological features (such as degree, connectivity, etc.), organize the analysis results into a report, including the circuit topology diagram and related data, use visualization tools to display the circuit topology features for easy understanding and communication, store the topology data in the database to support subsequent design and analysis work, use image processing software (such as MATLAB or OpenCV) to identify microfluidic channels on the initial design drawings, ensure the clarity and contrast of the drawings to improve recognition accuracy, set recognition parameters, such as edge detection thresholds and morphological processing, to ensure that the shape and position of the channel can be accurately identified, run the image processing algorithm, and automatically identify the microfluidic channels in the drawings. The recognition process includes edge detection, shape analysis, and channel marking. The identified channel position, size, and shape features are recorded to form a data set of microfluidic channels.Import the identified microfluidic channel data into spatial analysis software (such as ArcGIS or QGIS) for spatial distribution analysis, ensure data format compatibility for subsequent processing, set the coordinate system and spatial analysis parameters to ensure the accuracy of the analysis, apply spatial statistical analysis methods (such as heat map analysis or cluster analysis) to analyze the spatial distribution of microfluidic channels, identify the distribution pattern of channels and their dense areas, record the spatial distribution characteristics of channels, including the relative position, spacing and connection relationship of channels, and form a spatial distribution report, use visualization tools to generate channel distribution diagrams, and display the spatial layout of microfluidic channels. Ensure that the diagrams are clear and easy to understand for reporting to relevant personnel, explain the analysis results, identify potential design problems, such as channels that are too dense or have unreasonable layouts, and make suggestions for improvement, integrate multiple data sources, including Chip interface data, circuit topology and spatial distribution characteristics of microfluidic channels, determine the design requirements of the multi-level chip framework, determine the key parameters of the framework design, such as the number of layers, the function of each layer and the required connection method, use CAD software (such as SolidWorks or AutoCAD) to design the multi-level chip framework, design the specific layout and connection method of each layer based on the preliminary analysis results, and ensure that the interfaces and channels between different levels are effectively connected to meet functional requirements during the design process. Verify the designed multi-level chip framework to ensure that it meets the design specifications and functional requirements, use simulation software (such as ANSYS or COMSOL) for performance analysis, evaluate its performance in actual applications, and make necessary adjustments and optimizations based on the simulation results to ensure the rationality and effectiveness of the design.

[0057] In this embodiment, the specific steps of step S16 are:

[0058] Performing chip geometry calculation on the initial design drawing to extract chip geometry parameters;

[0059] Perform position calculation on multiple chip interfaces one by one to generate the position coordinates of each chip interface;

[0060] Designing the chip physical layer framework based on the position coordinates of each chip interface and the chip geometric parameters to obtain the chip physical layer framework;

[0061] Identify chip electrodes and calculate the position coordinates of chip electrodes;

[0062] Performing circuit signal transmission simulation on all connection circuits of the chip based on the position coordinates of the chip electrodes to generate chip internal row circuit signal transmission data;

[0063] Based on the internal row circuit signal transmission data of the chip, the electronic layer framework is designed for the internal circuit topology data of the chip to obtain the chip electronic layer framework;

[0064] Performing fluid flow path analysis on the spatial distribution characteristics of the microfluidic channel to generate a fluid flow path of the microfluidic channel;

[0065] Performing microfluidic fluid sequencing dynamics evolution according to the microfluidic channel fluid flow path to generate fluid sequencing dynamics evolution process data;

[0066] Designing the fluid layer framework of multiple microfluidic channels based on the fluid sequencing dynamics evolution process data to obtain the chip fluid layer framework;

[0067] A multi-level framework integration simulation is performed based on the chip physical layer framework, chip electronic layer framework and chip fluid layer framework to construct a multi-level chip simulation framework.

[0068] In this embodiment, geometric information is extracted from the chip design drawings, including the total area, shape, boundary length and each characteristic size of the chip. Graphics processing software (such as AutoCAD or MATLAB) is used to import the design drawings and perform image analysis. The geometric center, boundary points and key features of the chip (such as the size of electrodes, interfaces and microfluidic channels) are determined, and the relevant parameters are calculated using geometric formulas. The area of ​​the chip is calculated by the polygon area formula, and the side length is calculated by the point coordinate distance formula. The extracted geometric parameters are recorded in a spreadsheet or database, including position, size and shape features. Parameter identifiers are set for subsequent reference and analysis. These geometric parameters provide basic data for subsequent framework design and interface positioning. Multiple chip interface positions on the design drawings are identified by visual recognition techniques (such as template matching or edge detection). The drawings are analyzed using image processing tools (such as OpenCV) to locate the geometric center of each interface. According to the marks and features in the design drawing, the relative position coordinates of each interface are extracted. Calibration is performed using the image coordinate system to convert it into actual physical coordinates. Record the position coordinates of each interface into the database, ensure that each interface has a unique identifier and contains its relative position (such as x, y coordinates) and type information (such as input, output). These coordinates will be used for the subsequent chip physical layer frame design and signal transmission simulation. Combine the geometric morphology parameters and interface position coordinates, and use CAD software (such as SolidWorks or AutoCAD) to perform preliminary design of the physical layer frame. Set the design parameters, including the thickness, material and mechanical properties of the frame. The design should ensure that all interface positions match the geometric morphology parameters to form a reasonable structure. Implement three-dimensional modeling of the frame in the design software to ensure that the frame can effectively support the various parts of the chip. Record the connection method of each interface and its relationship with the frame. Perform mechanical analysis (such as ANSYS) to evaluate the strength and stability of the physical layer frame to ensure that it meets the requirements of use. Use image processing algorithms (such as Hough transform or threshold segmentation) to identify electrodes on the design drawings. Ensure that the shape and size characteristics of the electrode can be accurately identified. Set the identification parameters to optimize the electrode detection process and reduce the false recognition rate. Through the identification process, calculate the relative position coordinates of each electrode and record them in the database. Make sure each electrode has a unique identifier and contains its location coordinates (x, y) and type information (such as anode, cathode). These electrode coordinates will be used for subsequent circuit signal transmission simulation. Build a circuit signal transmission model based on the electrode location information and circuit connection data. Use circuit simulation software (such as SPICE or MATLAB Simulink) to perform signal transmission analysis. Define the component parameters of the circuit (such as resistance, capacitance, inductance), and enter the electrode location and connection information. Run the signal transmission simulation to analyze the transmission characteristics of the electrical signal in the circuit, including delay, attenuation, and waveform changes.Record the simulation results and generate circuit signal transmission data, including the input and output signal characteristics, delay and amplitude of each electrode. Based on the circuit signal transmission data, analyze the topological structure of the circuit and identify key nodes and connection relationships. Apply graph theory methods to generate the topological model of the circuit. Determine the position of each component in the electronic layer framework and its connection method to ensure the rationality and effectiveness of the framework. Use CAD software to design the electronic layer framework to ensure that the framework can accommodate circuit components and achieve effective connection. Set design parameters, including layer thickness, wire width, etc. Perform electrical performance simulation to ensure that the design meets the requirements of signal transmission and electrical characteristics. Export the design results of the electronic layer framework and record key parameters to support subsequent integrated simulation and manufacturing processes. Use fluid mechanics software (such as COMSOL Multiphysics or ANSYS Fluent) to analyze the flow path of the microfluidic channel. Input the geometric characteristics of the channel and fluid properties (such as viscosity, density). Set flow conditions (such as flow rate, pressure) to simulate the flow behavior of the fluid in the channel. Run the fluid flow simulation to observe the flow path, velocity distribution and pressure changes of the fluid in the channel. Record key data such as flow pattern and dead zone. Generate flow path data, including the position and velocity characteristics of the fluid at different time points. Establish a dynamic model for microfluidic fluid sequencing based on the fluid flow path data. Use fluid dynamics equations (such as the Navier-Stokes equations) to describe the movement of the fluid in the channel. Set model parameters, including fluid flow rate, channel size, and boundary conditions, to perform dynamic evolution simulations. Run dynamic evolution simulations to analyze the behavior of the fluid in the microfluidic channel and observe the dynamic changes and reaction characteristics of the fluid during sequencing. Record key data during the evolution process, such as concentration distribution, reaction rate, and time evolution characteristics. Integrate the fluid sequencing dynamic evolution data to design the fluid layer framework to ensure that it can support the effective transmission and reaction of the fluid. Use CAD software for preliminary design. Set framework design parameters, such as channel size, interlayer spacing, and material properties, to meet the fluid flow characteristics. Implement three-dimensional modeling of the fluid layer framework in the design software to ensure that the framework can effectively support the flow and sequencing process of the fluid. Perform fluid dynamics simulations to evaluate the performance of the fluid layer framework and ensure its effectiveness in practical applications. Integrate the physical layer framework, electronic layer framework, and fluid layer framework to establish an integrated simulation model of a multi-level chip. Ensure that the interfaces and connections between layers are clear. Use multi-physics simulation software (such as COMSOL Multiphysics) for integrated simulation and set the corresponding physical field models (such as electric field, flow field, thermal field). Run integrated simulations of multi-level frameworks to observe the interactions between layers and evaluate the performance of the chip under actual working conditions. Record simulation results, including electrical performance, fluid dynamics characteristics, and thermal characteristics to ensure that the design meets functional requirements. Analyze simulation results to identify potential design problems and room for improvement.Adjust design parameters based on simulation feedback to optimize the performance of the multi-level chip framework. Finally, generate documents and reports of the multi-level chip simulation framework to provide a basis for subsequent manufacturing and application.

[0069] In this embodiment, refer to Figure 3 , is a flowchart of detailed implementation steps of step S2. In this embodiment, the detailed implementation steps of step S2 include:

[0070] Step S21: performing surface DNA probe morphology analysis based on the gene sequencing chip design drawings to obtain probe array morphology parameters;

[0071] Step S22: performing arrangement density calculation on the probe array morphological parameters to generate a probe array arrangement density value;

[0072] Step S23: performing a probe array arrangement multi-parameter design according to the probe array arrangement density value to obtain a plurality of probe array arrangement parameters;

[0073] Step S24: performing feasibility adjustment of channel distribution according to the plurality of microfluidic channels to obtain a plurality of feasibility adjusted channel distribution data;

[0074] Step S25: performing multi-parameter adjustment optimization on multiple probe array arrangement parameters and multiple feasible adjustment channel distribution data, thereby obtaining multiple chip space arrangement solutions.

[0075] In this embodiment, the relevant data of the probe array, including the position, shape and size of the probe, are extracted from the gene sequencing chip design drawings. Ensure that the drawings are in high-resolution format for subsequent analysis. Use image processing software (such as MATLAB or ImageJ) to preprocess the drawings, remove background noise, and highlight the characteristics of the probe array. Morphological analysis methods (such as edge detection and shape analysis) are used to identify the shape and arrangement of the probes. Image processing algorithms are used to extract the geometric features of the probes, such as length, width, spacing and angle. The morphological parameters of the probe array are calculated, such as the average diameter of the probe, the arrangement spacing, and the overall shape of the array (such as rectangle, circle, etc.). The extracted probe array morphological parameters are recorded in a database for subsequent calculation and design use. Ensure that each parameter has a detailed description, including measurement units and calculation methods. Analyze the distribution characteristics of the probe array morphological parameters and evaluate their potential impact on subsequent experiments, such as the binding efficiency and sensitivity of the probes. According to the morphological parameters of the probe array, set the calculation formula for the arrangement density. The arrangement density is usually defined as the number of probes per unit area, arrangement density = number of probes / array area, determine the calculation method of the number of probes and array area, and ensure the accuracy of the data. Input the number of probes and the area data of the array into the calculation model, and run the calculation program (Python, MATLAB, etc. can be used) to calculate the arrangement density. Record the calculation results, generate the arrangement density value of the probe array, and evaluate the impact of the arrangement density under different conditions on the experimental results. Analyze the distribution of the arrangement density values ​​and identify areas with higher or lower density. Adjust the arrangement density of the probes according to the experimental requirements to optimize the sequencing effect. Verify the reliability of the calculation results and ensure the accuracy of the model by comparing with the experimental data. According to the arrangement density value of the probe array, determine the requirements for multi-parameter design, including the arrangement mode, spacing, direction, etc. of the probes. Set the design goals, such as improving the binding efficiency or enhancing the detection sensitivity. Evaluate the impact of different arrangement parameters on the experimental results to ensure that the design scheme meets the actual application requirements. Use design software (such as AutoCAD or SolidWorks) to perform multi-parameter design of the probe array. Set the arrangement spacing, arrangement mode (such as matrix, linear, etc.) of the probes and their relationship with the microfluidic channel. Generate multiple probe array arrangement parameters, such as different spacing, arrangement angles and quantities, and record the relevant parameters of each scheme. Evaluate the generated probe array layout scheme, use simulation software (such as COMSOL Multiphysics) to perform performance simulation, and evaluate the impact of different layouts on probe binding efficiency. According to the simulation results, adjust and optimize the probe layout parameters to ensure the rationality and effectiveness of the design scheme. Collect geometric features and fluid dynamics data of multiple microfluidic channels, and analyze their spatial layout and flow paths. Evaluate the impact of channel distribution on the probe array layout.Use fluid dynamics software (such as ANSYS Fluent) to simulate the flow of fluid in the channel to identify potential flow problems. According to the channel distribution characteristics, propose feasible adjustment plans, including channel rearrangement, width adjustment, and spacing optimization. Ensure that the channel layout can support the function of the probe array. Perform calculations and simulations for multiple adjustment plans and evaluate the performance of each plan in terms of flow efficiency and probe binding effect. According to multiple probe array layout parameters and channel distribution data, set the goals of multi-parameter optimization, including improving binding efficiency, reducing background signals, and optimizing fluid flow paths. Determine the selection of optimization algorithms, such as genetic algorithms, particle swarm optimization, etc., to achieve efficient parameter adjustment. Run the optimization algorithm to perform multi-parameter adjustments on the probe array layout parameters and channel distribution to achieve the best layout. Use simulation software (such as MATLAB or Simulink) to perform performance evaluation to ensure that the design scheme meets the expected experimental results. Record the results of each optimization and generate the final probe array and channel layout plan. Experimentally verify the final multiple chip space layout plans to ensure their effectiveness and reliability in practical applications. Make necessary adjustments and optimizations based on the experimental results. Finally, a complete design document is generated, including probe array layout parameters, channel distribution data and optimization results, providing a basis for subsequent chip manufacturing and application.

[0076] In this embodiment, refer to Figure 4 , is a flowchart of detailed implementation steps of step S3. In this embodiment, the detailed implementation steps of step S3 include:

[0077] Step S31: Calculating the component volume space of each scheme based on multiple chip space layout schemes, thereby obtaining the component volume space parameters of each scheme;

[0078] Step S32: Calculate the total volume of the chip substrate according to the gene sequencing chip design drawing to generate the total available volume space;

[0079] Step S33: Calculate the overall space utilization of the component volume space parameters of each solution according to the total available volume space, so as to generate the chip space utilization of each solution;

[0080] Step S34: extracting the optimal chip space layout solution based on the chip space utilization of each solution;

[0081] Step S35: optimizing the spatial arrangement of the multi-level chip simulation framework according to the optimal chip spatial arrangement solution to obtain a spatially optimized simulation framework.

[0082] In this embodiment, the geometric parameters of each component are determined, including length, width, height or radius, which are usually obtained on the design drawings. For each chip space layout scheme, the volume of its components is calculated one by one. Use a programming language (such as Python or MATLAB) to write a calculation script to automate the volume calculation process to ensure efficiency and accuracy. During the calculation process, the volume space parameters of each component in each scheme are recorded, including the type, size and total volume of each component. The calculation results are stored in a database to ensure that the component volume space parameters of each scheme have a detailed description and identification. Generate a report to summarize the volume calculation results of all schemes. Analyze the spatial distribution of component volumes of different schemes, identify components with larger volumes, and evaluate their impact on the overall spatial layout. According to the gene sequencing chip design drawings, determine the shape and size of the chip substrate. Generally, the substrate is regarded as a cuboid or other geometric shape, and the length, width, height and other parameters of the substrate need to be determined. Use the size information provided in the design drawings to calculate the total volume to ensure the accuracy and consistency of the calculation process. Use Excel or MATLAB for calculation. Record the calculation results, generate the total volume parameters of the substrate, and ensure that the results have units (such as cubic millimeters). Space utilization is defined as the ratio of the sum of the component volume space to the available volume of the substrate. Space utilization = ∑ component volume / total substrate volume × 100%. For each solution, calculate the sum of its component volumes and compare it with the total volume of the substrate. Use programming language to write an automated calculation script to ensure efficiency and accuracy. Record the space utilization of each solution and ensure that the result has units (%). Define the criteria for the optimal chip space layout solution, usually the solution with the highest space utilization. Set a threshold to ensure that the extracted solution meets the experimental and design requirements. Among all the solutions, evaluate the space utilization one by one and identify the solution with the highest utilization. Use a sorting algorithm (such as quick sort or merge sort) to sort the space utilization to ensure the efficiency of the extraction process. Record the detailed parameters of the optimal solution, including component layout, volume calculation, and utilization data. Verify whether the extracted optimal solution meets other design criteria, such as manufacturability, stability, etc. Ensure that the selected solution is feasible in practical applications. Record the detailed information of the optimal solution in the database to provide a basis for subsequent space optimization simulation. According to the optimal chip spatial layout solution, analyze the spatial layout requirements of the multi-level chip simulation framework and set optimization goals, such as improving component accessibility and reducing signal interference. Identify potential problems in the current framework layout, such as space waste and insufficient component spacing. Use CAD software (such as SolidWorks or AutoCAD) to optimize the spatial layout of the multi-level chip simulation framework. According to the parameters of the optimal solution, adjust the component position and layout to achieve more efficient space utilization. Perform multiple iterative optimizations and evaluate the impact of each optimization on the overall layout to ensure that the final design meets all technical requirements.Perform simulation analysis on the optimized frame and evaluate its performance under actual working conditions using multi-physics simulation software (such as ANSYS or COMSOL). Record the optimized spatial layout parameters and generate complete design documentation to ensure that all design details can be tracked and verified.

[0083] In this embodiment, step S4 includes the following steps:

[0084] Step S41: performing full-cycle gene sequencing simulation based on the spatial optimization simulation framework and collecting gene sequencing simulation data;

[0085] Step S42: performing chip sequencing sound signal analysis on the gene sequencing simulation data to extract the sound signal of the gene sequencing process;

[0086] Step S43: performing sequencing noise identification on the sound signal of the gene sequencing process to generate a gene sequencing noise signal;

[0087] Step S44: tracing the noise source of the gene sequencing noise signal to obtain the potential source of the sequencing noise;

[0088] Step S45: performing noise fluctuation evolution on potential sources of sequencing noise, thereby generating a noise fluctuation evolution law;

[0089] Step S46: Design a noise suppression circuit according to the noise fluctuation evolution rule, so as to obtain a noise suppression circuit strategy.

[0090] In this embodiment, the optimized multi-layer chip simulation framework is used to set the simulation model of gene sequencing. Simulation parameters are defined, including fluid flow rate, temperature, probe binding efficiency, etc. A three-dimensional simulation model can be constructed using software such as COMSOL Multiphysics or ANSYS Fluent. The cycle of gene sequencing is determined, and the time parameters of each stage are set from sample preparation, mixed reaction to signal detection to fully reflect the sequencing process. During the simulation process, data collection points are set to record key data such as molecular concentration, reaction rate, temperature change, and electrical signal. Use the built-in data recording function or external data acquisition system for real-time monitoring. Run the simulation to observe the dynamic changes of the entire sequencing cycle to ensure the integrity and accuracy of data collection. The gene sequencing data collected during the simulation process are sorted and recorded to ensure that each data point has a timestamp and related parameter identification. Generate a data report for subsequent analysis. Analyze the simulation results to ensure that they meet the expected gene sequencing effect and evaluate the key factors in the sequencing process, such as the impact of reaction time and temperature on the results. While the simulation framework is running, a sound sensor (such as a microphone or a piezoelectric sensor) is set to collect the sound signal of the chip during the sequencing process. Ensure that the sensitivity and frequency response of the sensor meet the experimental requirements. Record the sound signal data, including parameters such as sampling frequency, sampling time, and sound intensity, to ensure the accuracy and completeness of the data. Use signal processing software (such as MATLAB or Python library SciPy) to analyze the collected sound signals, and apply methods such as Fourier transform (FFT) to convert the time domain signal into a frequency domain signal in order to identify the frequency components of the sound. Extract the sound features related to the gene sequencing process, such as signal intensity, frequency spectrum, and time characteristics, and generate a sound signal analysis report. Record the extracted sound signal features in the database, ensuring that each signal feature has a detailed description and identification. Analyze the correlation between the sound signal and the sequencing process and evaluate its feasibility in practical applications. Verify the reliability of the sound signal analysis results and ensure the accuracy of the analysis method by comparing with known standards. Define the standards for sequencing noise based on the results of the sound signal analysis. Noise is usually defined as a frequency component that is not related to the gene sequencing signal. The frequency range and typical characteristics of the noise need to be determined. Set the standards for the noise identification algorithm, such as the signal-to-noise ratio (SNR) threshold, to ensure that the signal and noise can be effectively distinguished. Use signal processing tools (such as MATLAB or Python) to analyze the sound signal and identify the noise part by setting thresholds and frequency filters. Use filters (such as low-pass, high-pass, or band-pass filters) to remove unnecessary frequency components. Record the characteristics of the identified noise signal, including frequency, amplitude, and duration, and generate a noise signal report. Verify the accuracy of the noise identification results and ensure the effectiveness of the identification method by comparing with known noise sources.Record the identified noise signals in the database, ensuring that each noise feature is described and identified in detail to provide a basis for subsequent analysis. Analyze the identified noise signals to determine the characteristics and sources of the noise. Use spectrum analysis tools (such as FFT) to identify the frequency characteristics and patterns of the noise and evaluate its relationship with the sequencing process. Combined with the experimental settings, determine the physical location of the noise source, such as fluid flow, equipment vibration, or external interference. Use time series analysis methods to track the changes in noise signals and identify potential fluctuations in noise sources. Statistical methods such as correlation analysis can be used to evaluate the relationship between noise and various aspects of the sequencing process. Record the results of noise source tracing, including the characteristics, location, and impact of the noise source, and generate a noise source analysis report. Verify the reliability of the noise source tracing results, and compare the experimental data with the noise source characteristics to ensure the accuracy of the tracing analysis. Record the tracing results in the database, ensuring that each noise source is described and identified in detail to provide a basis for subsequent noise suppression strategies. Establish a mathematical model for the evolution of noise fluctuations to describe the law of change of noise sources over time. Random process models (such as white noise models or Gaussian noise models) can be used to simulate noise fluctuations. Determine the parameters of the model, including noise amplitude, frequency range, and evolution time, to ensure that the model can accurately reflect the dynamic changes of noise. Use numerical simulation tools (such as MATLAB or Simulink) to simulate noise fluctuations, generate time series data of noise fluctuations, and observe the evolution of noise over time. Record the simulation results, including noise amplitude, frequency change, and time characteristics, and generate a noise fluctuation evolution report. Analyze the noise fluctuation evolution results, identify the laws and trends of noise fluctuations, and evaluate their impact on the gene sequencing process. Record the results of noise fluctuation evolution in a database, ensuring that each evolution feature is described and identified in detail to provide a basis for subsequent noise suppression strategies. According to the noise fluctuation evolution law, determine the design requirements of the noise suppression circuit and set design goals, such as effectively reducing the noise amplitude and improving the signal-to-noise ratio. Select appropriate noise suppression methods, such as active noise control or passive noise suppression, and determine the required circuit components (such as filters, amplifiers, etc.). Use circuit design software (such as LTspice or Proteus) to design the noise suppression circuit, draw a circuit diagram, and ensure that the circuit layout is reasonable and meets the design standards. Perform circuit simulation to evaluate the performance of the circuit under different working conditions to ensure that it can effectively suppress noise.

[0091] In this embodiment, step S5 includes the following steps:

[0092] Step S51: Calculate the global circuit unit state parameters for the gene sequencing simulation data, and extract the electrical state parameters of each chip unit;

[0093] Step S52: performing inter-unit parameter difference analysis on the electrical state parameters of each chip unit, and extracting inter-unit parameter difference data;

[0094] Step S53: identifying circuit imbalance regions of the spatial optimization simulation framework based on inter-unit parameter difference data, and extracting circuit imbalance regions of the simulation framework;

[0095] Step S54: performing microfluidic response imbalance mining on gene sequencing simulation data, thereby marking response imbalance microfluidic channels;

[0096] Step S55: performing response imbalance compensation calculation based on the simulation framework circuit imbalance area and the response imbalance microfluidic channel, thereby generating chip response imbalance compensation parameters.

[0097] In this embodiment, for each chip unit, electrical state parameters are defined, including voltage, current, power, and impedance. These parameters are key indicators for evaluating circuit performance and can reflect the working state of each unit. According to the gene sequencing simulation data, the formula for parameter calculation is set. The power is calculated by the formula P=U×I, where U is voltage and I is current. Use a programming language (such as Python or MATLAB) to extract necessary information from the simulation data and automate the calculation process of the electrical state parameters. Set effective data screening conditions to ensure that only relevant units are calculated. During the calculation process, the electrical state parameters of each chip unit are recorded, including timestamps and unit identifications, for subsequent analysis. Verify the accuracy of the calculation results and ensure that the calculation of each electrical parameter meets expectations by comparing with known standards. Use experimental data for cross-validation. The calculation results are stored in a database to provide basic data for subsequent analysis of inter-unit parameter differences. Select an appropriate statistical analysis method (such as analysis of variance ANOVA or t-test) to evaluate the differences in electrical state parameters between units. Set a significance level (such as 0.05) to ensure the scientific nature of the analysis results. Determine the analysis goal, such as identifying the degree of variation in voltage or current between different chip units. Input the electrical state parameters of each chip unit into the analysis software (such as R or Python's SciPy library) to perform parameter difference analysis between units. Calculate the mean, standard deviation, and difference index of the parameters. Record the analysis results and pay attention to the units with significant parameter differences, especially those that affect gene sequencing performance. Define the criteria for circuit imbalance regions based on the parameter difference data between units. Imbalance regions are usually manifested as units where the electrical state parameters deviate significantly from the mean value, and thresholds need to be set to identify these regions. Determine the evaluation index for imbalance regions, such as whether the standard deviation of voltage or current exceeds the set threshold. Use programming tools (such as Python) to analyze the electrical state parameters and identify circuit imbalance regions according to the defined criteria. Generate a graphical display to facilitate intuitive identification of imbalance regions. Record the location information and parameter characteristics of the imbalance regions to ensure that each imbalance region is described in detail. Record the identified circuit imbalance regions in the database to provide basic data for subsequent microfluidic response imbalance mining. Analyze the characteristics of the imbalance regions, evaluate their potential impact on gene sequencing performance, and generate an imbalance region analysis report. Define the criteria for microfluidic response imbalance, which is usually manifested as the inhomogeneity of parameters such as fluid flow rate, pressure or temperature in different channels. Set corresponding thresholds to identify imbalance phenomena. Determine the evaluation indicators of response imbalance, such as whether the standard deviation of flow rate exceeds a preset threshold. Use data analysis tools (such as MATLAB or Python) to mine gene sequencing simulation data to identify microfluidic channels with response imbalance. Apply methods such as cluster analysis to detect outliers in the data.Record the characteristics of the imbalanced channels, including parameters such as flow rate, pressure, and temperature, and ensure that each imbalanced channel has a detailed description. Verify the accuracy of the imbalance mining results and ensure the effectiveness of the identification method by comparing with experimental data. Record the marked response imbalance microfluidic channels in the database to provide a basis for subsequent response imbalance compensation calculations. Analyze the needs of compensation calculations based on the characteristics of the circuit imbalance area and the response imbalance microfluidic channels. Determine the current or flow rate that needs to be adjusted to achieve a balanced state. Set compensation goals to ensure that the compensation scheme can effectively improve the working performance of the chip. Use programming tools (such as MATLAB or Simulink) to perform compensation calculations and establish a mathematical model to solve the required compensation parameters. Use an iterative algorithm (such as Newton's method) to solve. Record the calculation results, including the values ​​of the compensation parameters and adjustment suggestions, and ensure that each parameter has a detailed description. Verify the effectiveness of the compensation calculation results and evaluate the performance of the compensation scheme in actual applications through simulation tests. Ensure that the compensation parameters can effectively solve the imbalance problem. Record the generated chip response imbalance compensation parameters in the database to provide a basis for subsequent experimental optimization.

[0098] In this embodiment, the specific steps of step S54 are:

[0099] Perform microfluidic channel response analysis on gene sequencing simulation data to extract microfluidic channel response data;

[0100] Perform fluid flow feature recognition on microfluidic channel response data and extract fluid flow features of each channel;

[0101] Based on the fluid flow characteristics of each channel, channel resistance anomaly is identified and abnormal resistance channels are extracted;

[0102] Perform temperature distribution analysis on each channel of the microfluidic channel response data to obtain temperature distribution simulation data for each channel;

[0103] Perform thermal effect imbalance analysis based on the temperature distribution simulation data of each channel to identify the thermal effect imbalance channel;

[0104] Microfluidic response imbalance mining is carried out based on abnormal resistance channels and thermal effect imbalance channels, thereby marking response imbalance microfluidic channels.

[0105] In this embodiment, the response data of the microfluidic channel is extracted from the gene sequencing simulation to ensure that the data has high resolution and integrity. The response data generally includes flow rate, pressure, temperature and other relevant physical parameters. The extracted data is preprocessed using data processing software (such as MATLAB or Python), including denoising, normalization and data cleaning, to ensure the accuracy of subsequent analysis. The response characteristics of the microfluidic channel are analyzed, the fluid flow rate and pressure change of each channel are calculated, and analysis indicators are set, including the average value, maximum value and pressure fluctuation range of the flow rate. A chart of the response data is generated by a visualization tool (such as Matplotlib or Seaborn) to facilitate direct analysis. Observe the performance of the channel and determine the definition of fluid flow characteristics, including velocity distribution, shear rate, turbulence degree, etc. Use fluid dynamics analysis tools (such as OpenFOAM or COMSOL) to simulate the flow characteristics of each channel, extract the distribution of velocity field and pressure field, process the simulation results, calculate the flow characteristic parameters of each channel, such as average velocity, flow mode (laminar or turbulent), etc. Use statistical analysis methods (such as regression analysis) to evaluate the correlation of flow characteristics, combine with visualization tools to display the flow characteristic distribution of each channel to help identify potential problem areas, and calculate the fluid resistance of each channel based on the flow characteristic data. The formula 𝑅=Δ𝑃 / 𝑄 is usually used, where R is the resistance, ΔP is the pressure difference, and Q is the pressure difference. For flow, determine the standard of abnormal resistance, set thresholds to identify channels whose resistance deviates significantly from the normal range, use programming tools (such as MATLAB or Python) to analyze the resistance data of each channel, identify channels with abnormal resistance, apply statistical methods (such as Z-score analysis) to determine whether the resistance exceeds the set threshold, record the characteristics of channels with abnormal resistance, including resistance value, flow rate and pressure data, for subsequent analysis, extract temperature distribution data of each microfluidic channel from gene sequencing simulation data, ensure high resolution of data, response data usually includes records of temperature changes over time, use data processing software (such as MATLAB or Python) to preprocess temperature data, including denoising and interpolation processing, to ensure the accuracy of temperature data To ensure accuracy, analyze the temperature distribution characteristics of each channel, calculate the average, maximum and fluctuation range of the temperature, set corresponding analysis indicators to evaluate the impact of temperature changes on flow characteristics, use visualization tools (such as Matplotlib) to generate a heat map of the temperature distribution to help intuitively understand the temperature distribution, determine the standard for thermal effect imbalance, which is usually manifested as uneven temperature distribution, set thresholds to identify channels where the temperature deviates significantly from the normal range, set evaluation indicators such as the standard deviation of temperature or the temperature gradient according to the experimental parameters, use data analysis tools (such as MATLAB or Python) to analyze the temperature data of each channel, identify channels with thermal effect imbalance, and apply statistical methods (such as variance analysis) to evaluate the uniformity of temperature distribution.Record the characteristics of the thermal effect imbalance channel, including temperature values ​​and distribution, for subsequent analysis. Record the identified thermal effect imbalance channel in the database to ensure that each imbalance channel has a detailed description. Verify the accuracy of the analysis results. Ensure the reliability of the method by comparing with experimental data. Combine the characteristics of abnormal resistance channels and thermal effect imbalance channels to define the criteria for microfluidic response imbalance. Imbalance is usually manifested as significant non-uniformity in flow rate, temperature, and pressure. Set corresponding evaluation indicators to identify channels that respond to imbalance. Use programming tools (such as MATLAB or Python) to analyze abnormal resistance channels and thermal effect imbalance channels to identify microfluidic channels that respond to imbalance. Apply cluster analysis or other machine learning methods to detect abnormal patterns in the data. Record the characteristics of imbalance channels, including flow rate, temperature, and pressure, to ensure that each imbalance channel has a detailed description. ,

[0106] In this embodiment, step S6 includes the following steps:

[0107] Step S61: optimizing the chip response imbalance compensation for the spatial optimization simulation framework based on the noise suppression circuit strategy and the chip response imbalance compensation parameters, thereby generating a response imbalance compensation simulation framework;

[0108] Step S62: performing secondary sequencing simulation on the response imbalance compensation simulation framework, and extracting secondary sequencing simulation data;

[0109] Step S63: Calculate the gene test accuracy of the secondary sequencing simulation data to generate chip test accuracy;

[0110] Step S64: quantifying the channel fluid flow rate of the secondary sequencing simulation data to generate microfluidic channel flow parameters;

[0111] Step S65: Calculating the sequencing response speed of the secondary sequencing simulation data to generate a chip sequencing response speed;

[0112] Step S66: Perform comprehensive performance evaluation based on the chip sequencing response speed, microfluidic channel flow parameters and chip test accuracy, so as to obtain the comprehensive performance of the simulated chip;

[0113] Step S67: fine-tuning the final chip parameters of the response imbalance compensation simulation framework based on the comprehensive performance of the simulated chip, thereby obtaining the final chip framework.

[0114] In this embodiment, according to the previous noise suppression circuit strategy and chip response imbalance compensation parameters, the response imbalance characteristics of the current chip are analyzed, and the compensation optimization goals are set, such as improving signal quality, reducing noise interference, and improving fluid flow uniformity. The key parameters that need to be optimized, such as current setting, fluid flow rate, and temperature control, are determined so that targeted adjustments can be made in subsequent optimization. Simulation software (such as COMSOL The spatial optimization simulation framework is adjusted using Multiphysics or Ansys. According to the compensation parameters, the circuit design and fluid channels are reconfigured to achieve the compensation effect of response imbalance. Multiple iterative simulations are performed to evaluate the impact of different parameter combinations on chip performance. The performance data after each optimization is recorded to ensure that the final design can effectively compensate for the response imbalance. The optimized response imbalance compensation simulation framework is compared with the original framework. Statistical analysis methods (such as t-test) are used to evaluate the significance of performance improvement. Each optimized parameter has a detailed description and numerical record. The final response imbalance compensation simulation framework is saved in a data format that can be used for subsequent analysis to ensure its feasibility in practical applications. In the optimized compensation simulation framework, the specific process and parameters of secondary sequencing are set, including sample type, sequencing time, and fluid flow rate, to ensure that these parameters can fully reflect the actual sequencing process. The boundary conditions and initial conditions of the simulation model are set to ensure that the simulation environment is consistent with the actual sequencing conditions. The secondary sequencing simulation is run, the simulation process is monitored in real time, and key data such as sequencing signals, molecular concentrations, and current changes are recorded. The frequency of data acquisition is high enough to capture instantaneous changes. Secondary sequencing simulation data is generated, including various electrical signals and fluid dynamics, to ensure data Completeness and accuracy of the test, define the calculation standards for the accuracy of genetic tests, including the accuracy, recall rate and F1 score of sequencing reads, set corresponding thresholds to evaluate the overall performance of sequencing, determine the genetic reference data required for accuracy calculation, so as to perform accurate comparison analysis, use data analysis tools (such as Python or R) to perform accuracy calculation on the secondary sequencing simulation data, calculate the accuracy and other performance indicators by comparing the sequencing results with the reference data, record the calculation results, including the value and calculation method of each performance indicator, ensure the transparency and reliability of the results, record the calculation results of genetic test accuracy in the database, generate a detailed accuracy analysis report, summarize the performance of sequencing and potential improvement directions, analyze the accuracy results, identify the factors affecting the accuracy, and provide a basis for subsequent performance evaluation, define the quantitative standards for fluid flow, including flow rate, flow rate and fluid viscosity, determine the required fluid parameters for accurate flow calculation, use data analysis tools (such as MATLAB or Python) to perform flow quantification calculation on the secondary sequencing simulation data, extract the flow rate data of each channel, calculate the flow rate in combination with the geometric parameters of the channel, record the flow parameters of each channel, including flow rate, flow rate and other related information, to ensure the integrity of the data,The channel flow quantification results are recorded in the database to ensure that the flow characteristics of each channel are described in detail, and a flow analysis report is generated for subsequent performance evaluation. The flow data is analyzed to identify channels with uneven flow to provide a basis for subsequent improvements. The calculation standard for sequencing response speed is defined, including sequencing completion time and sample processing time, and the calculation formula is set, response speed 𝑅=N / T, where N is the number of sequencing reads and T is the number of sequencing reads. To process time, determine the required time parameters for accurate response speed calculation, use data analysis tools (such as MATLAB or Python) to calculate the response speed of the secondary sequencing simulation data, extract the time data required for sequencing completion, calculate the response speed based on the number of reads, record the calculation results of the sequencing response speed, including the speed value and calculation method, to ensure the transparency and reliability of the data, record the sequencing response speed calculation results in the database, generate a detailed speed analysis report, summarize the sequencing response speed performance and its influencing factors, analyze the response speed results, identify the factors affecting the speed, and provide a basis for subsequent comprehensive performance evaluation, determine the standards for comprehensive performance evaluation, including weighted scores for sequencing accuracy, response speed, and flow parameters, set corresponding weights to reflect the importance of each indicator, develop a comprehensive performance evaluation model, and ensure that the model can accurately reflect the impact of each indicator on the overall performance, use data analysis tools (such as MATLAB or Python) to comprehensively evaluate the sequencing response speed, channel flow parameters, and test accuracy, substitute each indicator into the evaluation model, and calculate the comprehensive performance score , record the contribution of each indicator in the comprehensive evaluation to ensure the transparency and traceability of the results, record the comprehensive performance evaluation results in the database, generate a detailed performance evaluation report, analyze the performance of the chip under different indicators, identify the potential direction of performance improvement, and provide a basis for subsequent optimization. According to the results of the comprehensive performance evaluation, analyze the shortcomings of the current chip parameters, set fine-tuning goals, such as improving sequencing accuracy or optimizing flow speed, determine the key parameters that need to be fine-tuned, such as current, flow rate, and temperature, so as to make targeted adjustments, and use simulation software (such as COMSOL or ANSYS) to fine-tune the parameters of the response imbalance compensation simulation framework. According to the evaluation results, adjust the design of the circuit and fluid channel to optimize the performance of the chip, perform multiple simulation tests, record the changes in performance after each fine-tuning, and ensure that the final design can meet the expected performance goals. Compare the final fine-tuning results with the previous performance, use statistical analysis methods (such as variance analysis) to evaluate the effectiveness of fine-tuning, ensure that each fine-tuning parameter is recorded in detail, and save the final chip framework in a data format that can be used for subsequent applications to ensure its feasibility and effectiveness in practical applications. ,

[0115] In this embodiment, an integrated design system for a gene sequencing chip is provided, which is used to execute the integrated design method for a gene sequencing chip as described above, including:

[0116] A multi-level framework is used to obtain the initial design drawings of the gene sequencing chip; a multi-level chip framework is designed for the initial design drawings, thereby constructing a multi-level chip simulation framework;

[0117] A multi-parameter design module is used to perform multi-parameter design of probe array layout and feasibility adjustment of channel distribution based on the gene sequencing chip design drawings, thereby obtaining multiple chip space layout schemes;

[0118] A space layout optimization module is used to extract the optimal chip space layout scheme based on multiple chip space layout schemes; and optimize the space layout of the multi-level chip simulation framework to obtain a space optimization simulation framework;

[0119] The noise suppression module is used to perform full-cycle gene sequencing simulation based on the spatial optimization simulation framework, collect gene sequencing simulation data, and perform noise suppression circuit design to obtain a noise suppression circuit strategy;

[0120] The response imbalance compensation module is used to mine the microfluidic response imbalance of gene sequencing simulation data and perform response imbalance compensation calculations to generate chip response imbalance compensation parameters;

[0121] The parameter fine-tuning module is used to fine-tune the final chip parameters based on the noise suppression circuit strategy and the chip response imbalance compensation parameters, so as to obtain the final chip framework.

[0122] The present invention lays the foundation for the entire design process by obtaining the initial design drawings of the gene sequencing chip. By analyzing the initial design drawings, the preliminary design structure of the chip can be fully understood, and potential design defects or bottlenecks can be identified. The multi-level chip framework design combines the electrical, fluid, thermal and other dimensional behaviors of the chip for comprehensive analysis. The topological structure of the circuit, the flow conditions of the microfluidic channel, the distribution of the probes, etc., each layer is independently simulated, thereby improving the design accuracy, discovering problems in advance and adjusting the design. The layout of the probe array directly affects the efficiency and accuracy of gene sequencing. The array layout is optimized through multi-parameter design (such as probe spacing, arrangement density, etc.), which significantly improves the accuracy of the sequencing results and avoids interference and overlapping signals. The distribution and design of microfluidic channels can achieve more efficient fluid control and optimize the flow path and reaction efficiency of liquid samples. This optimization not only affects the sequencing speed, but is also directly related to the stability and reliability of the chip. By adjusting the feasibility of different design schemes, various configuration schemes can be evaluated in the early stages of design to avoid unfeasible or costly schemes in the later design process and reduce the investment in ineffective designs. By comparing multiple design schemes, the design scheme with the highest space utilization and the best performance can be extracted to ensure that the design density and function of the chip are maximized and to avoid wasting precious space resources. The spatial layout of the multi-level simulation framework can be further optimized to better integrate different functional modules such as circuits, microfluidic channels, and probe arrays. Reduce the interference between modules and improve the overall efficiency of the system. By optimizing the spatial layout, reduce the mechanical or fluid problems caused by unreasonable design, reduce the failure rate in chip production, and conduct full-cycle gene sequencing simulation, it can simulate the entire working process of the chip and identify the performance bottlenecks that appear at different stages, such as probe signal distortion and fluid dynamics inequality. Noise is an important factor affecting sequencing accuracy in the gene sequencing process. By specially designing noise suppression circuits, it can effectively reduce the impact of external noise, signal interference, etc. on sequencing results, ensuring that the signal is more accurate and clear. The effectiveness of the noise suppression circuit design directly improves the signal-to-noise ratio (SNR) in the gene sequencing process, thereby improving the accuracy and reliability of the final sequencing results and improving the overall Performance, response imbalance problems in fluid dynamics are common in microfluidic systems, resulting in uneven fluid flow, uneven sample distribution, etc. By exploring the response imbalance problem, these problems can be effectively identified and solved to ensure that the fluid response of the chip is accurate and balanced. By generating response imbalance compensation parameters, the microfluidic system of the chip can be accurately adjusted to ensure consistent responses of each channel, avoid errors or deviations in the sequencing process due to local imbalance, timely detect and compensate for response imbalance, improve the stability of the chip under long-term and high-load use, reduce the probability of errors in the sequencing process, and optimize the reliability of sequencing. By optimizing the two aspects of noise suppression and response imbalance compensation, the chip design is finally fine-tuned to ensure that the chip performance reaches the best state.These fine-tunings improve the adaptability and stability of the chip in different working environments. By comprehensively considering the optimization of noise control, response balance, spatial layout and other aspects, the final chip framework will have higher gene sequencing accuracy, faster response speed and lower error rate. The finely optimized chip design can reduce the defective rate in production, improve mass production efficiency, and better cope with complex conditions in actual applications, ensuring the commercialization and market application of the chip.

[0123] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0124] The above is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. An integrated design method for a gene sequencing chip, characterized in that: The following steps are involved: Step S1: Obtaining the initial design drawings of the gene sequencing chip; Performing a multi-level chip framework design on the initial design drawings, thereby constructing a multi-level chip simulation framework; Step S2: Based on the gene sequencing chip design drawings, multi-parameter design of probe array layout and feasibility adjustment of channel distribution are performed to obtain multiple chip space layout schemes; Step S3: extracting an optimal chip space arrangement scheme based on multiple chip space arrangement schemes; And optimizing the spatial arrangement of the multi-level chip simulation framework to obtain a spatially optimized simulation framework; Step S4: performing full-cycle gene sequencing simulation based on the spatial optimization simulation framework, collecting gene sequencing simulation data, and performing noise suppression circuit design to obtain a noise suppression circuit strategy; Step S5: performing microfluidic response imbalance mining on gene sequencing simulation data and performing response imbalance compensation calculation to generate chip response imbalance compensation parameters; Step S6: fine-tuning the final chip parameters based on the noise suppression circuit strategy and chip response imbalance compensation parameters, thereby obtaining the final chip framework.

2. The integrated design method of gene sequencing chip according to claim 1, characterized in that: The specific steps of step S1 are: Step S11: obtaining an initial design drawing of a gene sequencing chip; performing visual identification of chip interfaces on the initial design drawing, and marking multiple chip interfaces; Step S12: Performing physical connection circuit analysis on the initial design drawing to extract all connection circuits of the chip; Step S13: performing circuit topology analysis on all the connection circuits of the chip, thereby generating circuit topology data inside the chip; Step S14: performing microfluidic channel identification on the initial design drawing to extract multiple microfluidic channels; Step S15: performing channel spatial distribution analysis on a plurality of microfluidic channels to obtain microfluidic channel spatial distribution characteristics; Step S16: Design a multi-level chip framework for multiple chip interfaces, chip internal circuit topology data, and microfluidic channel spatial distribution characteristics, thereby constructing a multi-level chip simulation framework.

3. The method according to claim 2, characterized in that The specific steps of step S16 are: Performing chip geometry calculation on the initial design drawing to extract chip geometry parameters; Perform position calculation on multiple chip interfaces one by one to generate the position coordinates of each chip interface; Designing the chip physical layer framework based on the position coordinates of each chip interface and the chip geometric parameters to obtain the chip physical layer framework; Identify chip electrodes and calculate the position coordinates of chip electrodes; Performing circuit signal transmission simulation on all connection circuits of the chip based on the position coordinates of the chip electrodes to generate chip internal row circuit signal transmission data; Based on the internal row circuit signal transmission data of the chip, the electronic layer framework is designed for the internal circuit topology data of the chip to obtain the chip electronic layer framework; Performing fluid flow path analysis on the spatial distribution characteristics of the microfluidic channel to generate a fluid flow path of the microfluidic channel; Performing microfluidic fluid sequencing dynamics evolution according to the microfluidic channel fluid flow path to generate fluid sequencing dynamics evolution process data; Designing the fluid layer framework of multiple microfluidic channels based on the fluid sequencing dynamics evolution process data to obtain the chip fluid layer framework; A multi-level framework integration simulation is performed based on the chip physical layer framework, chip electronic layer framework and chip fluid layer framework to construct a multi-level chip simulation framework.

4. The method according to claim 1, characterized in that The specific steps of step S2 are: Step S21: performing surface DNA probe morphology analysis based on the gene sequencing chip design drawings to obtain probe array morphology parameters; Step S22: performing arrangement density calculation on the probe array morphological parameters to generate a probe array arrangement density value; Step S23: performing a probe array arrangement multi-parameter design according to the probe array arrangement density value to obtain a plurality of probe array arrangement parameters; Step S24: performing feasibility adjustment of channel distribution according to the plurality of microfluidic channels to obtain a plurality of feasibility adjusted channel distribution data; Step S25: performing multi-parameter adjustment optimization on multiple probe array arrangement parameters and multiple feasible adjustment channel distribution data, thereby obtaining multiple chip space arrangement solutions.

5. The integrated design method of gene sequencing chip according to claim 1, characterized in that: The specific steps of step S3 are: Step S31: Calculating the component volume space of each scheme based on multiple chip space layout schemes, thereby obtaining the component volume space parameters of each scheme; Step S32: Calculate the total volume of the chip substrate according to the gene sequencing chip design drawing to generate the total available volume space; Step S33: Calculate the overall space utilization of the component volume space parameters of each solution according to the total available volume space, so as to generate the chip space utilization of each solution; Step S34: extracting the optimal chip space layout solution based on the chip space utilization of each solution; Step S35: optimizing the spatial arrangement of the multi-level chip simulation framework according to the optimal chip spatial arrangement solution to obtain a spatially optimized simulation framework.

6. The integrated design method of gene sequencing chip according to claim 1, characterized in that: The specific steps of step S4 are: Step S41: performing full-cycle gene sequencing simulation based on a spatial optimization simulation framework and collecting gene sequencing simulation data; Step S42: performing chip sequencing sound signal analysis on the gene sequencing simulation data to extract the sound signal of the gene sequencing process; Step S43: performing sequencing noise identification on the sound signal of the gene sequencing process to generate a gene sequencing noise signal; Step S44: tracing the noise source of the gene sequencing noise signal to obtain the potential source of the sequencing noise; Step S45: performing noise fluctuation evolution on potential sources of sequencing noise, thereby generating a noise fluctuation evolution law; Step S46: Design a noise suppression circuit according to the noise fluctuation evolution rule, so as to obtain a noise suppression circuit strategy.

7. The integrated design method of gene sequencing chip according to claim 1, characterized in that: The specific steps of step S5 are: Step S51: Calculate the global circuit unit state parameters for the gene sequencing simulation data, and extract the electrical state parameters of each chip unit; Step S52: performing inter-unit parameter difference analysis on the electrical state parameters of each chip unit, and extracting inter-unit parameter difference data; Step S53: identifying circuit imbalance regions of the spatial optimization simulation framework based on inter-unit parameter difference data, and extracting circuit imbalance regions of the simulation framework; Step S54: performing microfluidic response imbalance mining on gene sequencing simulation data, thereby marking response imbalance microfluidic channels; Step S55: performing response imbalance compensation calculation based on the simulation framework circuit imbalance area and the response imbalance microfluidic channel, thereby generating chip response imbalance compensation parameters.

8. The integrated design method of gene sequencing chip according to claim 7, characterized in that: The specific steps of step S54 are: Perform microfluidic channel response analysis on gene sequencing simulation data to extract microfluidic channel response data; Perform fluid flow feature recognition on microfluidic channel response data and extract fluid flow features of each channel; Based on the fluid flow characteristics of each channel, channel resistance anomaly is identified and abnormal resistance channels are extracted; Perform temperature distribution analysis on each channel of the microfluidic channel response data to obtain temperature distribution simulation data for each channel; Perform thermal effect imbalance analysis based on the temperature distribution simulation data of each channel to identify the thermal effect imbalance channel; Microfluidic response imbalance mining is carried out based on abnormal resistance channels and thermal effect imbalance channels, thereby marking response imbalance microfluidic channels.

9. The integrated design method of a gene sequencing chip according to claim 1, characterized in that: The specific steps of step S6 are: Step S61: optimizing the chip response imbalance compensation for the spatial optimization simulation framework based on the noise suppression circuit strategy and the chip response imbalance compensation parameters, thereby generating a response imbalance compensation simulation framework; Step S62: performing secondary sequencing simulation on the response imbalance compensation simulation framework, and extracting secondary sequencing simulation data; Step S63: Calculate the gene test accuracy of the secondary sequencing simulation data to generate chip test accuracy; Step S64: quantifying the channel fluid flow rate of the secondary sequencing simulation data to generate microfluidic channel flow parameters; Step S65: Calculating the sequencing response speed of the secondary sequencing simulation data to generate a chip sequencing response speed; Step S66: Perform comprehensive performance evaluation based on the chip sequencing response speed, microfluidic channel flow parameters and chip test accuracy, so as to obtain the comprehensive performance of the simulated chip; Step S67: fine-tuning the final chip parameters of the response imbalance compensation simulation framework based on the comprehensive performance of the simulated chip, thereby obtaining the final chip framework.

10. An integrated design system for a gene sequencing chip, characterized in that: The integrated design method for executing the gene sequencing chip according to claim 1 comprises: A multi-level framework is used to obtain the initial design drawings of the gene sequencing chip; a multi-level chip framework is designed for the initial design drawings, thereby constructing a multi-level chip simulation framework; A multi-parameter design module is used to perform multi-parameter design of probe array layout and feasibility adjustment of channel distribution based on the gene sequencing chip design drawings, thereby obtaining multiple chip space layout schemes; A space layout optimization module is used to extract the optimal chip space layout scheme based on multiple chip space layout schemes; and optimize the space layout of the multi-level chip simulation framework to obtain a space optimization simulation framework; The noise suppression module is used to perform full-cycle gene sequencing simulation based on the spatial optimization simulation framework, collect gene sequencing simulation data, and perform noise suppression circuit design to obtain a noise suppression circuit strategy; The response imbalance compensation module is used to mine the microfluidic response imbalance of gene sequencing simulation data and perform response imbalance compensation calculations to generate chip response imbalance compensation parameters; The parameter fine-tuning module is used to fine-tune the final chip parameters based on the noise suppression circuit strategy and the chip response imbalance compensation parameters, so as to obtain the final chip framework.

Images