Quantum bit mapping method and device, equipment and storage medium

Abstract

The invention discloses a quantum bit mapping method and device, equipment and a storage medium, and belongs to the technical field of quantum. The method comprises the steps that a coupling graph corresponding to quantum equipment is acquired, each vertex in the coupling graph represents one quantum bit in the quantum equipment, and an edge between the two vertexes represents that a double-quantum-bit gate is allowed to directly act on the quantum bits corresponding to the two vertexes; at least two connected sub-graphs are generated according to the coupled graph, the number of vertexes of each connected sub-graph is larger than or equal to 2 and smaller than or equal to the routing number of the coupled graph, and the sum of the number of the vertexes of the at least two connected sub-graphs is equal to a constant multiple of the number of the vertexes of the coupled graph; and based on the at least two connected subgraphs, performing quantum bit mapping on the logic circuit to obtain a hardware compilable circuit equivalent to the logic circuit. According to the method, the problem that the depth is too large due to quantum bit permutation under the limitation of a coupling graph is solved, and the technical effect of effectively reducing the time complexity of quantum bit mapping is achieved.

Description

Technical Field

[0001] The present application relates to the field of quantum technology, and in particular to a quantum bit mapping method, device, equipment and storage medium. Background Art

[0002] The study of quantum bit mapping methods is very important for realizing quantum algorithms and improving the performance of quantum computers. This is also one of the key issues in current quantum computing research.

[0003] When studying the quantum bit mapping method, the optimization problem-based method refers to reducing the quantum bit mapping problem to an equivalent mathematical optimization problem, and then using the existing optimization problem solver to solve it. Specifically, it is necessary to first establish a mathematical model to transform the various constraints and objective functions in the quantum bit mapping problem into the constraints and objective functions in the optimization problem. When establishing the model, it is necessary to ensure that the original problem and the transformed optimization problem are equivalent, and to ensure that the solution to the optimization problem is the feasible solution to the original mapping problem. Then, according to the type of optimization problem, select ready-made solution algorithms and packages, such as linear programming, quadratic programming, semidefinite programming solvers, etc. The established mathematical model is input into the solver, and after iterative calculations by the solver, a solution that satisfies the constraints and makes the objective function reach the optimal value can be obtained. Finally, the optimized solution given by the solver is mapped back to the solution space of the quantum bit mapping problem, and a feasible solution to the original mapping problem is obtained.

[0004] In the related art, the use of optimization-based methods for quantum bit mapping results in a high time complexity problem. Summary of the invention

[0005] The embodiments of the present application provide a quantum bit mapping method, device, equipment and storage medium. The technical solutions provided by the embodiments of the present application are as follows:

[0006] According to one aspect of an embodiment of the present application, a quantum bit mapping method is provided, the method comprising:

[0007] Obtaining a coupling graph corresponding to a quantum device, wherein each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices;

[0008] At least two connected subgraphs are generated according to the coupling graph, the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph;

[0009] Based on the at least two connected subgraphs, quantum bit mapping is performed on the logic circuit to obtain a hardware compilable circuit equivalent to the logic circuit.

[0010] According to one aspect of an embodiment of the present application, a quantum bit mapping device is provided, the device comprising:

[0011] An acquisition module is used to acquire a coupling graph corresponding to a quantum device, wherein each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices;

[0012] A generating module, configured to generate at least two connected subgraphs according to the coupling graph, wherein the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph;

[0013] A mapping module is used to perform quantum bit mapping on the logic circuit based on the at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit.

[0014] According to one aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the above-mentioned quantum bit mapping method.

[0015] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the above-mentioned quantum bit mapping method.

[0016] According to one aspect of an embodiment of the present application, a computer program product is provided, wherein the computer program product comprises a computer program, and the computer program is loaded and executed by a processor to implement the above-mentioned quantum bit mapping method.

[0017] The technical solution provided by the embodiments of the present application has at least the following beneficial effects:

[0018] By dividing the coupling graph into at least two connected subgraphs, the quantum bit replacement originally performed under the restriction of the entire coupling graph is transformed into quantum bit replacement on multiple connected subgraphs, thus solving the problem of excessive depth caused by quantum bit replacement under the restriction of the coupling graph, thereby controlling the circuit depth of the hardware-compilable circuit and achieving the technical effect of effectively reducing the time complexity of quantum bit mapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a flow chart of a quantum bit mapping method provided by an embodiment of the present application;

[0021] Figure 2 It is a schematic diagram of two coupling diagrams corresponding to a superconducting quantum device provided in one embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of calculating the number of common connected graph routes provided by an embodiment of the present application;

[0023] Figure 4 is a schematic diagram of a graph algorithm pseudo code provided by an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of a graph algorithm example provided by an embodiment of the present application;

[0025] Figure 6 is a schematic diagram of the number of quantum circuit layers provided by one embodiment of the present application;

[0026] Figure 7 It is a schematic diagram of a hardware compilable circuit structure provided by an embodiment of the present application;

[0027] Figure 8 is a block diagram of a quantum bit mapping device provided by one embodiment of the present application;

[0028] Fig. 9 It is a structural block diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0030] Before introducing and explaining the technical solution of the present application, some concepts involved in the present application are first defined and explained.

[0031] 1. Quantum circuit: A quantum computing model consisting of a series of quantum gates and measurement sequences, and the calculation is completed by the quantum gates.

[0032] 2. Quantum bit: the basic unit of quantum computing. Traditional computers use 0 and 1 as the basic units of binary. The difference is that quantum computing can process 0 and 1 at the same time, and the system can be in a linear superposition state of 0 and 1: |ψ>=α|0>+β|1>, where α and β represent the complex probability amplitude of the system at 0 and 1. Their squared modulus |α| 2 ,|β| 2 represent the probabilities of being 0 and 1 respectively.

[0033] 3. Coupling graph: It uses quantum bits as vertices and the coupling relationship between quantum bits as edges, forming a graph model for representing the mutual coupling relationship between quantum bits. If there is an edge connecting the vertices corresponding to two quantum bits in the coupling graph, it means that the pair of quantum bits can directly perform a two-qubit gate operation, while the quantum bit pairs that are not directly connected need to first use the exchange gate operation to exchange the states of the two quantum bits before implementing the two-qubit gate operation.

[0034] 4. Quantum bit mapping: For any coupled graph G = (V, E), the vertex set V represents the set of quantum bits. If in a quantum circuit, any two-qubit gate acting on quantum bits u, w∈V satisfies (u, w)∈E, then the quantum circuit is called a hardware compilable circuit.

[0035] 5. Quantum bit mapping problem: Given an arbitrary coupling graph G and an arbitrary logic circuit C, a hardware-compilable circuit C′ equivalent to the above logic circuit C can be obtained simply by inserting swap gates.

[0036] 6. Routing on graphs: Given a coupled graph G = (V, E), there is an element at each vertex. In the following example, the element is a stone. Routing on graphs refers to the following process: for any permutation π∈S V , then move the stone on each vertex v∈V to π(v). In the i-th round, there is a matching If (u,v)∈M i , then the two stones on vertices u and v are allowed to be exchanged. rt(G,π) represents the minimum number of rounds required to move all the stones from their initial position v to the target position π(v). The routing number of the graph G is defined as:

[0037]

[0038] That is, the number of routes of a graph is equal to the maximum number of permutation rounds considering all permutations of the graph. The number of rounds refers to the number of permutation rounds required to move the stone on each vertex v∈V to π(v).

[0039] 7. Basic symbols: [n] represents the set of integers {1,2,…,n}. For the set V 1 and V 2 ,gather The symbol \ represents the difference set, and the set V 1 \V 2 Indicates that it belongs to the set V 1 but not in set V 2 For a graph G = (V, E), V and E represent the vertex set and edge set of the graph G respectively. For a graph G = (V, E) and the set Defining edge sets Then the graph G′=(V′,E′) is called the subgraph of G generated by V′. For any set V of size n, S V represents the set of all permutations defined on V. For a set S, |S| represents the size of the set.

[0040] 8. Worst depth overhead: Let G = (V, E) represent a coupled graph with n vertices, K n represents a complete graph containing n vertices, C n represents an n-qubit logic circuit, that is, a qubit logic circuit containing n vertices in the graph G. The worst extra depth on the coupled graph G is defined as:

[0041]

[0042] Among them, d(C n ,G) indicates C n The minimum depth of the hardware-compilable circuit corresponding to the coupling graph G, d(C n ,K n ) represents the logic circuit C n circuit depth.

[0043] In the quantum bit mapping method provided in the embodiment of the present application, the execution subject of each step may be a computer device, and the computer device may be any electronic device with computing and storage capabilities, for example, a PC (Personal Computer), a server, and other electronic devices.

[0044] Please refer to Figure 1 , which shows a flow chart of a quantum bit mapping method provided by an embodiment of the present application. The execution subject of each step of the method may be a computer device. The method may include at least one of the following steps 110 to 130.

[0045] Step 110, obtaining a coupling graph corresponding to the quantum device, where each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices.

[0046] Quantum devices refer to devices that use quantum physical effects to achieve functions such as accelerated computing, communication, and detection. Quantum bits are the basic units of quantum devices. The coupling relationship between multiple quantum bits in a quantum device can be represented by a graph, which can be called a coupling graph. In other words, the coupling graph abstractly presents the physical interaction relationship between quantum bits in a quantum device.

[0047] In some embodiments, the coupling graph of the present application is a connected graph. Because the connectivity of the coupling graph corresponding to the quantum device depends on the design goal and physical implementation of the quantum device, the coupling graph corresponding to the quantum device may be disconnected. This connectivity refers to whether there is a path connecting any two vertices. Since the present application studies the problem of quantum bit mapping of arbitrary logic circuits, it includes acting on dual quantum bit gates on arbitrary quantum bit pairs. This requires that the coupling graph is at least connected. Therefore, in the present application, the coupling graph is a connected graph by default.

[0048] In the coupling graph, the vertices represent the qubits in the quantum device, and the edges represent the two qubit gates that can be applied to the two qubits connected by the edge. A two-qubit gate is a quantum gate that acts on two qubits and is used to implement logical operations and interactions between qubits. Two-qubit gates include but are not limited to: CNOT (ControlledNOT), SWAP (Swap Gate), SQSWAP (Square root of SWAP), CZ (Controlled Z), CR (Controlled Rotation), ISWAP (Interaction SWAP), etc.

[0049] In one possible implementation, the coupling diagram corresponding to any quantum device is obtained through a design drawing or document, or the coupling diagram corresponding to any quantum device is obtained by experimentally measuring the interaction relationship between different quantum bits, which is not limited in this application.

[0050] Please refer to Figure 2, which shows a schematic diagram of two coupling graphs corresponding to a superconducting quantum device provided by an embodiment of the present application, where subgraph (a) is a path graph and subgraph (b) is a brick wall graph. The vertices represent quantum bits in the quantum device. If there is an edge connecting two vertices, it means that the two-qubit gate can directly act on the quantum bits corresponding to these two vertices. In a logic circuit, the two logic bits corresponding to any two-qubit gate may not have an edge between the coupling graphs, that is, they cannot be directly implemented on a quantum device. For example, please refer to Figure 2 In sub-figure (b), if we want to implement a two-qubit gate, such as CNOT, between qubits 0 and 18, we cannot directly implement it because qubits 0 and 18 are not directly connected. For example, please refer to Figure 2 Sub-figure (b), if we want to implement a two-qubit gate, such as CNOT, between qubits 0 and 1, since qubits 0 and 1 are directly connected, we can implement CNOT directly on the qubit pair 0 and 1.

[0051] Step 120, generating at least two connected subgraphs according to the coupling graph, the number of vertices of each connected subgraph being greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs being equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph.

[0052] The permutation refers to the movement of an element on a vertex of the coupling graph from an initial vertex position to a target vertex position. There is an element on each vertex of the coupling graph, wherein the initial vertex position refers to the vertex position where the element is currently located, and the target vertex position refers to the vertex position where the element wants to reach. The initial vertex position and the target vertex position are not at the same vertex position, and the present application does not limit the notation of the element. Exemplarily, permutation 1→2 refers to the exchange of positions of an element on vertex 1 with an element on vertex 2. For the element on vertex 1, its initial vertex position is the position of vertex 1, and the target vertex position is the position of vertex 2. A permutation may include the movement of some or all elements from an initial vertex position to a target vertex position, and the present application does not limit this.

[0053] For a coupled graph G = (V, E), if a subgraph H of G satisfies: the node set of H is a subset of V, and the edge set is a subset of E; H is connected, that is, any two vertices in H are always connected by a path. Then this subgraph H is called a connected subgraph of graph G.

[0054] The number of routes in the coupling graph G is denoted as Where rt(G,π) represents the number of routes for a certain permutation π in graph G, and rt(G) represents the maximum number of routes among all permutations in graph G. For details, please refer to the definition of the number of routes above, and a specific example is given below.

[0055] Please refer to Figure 3 , which shows a schematic diagram of calculating the number of common connected graph routes provided by an embodiment of the present application. For example, as shown in subgraph (a), in a complete graph K with 4 vertices 4 Permutate π 1 :1→2, 2→3, 3→4, 4→1, the replacement steps are as follows: in the first round, 1, 2 and 3, 4 are exchanged, and in the second round, 2, 4 are exchanged. A total of two rounds are required, so rt(K 4 ,π 1 )=2.

[0056] For example, as shown in sub-figure (b), in the path graph P 4 Permutate π 2 :1→2, 2→3, 3→4, 4→1, the replacement steps are as follows: the first round of exchange 1, 2, the second round of exchange 1, 3, the third round of exchange 1, 4, a total of 3 rounds are required, so rt(P 4 ,π 2 )=3. For any rt(G,π), there is actually a permutation algorithm for π. For example, 4 For permutation π 1 The swaps 1, 2 and 3, 4 are performed by a permutation algorithm. More details about the permutation algorithm are described later.

[0057] In some embodiments, the number of routes of different connected graphs may be different. n , the number of routes is rt(K n )=2. For a path P of length n n , whose routing number is rt(P n )=O(n). Among them, O(n) describes rt(P n ), which means that there exists a positive number c such that all rt(P n )≤cn, the O symbol has a similar meaning below. 1 ×n 2 The two-dimensional grid The number of routes is For a tree T with n vertices n , whose routing number is rt(T n )=O(n).

[0058] In some embodiments, for a connected graph G = (V, E), the upper bound of its routing number is O(|V|). This is because the above description has described that for a tree T with n vertices n , whose routing number is rt(T n )=O(n). For any connected graph G, it corresponds to a spanning tree, because the spanning tree contains all the vertices of graph G, so rt(G)=O(|V|), which means that the number of routes of a connected graph is at most a constant multiple of its number of vertices.

[0059] In some embodiments, the number of routes in the graph is lower bounded by Ω(|V 1 | / |V 2 |), which means that there exists a positive number c such that all rt(G)≥c(|V 1 | / |V 2 |), which reflects the ratio of rt(G) to the point set size |V 1 | / |V 2 |The lower bound of the number of routes is Ω(|V 1 | / |V 2 |), the proof process is as follows: For a connected graph G = (V, E), suppose there are two vertex sets satisfy: For any u∈V 1 , in That is, N(u) is represented in the graph G, and the set V 1 The set of vertices directly connected to the vertices in . We call the vertex set V 1 The stones on the board are marked as 1, 2, ..., |V 1 |. Definition And permutation π: =(1,1+s)(2,2+s)…(s,2s). To implement permutation π on graph G, move stone i to the vertex where stone i+s is located. Because for any u∈V 1 , Stone i must pass through set V 2 The vertex in the can reach the vertex where the stone i+s is located. In one round, V 1 At most |V 2 | A stone can pass through V 2 , so moving s stones requires at least Wheel, of which Indicates s / |V 2 | is rounded up to an integer. So

[0060] In some embodiments, the number of vertices of each connected subgraph is limited: the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, in order to ensure that each connected subgraph has at least 2 quantum bits and to ensure that the mapping complexity of each connected subgraph is controlled. And the number of vertices of all connected subgraphs covers a constant multiple of the vertex set of the coupling graph, where the constant refers to a positive number, which can be pre-set according to actual conditions, for example, it can be set to 2. The multiple connected subgraphs generated in this way not only meet certain scale restrictions, but also achieve coverage of most or even all vertices of the coupling graph, providing favorable conditions for subsequent quantum bit mapping.

[0061] Step 130, based on at least two connected subgraphs, perform quantum bit mapping on the logic circuit to obtain a hardware compilable circuit equivalent to the logic circuit.

[0062] The logic circuit here refers to the quantum circuit corresponding to the quantum algorithm that the user wants to implement. The quantum algorithm implements the algorithm task by designing the quantum gates of the quantum circuit. When the quantum circuit corresponding to any logic circuit is implemented on a quantum device, it will be restricted by the coupling graph corresponding to the quantum device. If the quantum circuit has a two-qubit gate acting on two qubits, and the two qubits are not directly connected in the coupling graph, then the quantum circuit is not a hardware compilable circuit.

[0063] However, in practice, the quantum circuit corresponding to the quantum algorithm that users want to implement is often not a hardware compilable circuit. In order to implement any logic circuit, we can insert a swap gate, which can swap the quantum states of the two quantum bits it acts on, thereby changing the order of interaction between quantum bits and obtaining a hardware compilable circuit equivalent to the logic circuit. Therefore, we study how to perform quantum bit mapping on any logic circuit by inserting a swap gate to obtain an equivalent hardware compilable circuit, which is the so-called quantum bit mapping problem.

[0064] Please refer to Figure 2 , if we want to implement a two-qubit gate on qubit 0 and qubit 18, since we cannot directly act on qubit 0 and qubit 18, we introduce a swap gate to obtain a hardware-compilable circuit equivalent to the logic circuit. In one possible implementation, we first exchange the quantum states of qubit 0 and qubit 14 through a swap gate. Now that qubit 0 and qubit 18 are adjacent, we can implement the required two-qubit gate between them. For example, to implement a CNOT, we can use qubit 0 as the control bit and qubit 18 as the target bit to execute CNOT. At this time, the number of swap gates acted on by the hardware-compilable circuit is 1, CNOT is 1, and they are executed one after another. It can be said that its circuit depth is 2.

[0065] In some embodiments, the hardware compilable circuit equivalent to any logic circuit is not unique, and the corresponding circuit depth may be different. Figure 2 , if you want to implement a two-qubit gate between qubit 0 and qubit 18, in another possible implementation, first use the exchange gate to exchange the quantum states of qubit 0 and qubit 1. Now qubit 0 and qubit 2 are adjacent, then exchange the quantum states of qubit 0 and qubit 2, now qubit 0 and qubit 3 are adjacent, then exchange the quantum states of qubit 0 and qubit 3, now qubit 0 and qubit 4 are adjacent, continue to use the exchange gate, so that qubit 0 is exchanged to the vertex where qubits 4, 15, 22, 21, 20, and 19 are located, now qubit 0 and qubit 18 are adjacent, and the required two-qubit gate can be implemented between them, such as implementing a CNOT, you can use qubit 0 as the control bit and qubit 18 as the target bit, and execute CNOT. At this time, the number of exchange gates used by the hardware compilable circuit is 9, CNOT is 1, and they are executed in sequence, so it can be said that its circuit depth is 10.

[0066] When studying the quantum bit mapping problem, the circuit depth reflects the time complexity of the quantum algorithm, that is, the number of executions of the quantum gate operation. Therefore, when designing a hardware-compilable circuit equivalent to a logic circuit, by optimizing the circuit depth, the time complexity of the quantum algorithm can be reduced and the speed and efficiency of quantum computing can be improved.

[0067] In some embodiments, based on at least two connected subgraphs, if the quantum bit pairs acted upon by a two-qubit gate in a logic circuit are in the same connected subgraph, then the quantum bits can be permuted within the connected subgraph to complete the quantum bit mapping of the logic circuit; if the quantum bit pairs acted upon by a two-qubit gate in the logic circuit are not in the same connected subgraph, partial permutation within the connected subgraph can be used to help reduce the distance between the quantum bit pairs, and then global adjustment can be used to complete the quantum bit mapping of the logic circuit to obtain a hardware compilable circuit equivalent to the logic circuit.

[0068] In this process, the connected subgraph ensures that the distance between all the quantum bit pairs affected by the two-qubit gate will not be too far after a constant number of permutations. The circuit depth corresponding to each quantum bit pair permutation process is equal to the number of routes of the graph after a certain permutation.

[0069] The technical solution provided in the embodiment of the present application, by dividing the coupling graph into at least two connected subgraphs, transforms the original quantum bit replacement under the restriction of the entire coupling graph into quantum bit replacement on multiple connected subgraphs, thereby solving the problem of excessive depth caused by quantum bit replacement under the restriction of the coupling graph, thereby controlling the circuit depth of the hardware compilable circuit and achieving the technical effect of effectively reducing the time complexity of quantum bit mapping.

[0070] Next, the process of generating at least two connected subgraphs according to the coupling graph is introduced and explained.

[0071] In some embodiments, a first vertex set family and a second vertex set family are generated based on a coupling graph, the first vertex set family includes at least one vertex set, the second vertex set family includes at least one vertex set, and each vertex set includes at least two vertices in the coupling graph; after obtaining the first vertex set family and the second vertex set family, a connected subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family is generated to obtain at least two connected subgraphs.

[0072] Among them, the first vertex set family and the second vertex set family satisfy the following conditions: the subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family is a connected graph; there are no identical vertices in any two vertex sets in the first vertex set family, and there are no identical vertices in any two vertex sets in the second vertex set family; the number of vertices contained in each vertex set in the first vertex set family and the second vertex set family is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph; the total number of vertices in the first vertex set family and the second vertex set family is equal to a constant multiple of the number of vertices in the coupling graph.

[0073] A set is a collection whose elements are vertex sets consisting of some vertices of the coupling graph. We restrict vertex sets. Since the two-qubit gate describes the action or correlation between two qubits, if the subgraph is not connected, the two-qubit gate defined between them has no practical meaning. Therefore, the subgraph corresponding to each vertex set is a connected graph. In order to allow subgraphs to be mapped in parallel without mapping conflicts and to improve the degree of concurrency, there are no identical vertices in any two vertex sets in each set.

[0074] The above method first generates a set of subgraph vertices that meet certain restrictions, and then constructs the corresponding connected subgraph, which provides a basis for the quantum bit mapping of subsequent logic circuits.

[0075] In some embodiments, the steps of generating the first vertex cluster and the second vertex cluster according to the coupling graph are as follows: first, construct a maximum matching of the coupling graph, the maximum matching includes at least one edge in the coupling graph; then, based on the maximum matching, generate a first vertex cluster, each vertex set in the first vertex cluster corresponds to two vertices connected by an edge included in the maximum matching; the first vertex cluster is denoted as Let the vertex set be W i , where i is an integer not greater than the maximum number of matching edges; then based on the first vertex set, generate the second vertex set.

[0076] The matching of a graph refers to a subset of edges in the graph, where any two edges do not share a common vertex, and the maximum matching of a graph refers to the matching that contains the largest number of edges. Algorithms for constructing the maximum matching of a graph include but are not limited to the Hungarian algorithm, the Kuhn-Munkres (Hungarian matrix matching) algorithm, the Edmonds algorithm, the flow algorithm, and the like. In one possible implementation, the Hungarian algorithm is used to solve the maximum matching problem of a quantum bit coupling graph. First, the quantum bits are represented as vertices in the graph, and the two-qubit gate operations between them are represented as edges. A quantum coupling relationship graph G = (V, E) is constructed, assuming that the number of vertices is n. Then an n×n distance weight matrix is ​​initialized, all set to 0. Next, find an unmatched node in the residual graph, perform a breadth-first search from this node, obtain the shortest path length from it to each unmatched node, and update the value in the weight matrix accordingly. Afterwards, find an element with the smallest weight in the weight matrix, representing a shortest augmented path, and update the matching relationship based on it. The residual graph needs to be updated after matching. This process is repeated, each time finding the minimum weight augmenting path and expanding the match until all nodes are matched. The final matching result is the maximum match.

[0077] After obtaining the maximum matching of the graph, a pair of quantum bits connected by each matching edge is added as a vertex set to the first vertex set cluster. Then, other vertices in the coupling graph that are directly connected to the vertices included in the first vertex set cluster and do not belong to the first vertex set cluster are added to the second vertex set cluster.

[0078] In some embodiments, according to the first vertex cluster Generate the second vertex cluster The steps are as follows:

[0079] According to the first vertex set, determine the initialized set T p , the initialized set T p Includes vertices that belong to the coupled graph and do not belong to the first vertex set, p is a positive integer with an initial value of 1;

[0080] According to the initialized set T p , determine the initialized set Sp , the initialized set S p Includes the first vertex set and the initialized set T p The vertices in are connected to each other;

[0081] Determine the initialized collection is an empty set, and determines the initialized set A 0,p is an empty set, i is a positive integer with an initial value of 1;

[0082] The set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p In which, \ represents the difference of two sets, and the adjacent vertices of the i-th vertex refer to the vertices connected to the i-th vertex;

[0083] Will gather With set A i,p The union of is determined as the set

[0084] If i is less than k 1 , then let i = i + 1, and again from the set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in start execution; among them, k 1 For the set S 1 The number of vertices in ;

[0085] If i equals k 1 , then in Greater than or equal to |T p | / 2, a second vertex set is generated; wherein the vertex set included in the second vertex set is a set and set S p The union of the i-th vertex in , represent The number of vertices in |T p | represents the set T p The number of vertices in ;

[0086] Will gather Determine the set T p+1 ;

[0087] Based on the set T p and k p Determine the set S p+1 ;

[0088] |S p+1 |Determined as k p+1 ; Among them, |Sp+1 | represents the set S p+1 The number of vertices in ;

[0089] If p is less than |T 1 |, then let p = p + 1, and again from the set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in start to execute;

[0090] If p equals |T 1 |, then the process ends and the final generated second vertex set is obtained.

[0091] In the description of the above steps, the symbols used are only used to illustrate the ideas and processes of the algorithm. The specific symbol marking method is not limited in the embodiments of the present application.

[0092] In some embodiments, in order to ensure that the number of vertices contained in each vertex set in the generated second vertex set family is greater than or equal to 2 and does not exceed the number of routes in the coupling graph, the set S is implemented. p The i-th vertex in the set The adjacent vertices in are put into set A i,p In the case of set S p The i-th vertex in the set At most adjacent vertices, then select the i-th vertex in the set All adjacent vertices in are put into set A i,p If the set S p The i-th vertex in the set More than adjacent vertices, then select the i-th vertex in the set Most hits The adjacent vertices are put into the set A i,p Among them, Represents |T p | / k p Round up.

[0093] In a possible implementation, the present application designs a graph algorithm according to the above steps, and the following describes the generated first vertex set family: and the second vertex set Conditions to be met. Please refer to Figure 4 , which shows a schematic diagram of a graph algorithm pseudocode provided by an embodiment of the present application.

[0094] For any input graph G = (V, E), there exist integers s and t such that the algorithm outputs two families of vertices and The following conditions must be met:

[0095] Condition 1: For any i∈[s] and j∈[t], W i and W′ j The resulting subgraph is a connected graph.

[0096] Condition 2: For any i 1 ≠i 2 ∈[s] and j 1 ≠j 2 ∈[t], and

[0097] Condition 3: For any i∈[s] and j∈[t], 2≤|W i |=O(rt(G)) and 2≤|W′ j |=O(rt(G)). To ensure that the number of vertices of the connected subgraph is greater than or equal to 2 and does not exceed O(rt(G)).

[0098] Condition 4: |∪ i∈[s] W i |+|∪ j∈[t] W′ j |=Ω(|V|), in order to ensure that all vertices of the subgraph can cover a constant multiple of the vertex set of the coupled graph.

[0099] Conditions 1 to 4 correspond to the conditions satisfied by the first vertex cluster and the second vertex cluster respectively.

[0100] Please refer to Figure 5 , which shows a schematic diagram of a graph algorithm example provided by an embodiment of the present application. For example, the following example is used to illustrate the Figure 4 The operation process of the graph algorithm pseudocode shown is explained in detail.

[0101] Step 1: Select the maximum matching (double solid line) in the graph, and its corresponding white vertex set can be used to construct a set family

[0102] Step 2: Select black vertices (vertices other than white vertices in step 1) as set T 1 :={7,8,9,10,11,12}, select 1 The vertices adjacent to the middle vertex (white vertices) are S 1 : ={1,2,3,4,5,6}.

[0103] Step 3: Due to (where k 1 =|S 1 |), for vertex 1, in T 1 Select one of its neighbors from {7}; for vertex 2, in T 1 \{7}: = Select a neighbor {8} from {8,9,10,11,12}; Since vertices 3,4,5,6 are in T 1 \{7,8}:={9,10,11,12} has no neighbors, so it is not selected. Then for S 1 The corresponding set of vertices in is defined as:

[0104]

[0105] because So onto the next step.

[0106] Step 4: Due to (where k 1 =|S 1 |), then select S 2 ={1,2} and T 2 :=T 1 \{7,8}={9,10,11,12}.

[0107] Step 5: Since (where k 2 =|S 2 |), for vertex 1, in T 2 Select one of its neighbors {9,10}; since vertices 2,3,4,5,6 are in T 2 \{9,10}: = {11,12} has no neighbors, so it is not selected. Then for S 1 The corresponding set of vertices in is defined as:

[0108]

[0109] because The algorithm output is:

[0110]

[0111]

[0112] The final connected subgraph includes and The connected subgraph formed by the set of vertices contained.

[0113] In some embodiments, the present application Figure 4 The correctness of the graph algorithm shown is proved as follows:

[0114] Condition 1: Group clan The set W in i ={w 2i-1 ,w 2i}Satisfy(w 2i-1 ,w 2i )∈M, where M is the maximum matching of the graph; The collection in middle Each vertex and w j Adjacent. Therefore W i and W′ j The resulting subgraph is a connected graph.

[0115] Condition 2: By the group and From the construction, we can see that for any i 1 ≠i 2 ∈[s] and j 1 ≠j 2 ∈[t], and

[0116] Condition 3: (1) Group clan Depend on Figure 4 The number of routes for the graph algorithm shown in line 2 and the complete graph described above is 2, and the set family Each element W in i Satisfy 2=|W i |=rt(K n )≤rt(G). (2) Set family Depend on Figure 4 Line 13 of the graph algorithm shown, the set family Each element W′ in j Satisfy |W′ j |≥2. Assume that the algorithm stops at step l of the outer loop. We will set S l Re-write and For any because Figure 4 The definition of line 17 of the graph algorithm shown is, and Therefore, we can know that:

[0117]

[0118] Definition S l The union of the sets corresponding to the vertices in is This can be obtained from the above equation:

[0119]

[0120] Since the graph algorithm has not stopped at step l-1, therefore:

[0121]

[0122]

[0123] Therefore, we get |T l |≥|T 1 | / 2>|C|. By T l and S l From the structure of , we can see that And for all u∈T l All neighbors of u are included in S l In From the above description, we can know that rt(G)=Ω(|T l | / k l ). In summary, rt(G) satisfies:

[0124]

[0125] Therefore, for Any set in The size of its set satisfies:

[0126]

[0127] so The size of any set in is O(rt(G)).

[0128] Condition 4: Assume that the algorithm ends at step l of the outer loop. Figure 4 From lines 3 and 12 of the graph algorithm shown, we can see that the set family The elements satisfy |∪ i∈[s] W i |=|V|-|T 1 | and the group The elements satisfy So we can get |∪ i∈[s] W i |+|∪ j∈[t] W′ j |=Ω(|V|).

[0129] The above method designs a graph algorithm that can output a set of vertices that meet specific conditions for any coupled graph to construct a connected subgraph. The verification of the algorithm proves that it works as expected. This ensures that the designed quantum bit mapping method can be actually implemented, and the corresponding graph algorithm can correctly and effectively generate the required connected subgraph. The graph algorithm is verified to ensure the feasibility of the theory of this application and the feasibility of the algorithm.

[0130] The technical solution provided in the embodiment of the present application utilizes the maximum matching of the coupling graph to construct a first vertex cluster containing the quantum bit pairs corresponding to the maximum matching. Then, based on the first vertex cluster, its neighbors are found to form a second vertex cluster. And the generation of these two clusters takes into account conditions such as the range limit of the set size and the connectivity requirements. By constructing these vertex sets that are conducive to mapping, this solution provides a simple and efficient preprocessing method for the realization of any logic circuit to an equivalent hardware compilable circuit.

[0131] Next, the process of performing quantum bit mapping on a logic circuit based on at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit is described.

[0132] In some embodiments, based on at least two connected subgraphs, a first number of logic bit pairs in a logic circuit are permuted; wherein the first number is the number of edges included in the maximum matching of the coupling graph, and each logic bit pair corresponds to two quantum bits acted on by a two-qubit gate in the logic circuit; a first portion of hardware-compilable circuits corresponding to the first number of logic bit pairs are generated; according to at least two connected subgraphs, the remaining logic bit pairs in the logic circuit are permuted; a second portion of hardware-compilable circuits corresponding to the remaining logic bit pairs are generated; and according to the first portion of the hardware-compilable circuits and the second portion of the hardware-compilable circuits, a hardware-compilable circuit equivalent to the logic circuit is obtained.

[0133] Here, permutation refers to the permutation of a graph: for a graph G = (V, E), the structure of the graph is reconstructed by changing the position of the nodes in V. Common algorithms for implementing graph permutation include matching-based permutation algorithms, such as the exchange algorithm and the permutation tree algorithm, sorting-based permutation algorithms, such as bubble sort, insertion sort, merge sort, and search-based permutation algorithms, such as DFS (Depth First Search) and BFS (Breadth First Search).

[0134] In one possible implementation, an exchange algorithm is used to achieve the permutation of the qubit coupling graph. The implementation process is as follows: Analyze the internal structure of each connected subgraph and determine the qubits that need to be permuted in the connected subgraph. In each subgraph, use the exchange algorithm to complete the local permutation of the qubit. That is, find the augmented path in the matching of the subgraph and perform the exchange operation. Repeat the exchange operation until the permutation within each subgraph is completed. According to the needs of global permutation, adjust the connection relationship between the connected subgraphs, and combine the local permutation of the connected subgraphs into a global permutation. Check the global permutation results and make necessary corrections or adjustments. Repeat the above steps to gradually improve the accuracy of the permutation until it meets the needs of the logic circuit. Finally, the global permutation of the entire coupling graph is achieved. Finally, verify the permutation effect and save the new graph structure after permutation.

[0135] The number of base quantum gate layers in a quantum circuit corresponds to the parallel running time of a quantum algorithm. The number of base quantum gate layers in a quantum circuit refers to the number of layers into which the quantum circuit is decomposed that only contains basic quantum gates (basic quantum gates are the basic operating units of quantum computing, such as CNOT gates, Hadamard gates, etc.). Each layer only contains basic gates that can be run in parallel. There is no dependency within the same layer, but there is dependency across layers, which determines the parallel execution capability of the quantum circuit and the time complexity of the quantum algorithm. In other words, if a quantum circuit consists of L layers of base quantum gates, the time complexity of the quantum algorithm that can be run in parallel on a quantum computer is O(L). For example, please refer to Figure 6 , which shows a schematic diagram of the number of quantum circuit layers provided by an embodiment of the present application. The figure represents a four-layer quantum circuit diagram, so the time complexity of running the quantum algorithm on a quantum computer is O(4).

[0136] The maximum number of matchings reflects the upper limit of the number of quantum gates that can be implemented in parallel in a quantum circuit. That is, if the size of the maximum matching of a graph G is m, then in the quantum circuit, at most m two-qubit gates can be implemented in one layer. In one possible implementation, m two-qubit gates can be implemented by permuting π1. Suppose we want to implement a logical quantum circuit with a depth of 1 and a layer with double qubits. By replacing π 1 m two-qubit gates have been implemented, and the remaining The two-qubit gates are then permuted based on the connected subgraph obtained above.

[0137] For example, please refer to Figure 7 , which shows a schematic diagram of a hardware compilable circuit structure provided by an embodiment of the present application. First, two sets of connected graphs G are constructed by a graph algorithm. and The construction process is based on the flow of the graph algorithm described above and will not be elaborated on here. Construct a hardware compilable circuit with the input circuit shown in the figure. The two-bit quantum gates in the circuit are recorded as (1,8), (2,9), (3,6), (4,7), (5,10), where the two-qubit gate (i,j) means that it acts on qubits i and j. For example, (1,8) means that the two-qubit gate acts on qubits 1 and 8. The construction process is as follows: First, use the permutation algorithm (π 1 ) replaces the quantum bits 6, 7, 8, 9 with 8, 9, 6, 7. In this way, the quantum bit pairs (1, 8), (2, 9), (3, 6), and (4, 7) are adjacent in the graph, so their corresponding two-bit quantum gates can be directly acted on. The depth of this step is O(rt(G))+1=O(rt(G)), and its depth is O(rt(G)), as described below; secondly, the permutation algorithm (π 2 ) replace qubits 7,10 with 10,7. In this way, the qubit pair (5,10) is adjacent in the graph, so their corresponding two-qubit gates can be directly acted on. The depth of this step is O(rt(G))+1=O(rt(G)).

[0138] Therefore, only a depth of O(rt(G)) is needed to complete the construction of the hardware compilable circuit of the logic circuit.

[0139] In some embodiments, for any input logic circuit, the additional circuit depth of the algorithm output hardware compilable circuit is at most O(rt(G)), where the additional circuit depth is the ratio of the output circuit depth to the input circuit depth.

[0140] The proof process is as follows: According to |∪ i∈[s] W i |+|∪ j∈[t] W′ j |=Ω(|V|), then there exists a constant c>0, satisfying |∪ i∈[s] Wi|≥c|V|or|∪ j∈[t] W′ j |≥c|V|. Without loss of generality, assume that |∪ i∈[s] W i |≥c|V|. For some integer

[0141]

[0142] represents the set of two-qubit gates composed of one layer of any |V|-qubit logic circuit, q i ,q i+1 Represents the logical bit in Gate. The corresponding hardware compilable quantum circuit is constructed below:

[0143] Will Replace the logical bits in Gate to the vertex set ∪ i∈[s] W i , for every set W i , which can be assigned to For logical bits. This process is equivalent to routing on the graph G, so the circuit depth is rt(G). i The generated subgraph G i In , since the distance between any two logical bits is at most 2, a two-qubit gate (a pair of logical bits) can be realized by inserting at most one exchange gate. i |=O(rt(G)), so in W i Existence Two-qubit gates. i (W i ) requires a quantum circuit of depth O(rt(G)). Since all G i The vertices do not intersect, so each G i The two-qubit gates on can be implemented in parallel. The circuit depth of this step is O(rt(G))+O(rt(G))=O(rt(G)).

[0144] Because |W i |≥2, so Repeat the above steps times, that is, all two-qubit gates in Gate can be realized by a constant number of times.

[0145] According to the above method, for one layer of logic circuit, the present application obtains a logic circuit with a depth of 2·O(rt(G))=O(rt(G)). Therefore, for any coupling graph G, its worst additional depth is

[0146] In some embodiments, after obtaining a hardware compilable circuit equivalent to a logic circuit according to the first part of the hardware compilable circuit and the second part of the hardware compilable circuit, the method further includes: replacing each logic bit in the logic circuit to its original position. The replacement to the original position is to facilitate the implementation of the next quantum algorithm. For example, Figure 7 In the permutation algorithm (π 3 ) is used to restore the qubits to their initial positions. The depth of this step is O(rt(G)).

[0147] The technical solution provided in the embodiment of the present application completes the permutation of quantum bits based on connected subgraphs, and this permutation process has high concurrency. We can complete the permutation of logical quanta within the subgraph, thereby reducing the number of inserted exchange gates and effectively controlling the additional depth of the total mapping circuit. Even if mapping is performed between subgraphs, the mapping within the subgraph can be used to help reduce the distance between quantum bits. This mapping method based on graph partitioning can globally optimize the distance between quantum bits and control the additional circuit depth of the mapping as a whole. That is, for any input logic circuit, the additional circuit depth of the algorithm output hardware compilable circuit is at most O(rt(G)), where the additional circuit depth is the ratio of the output circuit to the input circuit depth.

[0148] The following is an embodiment of the device of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the method of the present application.

[0149] Please refer to Figure 8 , which shows a block diagram of a quantum bit mapping device provided by an embodiment of the present application. The device has the function of implementing the above-mentioned quantum bit mapping method, and the function can be implemented by hardware, or by hardware executing corresponding software. The device can be a computer device, or it can be set in a computer device. The device 800 may include: an acquisition module 810, a generation module 820 and a mapping module 830.

[0150] The acquisition module 810 is used to acquire a coupling graph corresponding to the quantum device, where each vertex in the coupling graph represents a quantum bit in the quantum device, and the edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices.

[0151] A generation module 820 is used to generate at least two connected subgraphs according to the coupling graph, wherein the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph.

[0152] The mapping module 830 is used to perform quantum bit mapping on the logic circuit based on the at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit.

[0153] In some embodiments, the generating module 820 includes: a first generating unit and a second generating unit ( Figure 8 not shown).

[0154] The first generating unit is used to generate a first vertex set family and a second vertex set family according to the coupling graph, wherein the first vertex set family includes at least one vertex set, the second vertex set family includes at least one vertex set, and each vertex set includes at least two vertices in the coupling graph.

[0155] The second generating unit is used to generate a connected subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family to obtain the at least two connected subgraphs.

[0156] The first vertex group and the second vertex group satisfy the following conditions:

[0157] The subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family is a connected graph;

[0158] There are no identical vertices in any two vertex sets in the first vertex set family, and there are no identical vertices in any two vertex sets in the second vertex set family;

[0159] The number of vertices contained in each vertex set in the first vertex set family and the second vertex set family is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph;

[0160] The total number of vertices in the first vertex group and the second vertex group is equal to a constant multiple of the number of vertices in the coupling graph.

[0161] In some embodiments, the first generation unit includes: a construction subunit, a first generation subunit and a second generation subunit ( Figure 8 not shown).

[0162] The construction subunit is used to construct a maximum matching of the coupling graph, where the maximum matching includes at least one edge in the coupling graph.

[0163] The first generating subunit is used to generate the first vertex set family according to the maximum matching, each vertex set in the first vertex set family corresponds to two vertices connected by an edge included in the maximum matching.

[0164] The second generating subunit is used to generate the second vertex set group according to the first vertex set group.

[0165] In some embodiments, the second generating subunit is used to:

[0166] According to the first vertex set, determine the initialized set T p , the initialized set T p includes vertices belonging to the coupling graph and not belonging to the first vertex set, and p is a positive integer with an initial value of 1;

[0167] According to the set T initialized p , determine the initialized set S p , the initialized set S p The first vertex set and the initialized set T are included in p The vertices in are connected to each other;

[0168] Determine the initialized collection is an empty set, and determines the initialized set A 0,p is an empty set, i is a positive integer with an initial value of 1;

[0169] The set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p In which, \ represents the difference of two sets, and the adjacent vertices of the i-th vertex refer to the vertices connected to the i-th vertex;

[0170] Will gather With set A i,p The union of is determined as the set

[0171] If i is less than k 1 , then let i=i+1, and again from the set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in start execution; among them, k 1 For the set S 1 The number of vertices in ;

[0172] If i equals k 1 , then in Greater than or equal to |T p | / 2, the second vertex set cluster is generated; wherein the vertex set included in the second vertex set cluster is the set and the set S p The union of the i-th vertex in , represent The number of vertices in |T p | represents the set T p The number of vertices in ;

[0173] Will gather Determine the set T p+1 ;

[0174] Based on the set T p and k p Determine the set S p+1 ;

[0175] |S p+1 |Determined as k p+1 ; Among them, |S p+1 | represents the set S p+1 The number of vertices in ;

[0176] If p is less than |T 1 |, then let p = p + 1, and again from the said set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in start to execute;

[0177] If p equals |T 1 |, then the process ends and the second vertex set is finally generated.

[0178] In some embodiments, the second generating subunit is used to:

[0179] If the set S p The i-th vertex in the set At most adjacent vertices, then select the i-th vertex in the set All adjacent vertices in are put into the set A i,p middle;

[0180] If the set S p The i-th vertex in the set More than adjacent vertices, then select the i-th vertex in the set Most hits The adjacent vertices are put into the set A i,p middle;

[0181] in, Represents |T p | / k p Round up.

[0182] In some embodiments, the mapping module 830 includes: a first replacement unit, a third generation unit, a second replacement unit, a fourth generation unit and an acquisition unit ( Figure 8 not shown).

[0183] A first permutation unit is used to permute a first number of logic bit pairs in the logic circuit according to the at least two connected subgraphs; wherein the first number is the number of edges included in the maximum matching of the coupling graph, and each logic bit pair corresponds to two quantum bits acted on by a two-qubit gate in the logic circuit.

[0184] The third generating unit is configured to generate a first portion of hardware compilable circuits corresponding to the first number of logic bit pairs.

[0185] The second replacement unit is used to replace the remaining logic bit pairs in the logic circuit according to the at least two connected subgraphs.

[0186] The fourth generating unit is configured to generate a second portion of hardware compilable circuits corresponding to the remaining logic bit pairs.

[0187] An acquiring unit is used to acquire a hardware compilable circuit equivalent to the logic circuit according to the first part of the hardware compilable circuit and the second part of the hardware compilable circuit.

[0188] In some embodiments, the mapping module 830 further includes a third replacement unit ( Figure 8 not shown).

[0189] The third replacement unit is used to replace each of the logic bits in the logic circuit to an original position.

[0190] It should be noted that the device provided in the above embodiment, when implementing its functions, is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0191] Please refer to Fig. 9 , which shows a structural block diagram of a computer device 900 provided in one embodiment of the present application.

[0192] Typically, the computer device 900 includes a processor 910 and a memory 920 .

[0193] The processor 910 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 910 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). The processor 910 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 910 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 910 may also include an AI processor for processing computing operations related to machine learning.

[0194] The memory 920 may include one or more computer-readable storage media, which may be non-transitory. The memory 920 may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 920 is used to store a computer program, which is configured to be executed by one or more processors to implement the above-mentioned quantum bit mapping method.

[0195] Those skilled in the art will understand that Fig. 9 The structure shown in the figure does not constitute a limitation on the computer device 900, and the computer device 900 may include more or less components than those shown in the figure, or combine some components, or adopt a different arrangement of components.

[0196] In some embodiments, a computer-readable storage medium is also provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the above-mentioned quantum bit mapping method.

[0197] Optionally, the computer readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives) or optical disks, etc. Among them, the random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0198] In some embodiments, a computer program product is also provided, which includes a computer program stored in a computer-readable storage medium, and a processor reads and executes the computer program from the computer-readable storage medium to implement the above-mentioned quantum bit mapping method.

[0199] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0200] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A quantum bit mapping method, characterized in that: The method comprises: Obtaining a coupling graph corresponding to a quantum device, wherein each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices; At least two connected subgraphs are generated according to the coupling graph, the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph; Based on the at least two connected subgraphs, quantum bit mapping is performed on the logic circuit to obtain a hardware compilable circuit equivalent to the logic circuit.

2. The method according to claim 1, characterized in that: Generating at least two connected subgraphs according to the coupling graph includes: Generate a first vertex set family and a second vertex set family according to the coupling graph, wherein the first vertex set family includes at least one vertex set, the second vertex set family includes at least one vertex set, and each vertex set includes at least two vertices in the coupling graph; Generate a connected subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family to obtain the at least two connected subgraphs; The first vertex group and the second vertex group satisfy the following conditions: The subgraph corresponding to each vertex set in the first vertex set family and the second vertex set family is a connected graph; There are no identical vertices in any two vertex sets in the first vertex set family, and there are no identical vertices in any two vertex sets in the second vertex set family; The number of vertices contained in each vertex set in the first vertex set family and the second vertex set family is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph; The total number of vertices in the first vertex group and the second vertex group is equal to a constant multiple of the number of vertices in the coupling graph.

3. The method according to claim 2, characterized in that Generating the first vertex cluster and the second vertex cluster according to the coupling graph comprises: Constructing a maximum matching of the coupling graph, wherein the maximum matching includes at least one edge in the coupling graph; According to the maximum matching, generating the first vertex set family, each vertex set in the first vertex set family corresponds to two vertices connected by an edge included in the maximum matching; The second vertex set is generated according to the first vertex set.

4. The method according to claim 3, characterized in that: The step of generating the second vertex set according to the first vertex set includes: According to the first vertex set, determine the initialized set T p , the initialized set T p includes vertices belonging to the coupling graph and not belonging to the first vertex set, and p is a positive integer with an initial value of 1; According to the set T initialized p , determine the initialized set S p , the initialized set S p The first vertex set and the initialized set T are included in p The vertices in are connected to each other; Determine the initialized collection is an empty set, and determines the initialized set A 0,p is an empty set, i is a positive integer with an initial value of 1; The set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p In which, \ represents the difference of two sets, and the adjacent vertices of the i-th vertex refer to the vertices connected to the i-th vertex; Will gather With set A i,p The union of is determined as the set If i is less than k1, let i=i+1, and again set the set S from p The u-th vertex in the set The adjacent vertices in are put into set A i,p The steps in are executed; wherein k1 is the number of vertices in the set S1; If i is equal to k1, then Greater than or equal to |T p | / 2, the second vertex set cluster is generated; wherein the vertex set included in the second vertex set cluster is the set and the set S p The union of the i-th vertex in , represent The number of vertices in |T p | represents the set T p The number of vertices in ; Will gather Determine the set T p+1 ; Based on the set T p and k p Determine the set S p+1 ; |S p+1 |Determined as k p+1 ; Among them, |S p+1 | represents the set S p+1 The number of vertices in ; If p is less than |T1|, then set p=p+1, and again set the set S from p The i-th vertex in the set The adjacent vertices in are put into set A i,p The steps in start to execute; If p is equal to |T1|, the process ends and the second vertex cluster is finally generated.

5. The method according to claim 4, characterized in that The set S p The i-th vertex in the set The adjacent vertices in are put into set A i,p Including: If the set S p The i-th vertex in the set At most adjacent vertices, then select the i-th vertex in the set All adjacent vertices in are put into the set A i,p middle; If the set S p The i-th vertex in the set More than adjacent vertices, then select the i-th vertex in the set Most hits The adjacent vertices are put into the set A i,p middle; in, Represents |T p | / k p Round up.

6. The method according to any one of claims 1 to 5, characterized in that: The step of performing quantum bit mapping on the logic circuit based on the at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit comprises: According to the at least two connected subgraphs, a first number of logic bit pairs in the logic circuit are permuted; wherein the first number is the number of edges included in the maximum matching of the coupling graph, and each logic bit pair corresponds to two qubits acted on by a two-qubit gate in the logic circuit, generating a first portion of hardware compilable circuits corresponding to the first number of logic bit pairs; According to the at least two connected subgraphs, permuting remaining logic bit pairs in the logic circuit; Generating a second portion of hardware compilable circuits corresponding to the remaining logic bit pairs; A hardware compilable circuit equivalent to the logic circuit is obtained according to the first part of the hardware compilable circuit and the second part of the hardware compilable circuit.

7. The method according to claim 6, characterized in that After obtaining a hardware compilable circuit equivalent to the logic circuit according to the first part of the hardware compilable circuit and the second part of the hardware compilable circuit, the method further includes: Each of the logic bits in the logic circuit is replaced to an original position.

8. A quantum bit mapping device, characterized in that: The device comprises: An acquisition module is used to acquire a coupling graph corresponding to a quantum device, wherein each vertex in the coupling graph represents a quantum bit in the quantum device, and an edge between two vertices indicates that a two-qubit gate is allowed to directly act on the quantum bits corresponding to the two vertices; A generating module, configured to generate at least two connected subgraphs according to the coupling graph, wherein the number of vertices of each connected subgraph is greater than or equal to 2 and less than or equal to the number of routes of the coupling graph, and the sum of the number of vertices of the at least two connected subgraphs is equal to a constant multiple of the number of vertices of the coupling graph; wherein the number of routes of the coupling graph is the maximum number of permutation rounds of all permutations on the coupling graph; A mapping module is used to perform quantum bit mapping on the logic circuit based on the at least two connected subgraphs to obtain a hardware compilable circuit equivalent to the logic circuit.

9. A computer device, characterized in that: The computer device includes a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the quantum bit mapping method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the quantum bit mapping method as described in any one of claims 1 to 7.

11. A computer program product, characterized in that The computer program product comprises a computer program, which is loaded and executed by a processor to implement the quantum bit mapping method according to any one of claims 1 to 7.

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