Memory signal calibration device and method

Abstract

The invention relates to a memory signal calibration device and method. The gating circuit generates a data flash control enabling setting signal according to the setting control signal, generates an enabling state of the data flash control enabling signal, and gates the data flash control signal according to the enabling state to generate a gated data flash control signal. The correction circuit is configured to: generate a pulse indication signal having an indication state corresponding to a pulse interval of the data strobe signal; delaying the data flash control enabling setting signal to generate a first delay signal; delaying the first delayed signal to generate a second delayed signal; sampling the pulse indication signal according to the first delay signal and the second delay signal to generate a sampling result; and enabling the enabling signal setting circuit to adjust the setting control signal according to the sampling result so as to control the gating circuit to adjust the data flash control enabling setting signal and the time sequence of the data flash control enabling signal.

Description

Technical Field

[0001] The present invention relates to a memory access technology, and in particular to a memory signal calibration device and method. Background Art

[0002] Generally speaking, when a double data rate synchronous dynamic random access memory (DDR SDRAM) is read, a data strobe (DQS) signal and a data (DQ) signal are sent to a memory access interface device. The data strobe signal includes a tristate interval, a preamble interval, and a pulse interval including multiple clocks in sequence. The tristate interval is the signal between the previous access operation and the current read operation. The preamble interval is used to remind the memory access interface device to prepare to read the data signal according to the pulse of the subsequent pulse interval.

[0003] In order to correctly allow the sampling circuit to sample the data signal according to the pulse interval of the data strobe signal instead of the tri-state interval, the memory access interface device uses the period of the specific level (e.g., high level) of the data strobe enable (DQS_EN) signal to cover the pulse interval of the data strobe signal. Preferably, the memory access interface device changes the level of the data strobe enable signal from the original level to the specific level in the middle of the leading interval of the data strobe signal, and restores the level of the data strobe enable signal to the original level according to the received read / write command. The period of the specific level of the data strobe enable signal can correctly cover the pulse interval of the data strobe signal instead of the tri-state interval. The sampling circuit can sample the data signal according to the pulse interval of the data strobe signal.

[0004] However, even if the position of the leading interval of the data strobe signal is correctly found and the time point of the level change of the data strobe enable signal is correctly set using the position, the position of the leading interval may change with the change of voltage and / or temperature. For a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), the position change amplitude of the leading interval of the data strobe signal may exceed the length of the leading interval, so that the data strobe enable signal cannot correctly cover the pulse interval of the data strobe signal, and the sampling circuit may sample the data signal too early according to an erroneous trigger signal (such as a tri-state interval) to obtain erroneous read data, or sample the data signal too late to obtain complete read data.

[0005] To address the above problems, the applicant has previously proposed solutions in US Patent No. 10978118 and US Patent Application No. 111142066. However, due to the use of delay circuits implemented with logic gates and increasingly high frequency data strobe signals, the timing judgment of the data strobe signal still has the problem of insufficient accuracy. Summary of the invention

[0006] In view of the problems in the prior art, an object of the present invention is to provide a memory signal calibration device and method to improve the prior art.

[0007] The present invention includes a memory signal calibration device, including: an enable signal setting circuit, a gating circuit and a correction circuit. The enable signal setting circuit is configured to generate a setting control signal. The gating circuit is configured to generate a data flash enable setting signal having a single pulse according to the setting control signal, generate an enable state of the data flash enable signal according to the single pulse start to maintain a preset timing, and gate the data flash signal according to the enable state to generate a gated data flash signal. The correction circuit is configured to: generate a pulse indication signal, the pulse indication signal has an indication state corresponding to the pulse interval of the data flash signal; delay the data flash enable setting signal to generate a first delay signal; delay the first delay signal to generate a second delay signal; sample the pulse indication signal according to the first delay signal and the second delay signal to generate a sampling result; and enable the enable signal setting circuit to adjust the setting control signal according to the sampling result, thereby controlling the gating circuit to adjust the timing of the data flash enable setting signal and the data flash enable signal.

[0008] The present invention also includes a memory signal calibration method, which is applied to a memory signal calibration device, including: generating a setting control signal by an enable signal setting circuit; generating a data flash enable setting signal with a single pulse by a gating circuit according to the setting control signal, generating an enable state of the data flash enable signal according to the single pulse start to maintain a preset timing, and gating the data flash signal according to the enable state to generate a gated data flash signal; generating a pulse indication signal by a correction circuit, the pulse indication signal having an indication state corresponding to a pulse interval of the data flash signal; delaying the data flash enable setting signal by the correction circuit to generate a first delay signal; delaying the first delay signal by the correction circuit to generate a second delay signal; sampling the pulse indication signal by the correction circuit according to the first delay signal and the second delay signal to generate a sampling result; and enabling the enable signal setting circuit to adjust the setting control signal according to the sampling result by the correction circuit, thereby controlling the gating circuit to adjust the timing of the data flash enable setting signal and the data flash enable signal.

[0009] The features, implementation and technical effects of the present disclosure are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram showing a memory signal calibration device according to an embodiment of the present invention;

[0011] Figure 2A waveform diagram showing a signal related to the operation of a memory signal calibration device according to an embodiment of the present invention;

[0012] Figure 3 A block diagram showing a correction circuit in one embodiment of the present invention;

[0013] Figure 4 A waveform diagram showing signals related to the operation of a memory signal calibration device according to another embodiment of the present invention;

[0014] Figure 5 A waveform diagram showing signals related to the operation of a memory signal calibration device in another embodiment of the present invention; and

[0015] Figure 6 A flow chart of a memory signal calibration method according to an embodiment of the present invention is shown.

[0016] Explanation of symbols

[0017] 100: Memory signal calibration device

[0018] 110: Enable signal setting circuit

[0019] 120: Gate control circuit

[0020] 130: Correction circuit

[0021] 300: Pulse indication signal generating circuit

[0022] 305: First delay circuit

[0023] 310: Second delay circuit

[0024] 315: First sampling trigger

[0025] 320: Second sampling trigger

[0026] 325: First non-inverting delay flip-flop

[0027] 330: First inverting delay trigger

[0028] 335: The first multiplexer

[0029] 340: Second non-inverting delay flip-flop

[0030] 345: Second inverting delay flip-flop

[0031] 350: Second multiplexer

[0032] 600: Memory signal calibration method

[0033] S610~S670: Steps

[0034] A, B: Direction

[0035] CK: clock signal

[0036] DRI1: First inversion delay result

[0037] DRI2: Second inversion delay result

[0038] DRN1: First non-inverting delayed result

[0039] DRN2: Second non-inverting delayed result

[0040] DQS: data strobe signal

[0041] DQS_EN: Data flash enable signal

[0042] DQS_EN_SET: Data flash enable setting signal

[0043] DQS_EN_SET_EARLY: First delayed signal

[0044] DQS_EN_SET_LATE: Second delayed signal

[0045] DQSG: gated data strobe signal

[0046] PD1: First delayed pulse

[0047] PD2: Second delayed pulse

[0048] PID: Pulse indication signal

[0049] PRE: Preamble interval

[0050] PU: Single Pulse

[0051] PUL: Pulse interval

[0052] SET: Set control signal

[0053] T1, T2: timing points

[0054] TRI: Tri-state interval

[0055] SR: Sampling results

[0056] SR_EARLY: First sampling state

[0057] SR_LATE: Second sampling state DETAILED DESCRIPTION

[0058] One object of the present invention is to provide a memory signal calibration device and method, which delays the data strobe enable setting signal without the need for logic gates to generate a delayed signal for sampling, thereby preventing the signal from being affected by temperature, voltage and process. In addition, by using a pulse indication signal corresponding to the pulse interval of the data strobe signal as the object to be sampled instead of the data strobe signal itself, a sampling result with a greater margin can be obtained because the frequency of the pulse indication signal is much lower than that of the data strobe signal. Not only the accuracy of the timing judgment of the data strobe signal or the accuracy of the timing adjustment of the data strobe enable signal can be improved.

[0059] Please also refer to Figure 1 as well as Figure 2 . Figure 1 A block diagram of a memory signal calibration device 100 according to an embodiment of the present invention is shown. Figure 2 The waveform diagram of the signals related to the operation of the memory signal calibration device 100 according to one embodiment of the present invention is shown.

[0060] In one embodiment, the memory signal calibration device 100 is disposed in a memory access interface device, and the memory access interface device is a device in a memory system for accessing a memory device according to a memory access controller.

[0061] In more detail, the memory access controller may be controlled by, for example but not limited to, a processor to generate relevant access instructions. When the access instruction is used to perform a read operation, the memory access interface device performs signal processing on the access instruction to read the memory device, and transmits the data returned by the memory device to the memory access controller, which is then transmitted to the processor by the memory access controller.

[0062] In one embodiment, the memory device is a double data rate (DDR) memory. In addition to returning data, the memory device also transmits a data strobe signal DQS to the memory access interface device, so that the memory access interface device samples the received data according to the data strobe signal DQS. The memory signal calibration device 100 can be configured to calibrate the timing of receiving the data strobe signal DQS.

[0063] The memory signal calibration device 100 includes an enable signal setting circuit 110 , a gate control circuit 120 and a correction circuit 130 .

[0064] The enable signal setting circuit 110 is configured to generate a setting control signal SET according to a system clock signal CK of the memory signal calibration device 100. In one embodiment, the enable signal setting circuit 110 includes a coarse clock edge selector and a fine delay chain controller (not shown). This embodiment is disclosed in the applicant's U.S. patent application with application number 16 / 177,603, but the present invention is not limited thereto.

[0065] The gate control circuit 120 is electrically coupled to the enable signal setting circuit 110. The gate control circuit 120 first generates a data flash enable setting signal DQS_EN_SET having a single pulse PU according to the setting control signal SET.

[0066] like Figure 2 As shown, in this embodiment, the data flash control enable setting signal DQS_EN_SET is maintained at a high state when the pulse PU is not generated, and generates a low pulse PU at the timing point T1. In other embodiments, the data flash control enable setting signal DQS_EN_SET can also generate a high pulse as required.

[0067] The gate control circuit 120 generates the enable state of the data flash control enable signal DQS_EN according to the single pulse PU of the data flash control enable setting signal DQS_EN_SET to maintain the preset timing. Since the data flash control enable signal DQS_EN is a signal only used inside the gate control circuit 120, it is not shown in FIG. Figure 1 In Figure 2 The waveform is shown.

[0068] like Figure 2 As shown, the data flash enable signal DQS_EN is originally in the disabled state, and changes from the disabled state to the enabled state corresponding to the timing point T1 and maintains the preset timing, so as to return from the enabled state to the disabled state at the timing point T2. In this embodiment, the disabled state is a low state, and the enabled state is a high state. However, the present invention is not limited to this.

[0069] The gating circuit 120 then gates the data strobe signal DQS having the receiving timing according to the enabling state of the data strobe enable signal DQS_EN to generate a gated data strobe signal DQSG.

[0070] In one embodiment, the data strobe signal DQS includes a preamble interval PRE and a pulse interval PUL. In one embodiment, the data strobe signal DQS may be received by the gating circuit 120 through a signal pad (not shown), and the signal pad may be electrically coupled to a terminal impedance calibration circuit (not shown) so that the terminal impedance calibration circuit adjusts the signal level of the tri-state interval TRI of the preamble interval PRE to a high state or a low state. The present invention is not limited thereto.

[0071] Ideally, the gate control circuit 120 can be configured as follows according to the enabling state of the data flash enable signal DQS_EN. Figure 2 As shown, the leading interval PRE and the pulse interval PUL in the corresponding data strobe signal DQS are gated and output to generate a gated data strobe signal DQSG.

[0072] However, when the data strobe signal DQS is received too early or too late, the data strobe enable signal DQS_EN cannot accurately gate the data strobe signal DQS, and thus data cannot be accurately sampled according to the subsequently generated gated data strobe signal DQSG.

[0073] The calibration circuit 130 can calibrate the timing of the data strobe enable setting signal DQS_EN_SET and the data strobe enable signal DQS_EN through the operation of its internal components, so as to accurately gate the data strobe signal DQS. The structure and operation of the calibration circuit 130 will be described in detail below.

[0074] Please refer to Figure 3 . Figure 3 The block diagram of the calibration circuit 130 in one embodiment of the present invention is shown. The calibration circuit 130 comprises a pulse indication signal generating circuit 300, a first delay circuit 305, a second delay circuit 310, a first sampling trigger 315 and a second sampling trigger 320.

[0075] The pulse indication signal generating circuit 300 is configured to receive the data strobe signal DQS to generate the pulse indication signal DQS as shown in FIG. Figure 2 The pulse indication signal PID in the embodiment has an indication state corresponding to the pulse interval PUL of the data flash control signal DQS. In the present embodiment, the indication state is a high state.

[0076] The first delay circuit 305 is configured to delay the data strobe enable setting signal DQS_EN_SET to generate a first delayed signal DQS_EN_SET_EARLY.

[0077] In one embodiment, the first delay circuit 305 includes a first non-inverting delay flip-flop 325 , a first inverting delay flip-flop 330 , and a first multiplexer 335 .

[0078] The first non-inverting delay flip-flop 325 is configured to receive the data strobe enable setting signal DQS_EN_SET and the clock signal CK to generate a first non-inverting delay result DRN1 delayed by one cycle relative to the data strobe enable setting signal DQS_EN_SET.

[0079] The first inverted delay flip-flop 330 is configured to receive the data strobe enable setting signal DQS_EN_SET and the inverted clock signal CK to generate a first inverted delay result DRI1 that is delayed by half a cycle relative to the data strobe enable setting signal DQS_EN_SET. Figure 3 In FIG. 1 , a “○” symbol is added to the terminal of the first inverting delay flip-flop 330 receiving the clock signal CK to indicate inversion.

[0080] The first multiplexer 335 is configured to select one of the first non-inverted delay result DRN1 and the first inverted delay result DRI1 as the first delay signal DQS_EN_SET_EARLY.

[0081] The second delay circuit 310 is configured to delay the first delayed signal DQS_EN_SET_EARLY to generate a second delayed signal DQS_EN_SET_LATE.

[0082] In one embodiment, the second delay circuit 310 includes a second non-inverting delay flip-flop 340 , a second inverting delay flip-flop 345 , and a second multiplexer 350 .

[0083] The second non-inverting delay flip-flop 340 is configured to receive the first delay signal DQS_EN_SET_EARLY and the clock signal CK to generate a second non-inverting delay result DRN2 delayed by one cycle relative to the first delay signal DQS_EN_SET_EARLY.

[0084] The second inverted delay flip-flop 345 is configured to receive the first delay signal DQS_EN_SET_EARLY and the inverted clock signal CK to generate a second inverted delay result DRI2 delayed by half a period relative to the first delay signal DQS_EN_SET_EARLY. Figure 3 In FIG. 1 , a “○” symbol is added to the terminal of the second inverting delay flip-flop 345 receiving the clock signal CK to indicate inversion.

[0085] The second multiplexer 350 is configured to select one of the second non-inverted delay result DRN2 and the second inverted delay result DRI2 as the second delay signal DQS_EN_SET_LATE.

[0086] It should be noted that Figure 3 The structures of the first delay circuit 305 and the second delay circuit 310 are only examples. In other embodiments, the first delay circuit 305 and the second delay circuit 310 may include more inverting delay flip-flops and non-inverting delay flip-flops to achieve more cycles of delay. The present invention is not limited thereto.

[0087] exist Figure 2In the embodiment, the first signal delay amount of the first delay signal DQS_EN_SET_EARLY relative to the data flash enable setting signal DQS_EN_SET is one cycle, and the second signal delay amount of the second delay signal DQS_EN_SET_LATE relative to the first delay signal DQS_EN_SET_EARLY is also one cycle. Therefore, the first signal delay amount corresponding to the first delay circuit 305 and the second signal delay amount corresponding to the second delay circuit 310 are the same.

[0088] However, in practical applications, the first signal delay amount corresponding to the first delay circuit 305 and the second signal delay amount corresponding to the second delay circuit 310 may also be set to be different. For example, the first signal delay amount corresponding to the first delay circuit 305 and the second signal delay amount corresponding to the second delay circuit 310 may be set to half a cycle and one cycle, respectively. The present invention is not limited thereto.

[0089] The first sampling trigger 315 and the second sampling trigger 320 sample the pulse indication signal PID according to the first delay signal DQS_EN_SET_EARLY and the second delay signal DQS_EN_SET_LATE to generate a sampling result SR.

[0090] In one embodiment, the first sampling trigger 315 is configured to receive the pulse indication signal PID and the first delay signal DQS_EN_SET_EARLY for sampling to generate the first sampling state SR_EARLY included in the sampling result SR.

[0091] Since the first delayed signal DQS_EN_SET_EARLY has a first delayed pulse PD1 generated by delaying a single pulse PU corresponding to the data flash enable setting signal DQS_EN_SET, the first sampling trigger 315 samples the pulse indication signal PID according to the first delayed pulse PD1. In one embodiment, the first sampling trigger 315 samples the pulse indication signal PID according to the negative edge (i.e., from a high state to a low state) of the first delayed pulse PD1 through inversion to become a positive edge.

[0092] The second sampling trigger 320 is configured to receive the pulse indication signal PID and the second delay signal DQS_EN_SET_LATE for sampling to generate a second sampling state SR_LATE included in the sampling result SR.

[0093] Since the second delayed signal DQS_EN_SET_EARLY has a second delayed pulse PD2 generated by delaying the first delayed pulse PD1 of the first delayed signal DQS_EN_SET_EARLY, the second sampling trigger 320 samples the pulse indication signal PID according to the second delayed pulse PD2. In one embodiment, the second sampling trigger 320 samples the pulse indication signal PID according to the negative edge (i.e., from a high state to a low state) of the second delayed pulse PD2 which is inverted to become a positive edge.

[0094] The first sampling trigger 315 and the second sampling trigger 320 transmit the first sampling state SR_EARLY and the second sampling state SR_LATE to the enable signal setting circuit 110 respectively, so that the enable signal setting circuit 110 adjusts the setting control signal SET according to the sampling result SR, thereby controlling the gating circuit 120 to adjust the timing of the data flash enable setting signal DQS_EN_SET and the data flash enable signal DQS_EN.

[0095] In one embodiment, when the sampling result SR shows that the first delay signal DQS_EN_SET_EARLY and the second delay signal DQS_EN_SET_LATE are sampled to different sampling states, for example Figure 2 When the first sampling state SR_EARLY is low and the second sampling state SR_LATE is high, the enable signal setting circuit 110 determines that the receiving timing of the data flash signal DQS corresponds to a "moderate" state, and controls the gating circuit 120 not to adjust the timing of the data flash enable setting signal DQS_EN_SET and the data flash enable signal DQS_EN by setting the control signal SET.

[0096] In one embodiment, when the sampling result SR shows that the first delay signal DQS_EN_SET_EARLY and the second delay signal DQS_EN_SET_LATE are sampled to the same sampling state, the enable signal setting circuit 110 determines whether the receiving timing of the data strobe signal DQS corresponds to the "too early" state or the "too late" state. At this time, the timing of the data strobe enable setting signal DQS_EN_SET and the data strobe enable signal DQS_EN needs to be adjusted.

[0097] Please refer to Figure 4 . Figure 4 The waveform diagram of signals related to the operation of the memory signal calibration device 100 according to another embodiment of the present invention is shown.

[0098] When the sampling result SR shows that the first delay signal DQS_EN_SET_EARLY and the second delay signal DQS_EN_SET_LATE are sampled to the same sampling state and the sampling state is the same as the indication state, for example Figure 4 When the first sampling state SR_EARLY and the second sampling state SR_LATE shown are both high and the same as the indicated state, the enable signal setting circuit 110 determines that the receiving timing of the data flash signal DQS corresponds to the "too late" state, and controls the gating circuit 120 by setting the control signal SET to adjust the timing of the data flash enable setting signal DQS_EN_SET and the data flash enable signal DQS_EN "forward" according to direction A.

[0099] Please refer to Figure 5 . Figure 5 The waveform diagram of signals related to the operation of the memory signal calibration device 100 according to another embodiment of the present invention is shown.

[0100] When the sampling result SR shows that the first delay signal DQS_EN_SET_EARLY and the second delay signal DQS_EN_SET_LATE are sampled to the same sampling state and the sampling state is different from the indication state, for example Figure 5 When the first sampling state SR_EARLY and the second sampling state SR_LATE shown are both low states and different from the indicated state, the enable signal setting circuit 110 determines that the receiving timing of the data flash signal DQS corresponds to the "too early" state, and controls the gating circuit 120 by setting the control signal SET to adjust the timing of the data flash enable setting signal DQS_EN_SET and the data flash enable signal DQS_EN "backward" according to direction B.

[0101] In one embodiment, the timing of the data flash enable setting signal DQS_EN_SET and the data flash enable signal DQS_EN can be adjusted once or multiple times, and each adjustment can be performed by, for example but not limited to, the length of a cycle, until the first delay signal DQS_EN_SET_EARLY and the second delay signal DQS_EN_SET_LATE are sampled to different sampling states.

[0102] In some technologies, in order to determine the timing of the data strobe signal, the memory signal calibration device is often provided with a combination of logic gates, such as NAND gates, to delay the data strobe enable setting signal and / or the data strobe signal, and generate a related judgment signal accordingly. This method often causes the delay time to change because the logic gate is easily affected by temperature, voltage and process, thereby making the timing judgment inaccurate. In addition, the method of directly using the data strobe signal for judgment is also prone to inaccurate timing judgment due to the high frequency of the data strobe signal.

[0103] The memory signal calibration device of the present invention can generate a delayed signal for sampling by delaying the data strobe enable setting signal without the need for a logic gate, thereby preventing the signal from being affected by temperature, voltage and process. In addition, by using a pulse indication signal corresponding to the pulse interval of the data strobe signal as the object to be sampled instead of the data strobe signal itself, a sampling result with a greater margin can be obtained because the frequency of the pulse indication signal is much lower than that of the data strobe signal. Not only the accuracy of the timing judgment of the data strobe signal or the accuracy of the timing adjustment of the data strobe enable signal can be improved.

[0104] Please refer to Figure 6 . Figure 6 A flow chart of a memory signal calibration method 200 according to an embodiment of the present invention is shown.

[0105] In addition to the aforementioned apparatus, the present invention also discloses a memory signal calibration method 600, which is applied to, for example, but not limited to Figure 1 In the memory signal calibration device 100. An embodiment of the memory signal calibration method 600 is as follows: Figure 6 As shown, the following steps are included.

[0106] In step S610 , the enable signal setting circuit 110 generates a setting control signal SET.

[0107] In step S620, the gating circuit 120 generates a data strobe enable setting signal DQS_EN_SET having a single pulse according to the setting control signal SET, starts generating an enable state of the data strobe enable signal DQS_EN according to the single pulse to maintain a preset timing, and gates the data strobe signal DQS according to the enable state to generate a gated data strobe signal DQSG.

[0108] In step S630 , the calibration circuit 130 generates a pulse indicating signal PID. The pulse indicating signal PID has an indicating state corresponding to the pulse period PUL of the data strobe signal DQS.

[0109] In step S640 , the calibration circuit 130 delays the data strobe enable setting signal DQS_EN_SET to generate a first delayed signal.

[0110] In step S650 , the calibration circuit 130 delays the first delay signal DQS_EN_SET_EARLY to generate a second delay signal DQS_EN_SET_LATE.

[0111] In step S660 , the calibration circuit 130 samples the pulse indication signal PID according to the first delay signal DQS_EN_SET_EARLY and the second delay signal DQS_EN_SET_LATE to generate a sampling result SR.

[0112] In step S670 , the calibration circuit 130 enables the enable signal setting circuit 110 to adjust the setting control signal SET according to the sampling result SR, thereby controlling the gating circuit 120 to adjust the timing of the data flash enable setting signal DQS_EN_SET and the data flash enable signal DQS_EN.

[0113] It should be noted that the above implementation is only an example, and those skilled in the art may make changes in other embodiments without departing from the concept of the present invention.

[0114] In summary, the memory signal calibration device and method of the present invention can delay the data strobe enable setting signal without the need for logic gates to generate a delayed signal for sampling, thereby preventing the signal from being affected by temperature, voltage, and process. In addition, by using the pulse indication signal corresponding to the pulse interval of the data strobe signal as the object to be sampled instead of the data strobe signal itself, the frequency of the pulse indication signal is much lower than that of the data strobe signal, so that a more tolerant sampling result can be obtained. Not only the accuracy of the timing judgment of the data strobe signal or the accuracy of the timing adjustment of the data strobe enable signal can be improved.

[0115] Although the embodiments of the present disclosure are described above, the embodiments are not intended to limit the present disclosure. Technicians in this technical field may make changes to the technical features of the present disclosure based on the explicit or implicit contents of the present disclosure. All these changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be based on what is defined in the claims of this specification.

Claims

1. A memory signal calibration device, comprising: An enable signal setting circuit configured to generate a setting control signal; a gating circuit configured to generate a data strobe enable setting signal having a single pulse according to the setting control signal, to start generating an enable state of the data strobe enable signal according to the single pulse to maintain for a preset time, and to gate a data strobe signal having a receiving timing according to the enable state to generate a gated data strobe signal; and A correction circuit is configured to: Generate a pulse indication signal, the pulse indication signal having an indication state corresponding to a pulse interval of the data flash signal; Delaying the data flash enable setting signal to generate a first delay signal; Delaying the first delayed signal to generate a second delayed signal; Sampling the pulse indication signal according to the first delay signal and the second delay signal to generate a sampling result; and The enabling signal setting circuit is made to adjust the setting control signal according to the sampling result, thereby controlling the gate control circuit to adjust the timing of the data flash enabling setting signal and the data flash enabling signal.

2. The memory signal calibration device as claimed in claim 1 , wherein when the sampling result shows that the first delay signal and the second delay signal are sampled to the same sampling state and the sampling state is the same as the indication state, the enable signal setting circuit determines that the receiving timing of the data strobe signal corresponds to a premature state, and controls the gate control circuit to adjust the timing of the data strobe enable setting signal and the data strobe enable signal forward through the setting control signal; When the sampling result shows that the first delay signal and the second delay signal are sampled to the same sampling state and the sampling state is different from the indication state, the enable signal setting circuit determines that the receiving timing of the data flash control signal corresponds to a too late state, and controls the gate control circuit to adjust the timing of the data flash control enable setting signal and the data flash control enable signal backward through the setting control signal; When the sampling result shows that the first delay signal and the second delay signal are sampled to different sampling states, the enable signal setting circuit determines that the receiving timing of the data flash control signal corresponds to a moderate state, and controls the gate circuit through the setting control signal not to adjust the timing of the data flash control enable setting signal and the data flash control enable signal.

3. The memory signal calibration device as claimed in claim 1, wherein the correction circuit comprises: a pulse indication signal generating circuit configured to receive the data strobe signal to generate the pulse indication signal; a first sampling trigger configured to receive the pulse indication signal and the first delay signal for sampling to generate a first sampling state included in the sampling result; and A second sampling trigger is configured to receive the pulse indication signal and the second delay signal for sampling to generate a second sampling state included in the sampling result.

4. The memory signal calibration device as claimed in claim 1, wherein the correction circuit comprises: A first delay circuit comprising: A first non-inverting delay trigger configured to receive the data flash control enable setting signal and a clock signal to generate a first non-inverting delay result delayed by one cycle relative to the data flash control enable setting signal; a first inverting delay flip-flop configured to receive the data flash control enable setting signal and an inverted clock signal to generate a first inverting delay result delayed by half a cycle relative to the data flash control enable setting signal, wherein the inverted clock signal is the inverted clock signal; and a first multiplexer configured to select one of the first non-inverted delay result and the first inverted delay result as the first delayed signal; and A second delay circuit comprising: a second non-inverting delay flip-flop, configured to receive the first delay signal and the clock signal to generate a second non-inverting delay result delayed by one cycle relative to the first delay signal; a second inverting delay flip-flop configured to receive the first delay signal and the inverted clock signal to generate a second inverting delay result delayed by half a cycle relative to the first delay signal; and A second multiplexer is configured to select one of the second non-inverted delay result and the second inverted delay result as the second delayed signal. 5 . The memory signal calibration device as claimed in claim 4 , wherein a first signal delay amount corresponding to the first delay circuit and a second signal delay amount corresponding to the second delay circuit are the same or different. 6 . The memory signal calibration device as claimed in claim 1 , wherein the first delay signal and the second delay signal have a first delay pulse and a second delay pulse respectively, and the pulse indication signal is sampled according to the first delay pulse and the second delay pulse respectively.

7. The memory signal calibration device as claimed in claim 1, wherein the memory signal calibration device is disposed in a memory access interface device in a memory system for accessing a memory device according to a memory access controller.

8. The memory signal calibration device as claimed in claim 1, wherein the gating circuit adjusts the timing of the data strobe enable signal to perform gating output corresponding to a leading interval and the pulse interval of the data strobe signal to generate the gated data strobe signal.

9. A memory signal calibration method, applied to a memory signal calibration device, comprising: A setting control signal is generated by an enable signal setting circuit; A gating circuit generates a data strobe enable setting signal having a single pulse according to the setting control signal, generates an enable state of a data strobe enable signal according to the single pulse to maintain a preset timing, and gates a data strobe signal having a receiving timing according to the enable state to generate a gated data strobe signal; A pulse indication signal is generated by a correction circuit, and the pulse indication signal has an indication state corresponding to a pulse interval of the data flash control signal; The correction circuit delays the data flash enable setting signal to generate a first delay signal; Delaying the first delay signal by the correction circuit to generate a second delay signal; The correction circuit samples the pulse indication signal according to the first delay signal and the second delay signal to generate a sampling result; and The correction circuit enables the enable signal setting circuit to adjust the setting control signal according to the sampling result, thereby controlling the gate control circuit to adjust the data flash control enable setting signal and the timing of the data flash control enable signal.

10. The memory signal calibration method according to claim 9, further comprising: When the sampling result shows that the first delay signal and the second delay signal are sampled to the same sampling state and the sampling state is the same as the indication state, the enable signal setting circuit determines that the receiving timing of the data strobe signal corresponds to a premature state, and controls the gate circuit to adjust the timing of the data strobe enable setting signal and the data strobe enable signal forward through the setting control signal; When the sampling result shows that the first delay signal and the second delay signal are sampled to the same sampling state and the sampling state is different from the indication state, the enable signal setting circuit determines that the receiving timing of the data strobe signal corresponds to a too late state, and controls the gate circuit to adjust the timing of the data strobe enable setting signal and the data strobe enable signal backward through the setting control signal; and When the sampling result shows that the first delay signal and the second delay signal are sampled to different sampling states, the enable signal setting circuit determines that the receiving timing of the data flash control signal corresponds to a moderate state, and controls the gate circuit through the setting control signal not to adjust the timing of the data flash control enable setting signal and the data flash control enable signal.

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