Storage device

Abstract

The invention relates to a storage device. According to one embodiment, a memory device includes a memory cell array including first to ninth regions, a first column switch circuit and a second column switch circuit, and a first row switch circuit and a second row switch circuit. When the first region is selected, the first column switch circuit and the second column switch circuit and the first row switch circuit and the second row switch circuit are activated, and when any one of the second region to the fifth region is selected, one of the first column switch circuit and the second column switch circuit and one of the first row switch circuit and the second row switch circuit are activated. When either the sixth region or the eighth region is selected, both the first column switching circuit and the second column switching circuit and one of the first row switching circuit and the second row switching circuit are activated, and when either the seventh region or the ninth region is selected, both the first row switching circuit and the second row switching circuit are activated. One of the first column switching circuit and the second column switching circuit and both the first row switching circuit and the second row switching circuit are activated.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to storage devices. Background Art

[0002] There is known a memory device using a variable resistance element (eg, a magnetoresistive effect element) as a memory element. In order to improve the characteristics of the memory device, various technologies related to the memory device are being studied and developed. Summary of the invention

[0003] According to one embodiment, the storage device comprises:

[0004] A memory cell array, comprising a plurality of bit lines, a plurality of word lines and a plurality of memory cells, wherein a first region to a ninth region are set, and the plurality of memory cells are respectively connected to a bit line of the plurality of bit lines and a word line of the plurality of word lines;

[0005] A first column switch circuit connected to the plurality of bit lines and disposed on one end side of the memory cell array in a first direction;

[0006] a second column switch circuit connected to the plurality of bit lines and arranged on the other end side of the memory cell array in the first direction;

[0007] a first row switch circuit connected to the plurality of word lines and disposed on one end side of the memory cell array in the second direction; and

[0008] a second row switch circuit connected to the plurality of word lines and disposed on the other end side of the memory cell array in the second direction;

[0009] When a memory cell in the first area is selected, the first column switch circuit and the second column switch circuit, as well as the first row switch circuit and the second row switch circuit are activated; when a memory cell in the second area is selected, the first column switch circuit and the first row switch circuit are activated; when a memory cell in the third area is selected, the second column switch circuit and the first row switch circuit are activated; when a memory cell in the fourth area is selected, the second column switch circuit and the second row switch circuit are activated; when a memory cell in the fifth area is selected, the first column switch circuit and the second row switch circuit are activated. The 2nd row switch circuit is activated, and when the memory cell in the 6th zone is selected, the 1st column switch circuit, the 2nd column switch circuit, and the 1st row switch circuit are activated, and when the memory cell in the 7th zone is selected, the 2nd column switch circuit, the 1st row switch circuit, and the 2nd row switch circuit are activated, and when the memory cell in the 8th zone is selected, the 1st column switch circuit, the 2nd column switch circuit, and the 2nd row switch circuit are activated, and when the memory cell in the 9th zone is selected, the 1st column switch circuit, the 1st row switch circuit, and the 2nd row switch circuit are activated. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a block diagram showing a configuration example of a storage device according to the first embodiment.

[0011] Figure 2 This is a circuit diagram showing a configuration example of a memory cell array of the memory device according to the first embodiment.

[0012] Figure 3 This is a bird's-eye view showing a configuration example of a memory cell array of the memory device according to the first embodiment.

[0013] Figure 4 It is a cross-sectional view showing a configuration example of a memory cell array of the memory device according to the first embodiment.

[0014] Figure 5 It is a cross-sectional view showing a configuration example of a memory cell array of the memory device according to the first embodiment.

[0015] Figure 6 This is a schematic diagram showing a configuration example of a storage unit of the storage device according to the first embodiment.

[0016] Figure 7 This is a diagram showing a circuit configuration in the vicinity of a memory cell array of the memory device according to the first embodiment.

[0017] Figure 8This is a schematic diagram showing the operating state of the column switch circuit of the memory device according to the first embodiment.

[0018] Fig. 9 This is a schematic diagram showing the operating state of the row switch circuit of the memory device according to the first embodiment.

[0019] Fig.10 This is a diagram for explaining areas within a memory cell array of the memory device according to the first embodiment.

[0020] Fig.11 This is a diagram for explaining an operation example of the storage device according to the first embodiment.

[0021] Fig.12 This is a diagram for explaining an operation example of the storage device according to the first embodiment.

[0022] Fig.13 This is a diagram for explaining an operation example of the storage device according to the first embodiment.

[0023] Fig.14 This is a diagram for explaining an operation example of the storage device according to the first embodiment.

[0024] Fig.15 It is a diagram showing the characteristics of the storage device according to the first embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, the same reference numerals are given to elements having the same function and configuration.

[0026] In the following embodiments, for the same multiple components (e.g., circuits, wirings, various voltages and signals, etc.), numbers / letters for distinction are sometimes added at the end of the reference numerals. In the case where components assigned with reference numerals with numbers / letters for distinction at the end do not need to be distinguished from each other, the description (reference numerals) with the numbers / letters at the end omitted is used.

[0027] (1) First Embodiment

[0028] Reference Figures 1 to 15 , a storage device 100 according to an implementation mode is described.

[0029] (a) Example of composition

[0030] Reference Figures 1 to 10 , an example of the configuration of the storage device according to the first embodiment is described.

[0031] (a-1) Overall composition

[0032] Figure 1 1 is a diagram showing a configuration example of the storage device 100 according to the present embodiment.

[0033] like Figure 1 As shown, the storage device 100 of the present embodiment is connected to a device (hereinafter referred to as an external device) 900 outside the storage device 100 .

[0034] The external device 900 sends a command CMD, an address ADR, and a control signal CNT to the storage device 100. Data DT is transmitted between the storage device 100 and the external device 900. When the external device 900 performs a write operation, it sends data to be written into the storage device 100 (hereinafter referred to as write data) to the storage device 100. When the external device 900 performs a read operation, it receives data read from the storage device 100 (hereinafter referred to as read data) from the storage device 100.

[0035] The memory device 100 of this embodiment includes a memory cell array 110 , a column control circuit 120 , a row control circuit 130 , a write circuit 140 , a read circuit 150 , a voltage generation circuit 160 , an input / output circuit 170 , and a control circuit 180 .

[0036] The memory cell array 110 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0037] The plurality of memory cells MC are associated with the plurality of rows and the plurality of columns in the memory cell array 110. Each memory cell MC is connected to a corresponding one of the plurality of word lines WL. Each memory cell MC is connected to a corresponding one of the plurality of bit lines BL.

[0038] The column control circuit 120 controls the columns of the memory cell array 110. The column control circuit 120 is connected to the memory cell array 110 via the bit lines BL. The column control circuit 120 receives the column address of the memory cell array 110 in the address ADR (or the decoding result of the column address). The column control circuit 120 controls the plurality of bit lines BL based on the decoding result of the column address. Thus, the column control circuit 120 sets each of the plurality of bit lines BL (a plurality of columns) to a selected state or a non-selected state. Hereinafter, the bit lines BL set to the selected state are referred to as selected bit lines BL, and the bit lines BL other than the selected bit lines BL are referred to as non-selected bit lines BL. The column control circuit 120 includes a plurality of column switch circuits 121. Each column switch circuit 121 controls the connection between the selected bit line BL and the global wiring described later.

[0039] The row control circuit 130 controls the rows of the memory cell array 110. The row control circuit 130 is connected to the memory cell array 110 via the word line WL. The row control circuit 130 receives the row address of the memory cell array 110 in the address ADR (or the decoding result of the row address). The row control circuit 130 controls the plurality of word lines WL based on the decoding result of the row address. Thus, the row control circuit 130 sets each of the plurality of word lines WL (a plurality of rows) to a selected state or a non-selected state. Hereinafter, the word line WL set to the selected state is referred to as the selected word line WL, and the word line WL other than the selected word line WL is referred to as the non-selected word line WL. The row control circuit 130 includes a plurality of row switch circuits 131. Each row switch circuit 131 controls the connection between the selected word line WL and the global wiring described later.

[0040] The write circuit 140 writes data to the memory cell MC. The write circuit 140 supplies a voltage (or current) for writing data to each of the selected word line WL and the selected bit line BL via global wiring. Thus, a certain write voltage (or write current) is supplied to the selected memory cell MC. The write circuit 140 can supply any one of a plurality of write voltages corresponding to the write data to the selected memory cell MC. For example, each of the plurality of write voltages has a polarity (bias direction) corresponding to the write data. For example, the write circuit 140 includes a write driver (not shown) and a write synchronizer (not shown).

[0041] The read circuit 150 reads data from the memory cell MC. The read circuit 150 amplifies the signal output from the selected memory cell MC to the selected bit line BL. The read circuit 150 determines the data in the memory cell MC based on the amplified signal. For example, the read circuit 150 includes a preamplifier (not shown), a sense amplifier (not shown), a read driver (not shown), and a read synchronizer (not shown).

[0042] The voltage generating circuit 160 generates voltages for various operations of the memory cell array 110 using a power supply voltage provided from the external device 900. For example, the voltage generating circuit 160 generates various voltages used in a write operation. The voltage generating circuit 160 outputs the generated voltages to the write circuit 140. For example, the voltage generating circuit 160 generates various voltages used in a read operation. The voltage generating circuit 160 outputs the generated voltages to the read circuit 150.

[0043] The input / output circuit 170 functions as an interface circuit for various signals ADR, CMD, CNT, and DT between the storage device 100 and the external device 900. The input / output circuit 170 transmits an address ADR from the external device 900 to the control circuit 180. The input / output circuit 170 transmits a command CMD from the external device 900 to the control circuit 180. The input / output circuit 170 transmits various control signals CNT between the external device 900 and the control circuit 180. The input / output circuit 170 transmits write data DT from the external device 900 to the write circuit 140. The input / output circuit 170 transmits data DT from the read circuit 150 to the external device 900 as read data.

[0044] The control circuit (also called a sequencer, a state machine, or an internal controller) 180 decodes the command CMD. Based on the decoding result of the command CMD and the control signal CNT, the control circuit 180 controls the operation of the column control circuit 120, the row control circuit 130, the write circuit 140, the read circuit 150, the voltage generation circuit 160, and the input / output circuit 170 in the storage device 100. The control circuit 180 decodes the address ADR. The control circuit 180 sends the decoding result of the address ADR to the column control circuit 120 and the row control circuit 130. For example, the control circuit 180 includes a register circuit (not shown) for temporarily storing the command CMD and the address ADR. In addition, the register circuit, the circuit for decoding the command CMD (command decoder), and the circuit for decoding the address ADR (address decoder) may also be provided outside the control circuit 180 in the storage device 100.

[0045] (a-2) Memory Cell Array

[0046] Reference Figures 2 to 5 , a configuration example of the memory cell array 110 in the memory device 100 of the present embodiment is described.

[0047] Figure 2 2 is an equivalent circuit diagram showing a configuration example of the memory cell array 110 of the memory device 100 according to the present embodiment.

[0048] like Figure 2 As shown in FIG. 1 , a plurality of memory cells MC are arranged in a matrix in the memory cell array 110. Each memory cell MC is connected to a plurality of bit lines BL (BL <1> BL <2> ,…,BL <n>) in a corresponding bit line BL and a plurality of word lines WL (WL <1> , WL <2> ,…,WL <m>) in a corresponding word line WL. M and N are integers greater than 1.

[0049] Each memory cell MC includes a storage element 1 and a switching element 2 .

[0050] The storage element 1 is, for example, a variable resistance element. The resistance state of the storage element 1 changes to any one of a plurality of resistance states (for example, a low resistance state and a high resistance state) according to the voltage (or current) supplied. The storage element 1 can store data by associating the resistance state of the element 1 with data (for example, data "0" and data "1").

[0051] The switch element (or, also referred to as a selector element or simply a selector) 2 functions as a selection element of the memory cell MC. The switch element 2 has the following function: when writing data to the corresponding memory element 1 and when reading data from the corresponding memory element 1, it controls the supply of voltage (or current) to the memory element 1.

[0052] For example, when a certain voltage applied to a certain memory cell MC is lower than the threshold voltage of the switch element 2 in the memory cell MC, the switch element 2 is set to the off state (high resistance state, non-conducting state). In this case, the switch element 2 disconnects the voltage (or current) to the memory element 1. When a certain voltage applied to a certain memory cell MC is higher than the threshold voltage of the switch element 2 in the memory cell MC, the switch element 2 is set to the on state (low resistance state, conducting state). In this case, the switch element 2 supplies voltage (or current) to the memory element 1.

[0053] The switch element 2 can switch whether or not current flows in the memory cell MC, regardless of the direction in which current flows in the memory cell MC, according to the magnitude of a voltage applied to the memory cell MC.

[0054] For example, the switching element 2 is a two-terminal type element. Figure 2 In the example of , one end of the switch element 2 is connected to the word line WL. The other end of the switch element 2 is connected to one end of the memory element 1. The other end of the memory element 1 is connected to the bit line BL.

[0055] Figures 3 to 5 This is a diagram for explaining a configuration example of the memory cell array 110 of the memory device 100 according to the present embodiment. Figure 3 This is a bird's-eye view for explaining a configuration example of the memory cell array 110 . Figure 4 1 is a schematic cross-sectional view showing a cross-sectional structure of the memory cell array 110 along the first direction (axis). Figure 5 2 is a schematic cross-sectional view showing a cross-sectional structure of the memory cell array 110 along the second direction (axis). Figures 3 to 5 In the example, the first direction corresponds to the X direction, and the second direction corresponds to the Y direction.

[0056] like Figures 3 to 5 As shown, the memory cell array 110 is arranged above the upper surface of the substrate 90. The X direction is a direction parallel to the upper surface of the substrate 90. The Y direction is a direction parallel to the upper surface of the substrate 90 and intersecting with the X direction. Hereinafter, the plane parallel to the upper surface of the substrate 90 is referred to as the XY plane. The direction (axis) perpendicular to the XY plane is referred to as the Z direction (Z axis). The plane parallel to the plane including the X direction and the Z direction is referred to as the XZ plane. The plane parallel to the plane including the Y direction and the Z direction is referred to as the YZ plane.

[0057] A plurality of wirings (conductive layers) 50 are provided above the upper surface of the substrate 90 via the insulating layer 91 in the Z direction. The plurality of wirings 50 are arranged in the X direction. Each wiring 50 extends in the Y direction. The plurality of wirings 50 functions as word lines WL, for example.

[0058] A plurality of wirings (conductive layers) 51 are provided above the plurality of wirings 50 in the Z direction. The plurality of wirings 51 are arranged in the Y direction. Each wiring 51 extends in the X direction. The plurality of wirings 51 functions as, for example, bit lines BL.

[0059] The plurality of memory cells MC are provided between the plurality of wirings 50 and the plurality of wirings 51. The plurality of memory cells MC are arranged in a matrix in the XY plane.

[0060] A plurality of memory cells MC arranged in the Y direction are arranged above one wiring 50. Two memory cells MC arranged in the Y direction are adjacent to each other with a predetermined interval. Each of the plurality of memory cells MC arranged in the Y direction is connected to a common wiring 50 (word line WL) via a corresponding one of the contact portions 52. The plurality of contact portions 52 are arranged on one wiring 50.

[0061] A plurality of memory cells MC arranged in the X direction are arranged below one wiring 51. Two memory cells MC arranged in the X direction are adjacent to each other with a predetermined interval. Each of the plurality of memory cells MC arranged in the X direction is connected to a common wiring 51 (bit line BL) via a corresponding one of the contacts 53. The plurality of contacts 53 are arranged below one wiring 51.

[0062] For example, in the memory cell array 110 having Figure 2 In the case of the circuit configuration of , the switch element 2 is provided below the memory element 1 in the Z direction. The switch element 2 is provided between the memory element 1 and the wiring 50 (word line WL). The memory element 1 is provided between the wiring 51 (bit line BL) and the switch element 2.

[0063] In this way, each memory cell MC is a stacked body of the memory element 1 and the switch element 2. The memory cell array 110 has a stacked structure due to the memory cells MC.

[0064] The memory cell MC may have a tapered cross-sectional shape depending on a process (eg, etching method) for forming the memory cell array 110 .

[0065] The insulating layer 60 is provided on the substrate 90. The insulating layer 60 covers the memory cell MC, the wirings 50 and 51, and the contacts 52 and 53. The insulating layer 62 is provided on the insulating layer 60 and the wiring 51.

[0066] exist Figure 4 and Figure 5 , an example in which an insulating layer 91 is provided between a plurality of wirings 50 and a substrate 90 is shown. In the case where the substrate 90 is a semiconductor substrate, one or more field effect transistors (not shown) may be provided on the semiconductor region on the upper surface of the substrate 90. The field effect transistor is covered by the insulating layer 91 including a multilayer wiring structure. The field effect transistor on the substrate 90 is a constituent element of a circuit such as a column control circuit 120. The field effect transistor is connected to the memory cell array 110 via a contact plug (not shown) and wiring (not shown) in the insulating layer 91. In this way, a circuit for controlling the operation of the memory cell array 110 may also be provided below the memory cell array 110 in the Z direction. In addition, if the substrate 90 is an insulating substrate, the plurality of wirings 50 may also be provided directly on the upper surface of the substrate 90 without the insulating layer 91.

[0067] The circuit configuration and structure of the stacked memory cell array 110 are not limited to Figures 2 to 5 The circuit configuration and structure of the memory cell array 110 may be appropriately modified according to the connection relationship between the memory element 1 and the switch element 2 with respect to the bit line BL and the word line WL. Figure 2 The structure of the memory cell array 110 having the circuit structure is not limited to Figures 3 to 5 For example, the switch element 2 may be provided above the memory element 1 in the Z direction. In this case, the wiring 50 is used as the bit line BL, and the wiring 51 is used as the word line WL.

[0068] (a-3) Storage Unit

[0069] Figure 6 2 is a cross-sectional view showing a configuration example of a memory cell MC in the memory device 100 according to the present embodiment.

[0070] like Figure 6 As shown in FIG. 1 , in the memory cell MC of the stacked body, the memory element 1 and the switch element 2 are arranged in the Z direction. In this example, the memory element 1 is provided on the switch element 2 in the Z direction.

[0071] For example, the variable resistance element as the storage element 1 is a magnetoresistive element. In this case, the storage device 100 of the present embodiment is a magnetic memory such as an MRAM (Magnetoresistive Random Access Memory).

[0072] <Configuration Example of Magnetoresistive Effect Element>

[0073] For example, the magnetoresistance effect element 1 includes at least two magnetic layers 11 and 13 and a non-magnetic layer 12. The non-magnetic layer 12 is provided between the two magnetic layers 11 and 13 in the Z direction. Figure 6 In the example, a plurality of layers 11, 12, and 13 are arranged in the Z direction in the order of magnetic layer 11, nonmagnetic layer 12, and magnetic layer 13 from the word line WL (wiring 50) side toward the bit line BL (wiring 51).

[0074] The two magnetic layers 11 and 13 and the non-magnetic layer 12 form a magnetic tunnel junction. Hereinafter, the magnetoresistance effect element 1 including the magnetic tunnel junction is referred to as an MTJ (Magnetic Tunnel Junction) element 1. The non-magnetic layer 12 in the MTJ element 1 is referred to as a tunnel barrier layer.

[0075] The magnetic layers 11 and 13 are, for example, ferromagnetic layers containing cobalt (Co), iron (Fe) and (or) boron (B). The magnetic layers 11 and 13 may be single-layer films (for example, alloy films) or multi-layer films (for example, artificial lattice films). The tunnel barrier layer 12 is, for example, an insulating layer containing magnesium oxide. The tunnel barrier layer 12 may be single-layer films or multi-layer films.

[0076] When the MTJ element 1 is a perpendicular magnetization type magnetoresistance effect element, each magnetic layer 11, 13 has perpendicular magnetic anisotropy. The direction of the easy magnetization axis of each magnetic layer 11, 13 is perpendicular to the layer (film surface) of the magnetic layer 11, 13. Each magnetic layer 11, 13 has magnetization perpendicular to the layer of the magnetic layer 11, 13. The direction of magnetization of each magnetic layer 11, 13 is parallel to the arrangement direction (Z direction) of the magnetic layers 11, 13.

[0077] The magnetization direction of one of the two magnetic layers 11 and 13 is variable, while the magnetization direction of the other magnetic layer is constant. The MTJ element 1 can have a plurality of resistance states (resistance values) according to the relative relationship (magnetization arrangement) between the magnetization direction of one magnetic layer and the magnetization direction of the other magnetic layer.

[0078] For example, the magnetization direction of the magnetic layer 13 is variable. The magnetization direction of the magnetic layer 11 is constant (fixed state). Hereinafter, the magnetic layer 13 whose magnetization direction is variable is referred to as a storage layer. Hereinafter, the magnetic layer 11 whose magnetization direction is constant (fixed state) is referred to as a reference layer. In addition, the storage layer 13 is sometimes referred to as a free layer, a magnetization free layer, or a magnetization variable layer. The reference layer 11 is sometimes referred to as a pinned layer, a pinned layer, a magnetization constant layer, or a magnetization fixed layer.

[0079] In this embodiment, "the magnetization direction of the reference layer (magnetic layer) remains unchanged" or "the magnetization direction of the reference layer (magnetic layer) is in a fixed state" means that when a current or voltage for changing the magnetization direction of the storage layer 13 is supplied to the MTJ element 1, the magnetization direction of the reference layer 11 does not change due to the supplied current or voltage before and after the supply of the current / voltage.

[0080] When the magnetization direction of the storage layer 13 is the same as that of the reference layer 11 (when the magnetization arrangement state of the MTJ element 1 is a parallel arrangement state), the resistance state of the MTJ element 1 is a first resistance state. When the magnetization direction of the storage layer 13 is different from that of the reference layer 11 (when the magnetization arrangement state of the MTJ element 1 is an antiparallel arrangement state), the resistance state of the MTJ element 1 is a second resistance state different from the first resistance state. The resistance value of the MTJ element 1 in the second resistance state (antiparallel arrangement state) is higher than the resistance value of the MTJ element 1 in the first resistance state (parallel arrangement state).

[0081] Hereinafter, regarding the magnetization alignment state of the MTJ element 1 , the parallel alignment state is also referred to as a P state, and the antiparallel alignment state is also referred to as an AP state.

[0082] For example, the MTJ element 1 is connected to two electrodes 31 and 32. The magnetic layers 11 and 13 and the tunnel barrier layer 12 are arranged between the two electrodes 31 and 32 in the Z direction. The reference layer 11 is arranged between the electrode (referred to as the middle electrode) 31 and the tunnel barrier layer 12. The storage layer 13 is arranged between the electrode (referred to as the upper electrode) 32 and the tunnel barrier layer 12.

[0083] For example, a shift cancel layer 14 may be provided in the MTJ element 1. In this case, the shift cancel layer 14 is provided between the reference layer 11 and the intermediate electrode 31. The shift cancel layer 14 is a magnetic layer for alleviating the influence of the leakage magnetic field of the reference layer 11. In the case where the MTJ element 1 includes the shift cancel layer 14, the non-magnetic layer 15 is provided between the shift cancel layer 14 and the reference layer 11. The non-magnetic layer 15 is, for example, a metal layer such as a ruthenium (Ru) layer. The shift cancel layer 14 is antiferromagnetically coupled to the reference layer 11 via the non-magnetic layer 15. Thus, the stack including the reference layer 11 and the shift cancel layer 14 forms a SAF (Synthetic antiferromagnetic) structure. In the SAF structure, the magnetization direction of the shift cancel layer 14 becomes opposite to the magnetization direction of the reference layer 11. Through the SAF structure, the magnetization direction of the reference layer 11 can be more stably fixed. In addition, the set of the two magnetic layers 11 and 14 and the non-magnetic layer 15 forming the SAF structure is sometimes also referred to as a reference layer.

[0084] For example, the MTJ element 1 may also include at least one of a base layer (not shown) and a cap layer (not shown). The base layer is disposed between the magnetic layer (here, the transition elimination layer) 14 and the intermediate electrode 31. The base layer is a non-magnetic layer (e.g., a conductive layer). The base layer is a layer for improving the properties (e.g., crystallinity and / or magnetic properties) of the magnetic layer 14 connected to the base layer. The cap layer is disposed between the magnetic layer (here, the storage layer) 13 and the upper electrode 32. The cap layer is a non-magnetic layer (e.g., a conductive layer). The cap layer is a layer for improving the properties (e.g., crystallinity and / or magnetic properties) of the magnetic layer 13 connected to the cap layer. In addition, the base layer and the cap layer may each be regarded as a constituent element of the electrodes 31 and 32.

[0085] <Configuration Example of Switching Element>

[0086] like Figure 6 As shown, when the switch element 2 is a two-terminal element, the switch element 2 includes at least one variable resistance layer (also called a switch layer or a selection layer) 20. The variable resistance layer 20 is disposed between two electrodes 30 and 31 in the Z direction. The variable resistance layer 20 can take multiple resistance states.

[0087] The electrode (referred to as the lower electrode) 30 is provided below the variable resistance layer 20 in the Z direction, and the intermediate electrode 31 is provided above the variable resistance layer 20 in the Z direction. For example, the lower electrode 30 is provided between the wiring 50 and the variable resistance layer 20. The electrode 31 is provided between the variable resistance layer 20 and the MTJ element 1.

[0088] The variable resistance layer 20 is connected to the wiring 50 via the lower electrode 30 and the contact portion 52. The variable resistance layer 20 is connected to the MTJ element 1 via the intermediate electrode 31.

[0089] According to the voltage applied to the switch element 2 (memory cell MC), the resistance state of the variable resistance layer 20 becomes a high resistance state (non-conducting state) or a low resistance state (conducting state). When the resistance state of the variable resistance layer 20 is a high resistance state, the switch element 2 is turned off (cut off). When the resistance state of the variable resistance layer 20 is a low resistance state, the switch element 2 is turned on (conducting).

[0090] When the memory cell MC is set to the selected state, the switch element 2 is turned on, so the resistance state of the variable resistance layer 20 is the low resistance state. When the memory cell MC is set to the unselected state, the switch element 2 is turned off, so the resistance state of the variable resistance layer 20 is the high resistance state.

[0091] In addition, depending on the material of the variable resistance layer 20 , the change in the resistance state of the variable resistance layer 20 may also depend on the current (eg, the magnitude of the current) flowing in the switching element 2 (memory cell MC).

[0092] For example, the lower electrode 30 and the upper electrode 32 are conductive layers formed of titanium (Ti), tungsten (W), titanium nitride (TiN), or tungsten nitride (WN). The intermediate electrode 31 is a conductive layer formed of carbon (C) or carbon nitride (CN).

[0093] have Figures 3 to 6 The memory cell array 110 of the structure can be formed using well-known techniques.

[0094] (a-4) Configuration near the memory cell array

[0095] Figure 7 This is a diagram for explaining the structure of the vicinity of the memory cell array 110 of the MRAM 100 according to the present embodiment.

[0096] like Figure 7 As shown, when viewed from the Z direction, the memory cell array 110 has a quadrilateral layout.

[0097] M word lines WL <1> , WL <2> ,…,WL <x>…、WL <m-1>、WL <m>The N bit lines BL are arranged in the X direction at predetermined intervals in the memory cell array 110. <1> BL <2> ,…,BL <y>…、BL <n-1>、BL <n>The bit lines BL are arranged in the Y direction at predetermined intervals in the memory cell array 110. The bit lines BL are arranged above the word lines WL in the Z direction.

[0098] For example, a memory cell MCa is arranged at a coordinate represented by (x, y) in the memory cell array 110. The memory cell MCa is arranged on the word line WL <x>and bit line BL <y>The intersection position. x is an integer greater than or equal to 1 and less than or equal to M. y is an integer greater than or equal to 1 and less than or equal to N.

[0099] In this embodiment, the value of "M" is equal to the value of "N". The interval between the memory cells MC in the X direction is equal to the interval between the memory cells MC in the Y direction. When viewed from the Z direction, the memory cell array 110 has a square layout (planar structure).

[0100] In the case where a plurality of memory cells MC are arranged at a predetermined interval in the X direction, the resistance between two adjacent memory cells MC in the X direction has a resistance value of "Rs_x". When the address of the bit line BL changes by 1, the wiring resistance applied to the memory cell MC changes by the amount of "Rs_x". In the case where a plurality of memory cells MC are arranged at a predetermined interval in the Y direction, the resistance between two adjacent memory cells MC in the Y direction has a resistance value of "Rs_y". When the address of the word line WL changes by 1, the wiring resistance applied to the memory cell MC changes by the amount of "Rs_y".

[0101] For example, in this embodiment, the value of “Rs_x” is equal to the value of “Rs_y.” Hereinafter, the resistance between the memory cells MC is described as “Rs.”

[0102] In the MRAM 100 of the present embodiment, the column control circuit 120 includes two column switch circuits 121 - 1 and 121 - 2 .

[0103] One of the two column switch circuits 121-1 and 121-2 is provided on one end side in the X direction of the memory cell array 110. The other of the two column switch circuits 121-1 and 121-2 is provided on the other end side in the X direction of the memory cell array 110. The memory cell array 110 is provided between the two column switch circuits 121-1 and 121-2 in the X direction.

[0104] The two column switch circuits 121 - 1 and 121 - 2 are connected to a common global bit line GBL. The global bit line GBL is connected to the write circuit 140 and the read circuit 150 .

[0105] Each column switch circuit 121-1, 121-2 includes a plurality of column switches SWC. The column switch SWC is, for example, a field effect transistor. One end of each column switch SWC is electrically connected to a corresponding bit line BL among a plurality of bit lines BL. The other end of each column switch SWC is electrically connected to a global bit line GBL.

[0106] In the column switch circuits 121-1 and 121-2, each column switch SWC is set to an on state or an off state according to the supplied address ADR. According to the on / off of the plurality of column switches SWC in the column switch circuits 121-1 and 121-2, one bit line BL is electrically connected to the global bit line GBL via the on-state column switch SWC.

[0107] Here, the distance between the memory cell MC at the end in the X direction of the memory cell array 110 and the column switch circuit 121 is set to half the distance between the memory cells MC adjacent to each other in the X direction. Therefore, the resistance between the column switch circuit 121 and the memory cell MC at the end in the X direction is "0.5×Rs".

[0108] The wiring resistance between the memory cell MCa at coordinate (x, y) and the column switch circuit 121-1 is "(x-0.5)×Rs". The wiring resistance between the memory cell MCa at coordinate (x, y) and the column switch circuit 121-2 is "(M-x+0.5)×Rs".

[0109] Thus, the distance of the memory cell MCa from the voltage / current supply source (e.g., the write circuit 140 or the read circuit 150) used in various operations of the MRAM 100 changes according to the coordinates of the memory cell MCa in the memory cell array 110. As a result, when the MRAM 100 operates, the magnitude of the wiring resistance applied to the memory cell MCa changes according to the coordinates of the memory cell MCa.

[0110] In the present embodiment, when a read operation or a write operation is performed on the memory cell array 110, both or either of the two column switch circuits 121-1 and 121-2 is turned on (activated).

[0111] like Figure 7 As shown, in the MRAM of this embodiment, the row control circuit 130 includes two row switch circuits 131 - 1 and 131 - 2 .

[0112] One of the two row switch circuits 131-1 and 131-2 is provided at one end side in the Y direction of the memory cell array 110. The other of the two row switch circuits 131-1 and 131-2 is provided at the other end side in the Y direction of the memory cell array 110. The memory cell array 110 is provided between the two row switch circuits 131-1 and 131-2 in the Y direction.

[0113] The two row switch circuits 131 - 1 and 131 - 2 are connected to a common global word line GWL. The global word line GWL is connected to the write circuit 140 and the read circuit 150 .

[0114] Each row switch circuit 131-1, 131-2 includes a plurality of row switches SWR. The row switch SWR is, for example, a field effect transistor. One end of each row switch SWR is electrically connected to a corresponding word line WL among a plurality of word lines WL. The other end of each row switch SWR is electrically connected to a global word line GWL.

[0115] In the row switch circuits 131-1 and 131-2, each row switch SWR is set to an on state or an off state according to the supplied address ADR. According to the on / off of the plurality of row switches SWR in the row switch circuits 131-1 and 131-2, one word line WL is electrically connected to the global word line GWL via the on-state row switch SWR.

[0116] Here, the distance between the memory cell MC at the end in the Y direction of the memory cell array 110 and the row switch circuit 131 is set to half the distance between the memory cells MC adjacent to each other in the Y direction. Therefore, the wiring resistance between the row switch circuit 131 and the memory cell MC at the end in the Y direction is "0.5×Rs".

[0117] The wiring resistance between the memory cell MCa at coordinate (x, y) and the row switch circuit 131-1 is "(y-0.5)×Rs". The wiring resistance between the memory cell MCa at coordinate (x, y) and the row switch circuit 131-2 is "(N-y+0.5)×Rs".

[0118] In this way, the magnitude of the wiring resistance applied to the memory cell MCa changes according to the y coordinate of the memory cell MCa in the memory cell array 110 .

[0119] In the present embodiment, when a read operation or a write operation is performed on the memory cell array 110, both or either of the two row switch circuits 131-1 and 131-2 is turned on (activated).

[0120] In the MRAM 100 of this embodiment, the operation (on / off state) of the two column switch circuits 121-1 and 121-2 and the operation (on / off state) of the two row switch circuits 131-1 and 131-2 are controlled according to the coordinates of the memory cell MC to be operated in the memory cell array 110. Hereinafter, the memory cell to be operated is referred to as a selection cell.

[0121] (a-5) Relationship between the operating state of the switching circuit and wiring resistance

[0122] Reference Figure 8 and Fig. 9 , the relationship between the operating states of the column switch circuit 121 and the row switch circuit 131 and the wiring resistance applied to the memory cell MC in the MRAM 100 of the present embodiment will be described.

[0123] Figure 8 This is a schematic diagram for explaining the relationship between the operating state of the column switch circuit 121 and the wiring resistance applied to the selected cell MCa in the MRAM 100 of the present embodiment.

[0124] like Figure 8 As shown, when the selected cell MCa is connected to the global bit line GBL using both or either of the two column switch circuits 121-1 and 121-2, the wiring resistance between the memory cell MC and the global bit line GBL changes according to the path formed by the column switch circuit 121 in the on state.

[0125] Figure 8 (a) is a diagram schematically showing wiring resistance between the selection cell MCa and the global bit line GBL when the two column switch circuits 121 - 1 and 121 - 2 are set to an on state (an active state).

[0126] like Figure 8 As shown in (a), the two column switch circuits 121-1 and 121-2 are set to the on state. The resistor RX1 exists in the connection path between the memory cell MC and the global bit line GBL via the column switch circuit 121-1 in the on state. The resistor RX2 exists in the connection path between the selection cell MCa and the global bit line GBL via the column switch circuit 121-2 in the on state.

[0127] The resistor RX1 is "(x-0.5)×Rs". The resistor RX2 is "(M-x+0.5)×Rs".

[0128] When the selection unit MCa is connected to the global bit line GBL through the two column switch circuits 121-1 and 121-2, two resistors RX1 and RX2 are connected in parallel between the storage unit MCa and the global bit line GBL. In this case, the wiring resistance between the selection unit MCa and the global bit line GBL becomes "RX1×RX2 / (RX1+RX2)". Therefore, the wiring resistance of the bit line BL can be expressed as "Rs×(x-0.5)×(M-x+0.5) / M".

[0129] Figure 8 (b) is a diagram schematically showing wiring resistance between the selection cell MCa and the global bit line GBL when only one column switch circuit 121 - 1 is set to the on state.

[0130] like Figure 8 As shown in (b), one column switch circuit 121-1 is set to an on state, and the other column switch circuit 121-2 is set to an off state (inactive state). Therefore, the resistor RX2 is electrically disconnected from the global bit line GBL.

[0131] When the selected cell MCa is connected to the global bit line GBL via one column switch circuit 121-1, the resistor RX1 is connected between the selected cell MCa and the global bit line GBL. In this case, the wiring resistance between the selected cell MCa and the global bit line GBL can be expressed as "(x-0.5)×Rs".

[0132] Figure 8 (c) is a diagram schematically showing the wiring resistance between the selection cell MCa and the global bit line GBL when only the other column switch circuit 121 - 2 is set to the on state.

[0133] like Figure 8 As shown in (c), one column switch circuit 121-1 is set to an OFF state, and the other column switch circuit 121-2 is set to an ON state. Therefore, the resistor RX1 is electrically disconnected from the global bit line GBL.

[0134] When the selected cell MCa is connected to the global bit line GBL through the other column switch circuit 121-2, the resistor RX2 is connected between the selected cell MCa and the global bit line GBL. In this case, the wiring resistance between the selected cell MCa and the global bit line GBL can be expressed as "(M-x+0.5)×Rs".

[0135] If used Figure 8 As described above, the operation of the column switch circuit 121 related to the selection of the column of the memory cell array 110 can be controlled in three ways. Accordingly, with respect to the column of the memory cell array 110, according to the operation of the column switch circuit 121, any one of three wiring resistances is applied to the selected cell MCa.

[0136] Fig. 9 This is a schematic diagram for explaining the relationship between the operating state of the row switch circuit 131 and the wiring resistance of the selection cell MCa in the MRAM 100 of the present embodiment.

[0137] like Fig. 9 As shown, when the selection cell MCa is connected to the global word line GWL using both or either of the two row switch circuits 131-1 and 131-2, the wiring resistance between the memory cell MC and the global word line GWL changes according to the path formed by the row switch circuit 131 in the on state.

[0138] Fig. 9 (a) is a diagram schematically showing wiring resistance between the selection cell MCa and the global word line GWL when the two row switch circuits 131 - 1 and 131 - 2 are set to an on state (an active state).

[0139] like Fig. 9 As shown in (a), the two row switch circuits 131-1 and 131-2 are set to the on state. The resistor RY1 exists in the connection path between the selection cell MCa of the row switch circuit 131-1 in the on state and the global word line GWL. The resistor RY2 exists in the connection path between the selection cell MCa of the row switch circuit 131-2 in the on state and the global word line GWL.

[0140] The resistor RY1 is "(y-0.5)×Rs". The resistor RY2 is "(N-y+0.5)×Rs".

[0141] When the selection unit MCa is connected to the global word line GWL through the two row switch circuits 131-1 and 131-2, the two resistors RY1 and RY2 are connected in parallel between the selection unit MCa and the global word line GWL. In this case, the wiring resistance between the selection unit MCa and the global word line GWL becomes "RY1×RY2 / (RY1+RY2)". Therefore, the wiring resistance of the word line WL can be expressed as "Rs×(y-0.5)×(M-y+0.5) / N".

[0142] Fig. 9 (b) is a diagram schematically showing wiring resistance between the selection cell MCa and the global word line GWL when one row switch circuit 131 - 1 is set to the on state.

[0143] like Fig. 9 As shown in (b), one row switch circuit 131-1 is set to an on state, and the other row switch circuit 131-2 is set to an off state (inactive state). Therefore, the resistor RY2 is electrically disconnected from the global word line GWL.

[0144] When the selected cell MCa is connected to the global word line GWL through one row switch circuit 131-1, the resistor RY1 is connected between the selected cell MCa and the global word line GWL. In this case, the wiring resistance between the selected cell MCa and the global word line GWL can be expressed as "(y-0.5)×Rs".

[0145] Fig. 9 (c) is a diagram schematically showing the wiring resistance between the selection cell MCa and the global word line GWL when the other row switch circuit 131 - 2 is set to the on state.

[0146] like Fig. 9 As shown in (c), one row switch circuit 131-1 is set to an OFF state, and the other row switch circuit 131-2 is set to an ON state. Therefore, the resistor RY1 is electrically disconnected from the global word line GWL.

[0147] When the selected cell MCa is connected to the global word line GWL through the other row switch circuit 131-2, the resistor RY2 is connected between the selected cell MCa and the global word line GWL. In this case, the wiring resistance between the selected cell MCa and the global word line GWL can be expressed as "(N-y+0.5)×Rs".

[0148] If used Fig. 9 As described above, the operation of the row switch circuit 131 related to the selection of the row of the memory cell array 110 can be controlled in three ways. Accordingly, with respect to the row of the memory cell array 110, according to the operation of the row switch circuit 131, any one of three wiring resistances is applied to the selected cell MCa.

[0149] like Figure 8 and Fig. 9 As shown, in this embodiment, the memory cells MC in the memory cell array 110 can be selected in 3×3 (9) selection modes by controlling the two column switch circuits 121 - 1 and 121 - 2 and the two row switch circuits 131 - 1 and 131 - 2 .

[0150] The MRAM 100 of this embodiment can reduce the influence of the difference in wiring resistance according to the coordinates of the memory cell MC in the memory cell array 110 by using one of nine selection methods based on the address ADR of the memory cell MC to be operated during the MRAM operation.

[0151] For example, in this embodiment, the magnitude of the wiring resistance applied to the memory cell MC is controlled by the action of the switching circuits 121 and 131 so that the magnitude of the wiring resistance applied to the memory cell MC in the area close to the switching circuits 121 and 131 is close to the magnitude of the wiring resistance applied to the memory cell MC in the area far from the switching circuits 121 and 131.

[0152] (a-6) Area within the memory cell array

[0153] Reference Fig.10 , a plurality of regions set in the memory cell array 110 in the MRAM 100 of the present embodiment will be described.

[0154] The memory cell array 110 includes nine areas A1 , A2 , . . . , A9 divided according to nine selection modes (access modes) of memory cells in the memory cell array 110 implemented by the column switch circuit 121 and the row switch circuit 131 .

[0155] When performing a write operation or a read operation of the MRAM 100 , one of a plurality of memory cell MC selection methods implemented by the column switch circuits 121 - 1 and 121 - 2 and the row switch circuits 131 - 1 and 131 - 2 is determined based on the address (coordinate) of the memory cell MC.

[0156] Here, when the coordinates of the memory cell array 110 are associated with the orientation, the first row switch circuit 131-1 side corresponds to the north direction, the second row switch circuit 131-2 side corresponds to the south direction, the first column switch circuit 121-1 side corresponds to the west direction, and the second column switch circuit 121-2 side corresponds to the east direction.

[0157] The first area A1 is a region in the center of the memory cell array 110 .

[0158] With respect to the columns of the memory cell array 110, the memory cells MC in the first area A1 are arranged at positions far from the voltage / current supply source. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the X direction, the memory cells MC in the first area A1 are far from both the two column switch circuits 121. With respect to the rows of the memory cell array 110, the memory cells MC in the first area A1 are arranged at positions far from the voltage / current supply source. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the Y direction, the memory cells MC in the first area A1 are far from both the two row switch circuits 131.

[0159] The first area A1 is accessed through the two column switch circuits 121 - 1 and 121 - 2 in the on state and the two row switch circuits 131 - 1 and 131 - 2 in the on state.

[0160] like Figure 8 As shown in (a) of FIG. 1 , the memory cell MC in the first area A1 is electrically connected to the global bit line GBL via the two column switch circuits 121-1 and 121-2 in the on state. Fig. 9 As shown in (a), the memory cells MC in the first area A1 are electrically connected to the global word line GWL via the two row switch circuits 131-1 and 131-2 in the on state.

[0161] The second area A2 is located in a corner area on the northwest side of the memory cell array 110. The second area A2 is adjacent to the first column switch circuit 121-1 and the first row switch circuit 131-1.

[0162] With respect to the columns of the memory cell array 110, the memory cells MC in the second region A2 are arranged at positions close to the voltage / current supply source. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the X direction, the memory cells MC in the second region A2 are close to the first column switch circuit 121-1 and away from the second column switch circuit 121-2. With respect to the rows of the memory cell array 110, the memory cells MC in the second region A2 are arranged at positions close to the voltage / current supply source. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the Y direction, the memory cells MC in the second region A2 are close to the first row switch circuit 131-1 and away from the second row switch circuit 131-2.

[0163] The second area A2 is accessed through the first column switch circuit 121 - 1 in the on state and the first row switch circuit 131 - 1 in the on state.

[0164] like Figure 8 As shown in (b), the memory cell MC in the second area A2 is connected to the global bit line GBL through the first column switch circuit 121-1 in the on state. Fig. 9 As shown in (b), the memory cell MC in the second area A2 is connected to the global word line GWL via the first row switch circuit 131-1 in the on state.

[0165] When the memory cell MC in the second area A2 is selected as an operation target, the second column switch circuit 121 - 2 and the second row switch circuit 131 - 2 are set to the off state.

[0166] The third area A3 is an area located in a corner area on the northeast side of the memory cell array 110. The third area A3 is adjacent to the second column switch circuit 121-2 and the first row switch circuit 131-1.

[0167] With respect to the columns of the memory cell array 110, the memory cells MC in the third region A3 are arranged at positions close to the voltage / current supply source. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the X direction, the memory cells MC in the third region A3 are far from the first column switch circuit 121-1 and close to the second column switch circuit 121-2. With respect to the rows of the memory cell array 110, the memory cells MC in the third region A3 are arranged at positions close to the voltage / current supply source. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the Y direction, the memory cells MC in the third region A3 are close to the first row switch circuit 131-1 and far from the second row switch circuit 131-2.

[0168] The third area A3 is accessed through the second column switch circuit 121 - 2 in the on state and the first row switch circuit 131 - 1 in the on state.

[0169] like Figure 8 As shown in (c), the memory cell MC in the third area A3 is connected to the global bit line GBL through the second column switch circuit 121-2 in the on state. Fig. 9 As shown in (b), the memory cell MC in the third area A3 is connected to the global word line GWL via the first row switch circuit 131-1 in the on state.

[0170] When the memory cell MC in the third area A3 is selected as an operation target, the first column switch circuit 121 - 1 and the second row switch circuit 131 - 2 are set to the off state.

[0171] The fourth area A4 is located in a corner area on the southeast side of the memory cell array 110. The fourth area A4 is adjacent to the second column switch circuit 121-2 and the second row switch circuit 131-2.

[0172] With respect to the columns of the memory cell array 110, the memory cells MC in the 4th area A4 are arranged at positions close to the voltage / current supply source. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the X direction, the memory cells MC in the 4th area A4 are far from the first column switch circuit 121-1 and close to the second column switch circuit 121-2. With respect to the rows of the memory cell array 110, the memory cells MC in the 4th area A4 are arranged at positions close to the voltage / current supply source. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the Y direction, the memory cells MC in the 4th area A4 are far from the first row switch circuit 131-1 and close to the second row switch circuit 131-2.

[0173] The fourth area A4 is accessed through the second column switch circuit 121 - 2 in the on state and the second row switch circuit 131 - 2 in the on state.

[0174] like Figure 8 As shown in (c), the memory cell MC in the fourth area A4 is connected to the global bit line GBL through the second column switch circuit 121-2 in the on state. Fig. 9 As shown in (c), the memory cell MC in the fourth area A4 is connected to the global word line GWL via the second row switch circuit 131-2 in the on state.

[0175] When the memory cell MC in the fourth area A4 is selected as an operation target, the first column switch circuit 121 - 1 and the first row switch circuit 131 - 1 are set to the off state.

[0176] The fifth area A5 is located in a corner area on the southwest side of the memory cell array 110. The fifth area A5 is adjacent to the first column switch circuit 121-1 and the second row switch circuit 131-2.

[0177] With respect to the columns of the memory cell array 110, the memory cells MC in the 5th region A5 are arranged at positions close to the voltage / current supply source. With respect to the distance between the memory cells MC and the two column switch circuits 121 in the X direction, the memory cells MC in the 5th region A5 are close to the first column switch circuit 121-1 and away from the second column switch circuit 121-2. With respect to the rows of the memory cell array 110, the memory cells MC in the 5th region A5 are arranged at positions close to the voltage / current supply source. With respect to the distance between the memory cells MC and the two row switch circuits 131 in the Y direction, the memory cells MC in the 5th region A5 are away from the first row switch circuit 131-1 and close to the second row switch circuit 131-2.

[0178] The fifth area A5 is accessed through the first column switch circuit 121 - 1 in the on state and the second row switch circuit 131 - 2 in the on state.

[0179] like Figure 8 As shown in (b), the memory cell MC in the fifth area A5 is connected to the global bit line GBL through the first column switch circuit 121-1 in the on state. Fig. 9 As shown in (c), the memory cell MC in the fifth area A5 is connected to the global word line GWL via the second row switch circuit 131-2 in the on state.

[0180] When the memory cell MC in the fifth area A5 is selected as the operation target, the second column switch circuit 121 - 2 and the first row switch circuit 131 - 1 are set to the off state.

[0181] The sixth area A6 (A6-1, A6-2, A6-3) is an area between the second area A2 and the third area A3 and is located on the north side (the first row switch circuit 131-1 side) of the first area A1. The sixth area A6 is surrounded by the first area A1, the second area A2, and the third area A3.

[0182] The sixth area A6 includes an area A6-1 between the first area A1 and the first row switch circuit 131-1, an area A6-2 between the second area A2 and the ninth area A9 (A9-1, A9-3) to be described later, and an area A6-3 between the third area A3 and the seventh area A7 (A7-1, A7-2) to be described later. The area A6-1 is surrounded by the three areas A1, A2, and A3. The area A6-1 is adjacent to the first area A1 and the areas A7-2 and A9-3 to be described later.

[0183] The sixth area A6 is accessed through the two column switch circuits 121 - 1 and 121 - 2 in the on state and the first row switch circuit 131 - 1 in the on state.

[0184] like Figure 8 As shown in (a), the memory cell MC in the sixth area A6 is connected to the global bit line GBL via the first column switch circuit 121-1 and the second column switch circuit 121-2 in the on state. Fig. 9 As shown in (b), the memory cell MC in the sixth area A6 is connected to the global word line GWL via the first row switch circuit 131-1 in the on state.

[0185] When the memory cell MC in the sixth area A6 is selected as the operation target, the second row switch circuit 131 - 2 is set to the off state.

[0186] The seventh area A7 (A7-1, A7-2, A7-3) is an area between the third area A3 and the fourth area A4 and is located east of the first area A1 (on the second column switch circuit 121-2 side). The seventh area A7 is surrounded by the first area A1, the third area A3, and the fourth area A4.

[0187] The seventh area A7 includes an area A7-1 between the first area A1 and the second column switch circuit 121-2, an area A7-2 between the third area A3 and the sixth area A6 (A6-1, A6-2), and an area A7-3 between the fourth area A4 and the eighth area A8 (A8-1, A8-2) described later. The area A7-1 is surrounded by the three areas A1, A3, and A4. The area A7-1 is adjacent to the first area A1, the area A6-3, and the area A8-2 described later.

[0188] The seventh area A7 is accessed through the second column switch circuit 121 - 2 in the on state and the two row switch circuits 131 - 1 and 131 - 2 in the on state.

[0189] like Figure 8 As shown in (c), the memory cell MC in the seventh area A7 is connected to the global bit line GBL via the second column switch circuit 121-2 in the on state. Fig. 9 As shown in (a), the memory cells MC in the seventh area A7 are connected to the global word line GWL via the first row switch circuit 131-1 and the second row switch circuit 131-2 which are in the on state.

[0190] When the memory cell MC in the seventh area A7 is selected as the operation target, the first column switch circuit 121 - 1 is set to the off state.

[0191] The eighth area A8 is an area between the fourth area A4 and the fifth area A5 and is located on the south side (the second row switch circuit 131-2 side) of the first area A1. The eighth area A8 is surrounded by the first area A1, the fourth area A4, and the fifth area A5.

[0192] The eighth area A8 includes: an area A8-1 between the first area A1 and the second row switch circuit 131-2, an area A8-2 between the fourth area A4 and the seventh area A7 (A7-1, A7-3), and an area A8-3 between the fifth area A5 and the ninth area A9 (A9-1, A9-2) described later. Area A8-1 is surrounded by the three areas A1, A4, and A5. Area A8-1 is adjacent to the first area A1, area A7-3, and area A9-2 described later.

[0193] The eighth area A8 is accessed through the two column switch circuits 121-1 and 121-2 in the on state and the second row switch circuit 131-2 in the on state.

[0194] like Figure 8 As shown in (a), the memory cell MC in the sixth area A6 is connected to the global bit line GBL via the first column switch circuit 121-1 and the second column switch circuit 121-2 in the on state. Fig. 9 As shown in (c), the memory cell MC in the sixth area A6 is connected to the global word line GWL via the second row switch circuit 131-2 in the on state.

[0195] When the memory cell MC in the eighth area A8 is selected as the operation target, the first row switch circuit 131 - 1 is set to the off state.

[0196] The ninth area A9 (A9-1, A9-2, A9-3) is an area between the second area A2 and the fifth area A5 and is located westward (on the first column switch circuit 121-1 side) of the first area A1. The ninth area A9 is surrounded by the first area A1, the second area A2, and the fifth area A5.

[0197] The ninth area A9 includes an area A9-1 between the first area A1 and the first column switch circuit 121-1, an area A9-2 between the fifth area A5 and the eighth area A8 (A8-1, A8-3), and an area A9-3 between the second area A2 and the sixth area A6 (A6-1, A6-2). The area A9-1 is surrounded by the three areas A1, A2, and A5. The area A9-1 is adjacent to the first area A1, the area A6-2, and the area A8-3.

[0198] The ninth area A9 is accessed through the first column switch circuit 121 - 1 in the on state and the two row switch circuits 131 - 1 and 131 - 2 in the on state.

[0199] like Figure 8 As shown in (b), the memory cell MC in the ninth area A9 is connected to the global bit line GBL via the first column switch circuit 121-1 in the on state. Fig. 9 As shown in (a), the memory cell MC in the ninth area A9 is connected to the global word line GWL via the first row switch circuit 131-1 and the second row switch circuit 131-2 which are in the on state.

[0200] When the memory cell MC in the ninth area A9 is selected as the operation target, the second column switch circuit 121 - 2 is set to the off state.

[0201] As described above, in the MRAM 100 of the present embodiment, nine areas A1 , . . . , A9 are set in the memory cell array 110 .

[0202] As a tendency of the wiring resistance of the memory cells MC applied to each area A1, ..., A9, the wiring resistance of the memory cells MC applied to each area A6, A7, A8, A9 is higher than the wiring resistance of the memory cells MC applied to each area A2, A3, A4, A5, and lower than the wiring resistance of the memory cells MC applied to area A1.

[0203] In this embodiment, the area A1, ..., A9 including the memory cell MC to be operated is identified based on the address ADR provided to the MRAM 100. The column switch circuit 121 and the row switch circuit 131 to be activated are determined based on the identification result of the area A1, ..., A9.

[0204] (a-7) Allocation conditions of storage units in each area

[0205] The conditions under which each memory cell MC is allocated to each of the above-mentioned areas A1, ..., A9 are described.

[0206] Here, when the memory cell array 110 has a square array size, “M” is equal to “N.” In addition, the magnitude of the resistance between the memory cells MC adjacent to each other in the X direction is equal to the magnitude of the resistance between the memory cells MC adjacent to each other in the Y direction.

[0207] The wiring resistance between the memory cell MC in the first area A1 and the global bit line GBL is Rs×(x-0.5)(N-x+0.5) / N. The wiring resistance between the memory cell MC in the first area A1 and the global word line GWL is Rs×(y-0.5)(N-y+0.5) / N.

[0208] The memory cells MC allocated to the first area A1 satisfy the following conditional expressions (Expression 1a), (Expression 1b), (Expression 1c), and (Expression 1d).

[0209] (xN) 2 +(yN / 2) 2 ≤N 2 / 2…(Formula 1a)

[0210] x 2 +(yN / 2) 2 ≤N 2 / 2…(Formula 1b)

[0211] (xN / 2) 2 +(yN) 2 ≤N 2 / 2…(Formula 1c)

[0212] (xN / 2) 2 +y 2 ≤N 2 / 2…(Formula 1d)

[0213] The wiring resistance between the memory cell MC in the second area A2 and the global bit line GBL is Rs×(x-0.5). The wiring resistance between the memory cell MC in the second area A2 and the global word line GWL is Rs×(y-0.5).

[0214] The memory cells MC allocated to the second area A2 satisfy the conditional expression shown below (Expression 2).

[0215] x+y≤N / 2…(Formula 2)

[0216] The wiring resistance between the memory cell MC in the third area A3 and the global bit line GBL is Rs×(N-x+0.5). The wiring resistance between the memory cell MC in the third area A3 and the global word line GWL is Rs×(y-0.5).

[0217] The memory cells MC allocated to the third area A3 satisfy the conditional expression shown below (Expression 3).

[0218] (Nx)+y≤N / 2…(Formula 3)

[0219] The wiring resistance between the memory cell MC in the fourth area A4 and the global bit line GBL is Rs×(N-x+0.5). The wiring resistance between the memory cell MC in the fourth area A4 and the global word line GWL is Rs×(N-y+0.5).

[0220] The memory cells MC allocated to the fourth area A4 satisfy the conditional expression shown below (Expression 4).

[0221] (Nx)+(Ny)≤N / 2…(Formula 4)

[0222] The wiring resistance between the memory cell MC in the fifth area A5 and the global bit line GBL is Rs×(x-0.5). The wiring resistance between the memory cell MC in the fifth area A5 and the global word line GWL is Rs×(N-y+0.5).

[0223] The memory cells MC allocated to the fifth area A5 satisfy the conditional expression shown below (Expression 5).

[0224] x+(Ny)≤N / 2…(Formula 5)

[0225] The wiring resistance between the memory cell MC in the sixth area A6 and the global bit line GBL is Rs×(x-0.5)(N-x+0.5) / N. The wiring resistance between the memory cell MC in the sixth area A6 and the global word line GWL is Rs×(y-0.5).

[0226] The memory cells MC allocated to the sixth area A6 satisfy the following conditional expressions (Expression 6a), (Expression 6b), and (Expression 6c).

[0227] (xN) 2 +(yN / 2) 2 ≥N 2 / 2 and (xN / 2) 2 +(yN) 2 ≤N 2 / 2 and (xN / 2) 2 +y 2 ≤N 2 / 2…(Formula 6a)

[0228] (xN) 2 +(yN / 2) 2 ≥N 2 / 2 and x+y≥N / 2 and x+(Ny)≤N…(Formula 6b)

[0229] (xN) 2 +(yN / 2) 2 ≥N 2 / 2 and (Nx)+y≥N / 2 and (Nx)+(Ny)≤N…(Formula 6c)

[0230] The wiring resistance between the memory cell MC in the seventh area A7 and the global bit line GBL is Rs×(N-x+0.5) / N. The wiring resistance between the memory cell MC in the seventh area A7 and the global word line GWL is Rs×(y-0.5)(N-y+0.5) / N.

[0231] The memory cells MC allocated to the seventh area A7 satisfy the following conditional expressions (Expression 7a), (Expression 7b), and (Expression 7c).

[0232] x 2 +(yN) 2 ≥N 2 / 2 and (xN) 2 +(yN / 2) 2 ≤N 2 / 2 and x 2 +(yN / 2) 2 ≤N 2 / 2…(Formula 7a)

[0233] x 2 +(yN) 2 ≥N 2 / 2 and (Nx)+y≥N / 2 and x+y≤N…(Formula 7b)

[0234] x 2 +(yN) 2 ≥N 2 / 2 and (Nx)+(Ny)≥N / 2 and x+(Ny)≤N…(Formula 7c)

[0235] The wiring resistance between the memory cell MC in the eighth area A8 and the global bit line GBL is Rs×(x-0.5)(N-x+0.5) / N. The wiring resistance between the memory cell MC in the eighth area A8 and the global word line GWL is Rs×(N-y+0.5).

[0236] The memory cells MC allocated to the eighth area A8 satisfy the following conditional expressions (Expression 8a), (Expression 8b), and (Expression 8c).

[0237] x 2 +(yN / 2) 2 ≥N 2 / 2 and (xN / 2) 2 +(yN) 2 ≤N 2 / 2 and (xN / 2) 2 +y 2 ≤N 2 / 2…(Equation 8a)

[0238] x 2 +(yN / 2) 2 ≥N 2 / 2 and x+(Ny)≥N / 2 and x+y≤N…(Formula 8b)

[0239] x 2 +(yN / 2) 2 ≥N 2 / 2 and (Nx) + (Ny) ≥ N / 2 and (Nx) + y ≤ N… (Formula 8c)

[0240] The wiring resistance between the memory cell MC in the ninth area A9 and the global bit line GBL is Rs×(x-0.5). The wiring resistance between the memory cell MC in the ninth area A9 and the global word line GWL is Rs×(y-0.5)(N-y+0.5).

[0241] The memory cells MC allocated to the ninth area A9 satisfy the following conditional expressions (Expression 9a), (Expression 9b), and (Expression 9c).

[0242] (xN / 2) 2 +(yN) 2 ≥N 2 / 2 and (xN) 2 +(yN / 2) 2 ≤N 2 / 2 and x 2 +(yN / 2) 2 ≤N 2 / 2…(Formula 9a)

[0243] (xN / 2) 2 +(yN) 2 ≥N 2 / 2 and x+y≥N / 2 and (Nx)+y≤N…(Formula 9b)

[0244] (xN / 2) 2 +(yN) 2 ≥N 2 / 2 and x+(Ny)≥N / 2 and (Nx)+(Ny)≤N…(Formula 9c)

[0245] As described above, the wiring resistance applied to the memory cell MC (the wiring resistance between the memory cell MC and the global wirings GBL and GWL) corresponds to the coordinates of the memory cell MC in the memory cell array 110. Therefore, based on the coordinates of the memory cell MC in the memory cell array 110, the memory cell MC can be allocated to the areas A1, A2, ..., A9 set in the memory cell array.

[0246] In addition, according to the coordinates (x, y) of the memory cell MC, the memory cell MC existing at the boundary between multiple areas A (A1 to A9) (and near the boundary) may be suitable for the allocation conditions of multiple areas A. In this case, one memory cell MC can be allocated to multiple areas A. If the memory cell existing at the boundary between multiple areas A is suitable for the allocation conditions of each area A, it can be allocated to any area A. It is desirable to design the operation of the column switch circuit 121 and / or the operation of the row switch circuit 131 so that the memory cell MC existing at the boundary between multiple areas and suitable for multiple allocation conditions can be allocated to any area A. As a result, it is possible to prevent the malfunction of the memory cell MC at the boundary between multiple areas A.

[0247] (b) Action example

[0248] Reference Figures 11 to 14 , an operation example of the storage device (MRAM) 100 according to this embodiment is described.

[0249] The MRAM 100 of this embodiment receives a command CMD, an address ADR, and various control signals CNT from the external device 900. When the command CMD to be executed is a write operation, the MRAM 100 of this embodiment further receives write data DT from the external device 900.

[0250] The MRAM 100 of the present embodiment starts a commanded operation (a write operation or a read operation) based on the command CMD, the address ADR, and various control signals CNT.

[0251] The control circuit 180 performs various controls according to the operation to be executed based on the command CMD and various control signals CNT. The control circuit 180 decodes the address ADR.

[0252] The column control circuit 120 and the row control circuit 130 activate the column switch circuit 121 and the row switch circuit 131 based on the decoding result of the address ADR.

[0253] In the present embodiment, based on the coordinates (address ADR) of the memory cell MC to be operated, one or two column switch circuits 121 - 1 , 121 - 2 and one or two row switch circuits 131 - 1 , 131 - 2 are activated.

[0254] The memory cell (selected cell) MC indicated by the address ADR is accessed through one or two activated column switch circuits 121-1, 121-2 and one or two activated row switch circuits 131-1, 131-2. The voltage and current for the operation to be performed are supplied to the selected cell MC via the bit line BL and the word line WL.

[0255] Fig.11 Schematic diagram showing the supply path of voltage and current when the memory cell MC in the first area A1 is selected as the operation target. Fig.11 , an example in which the current Ia flows from the global bit line GBL to the global word line GWL is shown.

[0256] like Fig.11 As shown, when the memory cell MC in the first area A1 is selected, the two column switch circuits 121-1 and 121-2 are set to the on state, and the two row switch circuits 131-1 and 131-2 are set to the on state.

[0257] Current Ia flows from the column switch circuit 121-1 to the selection unit MC via the resistor (wiring resistor) RX1 (=(x-0.5)×Rs), and flows from the column switch circuit 121-2 to the selection unit via the resistor (wiring resistor) RX2 (=(M-x+0.5)×Rs).

[0258] Current Ia flows from the selection unit MC to the row switch circuit 131-1 via the resistor (wiring resistance) RY1 (=(y-0.5)×Rs), and flows from the selection unit MC to the row switch circuit 131-2 via the resistor (wiring resistance) RY2 (=(N-y+0.5)×Rs).

[0259] As described above, in the write operation or the read operation of the MRAM 100 , voltage and current are supplied to the selected cells MC in the first area A1 via the two column switch circuits 121 - 1 and 121 - 2 and the two row switch circuits 131 - 1 and 131 - 2 .

[0260] Fig.12 Schematic diagram showing the supply path of voltage and current when the memory cell MC in the second area A2 is selected as the operation target. Fig.12 , an example in which the current Ia flows from the global bit line GBL to the global word line GWL is shown.

[0261] like Fig.12 As shown, when the memory cell MC in the second area A2 is selected, one column switch circuit 121-1 is set to an on state, and one row switch circuit 131-1 is set to an on state.

[0262] The current Ia flows from the column switch circuit 121 - 1 to the selected cell MC via the resistor RX1 .

[0263] The current Ia flows from the selected cell MC to the row switch circuit 131 - 1 via the resistor RY1 .

[0264] In this way, in the write operation or the read operation of the MRAM 100 , a voltage and a current are supplied to the selected cell MC in the second area A2 via one column switch circuit 121 - 1 and one row switch circuit 131 - 1 .

[0265] Similar to the selected cell MC in the second area A2 , the selected cells MC in the third area A3 , the fourth area A4 , and the fifth area A5 are supplied with the current Ia via one of the two column switch circuits 121 and one of the two row switch circuits 131 .

[0266] Fig.13 Schematic diagram showing the supply path of voltage and current when the memory cell MC in the sixth area A6 is selected as the operation target. Fig.13 , an example in which the current Ia flows from the global bit line GBL to the global word line GWL is shown.

[0267] like Fig.13 As shown, when the memory cell MC in the sixth area A6 is selected, the two column switch circuits 121-1 and 121-2 are set to the on state, and the one row switch circuit 131-1 is set to the on state.

[0268] The current Ia flows from the column switch circuit 121 - 1 to the selected cell MC via the resistor RX1 , and flows from the column switch circuit 121 - 2 to the selected cell MC via the resistor RX2 .

[0269] The current Ia flows from the selected cell MC to the row switch circuit 131 - 1 via the resistor RY1 .

[0270] Thus, in the write operation or the read operation of the MRAM 100 , voltage and current are supplied to the selected cell MC in the sixth area A6 via the two column switch circuits 121 - 1 and 121 - 2 and the one row switch circuit 131 - 1 .

[0271] The selected cell MC in the eighth area A8 is also supplied with the current Ia via the two column switch circuits 121 - 1 and 121 - 2 and the one row switch circuit 131 - 2 in substantially the same manner as the selected cell MC in the sixth area A6 .

[0272] Fig.14 Schematic diagram showing the supply path of voltage and current when the memory cell MC in the seventh area A7 is selected as the operation target. Fig.14 , an example in which the current Ia flows from the global bit line GBL to the global word line GWL is shown.

[0273] like Fig.14 As shown, when the memory cell MC in the seventh area A7 is selected, one column switch circuit 121-2 is set to an on state, and two row switch circuits 131-1 and 131-2 are set to an on state.

[0274] The current Ia flows from the column switch circuit 121 - 2 to the selected cell MC via the resistor RX1 .

[0275] The current Ia flows from the selection cell MC to the row switch circuit 131 - 1 via the resistor RY1 , and flows from the selection cell MC to the row switch circuit 131 - 2 via the resistor RY2 .

[0276] In this way, in the write operation or the read operation of the MRAM 100 , voltage and current are supplied to the selected cell MC in the seventh area A7 via the one column switch circuit 121 - 2 and the two row switch circuits 131 - 1 and 131 - 2 .

[0277] The selected cell MC in the ninth area A9 is also supplied with the current Ia via one column switch circuit 121 - 1 and two row switch circuits 131 - 1 and 131 - 2 in substantially the same manner as the selected cell MC in the seventh area A7 .

[0278] As described above, when the MRAM 100 of this embodiment performs various operations, at least one of the two column switch circuits 121 and at least one of the two row switch circuits 131 are activated according to the coordinates of the memory cell MC corresponding to the supplied address ADR.

[0279] Thus, the MRAM 100 of the present embodiment can alleviate the influence of the difference in wiring resistance applied to the memory cells MC due to the positions of the memory cells MC in the memory cell array 110 .

[0280] (c) Experiment

[0281] Reference Fig.15 , the characteristics of the MRAM 100 of this embodiment are described.

[0282] Fig.15 Graph showing the results of experiments on the MRAM 100 of the present embodiment.

[0283] Fig.15 The horizontal axis of the graph corresponds to the wiring resistance applied to the memory cell. Fig.15 The vertical axis of the graph corresponds to the Z value associated with malfunction.

[0284] exist Fig.15 In FIG. 1 , a characteristic P1 formed by a set of quadrilateral plots shows the experimental result of the MRAM of the comparative example, and a characteristic P2 formed by a set of cross plots shows the experimental result of the MRAM 100 of the present embodiment.

[0285] In the MRAM of the comparative example, two column switch circuits and two row switch circuits are activated to access the selected memory cell in a manner independent of the coordinates of the memory cell in the memory cell array.

[0286] exist Fig.15 In the example, one of the memory cells MC in the first area A1 has the highest wiring resistance Rfar. One of the memory cells MC in each of the second area A2 to the fifth area A5 has the lowest wiring resistance Rnear. One of the memory cells MC in each of the sixth area A6 to the ninth area A9 has the wiring resistance R1.

[0287] like Fig.15 As shown in FIG. 1 , the Z value associated with the malfunction of the MRAM 100 of the present embodiment is lower than the Z value associated with the malfunction of the MRAM 100 of the comparative example.

[0288] For example, in the comparative example MRAM, 38% of the memory cells having a resistance value less than or equal to wiring resistance R1 may cause malfunction. In contrast, in the MRAM 100 of the present embodiment, 16% of the memory cells having a resistance value less than or equal to wiring resistance R1 may cause malfunction.

[0289] As described above, the MRAM 100 of the present embodiment can reduce the proportion of memory cells that may malfunction due to the coordinates of the memory cells (wiring resistance).

[0290] (d) Summary

[0291] In the MRAM 100 of the present embodiment, the memory cell array 110 includes nine areas A1, . . . , A9 set based on the coordinates of the memory cells MC.

[0292] The MRAM 100 of this embodiment activates one or both of the two column switch circuits 121 and one or both of the two row switch circuits 131 according to the coordinates of the memory cell MC to be operated.

[0293] The bit line BL connected to the selected memory cell MC is connected to the global bit line GBL via one column switch circuit 121 or two column switch circuits 121 according to the coordinates of the memory cell MC. The word line WL connected to the selected memory cell MC is connected to the global word line GWL via one row switch circuit 131 or two row switch circuits 131 according to the coordinates of the memory cell MC.

[0294] Thus, the MRAM 100 of the present embodiment can reduce the difference in wiring resistance applied to the memory cell MC due to the coordinates of the memory cell MC.

[0295] As a result, the MRAM 100 of the present embodiment can reduce malfunctions in the memory cells MC.

[0296] As described above, the storage device according to the present embodiment can improve reliability.

[0297] (2) Second Embodiment

[0298] A storage device according to a second embodiment will be described. In the description of the storage device of this embodiment, reference is made to Figures 1 to 14 .

[0299] Regarding the memory cell array 110 of a memory device such as the MRAM 100 , the size of the column of the memory cell array 110 and the size of the row of the memory cell array 110 may be different.

[0300] In the above Figure 7 as well as Fig.10 In the case where the size of the column of the memory cell array 110 is different from the size of the row of the memory cell array 110, the value of "M" is different from the value of "N". In this case, the memory cell array 110 has a rectangular layout when viewed from the Z direction.

[0301] Furthermore, the magnitude of the resistance (Rs_X) between two memory cells MC adjacent to each other in the X direction may be different from the magnitude of the resistance (Rs_Y) between two memory cells MC adjacent to each other in the Y direction.

[0302] In this embodiment, Figure 7 Similarly, nine areas A1, . . . , A9 are set in the rectangular memory cell array 110 based on the coordinates of the memory cells MC and the wiring resistance.

[0303] The following wiring resistance is applied to each of the memory cells MC in each of the areas A1, . . . , A9.

[0304] Regarding the columns of the first area A1, a wiring resistance of Rs_x×M / ((x-0.5)(M-x+0.5)) is applied to the memory cells MC in the first area A1 through the two column switch circuits 121-1 and 121-2. Regarding the rows of the first area A1, a wiring resistance of Rs_y×N / ((y-0.5)(N-y+0.5)) is applied to the memory cells MC in the first area A1 through the two row switch circuits 131-1 and 131-2.

[0305] Regarding the columns of the second area A2, the first column switch circuit 121-1 applies a wiring resistance of Rs_x×(x-0.5) to the memory cells MC in the second area A2. Regarding the rows of the second area A2, the first row switch circuit 131-1 applies a wiring resistance of Rs_y×(y-0.5) to the memory cells MC in the second area A2.

[0306] Regarding the column of the third area A3, the second column switch circuit 121-2 applies a wiring resistance of Rs_x×(M-x+0.5) to the memory cell MC in the third area A3. Regarding the row of the third area A3, the first row switch circuit 131-1 applies a wiring resistance of Rs_y×(y-0.5) to the memory cell MC in the third area A3.

[0307] For the column of the fourth area A4, the second column switch circuit 121-2 applies a wiring resistance of Rs_x×(M-x+0.5) to the memory cell MC in the fourth area A4. For the row of the fourth area A4, the second row switch circuit 131-2 applies a wiring resistance of Rs_y×(N-y+0.5).

[0308] Regarding the column of the fifth area A5, a wiring resistance of Rs_x×(x-0.5) is applied to the memory cell MC in the fifth area A5 through the first column switch circuit 121-1. Regarding the row of the fifth area A5, a wiring resistance of Rs_y×(N-y+0.5) is applied to the memory cell MC in the fifth area A5 through the two row switch circuits 131-1 and 131-2.

[0309] Regarding the column of the 6th area A6, a wiring resistance of Rs_x×M / ((x-0.5)(M-x+0.5)) is applied to the memory cell MC in the 6th area A6 through the two column switch circuits 121-1 and 121-2. Regarding the row of the 6th area A6, a wiring resistance of Rs_y×(y-0.5) is applied to the memory cell MC in the 6th area A6 through the first row switch circuit 131-1.

[0310] Regarding the column of the 7th area A7, a wiring resistance of Rs_x×(M-x+0.5) is applied to the memory cell MC in the 7th area A7 through the second column switch circuit 121-2. Regarding the row of the 7th area A7, a wiring resistance of Rs_y×N / ((y-0.5)(N-y+0.5)) is applied to the memory cell MC in the 7th area A7 through the two row switch circuits 131-1 and 131-2.

[0311] Regarding the column of the 8th area A8, a wiring resistance of Rs_x×M / ((x-0.5)(M-x+0.5)) is applied to the memory cell MC in the 8th area A8 through the two column switch circuits 121-1 and 121-2. Regarding the row of the 8th area A8, a wiring resistance of Rs_y×(N-y+0.5) is applied to the memory cell MC in the 8th area A8 through the second row switch circuit 131-2.

[0312] Regarding the column of the 9th area A9, a wiring resistance of Rs_x×(x-0.5) is applied to the memory cell MC in the 9th area A9 through the first column switch circuit 121-1. Regarding the row of the 9th area A9, a wiring resistance of Rs_y×N / ((y-0.5)(N-y+0.5)) is applied to the memory cell MC in the 9th area A9 through the two row switch circuits 131-1 and 131-2.

[0313] As described above, the MRAM 100 of the present embodiment can reduce the difference in wiring resistance according to the coordinates of the memory cells MC by controlling the column switch circuits 121 and the row switch circuits 131 .

[0314] Therefore, the storage device of this embodiment can obtain the same effects as those of the first embodiment.

[0315] (3) Others

[0316] In the storage device 100 of the above-described embodiment, nine areas A1, ..., A9 are set in the storage cell array 110. However, the number of areas set in the storage cell array 110 is not limited to nine. The number of areas set in the storage cell array 110 may be less than nine or more than nine. For example, five areas may be set in the storage cell array 110 by setting areas in the center and four corner areas of the quadrilateral storage cell array 110.

[0317] In the above-mentioned embodiment, MRAM is exemplified as the storage device 100 of this embodiment. However, the storage device 100 of this embodiment may be a storage device other than MRAM.

[0318] For example, the storage device 100 of the present embodiment may be a storage device that uses a transition metal oxide element having a variable resistance characteristic in a storage element (for example, a resistance change memory such as ReRAM (Resistive Random Access Memory)), a storage device that uses a phase change element in a storage element (for example, a phase change memory such as PCRAM (Phase Change Random Access Memory)), or a storage device that uses a ferroelectric element in a storage element (for example, a ferroelectric memory such as FeRAM (Ferroelectric Random Access Memory)).

[0319] The memory device 100 of the present embodiment can obtain the effects described in the above embodiments even if it is a memory device other than an MRAM.

[0320] Several embodiments have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope of their equivalents.< / y> < / x> < / n> < / y> < / m> < / x> < / m> < / n>

Claims

1. A storage device comprising: A memory cell array, comprising a plurality of bit lines, a plurality of word lines and a plurality of memory cells, wherein a first region to a ninth region are set, and the plurality of memory cells are respectively connected to a bit line of the plurality of bit lines and a word line of the plurality of word lines; A first column switch circuit connected to the plurality of bit lines and disposed on one end side of the memory cell array in a first direction; a second column switch circuit connected to the plurality of bit lines and arranged on the other end side of the memory cell array in the first direction; a first row switch circuit connected to the plurality of word lines and disposed on one end side of the memory cell array in the second direction; and a second row switch circuit connected to the plurality of word lines and disposed on the other end side of the memory cell array in the second direction; When a memory cell in the first area is selected, the first column switch circuit and the second column switch circuit, and the first row switch circuit and the second row switch circuit are activated. When the memory cell in the second area is selected, the first column switch circuit and the first row switch circuit are activated. When the memory cell in the third area is selected, the second column switch circuit and the first row switch circuit are activated. When the memory cell in the fourth area is selected, the second column switch circuit and the second row switch circuit are activated. When the memory cell in the fifth area is selected, the first column switch circuit and the second row switch circuit are activated. When the memory cell in the sixth area is selected, the first column switch circuit, the second column switch circuit, and the first row switch circuit are activated. When the memory cell in the seventh area is selected, the second column switch circuit, the first row switch circuit, and the second row switch circuit are activated. When the memory cell in the eighth area is selected, the first column switch circuit, the second column switch circuit, and the second row switch circuit are activated. When the memory cell in the ninth area is selected, the first column switch circuit, the first row switch circuit, and the second row switch circuit are activated.

2. The storage device according to claim 1, The memory cell array has a quadrilateral layout, The first region is arranged in a central area of ​​the memory cell array. The second region is arranged in a first corner region of the memory cell array, The third region is arranged in a second corner region of the memory cell array, The fourth region is arranged in the third corner region of the memory cell array, The fifth region is arranged in a fourth corner region of the memory cell array, The sixth zone is arranged between the first zone, the second zone and the third zone, The seventh zone is arranged between the first zone, the third zone and the fourth zone, The eighth zone is arranged between the first zone, the fourth zone and the fifth zone, The ninth area is arranged between the first area, the second area, and the fifth area.

3. The storage device according to claim 2, The sixth zone includes the first zone, the second zone and the third zone, The seventh zone includes the fourth zone, the fifth zone and the sixth zone, The eighth zone includes the seventh zone, the eighth zone and the ninth zone, The ninth zone includes a tenth zone, an eleventh zone, and a twelfth zone, The first region is disposed between the first zone, the second zone, and the third zone. The second region is disposed between the second zone and the tenth zone, The third region is disposed between the third area and the fourth region, The fourth area is disposed between the first area, the third area, and the fourth area. The fifth area is arranged between the third area and the first area, The sixth area is arranged between the fourth area and the seventh area, The seventh area is arranged between the first area, the fourth area and the fifth area, The eighth area is arranged between the fourth area and the fourth area, The ninth area is arranged between the fifth area and the tenth area, The tenth area is disposed between the first area, the second area, and the fifth area. The 11th area is arranged between the 5th area and the 7th area, The twelfth region is provided between the second region and the first region.

4. The storage device according to claim 1, further comprising: A global bit line connected to the first column switch circuit and the second column switch circuit; and The global word line is connected to the first row of switch circuits and the second row of switch circuits.

5. The storage device according to claim 4, When the memory cell in the sixth area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and the second column switch circuit, and is connected to the global word line via the first row switch circuit. When the memory cell in the seventh area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit, and is connected to the global word line via the first row switch circuit and the second row switch circuit. When the memory cell in the eighth region is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and the second column switch circuit, and is connected to the global word line via the second row switch circuit. When the memory cell in the ninth block is selected, the selected memory cell is connected to the global bit line via the first column switch circuit, and is connected to the global word line via the first row switch circuit and the second row switch circuit.

6. The storage device according to claim 5, When a memory cell in the first area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and the second column switch circuit, and is connected to the global word line via the first row switch circuit and the second row switch circuit. When a memory cell in the second area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and is connected to the global word line via the first row switch circuit. When a memory cell in the third area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and is connected to the global word line via the first row switch circuit. When a memory cell in the fourth area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and is connected to the global word line via the second row switch circuit. When a memory cell in the fifth area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and is connected to the global word line via the second row switch circuit.

7. The storage device according to claim 1, The wiring resistance applied to the memory cells in the 6th, 7th, 8th and 9th regions is higher than the wiring resistance applied to the memory cells in the 2nd, 3rd, 4th and 5th regions, and lower than the wiring resistance applied to the memory cells in the 1st region.

8. The storage device according to claim 1, According to the address of the memory cell to be operated among the plurality of memory cells, one or both of the first column switch circuit and the second column switch circuit are activated, and one or both of the first row switch circuit and the second row switch circuit are activated.

9. The storage device according to claim 1, Each of the plurality of storage units comprises: Storage element; and A switch element is connected in series with the storage element.

10. The storage device according to claim 9, The storage element is a magnetoresistive effect element.

11. A storage device comprising: A memory cell array, comprising a plurality of bit lines, a plurality of word lines and a plurality of memory cells, wherein a first region to a ninth region are set, and the plurality of memory cells are respectively connected to a bit line of the plurality of bit lines and a word line of the plurality of word lines; A first column switch circuit connected to the plurality of bit lines and disposed on one end side of the memory cell array in a first direction; a second column switch circuit connected to the plurality of bit lines and arranged on the other end side of the memory cell array in the first direction; a first row switch circuit connected to the plurality of word lines and disposed on one end side of the memory cell array in the second direction; and a second row switch circuit connected to the plurality of word lines and disposed on the other end side of the memory cell array in the second direction; According to the address of the memory cell to be operated among the plurality of memory cells, one or both of the first column switch circuit and the second column switch circuit are activated, and one or both of the first row switch circuit and the second row switch circuit are activated.

12. The storage device according to claim 11, The memory cell array has a quadrilateral layout, The first region is arranged in a central area of ​​the memory cell array. The second region is arranged in a first corner region of the memory cell array, The third region is arranged in a second corner region of the memory cell array, The fourth region is arranged in the third corner region of the memory cell array, The fifth region is arranged in a fourth corner region of the memory cell array, The sixth zone is arranged between the first zone, the second zone and the third zone, The seventh zone is arranged between the first zone, the third zone and the fourth zone, The eighth zone is arranged between the first zone, the fourth zone and the fifth zone, The ninth area is arranged between the first area, the second area, and the fifth area.

13. The storage device according to claim 12, The sixth zone includes the first zone, the second zone and the third zone, The seventh zone includes the fourth zone, the fifth zone and the sixth zone, The eighth zone includes the seventh zone, the eighth zone and the ninth zone, The ninth zone includes a tenth zone, an eleventh zone, and a twelfth zone, The first region is disposed between the first zone, the second zone, and the third zone. The second region is disposed between the second zone and the tenth zone, The third region is disposed between the third area and the fourth region, The fourth area is disposed between the first area, the third area, and the fourth area. The fifth area is arranged between the third area and the first area, The sixth area is arranged between the fourth area and the seventh area, The seventh area is arranged between the first area, the fourth area and the fifth area, The eighth area is arranged between the fourth area and the fourth area, The ninth area is arranged between the fifth area and the tenth area, The tenth area is disposed between the first area, the second area, and the fifth area. The 11th area is arranged between the 5th area and the 7th area, The twelfth region is provided between the second region and the first region.

14. The storage device according to claim 11, further comprising: A global bit line connected to the first column switch circuit and the second column switch circuit; and The global word line is connected to the first row of switch circuits and the second row of switch circuits.

15. The storage device according to claim 14, When the memory cell in the sixth area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and the second column switch circuit, and is connected to the global word line via the first row switch circuit. When the memory cell in the seventh area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit, and is connected to the global word line via the first row switch circuit and the second row switch circuit. When the memory cell in the eighth region is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and the second column switch circuit, and is connected to the global word line via the second row switch circuit. When the memory cell in the ninth block is selected, the selected memory cell is connected to the global bit line via the first column switch circuit, and is connected to the global word line via the first row switch circuit and the second row switch circuit.

16. The storage device according to claim 15, When a memory cell in the first area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and the second column switch circuit, and is connected to the global word line via the first row switch circuit and the second row switch circuit. When a memory cell in the second area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and is connected to the global word line via the first row switch circuit. When a memory cell in the third area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and is connected to the global word line via the first row switch circuit. When a memory cell in the fourth area is selected, the selected memory cell is connected to the global bit line via the second column switch circuit and is connected to the global word line via the second row switch circuit. When a memory cell in the fifth area is selected, the selected memory cell is connected to the global bit line via the first column switch circuit and is connected to the global word line via the second row switch circuit.

17. The storage device according to claim 11, The wiring resistance applied to the memory cells in the 6th, 7th, 8th and 9th regions is higher than the wiring resistance applied to the memory cells in the 2nd, 3rd, 4th and 5th regions, and lower than the wiring resistance applied to the memory cells in the 1st region.

18. The storage device according to claim 11, Each of the plurality of storage units comprises: Storage element; and A switch element is connected in series with the storage element.

19. The storage device according to claim 18, The storage element is a magnetoresistive effect element.

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