Semiconductor memory device, memory system, and control method

Abstract

Provided are a semiconductor memory device, a memory system, and a control method capable of suppressing deterioration of a memory cell. A control circuit of a semiconductor memory device determines whether a first threshold voltage of a memory cell to be written is higher than a second threshold voltage determined according to data to be stored in the memory cell to be written. When the first threshold voltage is higher than the second threshold voltage, the control circuit performs an erase operation for reducing the threshold voltage of the memory cell to be written using the erase voltage so as to cause the memory cell to be written to store the data to be stored.

Description

Related Applications

[0001] This application claims the priority of Japanese Patent Application No. 2023-150050 (filing date: September 15, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] The present embodiment of the present invention relates to a semiconductor storage device, a storage system, and a control method. Background Art

[0003] In recent years, semiconductor storage devices as nonvolatile memories have become widely used. As one of the storage systems including such semiconductor storage devices, a solid state drive (SSD) including a NAND flash memory is known.

[0004] A semiconductor memory device such as a NAND flash memory includes a plurality of memory cells each storing data. The data stored in a memory cell corresponds to the amount of charge accumulated in the charge storage layer of the memory cell. Before the programming operation to store data in the memory cell, an erasing operation to erase the data stored in the memory cell is performed. In a semiconductor memory device, as the erasing operation and programming operation are repeated on the memory cell, the degradation of the memory cell progresses.

[0005] Therefore, a technology capable of suppressing degradation of memory cells is required. Summary of the invention

[0006] An embodiment of the present invention aims to provide a semiconductor memory device, a memory system, and a control method that can suppress degradation of a memory cell.

[0007] According to an embodiment, a semiconductor memory device includes a plurality of memory cells and a control circuit. The plurality of memory cells are configured to store data corresponding to a threshold voltage range to which the threshold voltages of the plurality of memory cells belong. The control circuit is configured to control the plurality of memory cells. The control circuit determines whether a first threshold voltage of a memory cell to be written is higher than a second threshold voltage determined according to the data to be stored in the memory cell to be written. When the first threshold voltage is higher than the second threshold voltage, the control circuit generates an erase voltage applied to the memory cell to be written. The control circuit uses the erase voltage to perform an erase operation to reduce the threshold voltage of the memory cell to be written in such a manner that the memory cell to be written stores the data to be stored. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1This is a block diagram showing a configuration example of a storage system including a semiconductor storage device according to an embodiment. Figure 2 This is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment. Figure 3 FIG. 1 is a diagram showing a configuration example of each of a plurality of blocks included in a memory cell array of a semiconductor memory device according to an embodiment. Figure 4 FIG. 1 is a diagram showing an example of a circuit configuration of each of a plurality of blocks included in a memory cell array of a semiconductor memory device according to an embodiment. Figure 5 FIG. 1 is a diagram showing an example of threshold voltage distribution of a plurality of memory cells included in a semiconductor memory device according to an embodiment. Figure 6 FIG. 1 is a diagram showing an example of a relationship between a threshold voltage distribution and an erase voltage of a plurality of memory cells included in a semiconductor memory device according to an embodiment. Figure 7 FIG. 1 is a diagram showing an example of a memory cell selected as a target of an erase operation in the semiconductor memory device according to the embodiment. Figure 8 A diagram showing an example of the relationship between data in a write target memory cell and data to be written in the write target memory cell in the semiconductor memory device according to the embodiment and the semiconductor memory device according to the comparative example. Fig. 9 This is a block diagram showing a first example of the flow of a write process executed in the semiconductor memory device according to the embodiment. Fig.10 A diagram showing the relationship between a current value read from a memory cell included in a semiconductor memory device according to an embodiment and a threshold voltage. Fig.11 This is a flowchart showing a first example of the procedure of a write process executed in the semiconductor memory device according to the embodiment. Fig. 12A A diagram showing a first example of a change in threshold voltage due to a programming operation performed in the semiconductor memory device according to the embodiment. Fig. 12B FIG. 2 is a diagram showing a second example of a change in threshold voltage due to a program operation performed in the semiconductor memory device according to the embodiment. Fig. 12C FIG. 3 is a diagram showing a third example of a change in threshold voltage due to a programming operation performed in the semiconductor memory device according to the embodiment. Fig.12DFIG. 4 is a diagram showing a fourth example of a change in threshold voltage due to a programming operation performed in the semiconductor memory device according to the embodiment. Fig.13A A diagram showing a first example of a change in threshold voltage due to an erase operation performed in the semiconductor memory device according to the embodiment. Fig. 13B FIG. 2 is a diagram showing a second example of a change in threshold voltage due to an erase operation performed in the semiconductor memory device according to the embodiment. Fig.14 This is a block diagram showing a second example of the flow of the write process executed in the semiconductor memory device according to the embodiment. Fig.15 This is a flowchart showing a second example of the procedure of the write process executed in the semiconductor memory device according to the embodiment. Fig.16 The diagram shows a correspondence relationship between a combination of an original state and a state after writing of a memory cell to be written included in a semiconductor memory device according to an embodiment and a write process. DETAILED DESCRIPTION

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] Hereinafter, it is assumed that the semiconductor storage device according to the embodiment is implemented as a NAND flash memory. Hereinafter, the NAND flash memory is simply referred to as a NAND memory.

[0011] Figure 1 1 is a block diagram showing a configuration example of a storage system 3 including a semiconductor storage device according to an embodiment. The storage system 3 is included in an information processing system 1. The information processing system 1 also includes a host (host device) 2. The host 2 and the storage system 3 can be connected to each other via a bus 10.

[0012] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile device. The host 2 accesses the storage system 3. Specifically, the host 2 sends an input / output (I / O) command to the storage system 3. The I / O command is a command for writing data to the NAND memory 5 or reading data from the NAND memory 5. The I / O command is, for example, a write command or a read command.

[0013] The storage system 3 is a storage device that can be connected to the host 2. The storage system 3 is, for example, a solid state drive (SSD) or a universal flash storage (UFS) device. The storage system 3 includes a NAND memory 5 as a semiconductor storage device.

[0014] The communication between the storage system 3 and the host 2 is performed via the bus 10. The bus 10 is a communication path connecting the host 2 and the storage system 3. The bus 10 is based on, for example, PCI express TM (PCIe TM ) standard or Mobile Industry Processor InterfaceTM (MIPI TM The bus 10 is used to send data and I / O commands from the host 2 to the storage system 3, and to send data and responses from the storage system 3 to the host 2.

[0015] As a standard for the logical interface for connecting the host 2 and the storage system 3, for example, NVM express can be used. TM (NVMe TM )standard.

[0016] Next, the configuration of the host computer 2 will be described. The host computer 2 includes a processor 21 and a memory 22. The processor 21 and the memory 22 are connected to each other via an internal bus 20.

[0017] The processor 21 is, for example, a central processing unit (CPU). The processor 21 executes software (host software) loaded into the memory 22 from the storage system 3 or other storage devices connected to the host 2. The host software includes, for example, an operating system, a file system, and an application program.

[0018] The memory 22 is, for example, a volatile memory. The memory 22 is also called a main memory, a system memory, or a host memory. The memory 22 is, for example, a dynamic random access memory (DRAM).

[0019] Next, the configuration of the storage system 3 will be described.

[0020] The storage system 3 includes a controller 4 and a NAND memory 5. In addition, the storage system 3 further includes a random access memory (RAM), such as a DRAM 6. The DRAM 6 may also be built into the controller 4.

[0021] The controller 4 is a circuit that functions as a memory controller. The controller 4 is, for example, a semiconductor device such as a system-on-a-chip (SoC). The controller 4 is electrically connected to the NAND memory 5. The controller 4 performs write processing and read processing based on each I / O command received from the host 2. The write processing is a processing for writing data to the NAND memory 5. The read processing is a processing for reading data from the NAND memory 5. In the write processing, the controller 4 sends a write request (programming request) to the NAND memory 5. In the read processing, the controller 4 sends a read request to the NAND memory 5. As a standard for the interface that electrically connects the controller 4 to the NAND memory 5, for example, a Toggle interface or an open NAND flash interface (ONFI) is used. The functions of each part of the controller 4 can be implemented by dedicated hardware, a processor that executes a program, or a combination of these dedicated hardware and processors.

[0022] The NAND memory 5 is a semiconductor storage device. In response to a write request received from the controller 4, the NAND memory 5 writes data associated with the write request. In response to a read request received from the controller 4, the NAND memory 5 reads data associated with the read request.

[0023] The NAND memory 5 includes a plurality of blocks. Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages is a unit of a write operation (specifically, a program operation) and a read operation.

[0024] The DRAM 6 is a volatile memory and includes a storage area for storing a logical-to-physical address translation table (L2P table) 61, for example.

[0025] The L2P table 61 is a table for storing mapping information. The mapping information is information showing the mapping between each logical address and each physical address of the NAND memory 5 in units of a predetermined management size. The logical address is an address used by the host 2 to access the storage system 3. As the logical address, for example, a logical block address (LBA) is used. The physical address is an address showing a storage location (physical storage location) in the NAND memory 5.

[0026] Next, the internal structure of the controller 4 is described. The controller 4 includes, for example, a host interface (host I / F) 41, a static RAM (SRAM) 42, a CPU 43, a direct memory access controller (DMAC) 44, an error correction circuit 45, a NAND interface (NAND I / F) 46, and a DRAM interface (DRAM I / F) 47. These host interface 41, SRAM 42, CPU 43, DMAC 44, error correction circuit 45, NAND interface 46, and DRAM interface 47 are connected to each other via an internal bus 40. The controller 4 is configured as an electronic circuit having these components.

[0027] The host interface 41 is an interface circuit for performing communication with the host 2. The host interface 41 performs, for example: processing of taking out each I / O command (write command, read command) from the memory 22 of the host 2; processing of obtaining write data associated with each taken out write command from the memory 22 of the host 2; processing of transferring data read from the NAND memory 5 according to each taken out read command to the memory 22 of the host 2; processing of sending a completion response corresponding to each taken out I / O command to the host 2.

[0028] The SRAM 42 is a volatile memory. The storage area of ​​the SRAM 42 is used, for example, as a work area of ​​the CPU 43. In addition, a part of the storage area of ​​the SRAM 42 can also be used as a write buffer for temporarily storing write data received from the host 2. In addition, a part of the storage area of ​​the DRAM 6 can be used as a write buffer.

[0029] The CPU 43 is a processor. The CPU 43 loads a control program (firmware) stored in the NAND memory 5 or the ROM (not shown) into the SRAM 42. Then, the CPU 43 performs various processes by executing the firmware. Alternatively, the firmware may be loaded into the DRAM 6.

[0030] The CPU 43 manages the data stored in the NAND memory 5 and the blocks included in the NAND memory 5 as, for example, a flash translation layer (FTL). The management of the data stored in the NAND memory 5 includes, for example, the management of mapping information. The CPU 43 manages the mapping between each logical address and each physical address in units of a predetermined management size, for example, using the mapping information of the L2P table 61.

[0031] In the NAND memory 5, the controller 4 writes the update data corresponding to a certain logical address not to the physical storage location storing the previous data corresponding to the logical address, but to another physical storage location. Then, the controller 4 updates the L2P table 61, and associates the physical address showing the other physical storage location with the logical address. Then, the previous data is processed as invalid data.

[0032] Among the blocks included in the NAND memory 5, at least the blocks containing valid data are managed as active blocks. And, blocks containing no valid data but storing only invalid data are managed as free blocks. Valid data means data stored in a physical storage location associated with a logical address in the L2P table 61 (i.e., data associated with a logical address as the latest data). Valid data can be read from the host 2 later. Invalid data refers to data that is not associated with any logical address. Data that is not associated with any logical address is data that has been impossible to read from the host 2.

[0033] The DMAC 44 is a circuit that performs direct memory access (DMA). The DMAC 44 performs data transfer between the memory 22 of the host 2 and the SRAM 42 (or the DRAM 6).

[0034] When data is written to the NAND memory 5, the error correction circuit 45 performs an encoding process. In the encoding process, the error correction circuit 45 adds an error correction code (ECC) as a redundant code to the data to be written to the NAND memory 5. When data is read from the NAND memory 5, the error correction circuit 45 performs a decoding process. In the decoding process, the error correction circuit 45 uses the ECC added to the data read from the NAND memory 5 to perform error detection and error correction of the data.

[0035] The NAND interface 46 is a memory interface circuit that controls the NAND memory 5. The NAND interface 46 transmits a program request for writing data transmitted by the controller 4 to the NAND memory 5. In addition, the NAND interface 46 transmits a read request for reading data transmitted by the controller 4 to the NAND memory 5.

[0036] The DRAM interface 47 is a circuit for controlling the DRAM 6. The DRAM interface 47 stores data in the DRAM 6. In addition, the DRAM interface 47 reads data stored in the DRAM 6.

[0037] Next, the internal structure of the NAND memory 5 will be described. The NAND memory 5 includes a peripheral circuit 51 and a memory cell array 52. ​​The NAND memory 5 may include a memory cell array 52 of a two-dimensional structure or a three-dimensional structure.

[0038] The peripheral circuit 51 is a circuit for controlling the memory cell array 52. ​​The peripheral circuit 51 is also referred to as a control circuit. In response to receiving a program request from the NAND interface 46, the peripheral circuit 51 performs an action for writing data associated with the received program request into the memory cell array 52. ​​For example, the peripheral circuit 51 performs at least one of a program action, a read action, and an erase action in order to write data into the memory cell array 52. ​​In addition, in response to receiving a read request from the NAND interface 46, the peripheral circuit 51 performs an action for reading data specified by the received read request from the memory cell array 52.

[0039] The memory cell array 52 includes a plurality of nonvolatile memory cell transistors (hereinafter referred to as memory cells). Each of the plurality of memory cells stores data corresponding to a threshold voltage range to which the threshold voltage belongs by having a certain threshold voltage. In addition, the memory cell array 52 includes a plurality of blocks. Each block is a collection of a plurality of memory cells. Each block includes a plurality of memory cell groups. A memory cell group is also referred to as a string cell. Each string cell is a collection of memory cells. Each memory cell group includes a plurality of NAND strings (also referred to as strings). Each string is a collection of memory cells connected in series.

[0040] The storage cell group can be used as a unit for writing and reading operations. For example, a programming request includes information for specifying a storage cell group to be programmed. The peripheral circuit 51 performs processing for writing a portion of data associated with the programming request in each of the plurality of storage cells included in the storage cell group to be programmed. In addition, a read request includes information for specifying a storage cell group to be read. The peripheral circuit 51 performs processing for reading data from each of the plurality of storage cells included in the storage cell group to be read.

[0041] A memory cell is capable of storing at least 1 bit of data. For example, the memory cell array 52 can be used in a single-layer cell (SLC) mode, in which 1 bit of data is written in each memory cell. Alternatively, the memory cell array 52 can also be used in a mode in which more than 2 bits of data are written in each memory cell. The mode in which 2 bits of data are written in each memory cell is called a multi-layer cell (MLC) mode. The mode in which 3 bits of data are written in each memory cell is called a triple-layer cell (TLC) mode. The mode in which 4 bits of data are written in each memory cell is called a quad-layer cell (QLC) mode.

[0042] The larger the number of bits of data written in each storage unit, the more data can be stored even if the hardware configuration is the same, so the NAND memory 5 can be used efficiently. However, the larger the number of bits of data written in each storage unit, the longer it takes to write the data, so the performance of the storage system 3 may be reduced.

[0043] The plurality of blocks included in the storage cell array 52 may also include blocks in which data is written in different modes. For example, some of the plurality of blocks may be blocks in which data is written in the SLC mode, and another portion of the plurality of blocks may be blocks in which data is written in the QLC mode.

[0044] Next, the functional configuration of the CPU 43 will be described. The CPU 43 includes not only components that function as an FTL, but also a write processing unit 431 and a read processing unit 432. Part or all of the write processing unit 431 and the read processing unit 432 may be implemented by dedicated hardware of the controller 4.

[0045] The write processing unit 431 performs write processing by processing each write command received from the host 2. The write processing includes, for example, a process of obtaining write data associated with the write command from the memory 22 of the host 2; a process of writing the write data to a storage location in the NAND memory 5; and a process of updating the L2P table 61 to map (associate with) a physical address showing the storage location where the write data is written to the logical address specified by the write command. In addition, the write processing includes a process of sending a completion response indicating that the processing of the write command is completed to the host 2. For example, in response to the fact that the write data associated with the write command is transferred from the memory 22 of the host 2 to the SRAM 42, the completion response indicating that the processing of the write command is completed is sent to the host 2.

[0046] In the process of writing write data to a storage location in the NAND memory 5, the NAND interface 46 instructs the NAND memory 5 to perform a programming action by transmitting a programming request and the write data associated with the programming request to the NAND memory 5. The programming request, for example, includes information that specifies a storage area to which the write data is to be written. The storage area specified by the programming request, for example, corresponds to a storage cell group. The programming action is an action of writing the write data transmitted to the NAND memory 5 into a storage cell of the storage cell array 52. ​​The programming action is performed by the peripheral circuit 51 that receives the programming request.

[0047] The read processing unit 432 performs a read process by processing each read command received from the host 2. The read process includes: a process of reading data corresponding to the logical address specified by the read command from the NAND memory 5; a process of transferring the read data to the memory 22 of the host 2; and a process of sending a completion response indicating completion of the processing of the read command to the host 2. In the process of reading data from the NAND memory 5, specifically, the read processing unit 432 converts the logical address specified by the read command into a physical address by referring to the L2P table 61, and reads data from the storage location of the NAND memory 5 indicated by the physical address.

[0048] In the process of reading data from the storage location of the NAND memory 5 to be read, the NAND interface 46 instructs the peripheral circuit 51 to perform a read action (also called a sensing action, a read action) by sending a read request to the NAND memory 5. The read action is an action of reading data from the memory cell array 52. ​​The read action is performed by the peripheral circuit 51. Then, the NAND interface 46 performs a data output action for transmitting the read data from the NAND memory 5 to the controller 4.

[0049] Next, an example of the internal structure of the NAND memory 5 will be described. Figure 2 is a block diagram showing a configuration example of a NAND memory 5 according to an embodiment. Figure 2 In the example of FIG. 1 , a part of the connection between each component is shown by an arrow line. However, the connection between each component is not limited to this.

[0050] The NAND memory 5 is connected to the controller 4 . The NAND memory 5 operates according to instructions from the controller 4 .

[0051] The NAND memory 5 includes a peripheral circuit 51 and a memory cell array 52. ​​In addition, the NAND memory 5 includes a plurality of plane PLNs. The peripheral circuit 51 includes an input / output circuit 5101, a logic control circuit 5102, an address register 5103, a command register 5104, a status register 5105, a sequencer 5106, a ready / busy circuit 5107, a voltage generating circuit 5108, a comparison circuit 5109, a row decoder 5110, a sense amplifier module 5111, a data register 5112, and a column decoder 5113. Each component of the peripheral circuit 51 may be implemented by dedicated hardware or by the function of the peripheral circuit 51. In addition, the memory cell array 52 is included in each plane PLN of the plurality of plane PLNs. In addition, a part of the components of the peripheral circuit 51 may also be included in each plane PLN of the plurality of plane PLNs. Figure 2In the embodiment, a row decoder 5110, a sense amplifier module 5111, a data register 5112, and a column decoder 5113 are included in each plane PLN of a plurality of plane PLNs (PLN0-PLN3).

[0052] The input-output circuit 5101 is a circuit for inputting and outputting the signal DQ. The input-output circuit 5101 is connected to the controller 4. In addition, the input-output circuit 5101 is connected to the address register 5103, the command register 5104, the status register 5105, and the data register 5112 of each plane PLN. The signal DQ is, for example, an 8-bit signal DQ<7:0>. The signal <7:0> includes, for example, data DAT, an address ADD, and a command CMD. When the input signal DQ is data DAT (for example, data to be written into the memory cell array 52), the input-output circuit 5101 receives the input signal DQ according to the selection signals DQS and DQSn. Then, the input-output circuit 5101 sends the data DAT to the data register 5112 of the corresponding plane PLN. In addition, the input-output circuit 5101 outputs the data DAT (for example, data read from the memory cell array 52) and the status information STS to the controller 4 together with the selection signals DQS and DQSn. When the input signal DQ is an address ADD (e.g., a physical address), the input-output circuit 5101 sends the address ADD to the address register 5103. When the input signal DQ is a command CMD (e.g., a program request or a read request), the input-output circuit 5101 sends the command CMD to the command register 5104.

[0053] The logic control circuit 5102 is a circuit that performs logic control according to a control signal. The logic control circuit 5102 is connected to the controller 4. In addition, the logic control circuit 5102 is connected to the input / output circuit 5101 and the sequencer 5106. The logic control circuit 5102 receives various control signals from the controller 4. The logic control circuit 5102 controls the input / output circuit 5101 and the sequencer 5106 according to the received control signal.

[0054] The address register 5103 is a register that temporarily stores the address ADD received from the input / output circuit 5101. The address register 5103 is connected to the row decoder 5110 and the column decoder 5113 of each plane PLN. The address ADD includes a row address RA and a column address CA. The address register 5103 sends the row address RA to the row decoder 5110. In addition, the address register 5103 sends the column address CA to the column decoder 5113.

[0055] The command register 5104 is a register that temporarily stores the command CMD received from the input / output circuit 5101. The command register 5104 is connected to the sequencer 5106. The command register 5104 transmits the command CMD to the sequencer 5106.

[0056] The status register 5105 is a register that temporarily stores status information STS. The status register 5105 is connected to the sequencer 5106. The status register 5105 temporarily stores status information STS in programming operation, reading operation, erasing operation, etc. The status information STS is sent to the controller 4 via the input / output circuit 5101.

[0057] The sequencer 5106 controls the actions of the entire NAND memory 5. More specifically, the sequencer 5106 controls the ready / busy circuit 5107, the voltage generating circuit 5108, the row decoder 5110, the sense amplifier module 5111, the data register 5112, the column decoder 5113, etc. The sequencer 5106 performs programming actions, reading actions, and erasing actions according to the command CMD stored in the command register 5104. At this time, the sequencer 5106 controls the voltage generating circuit 5108 to generate voltages used when performing various actions. In addition, the sequencer 5106 can perform programming actions, reading actions, and erasing actions according to the comparison results received from the comparison circuit 5109. The sequencer 5106 sends the status information STS to the status register 5105.

[0058] For example, the sequencer 5106 performs a read operation on the storage cell group of the programming object according to the programming request. The sequencer 5106 determines whether to perform a programming operation and whether to perform an erase operation on the storage cell of the writing object according to the threshold voltage of the storage cell of the writing object among the multiple storage cells included in the storage cell group of the programming object and the threshold voltage corresponding to the data stored in the storage cell of the writing object. In addition, the sequencer 5106 performs a read operation on the storage cell group of the reading object according to the read request.

[0059] The ready / busy circuit 5107 is a circuit for transmitting a ready / busy signal RBn. The ready / busy circuit 5107 transmits the ready / busy signal RBn corresponding to the operation status of the sequencer 5106 to the controller 4.

[0060] The voltage generating circuit 5108 generates a voltage used in the control of the NAND memory 5. The voltage generating circuit 5108 generates a voltage, for example, according to the control of the sequencer 5106. The voltage generating circuit 5108 supplies the generated voltage to the comparison circuit 5109, the memory cell array 52 of each plane PLN, the row decoder 5110, the data register 5112, and the column decoder 5113. The voltage generated by the voltage generating circuit 5108 includes a programming voltage Vpg, a read voltage Vrv, an erase voltage Ver, and a target threshold voltage Vref. The programming voltage Vpg is a voltage applied to the memory cell group of the programming object during the programming action. The read voltage Vrv is a voltage applied to the word line of the memory cell group of the reading object during the reading action. The erase voltage Ver is a voltage applied to the memory cell of the erasing object during the erasing action. The target threshold voltage Vref is a voltage used by the comparison circuit 5109. The target threshold voltage Vref is a voltage determined according to the data to be written into the memory cell of the writing object. In addition, the voltage generating circuit 5108 generates a first voltage Vrefmax and a second voltage Vrefmin as a target threshold voltage Vref, the first voltage Vrefmax indicating the upper limit of the target threshold voltage range determined according to the data to be written into the memory cell to be written, and the second voltage Vrefmin indicating the lower limit of the target threshold voltage range, according to the control of the sequencer 5106. Alternatively, the voltage generating circuit 5108 generates a voltage (third voltage Vref) determined according to the data to be written into the memory cell to be written as the target threshold voltage Vref, according to the control of the sequencer 5106. The third voltage Vref is, for example, the median of the target threshold voltage range determined according to the data to be written into the memory cell to be written.

[0061] The comparison circuit 5109 compares the magnitude relationship between the threshold voltage of the memory cell to be written included in the memory cell array 52 and the target threshold voltage generated by the voltage generation circuit 5108. Then, the comparison circuit 5109 outputs the comparison result to the sequencer 5106.

[0062] For example, when the target threshold voltage includes a first voltage Vref max and a second voltage Vref min, the comparison circuit 5109 outputs a comparison result to the sequencer 5106 indicating one of the following cases: the threshold voltage of the storage cell to be written is greater than the first voltage Vref max, the threshold voltage of the storage cell to be written is less than the first voltage Vref max and greater than the second voltage Vref min, and the threshold voltage of the storage cell to be written is less than the second voltage Vref min.

[0063] For example, when the target threshold voltage is the third voltage Vref, the comparison circuit 5109 outputs a comparison result indicating one of the case where the threshold voltage of the memory cell to be written is greater than the third voltage Vref and the case where the threshold voltage of the memory cell to be written is less than or equal to the third voltage Vref to the sequencer 5106. However, the comparison circuit 5109 may determine whether the threshold voltage of the memory cell to be written is greater than or equal to the third voltage Vref instead of determining whether the threshold voltage of the memory cell to be written is less than or equal to the third voltage Vref.

[0064] The plane PLN is a unit for writing and reading data. Figure 2 In the example, the NAND memory 5 includes four planes PLN0, PLN1, PLN2, and PLN3. In addition, the number of plane PLNs is not limited to four. The number of plane PLNs may be one or more than four. Planes PLN0 to PLN3 can operate independently of each other. In addition, planes PLN0 to PLN3 can also operate in parallel.

[0065] Next, the internal structure of the plane PLN is described. Hereinafter, the case where planes PLN0 to PLN3 have the same structure is described. In addition, the structure of each plane PLN may also be different. Hereinafter, when any one of planes PLN0 to PLN3 is not limited, it is referred to as a plane PLN. The plane PLN includes a storage cell array 52, a row decoder 5110, a sense amplifier module 5111, a data register 5112, and a column decoder 5113.

[0066] The memory cell array 52 includes a plurality of blocks BLK. Figure 2 In the example of , the memory cell array 52 includes four blocks BLK0, BLK1, BLK2, and BLK3. In addition, the number of blocks BLK in the memory cell array 52 included in a certain plane PLN is arbitrary.

[0067] The row decoder 5110 is a circuit for decoding the row address RA. The row decoder 5110 selects a block BLK in the memory cell array 52 based on the decoding result. The row decoder 5110 applies a voltage to the row-direction wiring (a word line and a selection gate line described later) of the selected block BLK.

[0068] The sense amplifier module 5111 is a circuit that mainly reads a signal corresponding to data DAT. The sense amplifier module 5111 is connected to the memory cell array 52. ​​The sense amplifier module 5111 reads a voltage corresponding to data DAT from the memory cell array 52 during a read operation. The sense amplifier module 5111 amplifies the voltage read from the memory cell array 52.

[0069] The data register 5112 is a register for temporarily storing data DAT. The data register 5112 is connected to the sense amplifier module 5111. The data register 5112 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0070] The column decoder 5113 is a circuit that decodes the column address CA. The column decoder 5113 receives the column address CA from the address register 5103. The column decoder 5113 selects a latch circuit in the data register 5112 based on the decoding result of the column address CA.

[0071] Next, a configuration example of a block is described. Figure 3 1 is a diagram showing a configuration example of each of a plurality of blocks included in the memory cell array 52 of the NAND memory 5 according to the embodiment.

[0072] exist Figure 3 In the figure, the structure of the block is explained with an eye on block BLK0. The other blocks also have the same structure as block BLK0. Block BLK0 includes 4 string units (SU0, SU1, SU2 and SU3). The 4 string units (SU0, SU1, SU2 and SU3) are arranged in a direction (horizontal direction) orthogonal to the direction (vertical direction) in which multiple word lines WL0 to WL7 are stacked. Each string unit SU includes multiple strings NS. One end of each string NS is connected to a corresponding bit line among multiple bit lines (BL0 to BLn). Each string NS extends in the vertical direction. The control gates of the multiple memory cell transistors contained in each string NS are respectively connected to multiple word lines (WL0, WL1, ..., WL7).

[0073] Next, the circuit configuration of the block will be described. Figure 4 1 is a diagram showing an example of a circuit configuration of a block of the NAND memory 5 included in the storage system 3 according to the embodiment. Figure 4 Depicted on a plane Figure 3 An example of the block structure shown.

[0074] exist Figure 4 In the description, the circuit configuration of the block is described with attention paid to the block BLK0. The block BLK0 includes, for example, four string units SU0 to SU3. The number of string units SU included in each block BLK is arbitrary.

[0075] The string unit SU is, for example, a collection of multiple NAND strings NS selected together in a programming operation or a reading operation. Each string unit SU includes multiple strings NS.

[0076] Each string NS is a collection of multiple memory cells MC connected in series. Multiple strings NS in a string unit SU are connected to one of the bit lines BL0 to BLn (n is an integer greater than 1). The string NS includes multiple memory cells MC and selection transistors ST1 and ST2. Figure 4 In the example of FIG. 1 , the string NS includes eight memory cells MC0 to MC7 and two selection transistors ST1 and ST2 . In addition, the number of memory cells MC in the string NS is not limited to eight.

[0077] The memory cell MC is a storage element that stores data in a non-volatile manner. The memory cell MC includes a control gate and a charge storage layer. The memory cell MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or a FG (Floating Gate) type. The MONOS type uses an insulating layer in the charge storage layer. The FG type uses a conductive layer in the charge storage layer.

[0078] The selection transistors ST1 and ST2 are switch elements and are used to select the string unit SU in various operations.

[0079] The gate of each selection transistor ST1 of the string unit SU0 is connected to the selection gate line SGD0 corresponding to the string unit SU0. The gate of each selection transistor ST1 of the string unit SU1 is connected to the selection gate line SGD1 corresponding to the string unit SU1. The gate of each selection transistor ST1 of the string unit SU2 is connected to the selection gate line SGD2 corresponding to the string unit SU2. The gate of each selection transistor ST1 of the string unit SU3 is connected to the selection gate line SGD3 corresponding to the string unit SU3. In contrast, the gates of the selection transistors ST2 of the string units SU0 to SU3 are commonly connected to the selection gate line SGS. In addition, the gates of the selection transistors ST2 of the string units SU0 to SU3 can also be connected to different selection gate lines for each string unit. The control gates of the memory cells MC0 to MC7 located in the same block BLK are respectively commonly connected to the respective word lines WL0 to WL7.

[0080] The programming action and the reading action performed by the peripheral circuit 51 can be performed together on a plurality of memory cells MC connected to a word line in a string unit SU. The set of memory cells MC selected together during the programming action and the reading action is called a memory cell group MG. The memory cell group MG is a unit of programming action and reading action and is treated as a storage location. When each memory cell MC is configured to store 1 bit of data (SLC mode), the size of the data stored in each memory cell group MG is called a page. When each memory cell MC is configured to store 4 bits of data (QLC mode), the size of the data stored in each memory cell group MG is 4 pages.

[0081] Next, the threshold voltage distribution of a plurality of memory cells configured so that 4-bit data is stored in each memory cell will be described. Here, it is assumed that data is written to each of a plurality of blocks included in the NAND memory 5 in the QLC mode. Figure 5 1 is a diagram showing an example of threshold voltage distribution of a plurality of memory cells included in the NAND memory 5 according to the embodiment.

[0082] The threshold voltage Vth of each memory cell changes in accordance with the amount of charge accumulated in the charge storage layer of each memory cell. The 16 types of 4-bit data that can be stored in each memory cell in the NAND memory 5 correspond to 16 threshold voltage ranges represented by the threshold voltage Vth of the memory cell. Thus, each memory cell stores data corresponding to the threshold voltage range to which the threshold voltage Vth of the memory cell belongs.

[0083] In QLC mode, the threshold voltage of each memory cell is divided into 16 threshold voltage ranges. Figure 5 In the 16 threshold voltage ranges, the threshold voltages are called Er state, A state, B state, C state, ..., O state in order from low to high. The threshold voltage Vth of each memory cell is controlled to belong to a certain threshold voltage range through programming and erasing operations.

[0084] These 16 states correspond to different 4-bit data, respectively. For example, the threshold voltage Vth of a storage cell programmed with 4-bit data corresponding to the A state is set to a threshold voltage range from Vr1 to Vr2. Similarly, the threshold voltage Vth of a storage cell programmed with 4-bit data corresponding to the B state is set to a threshold voltage range from Vr2 to Vr3. Similarly, the threshold voltage Vth of a storage cell programmed with 4-bit data corresponding to the O state is set to a threshold voltage range from Vr15 to Vr16. The same is true for other states.

[0085] Here, the case where 4 bits of data are written in each storage cell (QLC mode) is described, but the data written in each storage cell may also be 1 bit of data (SLC mode), 2 bits of data (MLC mode), or 3 bits of data (TLC mode), or more than 5 bits of data.

[0086] In SLC mode, the threshold voltage of each memory cell is divided into two threshold voltage ranges. In MLC mode, it is divided into four threshold voltage ranges. In TLC mode, it is divided into eight threshold voltage ranges.

[0087] Next, the erasing operation will be described.

[0088] First, a reduction in the threshold voltage Vth of a memory cell due to an erase operation will be described.

[0089] In the erasing operation, the charge is removed from the charge storage layer by applying the erase voltage Ver to the memory cell to which the data is written (i.e., the memory cell to which the programming operation is performed). In the memory cell to which the programming voltage Vpg is applied by the programming operation, the amount of charge stored in the charge storage layer increases. As a result, the threshold voltage Vth of the memory cell to which the data is written becomes a value larger than the threshold voltage range of the erased state and belongs to the threshold voltage range corresponding to other states. By reducing the amount of charge stored in the charge storage layer, the threshold voltage Vth of the erased memory cell is reduced to the threshold voltage range of the erased state.

[0090] Here, the amount of reduction in the threshold voltage Vth of the memory cell caused by the erase operation depends on the magnitude of the erase voltage Ver used in the erase operation, the length of time the erase voltage Ver is applied, and the number of times the erase voltage Ver is applied. Figure 6 1 is a diagram showing an example of the relationship between the threshold voltage distribution of a plurality of memory cells included in the NAND memory 5 according to the embodiment and the erase voltage Ver.

[0091] Figure 6 Five graphs are shown. The horizontal axis of each graph represents the threshold voltage Vth of each of the plurality of memory cells. The vertical axis of each graph represents the number of memory cells. The dotted curve represents the relationship between the threshold voltage Vth of each memory cell and the number of memory cells before applying the erase voltage Ver. The solid curve represents the relationship between the threshold voltage Vth of each memory cell and the number of memory cells after applying the erase voltage Ver.

[0092] In each graph, a plurality of threshold voltage ranges correspond to the O state, the N state, . . . , the Er state, in order from the threshold voltage range having a peak value corresponding to a larger threshold voltage.

[0093] The topmost curve graph among the five curve graphs shows the case where the erase voltage Ver is the smallest, the time for applying the erase voltage Ver is the shortest, and the number of times the erase voltage Ver is applied is the least. In this case, the change in the threshold voltage Vth of each of the plurality of memory cells before and after the erase operation is performed is the smallest. For example, when focusing on a specific memory cell (target cell TC) that is in the O state before the erase operation is performed, the target cell TC is still in the O state after the erase operation is performed.

[0094] As the curve graph changes from the uppermost section to the lower section, the erase voltage Ver becomes larger, the time for applying the erase voltage Ver becomes longer, or the number of times the erase voltage Ver is applied becomes more. Therefore, as the curve becomes the lower section, the change amount of the threshold voltage Vth of each of the plurality of memory cells before and after the erase operation becomes larger. For example, in the second curve graph from the top, the target cell TC remains in the O state before and after the erase operation, while in the fourth curve graph from the top, the target cell TC changes from the O state to the N state before and after the erase operation.

[0095] In addition, the bottommost curve of the five curves shows the case where the erase voltage Ver is the largest, the time for applying the erase voltage Ver is the longest, and the number of times the erase voltage Ver is applied is the largest. In this case, before and after the erase operation is performed, the threshold voltage distribution of multiple memory cells is greatly shifted in the direction where the threshold voltage Vth becomes smaller. For example, in the case of focusing on the target cell TC that is in the O state before the erase operation is performed, the target cell TC has a threshold voltage Vth belonging to the M state after the erase operation is performed.

[0096] Thus, the peripheral circuit 51 can control the amount of reduction in the threshold voltage Vth before and after the erasing operation by controlling the parameters of the erasing operation. The parameters include the value of the erasing voltage Ver, the time for applying the erasing voltage Ver, or the number of times the erasing voltage Ver is applied.

[0097] For example, the peripheral circuit 51 can further increase the reduction amount of the threshold voltage Vth by setting the erase voltage Ver to a larger value. In addition, the peripheral circuit 51 can further increase the reduction amount of the threshold voltage Vth by further extending the time for which the erase voltage Ver is applied. In addition, the peripheral circuit 51 can further increase the reduction amount of the threshold voltage Vth by further increasing the number of times the erase voltage Ver is applied.

[0098] On the other hand, the peripheral circuit 51 can further reduce the reduction amount of the threshold voltage Vth by setting the erase voltage Ver to a smaller value. In addition, the peripheral circuit 51 can further reduce the reduction amount of the threshold voltage by further shortening the time for applying the erase voltage Ver. In addition, the peripheral circuit 51 can further reduce the reduction amount of the threshold voltage by further reducing the number of times the erase voltage Ver is applied.

[0099] Next, an erase operation performed on a specific memory cell will be described. Figure 7 1 is a diagram showing an example of a memory cell selected as a target of an erase operation in the NAND memory 5 according to the embodiment.

[0100] The peripheral circuit 51 selects a selection gate line SGD, a word line WL, and a bit line BL included in a certain block. Thus, the peripheral circuit 51 can select a memory cell included in the string unit SU corresponding to the selected selection gate line SGD and connected to the selected word line WL and the selected bit line BL among the plurality of memory cells included in the block. Then, the peripheral circuit 51 applies the erase voltage Ver only to the selected memory cell. Thus, the peripheral circuit 51 can perform an erase operation only on a specific memory cell among the plurality of memory cells included in the block.

[0101] Specifically, in Figure 7 , the peripheral circuit 51 selects the gate line SGD1, the word line WL6, and the bit line BL0. The peripheral circuit 51 selects a memory cell MC connected to the word line WL6 and the bit line BL0 from among the plurality of memory cells MC included in the string unit SU corresponding to the gate line SGD1. Then, the peripheral circuit 51 applies the erase voltage Ver only to the selected memory cell to perform the erase operation.

[0102] Thus, the peripheral circuit 51 can select a specific one memory cell among a plurality of memory cells included in a certain block and perform an erase operation only on the selected one memory cell.

[0103] As described above, the peripheral circuit 51 can control the reduction amount of the threshold voltage Vth of the memory cell by controlling the erase operation, and can perform the erase operation only on specific memory cells included in a certain block. Thus, the peripheral circuit 51 can select only specific memory cells and perform the erase operation adjusted in the direction of reducing the threshold voltage of the selected memory cell.

[0104] Next, the writing process using the erasing operation will be described. Figure 81 is a diagram showing an example of the relationship between the data of a target cell and the data to be written in the target cell in the NAND memory 5 according to the embodiment and the NAND memory according to the comparative example. Figure 8 In the embodiment, it is assumed that data is written to each of a plurality of memory cells in the MLC mode.

[0105] exist Figure 8 On the left side of , the correspondence between the threshold voltage distribution of multiple memory cells and the data stored in each memory cell (hereinafter also referred to as cell data) is shown. Here, the threshold voltage range C1 with the highest peak threshold voltage corresponds to the cell data (0,1). The threshold voltage range B1 with the second highest peak threshold voltage corresponds to the cell data (0,0). The threshold voltage range A1 with the third highest peak threshold voltage corresponds to the cell data (1,0). The threshold voltage range Er1 with the lowest peak threshold voltage corresponds to the cell data (1,1) indicating the erased state.

[0106] That is, the amount of charge accumulated in the charge storage layer of the memory cell storing the unit data (0,1) is greater than the amount of charge accumulated in the charge storage layer of the memory cell storing the other unit data. The amount of charge accumulated in the charge storage layer of the memory cell storing the unit data (0,0) is less than the amount of charge accumulated in the charge storage layer of the memory cell storing the unit data (0,1), and is greater than the amount of charge accumulated in the charge storage layer of the memory cell storing the unit data (1,0) or (1,1). The amount of charge accumulated in the charge storage layer of the memory cell storing the unit data (1,0) is less than the amount of charge accumulated in the charge storage layer of the memory cell storing the unit data (0,1) or (0,0), and is greater than the amount of charge accumulated in the charge storage layer of the memory cell storing the unit data (1,1). The amount of charge accumulated in the charge storage layer of the memory cell storing the cell data (1, 1) is smaller than the amount of charge accumulated in the charge storage layer of the memory cell storing the other cell data.

[0107] Here, it is assumed that a write process for writing new cell data (0, 0) is executed on a storage cell storing cell data (0, 1), that is, a storage cell to be written (target cell).

[0108] First, the writing process in the comparative example is described. In the writing process in the comparative example, when a new block including a target cell is selected as a writing destination block, the peripheral circuit performs an erasing operation on the writing destination block ( Figure 8(1-1) in the target block). Due to the erasing action, all storage cells included in the write destination block are in the erased state. In other words, the multiple storage cells included in the write destination block are in the state of storing the cell data (1,1). Therefore, the cell data stored in the target cell changes from the cell data (0,1) to (1,1).

[0109] Next, a programming operation is performed on the memory cell group including the target cell ( Figure 8 (1-2) in ). In the programming action, a programming voltage Vpg is applied to each of the multiple memory cells included in the memory cell group via the word line. The threshold voltage Vth of the memory cell to which the programming voltage Vpg is applied rises. Each time the programming voltage Vpg is applied, the peripheral circuit determines whether the threshold voltage Vth of each memory cell included in the memory cell group of the programming object belongs to the target threshold voltage range corresponding to each memory cell. Then, the memory cell having a threshold voltage Vth belonging to the target threshold voltage range corresponding to the data to be written among the multiple memory cells included in the memory cell group is set to the programming completion state (inhibit). The action including the operation of determining whether the threshold voltage Vth of each memory cell belongs to the target threshold voltage range corresponding to each memory cell, and the operation of setting each memory cell having a threshold voltage Vth belonging to the target threshold voltage range to the programming completion state is also called a verification action. In addition, the peripheral circuit repeatedly performs the action of applying the programming voltage Vpg to the memory cells that are not set to the programming completion state among the multiple memory cells included in the memory cell group, and the verification action. As a result, the threshold voltage Vth of the target cell included in the memory cell group to be programmed increases, the cell data stored in the target cell changes from cell data (1,1) to cell data (0,0), and the target cell is set to a programming completed state.

[0110] As described above, in the write process of the comparative example, the target cell undergoes an erase state and data is newly written thereto.

[0111] Next, the write process in this embodiment is described. In the write process in this embodiment, when a new block including a target cell is selected as a write destination block, the entire block of the write destination is not erased. Therefore, the target cell included in the write destination block does not necessarily become an erased state (a state storing cell data (1,1)).

[0112] The peripheral circuit 51 determines whether the current threshold voltage Vth of the target cell is greater than the target threshold voltage Vref corresponding to the data (cell data (0,0)) newly written to the target cell. Here, the current threshold voltage Vth of the target cell corresponds to the cell data (0,1). Thus, the peripheral circuit 51 determines whether the data stored in the target cell can be set to the cell data (0,0) by performing an erase operation on the target cell. Here, the target threshold voltage Vref corresponding to the cell data (0,0) may be a first voltage Vref max indicating an upper limit of the threshold voltage range corresponding to the cell data (0,0), or may be a third voltage Vref indicating a voltage belonging to the threshold voltage range corresponding to the cell data (0,0).

[0113] Here, since the threshold voltage Vth of the target cell is greater than the target threshold voltage Vref corresponding to the cell data (0, 0), the peripheral circuit 51 performs an erase operation on the target cell ( Figure 8 (2-1) in ). Through this erasing action, the peripheral circuit 51 reduces the threshold voltage Vth of the target cell so that it belongs to the threshold voltage range corresponding to the cell data (0,0). That is, the peripheral circuit 51 performs the erasing action in such a way that the target cell stores the data written to the target cell. At this time, the peripheral circuit 51 determines at least one of the magnitude of the erasing voltage Ver used in the erasing action, the length of time for applying the erasing voltage Ver, and the number of times the erasing voltage Ver is applied, based on the threshold voltage corresponding to the cell data (0,1) and the threshold voltage corresponding to the cell data (0,0).

[0114] Then, the peripheral circuit 51 reads data from the target cell and determines whether the read data is consistent with the data to be written into the target cell. When the data read from the target cell is consistent with the data to be written into the target cell, the peripheral circuit 51 completes the writing to the target cell. The peripheral circuit 51 sets the target cell to which the writing is completed to a programming completion state (inhibit). The target cell set to the programming completion state is not applied with a programming voltage or an erase voltage Ver during the programming action for other memory cells of the memory cell group including the target cell. Therefore, the target cell can maintain the data to be written.

[0115] Thus, in the write process of the present embodiment, the target cell does not undergo an erase state, and new data is written only through an erase action. Therefore, in the write process of the embodiment, the amount of charge removed from the charge storage layer of the target cell is the difference between the amount of charge stored in the charge storage layer of the storage cell storing the cell data (0,1) and the amount of charge stored in the charge storage layer of the storage cell storing the cell data (0,0). On the other hand, in the write process of the comparative example, since the target cell undergoes an erase state, the amount of charge removed from the charge storage layer of the target cell is the difference between the amount of charge stored in the charge storage layer of the storage cell storing the cell data (0,1) and the amount of charge stored in the charge storage layer of the storage cell storing the cell data (1,1). That is, in the write process of the embodiment, the amount of charge removed from the charge storage layer is reduced by the following amount compared to the write process of the comparative example, namely, the difference between the amount of charge stored in the charge storage layer of the storage cell storing the cell data (0,0) and the amount of charge stored in the charge storage layer of the storage cell storing the cell data (1,1).

[0116] Here, the case where an erase operation is performed on the target cell so that the target cell is in a state where data to be newly written (for example, cell data (0,0)) is stored is described, but the peripheral circuit 51 may also perform an erase operation so that the target cell is in a state other than an erased state and stores data corresponding to a threshold voltage range lower than a target threshold voltage range corresponding to the data to be newly written (for example, cell data (1,0)). In the case of performing such a rough erase operation, the peripheral circuit 51 does not set the target cell to a programming completed state in this state. Thereafter, in response to a case where the threshold voltage is raised to a state where cell data (0,0) is stored due to a programming operation on a storage cell group including the target cell, the target cell is set to a programming completed state.

[0117] Therefore, in the write process of the embodiment, when writing new data to the target cell, the amount of charge removed from the charge storage layer of the target cell can be reduced. The degradation of the memory cell progresses according to the amount of charge removed from the charge storage layer. Therefore, the progress of the degradation of the memory cell can be suppressed by the write process of the embodiment.

[0118] When executing the write process of the embodiment, the peripheral circuit 51 compares the threshold voltage Vth of the target cell with the target threshold voltage Vref corresponding to the new data written to the target cell. At this time, the peripheral circuit 51 uses one of the following first method and the following second method: in the first method, the first voltage Vref max indicating the upper limit of the threshold voltage range corresponding to the new data and the second voltage Vref min indicating the lower limit of the threshold voltage range are used as the target threshold voltage Vref, and in the second method, the third voltage Vref indicating a voltage determined according to the new data is used as the target threshold voltage Vref.

[0119] First, the write process using the first method will be described.

[0120] Fig. 9 1 is a block diagram showing a first example of the flow of a write process performed in the NAND memory 5 involved in the embodiment. First, in response to receiving a write command from the host 2, the controller 4 sends a programming request to the NAND memory 5 via the NAND interface 46. The controller 4 may also spontaneously send a programming request to the NAND memory 5 instead of according to the write command received from the host 2. The programming request includes information that specifies the storage cell group of the programming object. In addition, the programming request is associated with data to be written to each storage cell included in the storage cell group of the programming object.

[0121] S1: The sequencer 5106 receives a program request from the NAND interface 46. The sequencer 5106 selects a target cell from a plurality of memory cells included in a memory cell group of a program target specified by the program request.

[0122] S2: The sequencer 5106 sends a read instruction for generating a read voltage Vrv to the voltage generating circuit 5108, and the read voltage Vrv is used to obtain the threshold voltage Vth of the selected target cell. In addition, the sequencer 5106 specifies the target cell TC included in the memory cell array 52 by sending information for specifying the selected target cell to other components of the peripheral circuit 51. The sequencer 5106 outputs information specifying the word line WL and the bit line BL connected to the target cell TC and the selection gate lines SGD and SGS and the source line SL corresponding to the target cell TC, for example.

[0123] S3 : the voltage generating circuit 5108 generates a read voltage Vrv according to the received read instruction, and outputs the generated read voltage Vrv to the memory cell array 52 .

[0124] S4: The memory cell array 52 controls the read operation for the target cell TC using the read voltage Vrv generated by the voltage generation circuit 5108. The sense amplifier module 5111 obtains the threshold voltage Vth of the target cell TC through the read operation. For example, the sense amplifier module 5111 obtains the threshold voltage Vth by applying the read voltage Vrv to the word line connected to the memory cell group including the target cell TC while applying a predetermined voltage value to the bit line corresponding to the target cell TC.

[0125] S5 : The sense amplifier module 5111 outputs the acquired threshold voltage Vth to the comparison circuit 5109 .

[0126] S6: The sequencer 5106 instructs the voltage generation circuit 5108 to generate a first voltage Vref max indicating an upper limit and a second voltage Vrefmin indicating a lower limit of the target threshold voltage range corresponding to data to be newly written into the target cell TC.

[0127] S7: The voltage generation circuit 5108 outputs the first voltage Vref max and the second voltage Vref min generated according to the instruction from the sequencer 5106 to the comparison circuit 5109. Here, the processes of S6 to S7 are not necessarily executed after S5, and may be executed in parallel or independently of the processes of S2 to S5.

[0128] S8 : The comparison circuit 5109 determines the magnitude relationship between the threshold voltage Vth input from the sense amplifier module 5111 and the first voltage Vref max and the second voltage Vref min input from the voltage generation circuit 5108 , and outputs the determination result to the sequencer 5106 .

[0129] When the determination result outputted in S8 indicates that the threshold voltage Vth is greater than the first voltage Vref max, the peripheral circuit 51 executes the processing of S9 to S10.

[0130] S9: The sequencer 5106 sends an erase instruction to the voltage generating circuit 5108 to generate the erase voltage Ver used in the erase operation for the target cell TC. The erase instruction may include, for example, information specifying the magnitude of the erase voltage Ver, the time for applying the erase voltage Ver, or the number of times the erase voltage Ver is applied, which is determined based on the difference between the current threshold voltage Vth of the target cell TC and the target threshold voltage range. In addition, the sequencer 5106 specifies the target cell TC included in the memory cell array 52 by sending information for specifying the selected target cell to other components of the peripheral circuit 51. The sequencer 5106 outputs, for example, information specifying the word line WL, the bit line BL connected to the target cell TC, and the selection gate lines SGD, SGS, and the source line SL corresponding to the target cell TC.

[0131] S10: The voltage generating circuit 5108 outputs the erase voltage Ver generated according to the received erase instruction to the memory cell array 52. ​​The memory cell array 52 controls the erase operation for the target cell TC using the erase voltage Ver generated by the voltage generating circuit 5108. For example, the erase operation is controlled by applying the erase voltage Ver to the word line connected to the memory cell group including the target cell TC while applying a predetermined voltage value to the bit line corresponding to the target cell TC.

[0132] After S10 is completed, the peripheral circuit 51 may execute the processes of S2 to S8 again. Specifically, the peripheral circuit 51 repeatedly executes the erase operation until the threshold voltage Vth of the target cell TC becomes lower than the first voltage Vref max.

[0133] When the determination result outputted in S8 indicates that the threshold voltage Vth is equal to or lower than the first voltage Vref max and equal to or higher than the second voltage Vref min, the peripheral circuit 51 executes the process of S11 .

[0134] S11: The sequencer 5106 sets the target cell TC to the programming completion state (inhibit). Thus, when performing programming operations on other memory cells in the memory cell group including the target cell TC, the programming voltage Vpg is not applied to the target cell TC. After that, the sequencer 5106 selects the next target cell TC from the memory cell group to be programmed and performs the processing after S2 again.

[0135] In addition, when the comparison result outputted in S8 indicates that the threshold voltage Vth is less than the second voltage Vrefmin, the peripheral circuit 51 does not perform any operation on the target cell TC. That is, the target cell TC is not set to the programming completion state (inhibit). The next target cell TC is selected from the memory cell group to be programmed, and the processing after S2 is performed again.

[0136] When the selection of each memory cell included in the memory cell group of the programming object as the target cell TC is completed, and there is one or more memory cells whose threshold voltage Vth is less than the second voltage Vrefmin and do not store the data to be stored among the memory cells included in the memory cell group of the programming object, the peripheral circuit 51 performs the processing of S12-S13. The one or more memory cells are memory cells that are not set to the programming completion state (inhibit).

[0137] S12: The sequencer 5106 sends a programming instruction for generating a programming voltage Vpg used in a programming operation for the memory cell group at the write destination to the voltage generating circuit 5108. In addition, the sequencer 5106 specifies the memory cell group at the write destination included in the memory cell array 52 by sending information for specifying the memory cell group at the write destination to other components of the peripheral circuit 51. The sequencer 5106 outputs information specifying the word line WL to which the memory cell group at the write destination is connected, for example.

[0138] S13: The voltage generating circuit 5108 outputs the programming voltage Vpg generated according to the received programming instruction to the memory cell array 52. ​​The memory cell array 52 uses the programming voltage Vpg generated by the voltage generating circuit 5108 to control the programming action for the memory cell group of the write destination. For example, in a state where a prescribed voltage value is applied to each bit line corresponding to each memory cell included in the memory cell group of the programming object that is not set to the programming completed state, the programming voltage Vpg is applied to the word line connected to the memory cell group of the programming object, thereby controlling the programming action. In addition, the comparison result output in S8 is that the target cell TC whose threshold voltage Vth is less than the second voltage Vref min is included in the object of the programming action in S13.

[0139] Next, the relationship between the current value read from the memory cell and the threshold voltage Vth of the memory cell is described. Fig. 9 As shown in S4 of FIG. 5 , when the read voltage Vrv is applied to the memory cell, the peripheral circuit 51 obtains the threshold voltage of the memory cell based on the current value output from the memory cell. Fig.10 1 is a diagram showing the relationship between the current value read from the memory cell included in the NAND memory 5 according to the embodiment and the threshold voltage.

[0140] The vertical axis represents the current value of the current output from the memory cell to which the read voltage Vrv is applied, and the horizontal axis represents the threshold voltage of the memory cell.

[0141] Fig.10 The curve Cu shows the relationship between the current value output from each memory cell and the threshold voltage of the memory cell. That is, the threshold voltage of the memory cell can be determined based on the current value of the current output from a certain memory cell.

[0142] Specifically, by applying a read voltage Vrv to the word line of the memory cell and applying a predetermined voltage to the bit line of the memory cell, the sense amplifier module 5111 obtains a current value Ith indicating the amount of current output from the memory cell. Referring to the correspondence between the current value Ith and the threshold voltage Vth related to the memory cell, the peripheral circuit 51 can obtain the threshold voltage Vth based on the obtained current value Ith.

[0143] Therefore, for simplicity, it is described that the sense amplifier module 5111 obtains the threshold voltage Vth from the memory cell to be read through the read operation.

[0144] Next, the procedure of the write process using the first method will be described. Fig.11 1 is a flowchart showing a first example of the procedure of the write process executed in the NAND memory 5 according to the embodiment. In response to receiving a program request from the controller 4, the peripheral circuit 51 starts the write process.

[0145] The peripheral circuit 51 selects a memory cell group to be programmed according to the received program request ( S101 ).

[0146] The peripheral circuit 51 selects a memory cell (target cell) to be written from among the plurality of memory cells included in the memory cell group selected in S101 ( S102 ).

[0147] The peripheral circuit 51 determines the target threshold voltage range of the target cell according to the data associated with the programming request (S103). The target threshold voltage range is a threshold voltage range corresponding to the data to be newly written into the target cell. The peripheral circuit 51 determines, for example, a first voltage Vref max representing the upper limit of the target threshold voltage range and a second voltage Vref min representing the lower limit of the target threshold voltage range.

[0148] The peripheral circuit 51 applies a read voltage Vrv to the target cell to obtain a current threshold voltage Vth of the target cell ( S104 ).

[0149] The peripheral circuit 51 determines whether the target cell threshold voltage Vth obtained in S104 is within the target threshold voltage range determined in S103 (S105). In other words, the peripheral circuit 51 determines whether the current threshold voltage Vth of the target cell obtained in S104 is less than the first voltage Vref max and greater than the second voltage Vref min determined in S103.

[0150] When the threshold voltage Vth of the target cell acquired in S104 is within the target threshold voltage range determined in S103 (Yes in S105 ), the peripheral circuit 51 sets the target cell to a program completion state (inhibit) ( S106 ).

[0151] In addition, when the threshold voltage Vth of the target cell obtained in S104 is not within the target threshold voltage range determined in S103 (No in S105), the peripheral circuit 51 determines whether the threshold voltage Vth of the target cell is lower than the target threshold voltage range (S107). Specifically, the peripheral circuit 51 determines whether the current threshold voltage Vth of the target cell obtained in S104 is lower than the second voltage Vref min or higher than the first voltage Vref max.

[0152] When the threshold voltage Vth of the target cell is higher than the target threshold voltage range, that is, when the current threshold voltage Vth of the target cell is greater than the first voltage Vref max ("No" in S107), the peripheral circuit 51 applies the erase voltage Ver to the target cell (S108). The peripheral circuit 51 can determine the magnitude of the applied erase voltage Ver based on the difference between the threshold voltage Vth of the target cell and the target threshold voltage range. In addition, the peripheral circuit 51 can not only determine the magnitude of the erase voltage Ver, but also determine the time and number of times the erase voltage Ver is applied. Then, the peripheral circuit 51 returns to S104, obtains the threshold voltage Vth of the target cell again, and determines whether the threshold voltage Vth of the target cell drops to the target threshold voltage range.

[0153] After S106 , or when the threshold voltage Vth of the target cell is lower than the target threshold voltage range (Yes in S107 ), the peripheral circuit 51 determines whether all the memory cells included in the memory cell group to be programmed have been selected as target cells ( S109 ).

[0154] When there are memory cells that have not yet been selected among the memory cells included in the memory cell group of the programming object ("No" in S109), the peripheral circuit 51 returns to S102 and selects the next target cell from the multiple memory cells included in the memory cell group of the programming object that have not yet been selected as the target cell.

[0155] When all the memory cells included in the memory cell group to be programmed are selected (Yes in S109 ), the peripheral circuit 51 executes a program operation on the memory cell group to be programmed ( S110 ).

[0156] Thus, in the write process using the first method, the peripheral circuit 51 including the sequencer 5106, the voltage generating circuit 5108, the comparison circuit 5109 and the sense amplifier module 5111 controls the read action, the erase action and the programming action for the target cell according to the magnitude relationship between the current threshold voltage Vth of the target cell and the target threshold voltage range determined based on the data to be written into the target cell. Then, the peripheral circuit 51 sets the memory cell whose threshold voltage Vth belongs to the target threshold voltage range to the programming completion state.

[0157] Thus, when the current threshold voltage Vth of the target cell is greater than the first voltage Vref max indicating the upper limit of the target threshold voltage range, the peripheral circuit 51 can set the target cell to the programming completed state by lowering the threshold voltage Vth only through the erasing operation without going through the erasing state. In addition, when the current threshold voltage Vth of the target cell is less than the second voltage Vref min indicating the lower limit of the target threshold voltage range, the peripheral circuit 51 can set the target cell to the programming completed state by raising the threshold voltage Vth only through the programming operation without going through the erasing state.

[0158] Next, the write process using the second method is described. In the write process using the second method, as the target threshold voltage Vref, a third voltage Vref representing a voltage value determined according to the data to be newly written into the memory cell to be written is used. Here, the third voltage Vref is less than the value representing the upper limit of the target threshold voltage range (the first voltage Vref max), and is greater than the value representing the lower limit of the target threshold voltage range (the second voltage Vref min). In addition, the peripheral circuit 51 sets the magnitude of the programming voltage Vpg so that the amount of change in the threshold voltage Vth of the memory cell that changes each time the programming voltage Vpg is applied to the memory cell is less than the difference between the third voltage Vref and the value representing the upper limit of the target threshold voltage range, and the difference between the third voltage Vref and the value representing the lower limit of the target threshold voltage. In addition, the peripheral circuit 51 sets the magnitude of the erase voltage Ver so that the amount of change in the threshold voltage Vth of the memory cell that changes each time the erase voltage Ver is applied to the memory cell to be written is less than the difference between the third voltage Vref and the value representing the upper limit of the target threshold voltage range, and the difference between the third voltage Vref and the value representing the lower limit of the target threshold voltage range.

[0159] First, the programming action is described. The peripheral circuit 51 performs a programming action on the memory cell group of the programming object specified by the programming request. The peripheral circuit 51 applies a programming voltage Vpg to each memory cell that is not set to the programming completion state among the multiple memory cells included in the memory cell group of the programming object. At this time, each time the peripheral circuit 51 applies the programming voltage Vpg to each memory cell that is not set to the programming completion state in the memory cell group of the programming object, it determines whether the threshold voltage Vth of each memory cell included in the memory cell group of the programming object reaches the third voltage Vref corresponding to each memory cell. Then, the peripheral circuit 51 sets each memory cell having a threshold voltage Vth reaching the third voltage Vref to the programming completion state. The action including the operation of determining whether the threshold voltage Vth of each memory cell reaches the third voltage Vref corresponding to each memory cell and the operation of setting each memory cell having a threshold voltage Vth reaching the third voltage Vref to the programming completion state is also called a verification action. The peripheral circuit 51 sets each of the multiple memory cells included in the memory cell group of the programming object to the programming completion state by repeatedly performing the action of applying the programming voltage Vpg and the verification action.

[0160] Here, the description will be made focusing on one memory cell (target cell) included in a memory cell group to be programmed. FIG. 12A to FIG. 12D Each of them is a diagram showing an example of a change in threshold voltage due to a program operation executed in the NAND memory 5 according to the embodiment.

[0161] FIG. 12A to FIG. 12D The vertical axis represents the current value read from each memory cell to which the read voltage Vrv is applied, and the horizontal axis represents the threshold voltage of each memory cell.

[0162] The target threshold voltage Vref represents a voltage (third voltage Vref) determined according to the data to be written into the target cell. Here, the third voltage Vref is less than the value representing the upper limit of the target threshold voltage range and greater than the value representing the lower limit of the target threshold voltage range. The threshold voltage Vth represents the current threshold voltage value of the target cell.

[0163] Fig. 12AThe threshold voltage Vth of the target cell before the programming voltage is applied in the first programming operation and the change ΔVpg of the threshold voltage Vth caused by the application of the programming voltage Vpg are shown. For example, each time the peripheral circuit 51 applies the programming voltage Vpg to each memory cell, it determines whether the threshold voltage Vth of each memory cell has become greater than the third voltage Vref. Since the threshold voltage Vth of the target cell after the first application of the programming voltage Vpg is still less than the third voltage Vref, the peripheral circuit 51 has not yet set the target cell to the programming completion state.

[0164] in addition, Fig. 12B and Fig. 12C The threshold voltage Vth of the target cell before the application of the programming voltage Vpg and the threshold voltage change ΔVpg caused by the application of the programming voltage Vpg are shown in the second and third programming actions, respectively. After each programming action, the peripheral circuit 51 determines whether the threshold voltage Vth of each memory cell has become greater than the third voltage Vref. In either case after the second or third application of the programming voltage Vpg, since the threshold voltage Vth of the target cell is less than the third voltage Vref, the peripheral circuit 51 does not set the memory cell to be written to the programming completion state.

[0165] exist Fig.12D , the threshold voltage Vth of the target cell before the programming voltage Vpg is applied in the fourth programming operation, and the change ΔVpg of the threshold voltage Vth caused by the application of the programming voltage Vpg are shown. By increasing the threshold voltage Vth by the amount ΔVpg, the threshold voltage Vth of the target cell becomes a value greater than the third voltage Vref. Then, in response to the threshold voltage Vth of the target cell becoming a value greater than the third voltage Vref, the peripheral circuit 51 sets the target cell to a programming completion state.

[0166] At this time, ΔVpg is set to be smaller than the difference between the third voltage Vref and the first voltage Vref max, and the difference between the third voltage Vref and the second voltage Vref min. Therefore, when the threshold voltage Vth does not reach the third voltage Vref in the third application of the programming voltage Vpg, and the threshold voltage Vth reaches the third voltage Vref in the fourth application of the programming voltage Vpg, the threshold voltage Vth of the target cell immediately after the fourth application of the programming voltage Vpg is performed belongs to the target threshold voltage range. That is, the target cell is in a state where the data to be written is stored.

[0167] Next, the erasing action is described. The peripheral circuit 51 selects a memory cell to be written from the memory cell group to be programmed, and determines whether the threshold voltage Vth of the memory cell to be written is greater than the target threshold voltage Vref of the memory cell to be written. When the threshold voltage Vth of the memory cell to be written is greater than the target threshold voltage Vref, the peripheral circuit 51 performs an erasing action on the selected memory cell to be written. That is, the peripheral circuit 51 performs an erasing action of applying the erasing voltage Ver only to the memory cell to be written. In the write process using the second method, each time the peripheral circuit 51 applies the erasing voltage Ver to the memory cell to be written, it determines whether the threshold voltage Vth of the memory cell to be written has become less than the target threshold voltage Vref. Then, when the threshold voltage Vth becomes less than the target threshold voltage Vref, the peripheral circuit 51 sets the memory cell to be written to a programming completion state. The peripheral circuit 51 makes the memory cell to be written become a programming completion state by repeatedly performing the action of applying the erasing voltage Ver to the memory cell to be written and the action of determining whether the threshold voltage Vth of the memory cell to be written has become less than the target threshold voltage Vref.

[0168] Here, it is assumed that an erasing operation is performed on a certain memory cell to which writing is to be performed. Fig.13A and Fig. 13B 1 is a diagram showing an example of a change in the threshold voltage Vth due to an erase operation performed in the NAND memory 5 according to the embodiment.

[0169] Fig.13A and Fig. 13B The vertical axis represents the current value read from each memory cell to which the read voltage Vrv is applied, and the horizontal axis represents the threshold voltage Vth of each memory cell.

[0170] The target threshold voltage Vref represents a voltage (third voltage) determined according to the data to be written into the target cell of the write object. Here, the third voltage Vref is less than the value representing the upper limit of the target threshold voltage range and greater than the value representing the lower limit of the target threshold voltage range. The threshold voltage Vth represents the current threshold voltage value of the memory cell of the write object.

[0171] Fig.13AThe threshold voltage Vth of the target cell before the application of the erase voltage Ver in the first erase operation and the threshold voltage change ΔVer caused by the application of the erase voltage Ver are shown. For example, each time the erase voltage Ver is applied to the target cell, the peripheral circuit 51 determines whether the threshold voltage Vth of the target cell has become less than the third voltage Vref. Since the threshold voltage Vth of the target cell after the first application of the erase voltage Ver is still greater than the third voltage Vref, the peripheral circuit 51 has not yet set the target cell to the programming completed state.

[0172] Fig. 13B The threshold voltage Vth of the target cell before the application of the erase voltage in the second erase operation and the change ΔVer of the threshold voltage caused by the application of the erase voltage Ver are shown. By reducing the threshold voltage Vth by the amount ΔVer, the threshold voltage Vth of the target cell becomes lower than the third voltage Vref. Then, in response to the threshold voltage Vth of the target cell becoming lower than the third voltage Vref, the peripheral circuit 51 sets the target cell to the programming completion state.

[0173] At this time, ΔVer is set to be smaller than the difference between the third voltage Vref and the first voltage Vref max, and the difference between the third voltage Vref and the second voltage Vref min. Therefore, when the threshold voltage Vth does not reach the third voltage Vref in the first application of the erase voltage, and the threshold voltage Vth is lower than the third voltage Vref in the second application of the erase voltage Ver, the threshold voltage Vth of the target cell immediately after the second application of the erase voltage Ver is performed belongs to the target threshold voltage range. That is, the target cell is in a state where the data to be written is stored.

[0174] Fig.14 1 is a block diagram showing a second example of the flow of the write process performed in the NAND memory 5 involved in the embodiment. First, in response to receiving a write command from the host 2, the controller 4 sends a program request to the NAND memory 5 via the NAND interface 46. The controller 4 may also spontaneously send a program request to the NAND memory 5 instead of according to the write command received from the host 2.

[0175] The peripheral circuit 51 performs the following steps in S21 to S25: Fig. 9 The same processing as processing S1 to S5 described in .

[0176] S26: The sequencer 5106 instructs the voltage generation circuit 5108 to generate a target threshold voltage Vref (eg, a third voltage Vref) corresponding to the data to be newly written to the target cell TC. The target threshold voltage Vref is, for example, a median value of the target threshold voltage range.

[0177] S27: The voltage generation circuit 5108 outputs the target threshold voltage Vref generated according to the instruction from the sequencer 5106 to the comparison circuit 5109. Here, the processes of S26 to S27 are not necessarily executed after S25, and may be executed in parallel with or independently of the processes of S22 to S25.

[0178] S28 : The comparison circuit 5109 determines the magnitude relationship between the threshold voltage Vth input from the sense amplifier module 5111 and the target threshold voltage Vref, and outputs the determination result to the sequencer 5106 .

[0179] When the determination result outputted in S28 indicates that the threshold voltage Vth is greater than the target threshold voltage Vref, the peripheral circuit 51 executes the processes of S29 to S30.

[0180] S29: The sequencer 5106 sends an erase instruction to the voltage generating circuit 5108 to generate the erase voltage Ver used in the erase operation for the target cell TC. The erase instruction may include information such as the size of the predetermined erase voltage Ver, the time for applying the erase voltage Ver, or the number of times the erase voltage Ver is applied. In addition, the sequencer 5106 specifies the target cell TC included in the memory cell array 52 by sending information for specifying the selected target cell to other components of the peripheral circuit 51. The sequencer 5106 outputs information specifying the word line WL, the bit line BL connected to the target cell TC, and the selection gate lines SGD, SGS, and the source line SL corresponding to the target cell TC, for example.

[0181] S30: The voltage generating circuit 5108 outputs the erase voltage Ver generated according to the received erase instruction to the memory cell array 52. ​​The memory cell array 52 controls the erase operation for the target cell TC using the erase voltage Ver generated by the voltage generating circuit 5108. For example, the erase operation is controlled by applying the erase voltage Ver to the word line connected to the memory cell group including the target cell TC while applying a predetermined voltage value to the bit line corresponding to the target cell TC.

[0182] After S30 is completed, the peripheral circuit 51 executes the process of S22 to S28 again. Thus, the peripheral circuit 51 repeatedly executes the erasing operation until the threshold voltage Vth of the target cell TC becomes equal to or lower than the target threshold voltage Vref.

[0183] S31: After S30, when receiving the determination result indicating that the threshold voltage Vth of the target cell TC is lower than the target threshold voltage Vref, the sequencer 5106 sets the target cell TC to the programming completion state (inhibit). Thus, when performing programming operations on other memory cells in the memory cell group including the target cell TC, the programming voltage Vpg is not applied to the target cell TC. After that, the sequencer 5106 selects the next target cell TC from the memory cell group to be programmed, and performs the processing after S22 again.

[0184] In addition, when the judgment result output for the first time in S28 after the target cell TC is selected indicates that the threshold voltage Vth is below the target threshold voltage Vref, the peripheral circuit 51 does not perform any action on the target cell TC, but selects the next target cell TC from the storage cell group of the programming object and executes the processing after S22 again.

[0185] When the selection of each memory cell included in the memory cell group to be programmed as the target cell TC is completed, the peripheral circuit 51 performs the processing of S32-33. The processing of S32-33 is the same as Fig. 9 The same processing as S12-S13 described in .

[0186] Next, the procedure of the write process using the second method will be described. Fig.15 1 is a flowchart showing a second example of the procedure of the write process executed in the NAND memory 5 according to the embodiment. In response to receiving a program request from the controller 4, the peripheral circuit 51 starts the write process.

[0187] The peripheral circuit 51 selects a memory cell group to be programmed according to the received program request ( S201 ).

[0188] The peripheral circuit 51 selects a memory cell (target cell) to be written from among the plurality of memory cells included in the memory cell group selected in S201 ( S202 ).

[0189] The peripheral circuit 51 determines the target threshold voltage Vref of the target cell according to the data associated with the programming request (S203). The target threshold voltage Vref is a voltage (third voltage Vref) belonging to the threshold voltage range corresponding to the data to be newly written into the target cell. Here, the target threshold voltage Vref is less than the value representing the upper limit of the target threshold voltage range and greater than the value representing the lower limit of the target threshold voltage range. For example, the target threshold voltage Vref is the median of the target threshold voltage range.

[0190] The peripheral circuit 51 performs a read operation on the target cell using the read voltage Vrv to obtain the current threshold voltage Vth of the target cell ( S204 ).

[0191] The peripheral circuit 51 determines whether the threshold voltage Vth of the target cell acquired in S204 is equal to or lower than the target threshold voltage Vref determined in S203 ( S205 ).

[0192] When the threshold voltage Vth of the target cell obtained in S204 is greater than the target threshold voltage Vref determined in S203 (No in S205), the peripheral circuit 51 applies the erase voltage Ver to the target cell (S206). The peripheral circuit 51 determines the magnitude of the applied erase voltage Ver so that the magnitude of the threshold voltage Vth changed by the application of the erase voltage Ver is smaller than the difference between the target threshold voltage Vref and the value indicating the upper limit of the target threshold voltage range and the difference between the target threshold voltage Vref and the value indicating the lower limit of the target threshold voltage range. The peripheral circuit 51 can determine not only the magnitude of the erase voltage Ver, but also the time and number of times to apply the erase voltage Ver.

[0193] The peripheral circuit 51 performs a read operation on the target cell using the read voltage Vrv, and obtains the current threshold voltage Vth of the target cell again ( S207 ).

[0194] The peripheral circuit 51 determines whether the threshold voltage Vth of the target cell is lower than or equal to the target threshold voltage Vref ( S208 ).

[0195] When the threshold voltage Vth of the target cell is still greater than the target threshold voltage Vref even after the erasing voltage Ver is applied (No in S208 ), the peripheral circuit 51 returns to S206 and applies the erasing voltage Ver to the target cell again.

[0196] When the threshold voltage Vth of the target cell is lower than or equal to the target threshold voltage Vref (Yes in S208 ), the peripheral circuit 51 sets the target cell to a program completion state (inhibit) ( S209 ).

[0197] When the threshold voltage Vth of the target cell is lower than the target threshold voltage Vref (Yes in S205 ) or after completing the process of S209 , the peripheral circuit 51 determines whether all the memory cells included in the memory cell group to be programmed have been selected as target cells ( S210 ).

[0198] When there are memory cells that have not yet been selected among the memory cells included in the memory cell group of the programming object ("No" in S210), the peripheral circuit 51 returns to S202 and selects the next target cell from the multiple memory cells included in the memory cell group of the programming object that have not yet been selected as the target cell.

[0199] When all the memory cells included in the memory cell group to be programmed are selected (Yes in S210 ), the peripheral circuit 51 executes a program operation on the memory cell group to be programmed ( S211 ).

[0200] Thus, in the write process using the second method, the peripheral circuit 51 including the sequencer 5106, the voltage generating circuit 5108, the comparison circuit 5109 and the sensing amplifier module 5111 controls the read action, the erase action and the programming action for the target cell according to the relationship between the current threshold voltage Vth of the target cell and the target threshold voltage Vref determined based on the data to be written into the target cell.

[0201] Thus, similar to the case where the first method is used, in the write process using the second method, when the current threshold voltage Vth of the target cell is greater than the target threshold voltage Vref, the peripheral circuit 51 can set the target cell to the programming completed state by lowering the threshold voltage Vth only through the erasing operation without going through the erasing state. In addition, when the current threshold voltage Vth of the target cell is less than the target threshold voltage Vref, the peripheral circuit 51 can set the target cell to the programming completed state by raising the threshold voltage Vth only through the programming operation without going through the erasing state.

[0202] Next, the correspondence between the combination of the original state of the write-target storage cell and the state after data is written and the operation performed on the write-target storage cell in the write process will be described. Fig.16 The figure shows the correspondence between the combination of the original state and the state after writing of the memory cell of the writing object included in the NAND memory 5 involved in the embodiment and the writing process. Here, it is assumed that the writing process using the first method is performed. In addition, it is assumed that data is written to the memory cell in the MLC mode.

[0203] For example, when the current threshold voltage Vth of the target cell is within the target threshold voltage range, the peripheral circuit 51 does not perform programming and erasing actions in the write process. In addition, when the current threshold voltage Vth of the target cell is greater than the value representing the upper limit of the target threshold voltage range, the peripheral circuit 51 only performs an erasing action on the target cell. In addition, when the current threshold voltage Vth of the target cell is less than the value representing the lower limit of the target threshold voltage range, the peripheral circuit 51 only performs programming actions on the target cell. That is, the peripheral circuit 51 controls the actions performed on the target cell in the write process based on the combination of the data currently stored in the target cell (the state of the storage cell before the write process is performed) and the data to be written into the target cell (the state of the storage cell after the write process is performed).

[0204] The following specifically illustrates a combination of an original state of a target cell and a state of the target cell after writing, and an operation to be performed on the target cell.

[0205] In addition, Fig.16 In, with Figure 8 Similarly, the following situations are also shown: the threshold voltage range with the highest peak threshold voltage corresponds to the cell data (0,1), the threshold voltage range with the second highest peak threshold voltage corresponds to the cell data (0,0), the threshold voltage range with the third highest peak threshold voltage corresponds to the cell data (1,0), and the threshold voltage range with the lowest peak threshold voltage corresponds to the cell data (1,1) indicating the erased state.

[0206] When the original state is the state of storage cell data (1,1) and the state after writing is the state of storage cell data (0,1), since the threshold voltage range corresponding to the cell data (1,1) is lower than the threshold voltage range corresponding to the cell data (0,1), the peripheral circuit 51 only performs programming action on the target cell.

[0207] When the original state is the state of storage cell data (1,1) and the state after writing is the state of storage cell data (0,0), since the threshold voltage range corresponding to the cell data (1,1) is lower than the threshold voltage range corresponding to the cell data (0,0), the peripheral circuit 51 only performs programming action on the target cell.

[0208] When the original state is the state of storage cell data (1,1) and the state after writing is the state of storage cell data (1,0), since the threshold voltage range corresponding to the cell data (1,1) is lower than the threshold voltage range corresponding to the cell data (1,0), the peripheral circuit 51 only performs programming action on the target cell.

[0209] When the original state is the state of the memory cell data (1, 1) and the state after writing is the state of the memory cell data (1, 1), the peripheral circuit 51 does not perform any of the programming operation and the erasing operation on the target cell.

[0210] In the case where the original state is the state of the storage cell data (1, 0) and the state after writing is the state of the storage cell data (0, 1), since the threshold voltage range corresponding to the cell data (1, 0) is lower than the threshold voltage range corresponding to the cell data (0, 1), the peripheral circuit 51 performs only the programming operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs the erasing operation until the target cell becomes the state of the storage cell data (1, 1) (erased state) and then performs the programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0211] In the case where the original state is the state of the storage cell data (1, 0) and the state after writing is the state of the storage cell data (0, 0), since the threshold voltage range corresponding to the cell data (1, 0) is lower than the threshold voltage range corresponding to the cell data (0, 0), the peripheral circuit 51 performs only the programming operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs the erasing operation until the target cell becomes the erased state and then performs the programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0212] When the original state is the state of the storage cell data (1, 0) and the state after writing is the state of the storage cell data (1, 0), the peripheral circuit 51 does not perform any of the programming operation and the erasing operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs the erasing operation until the target cell becomes the erased state and then performs the programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0213] When the original state is the state of storage cell data (1,0) and the state after writing is the state of storage cell data (1,1), since the threshold voltage range corresponding to the cell data (1,0) is higher than the threshold voltage range corresponding to the cell data (1,1), the peripheral circuit 51 only performs an erase operation on the target cell.

[0214] In the case where the original state is the state of the storage cell data (0,0) and the state after writing is the state of the storage cell data (0,1), since the threshold voltage range corresponding to the cell data (0,0) is lower than the threshold voltage range corresponding to the cell data (0,1), the peripheral circuit 51 performs only the programming operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs the erasing operation until the target cell becomes the erased state and then performs the programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0215] When the original state is the state of the storage cell data (0, 0) and the state after writing is the state of the storage cell data (0, 0), the peripheral circuit 51 does not perform any of the programming operation and the erasing operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs the erasing operation until the target cell becomes the erased state and then performs the programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0216] In the case where the original state is the state of the storage cell data (0,0) and the state after writing is the state of the storage cell data (1,0), since the threshold voltage range corresponding to the cell data (0,0) is higher than the threshold voltage range corresponding to the cell data (1,0), the peripheral circuit 51 performs only the erasing operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs the erasing operation until the target cell becomes the erased state and then performs the programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0217] When the original state is the state of storage cell data (0,0) and the state after writing is the state of storage cell data (1,1), since the threshold voltage range corresponding to the cell data (0,0) is higher than the threshold voltage range corresponding to the cell data (1,1), the peripheral circuit 51 only performs an erase operation on the target cell.

[0218] When the original state is the state of the storage cell data (0, 1) and the state after writing is the state of the storage cell data (0, 1), the peripheral circuit 51 does not perform any of the programming operation and the erasing operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs the erasing operation until the target cell becomes the erased state and then performs the programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0219] In the case where the original state is the state of the storage cell data (0,1) and the state after writing is the state of the storage cell data (0,0), since the threshold voltage range corresponding to the cell data (0,1) is higher than the threshold voltage range corresponding to the cell data (0,0), the peripheral circuit 51 performs only an erase operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs an erase operation until the target cell becomes an erased state and then performs a programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0220] In the case where the original state is the state of the storage cell data (0, 1) and the state after writing is the state of the storage cell data (1, 0), since the threshold voltage range corresponding to the cell data (0, 1) is higher than the threshold voltage range corresponding to the cell data (1, 0), the peripheral circuit 51 performs only an erase operation on the target cell. In this case, compared with the case where the peripheral circuit 51 performs an erase operation until the target cell becomes an erased state and then performs a programming operation, the amount of charge removed from the charge storage layer of the target cell can be reduced.

[0221] When the original state is the state of storage cell data (0, 1) and the state after writing is the state of storage cell data (1, 1), since the threshold voltage range corresponding to the cell data (0, 1) is higher than the threshold voltage range corresponding to the cell data (1, 1), the peripheral circuit 51 only performs an erase operation on the target cell.

[0222] As described above, in the NAND memory 5 involved in the present embodiment, when the threshold voltage Vth of the target cell is greater than the target threshold voltage Vref, the peripheral circuit 51 performs an erase operation on the target cell to save the data to be written into the target cell. Then, the peripheral circuit 51 sets the target cell to a programming completed state. At this time, the amount of charge removed from the charge storage layer of the target cell is less than the case where the programming operation is performed after the target cell is in an erased state. Thus, the peripheral circuit 51 can perform data writing for the target cell while suppressing the degradation of the memory cell.

[0223] In addition, the peripheral circuit 51 may also perform a write process using the first method or the second method when receiving a programming request and information specifying a write process of the embodiment. When the controller 4 does not specify a write process of the embodiment or specifies a write process of the comparative example, the peripheral circuit 51 may perform a write process of the comparative example, in which a programming action is performed on each page after performing an erase action to make each storage unit of the entire block of the write destination into an erased state. In this way, the peripheral circuit 51 can selectively perform a write process of the embodiment and a write process of the comparative example.

[0224] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the scope equivalent to the invention described in the claims. [Explanation of Reference Numerals]

[0225] 1: Information processing system, 2: Host, 3: Storage system, 4: Controller, 5: NAND type flash memory, 6: DRAM, 21: Processor, 22: Memory, 41: Host interface, 42: SRAM, 43: CPU, 44: DMAC, 45: Error correction circuit, 46: NAND interface, 47: DRAM interface, 51: Peripheral circuit, 52: Storage cell array, 61: L2P table, 431: Write processing unit, 432: Read processing unit, 5101: Input and output circuit, 5102: Logic control circuit, 5103: Address register, 5104: Command register, 5105: Status register, 5106: Sequencer, 5107: Ready / busy circuit, 5108: Voltage generation circuit, 5109: Comparison circuit, 5110: Row decoder, 5111: Sense amplifier module, 5112: Data register, 5113: Column decoder.

Claims

1. A semiconductor storage device comprising: a plurality of memory cells configured to store data corresponding to a threshold voltage range to which a threshold voltage possessed by each memory cell belongs; and a control circuit configured to control the plurality of storage units, The control circuit is composed of: determining whether a first threshold voltage of a memory cell to be written is higher than a second threshold voltage determined according to data to be stored in the memory cell to be written, When the first threshold voltage is higher than the second threshold voltage, generating an erasing voltage to be applied to the memory cell to be written, An erasing operation of lowering a threshold voltage of the memory cell to be written is performed using the erasing voltage so that the memory cell to be written stores the data to be stored.

2. The semiconductor memory device according to claim 1, wherein: The control circuit comprises: a sequencer that controls programming and erasing actions performed on the plurality of memory cells; a voltage generating circuit that generates a voltage applied to each of the plurality of memory cells and the second threshold voltage; as well as A comparison circuit compares the magnitude relationship between the threshold voltage of the memory cell to be written and the second threshold voltage generated by the voltage generation circuit.

3. The semiconductor memory device according to claim 1, wherein: The plurality of storage units include a plurality of storage unit groups, The control circuit is composed of: Receive a write request, According to the write request, a storage unit group of a write target is selected from the plurality of storage unit groups, Each storage cell included in the storage cell group of the writing object is selected as the storage cell of the writing object.

4. The semiconductor memory device according to claim 3, wherein: The second threshold voltage is a first voltage indicating an upper limit of a threshold voltage range, the threshold voltage range being determined based on data to be stored in the storage cell to be written, among data associated with the write request. The control circuit is composed of: generating the first voltage and a second voltage representing a lower limit of the threshold voltage range, comparing the first threshold voltage with the first voltage and the second voltage, When the first threshold voltage is lower than the first voltage and higher than the second voltage, writing to the memory cell to be written is completed. In the case where there is one or more memory cells in the memory cell group as the write target whose threshold voltage is lower than the second voltage and which do not store the data to be stored, a programming voltage is generated to be applied to the one or more memory cells, Using the programming voltage, a programming operation is performed on each of the one or more memory cells until a threshold voltage of each of the one or more memory cells becomes lower than the first voltage and higher than the second voltage corresponding to each of the one or more memory cells.

5. The semiconductor memory device according to claim 3, wherein: The second threshold voltage is a third voltage, and the third voltage is a voltage determined according to data associated with the write request. The control circuit is composed of: generating the erase voltage when the first threshold voltage is higher than the third voltage, Repeating the process including: performing the erasing operation using the generated erasing voltage; and determining whether the threshold voltage of the memory cell to be written has become lower than the third voltage. After the threshold voltage of the memory cell to be written becomes lower than the third voltage, the erasing operation on the memory cell to be written is completed. In the case where there are one or more memory cells in the memory cell group of the write target whose threshold voltage is lower than the third voltage and which do not store the data to be stored, a programming voltage is generated to be applied to the one or more memory cells, Using the programming voltage, a programming operation is performed on each of the one or more memory cells until a threshold voltage of each of the one or more memory cells becomes equal to or higher than the third voltage corresponding to each of the one or more memory cells.

6. The semiconductor memory device according to claim 1, wherein: The control circuit is composed of: When performing the erase operation, at least one of the size of the erase voltage, the time for applying the erase voltage, and the number of times the erase voltage is applied is determined based on the data currently stored in the storage unit of the write object and the data to be stored in the storage unit of the write object.

7. A storage system comprising: The semiconductor memory device according to any one of claims 1 to 6; and A controller is configured to control the semiconductor storage device.

8. The storage system according to claim 7, wherein: The controller is composed of: A memory cell storing invalid data among the memory cells included in the semiconductor memory device is designated as a memory cell to which data is to be written next, and a write request is sent to the semiconductor memory device.

9. A control method, which is a method of controlling a plurality of memory cells, wherein the plurality of memory cells are configured to store data corresponding to a threshold voltage range to which a threshold voltage of each memory cell belongs, The control method comprises: An operation of determining whether a first threshold voltage of a memory cell to be written is higher than a second threshold voltage determined according to data to be stored in the memory cell to be written; generating an erase voltage to be applied to the memory cell to be written when the first threshold voltage is higher than the second threshold voltage; as well as An operation of performing an erasing operation of lowering a threshold voltage of the memory cell to be written using the erasing voltage so that the memory cell to be written stores the data to be stored.

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