Method, system and apparatus for reading non-volatile memory

Abstract

The present disclosure relates to methods, systems, and devices for reading non-volatile memory. Example methods, systems, and apparatuses for reading non-volatile memory are provided in accordance with various examples of the present disclosure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 582,980, filed on September 15, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure relate to reading semiconductor memory, and more particularly to methods, systems, and apparatus for reading non-volatile memory, such as multi-time programmable (eMTP) memory. Background Art

[0003] Applicants have identified many technical challenges and difficulties associated with reading semiconductor memories. Through effort, ingenuity, and innovation, Applicants have solved many of these identified problems by developing embodiments of the present disclosure, which are described in detail below. Summary of the invention

[0004] Various embodiments described herein are provided that relate to methods, apparatus, and systems for reading non-volatile memory.

[0005] According to one aspect of the present disclosure, a method for reading a memory cell is provided. In some embodiments, the method includes receiving a cell current of the memory cell; receiving a first reference current, a second reference current, and a third reference current; generating a first comparison output signal based on comparing the cell current with the first reference current; generating a second comparison output signal based on comparing the cell current with the second reference current; generating a third comparison output signal based on comparing the cell current with the third reference current; and determining a granularity state of the memory cell based at least in part on one or more of comparing the cell current with the first reference current, comparing the cell current with the second reference current, or comparing the cell current with the third reference current.

[0006] In some embodiments, the first reference current corresponds to a minimum erased cell current based on a voltage threshold distribution associated with the memory cells.

[0007] In some embodiments, the second reference current corresponds to a maximum virgin cell current based on a voltage threshold distribution associated with the memory cell.

[0008] In some embodiments, the third reference current corresponds to a minimum primitive cell current based on a voltage threshold distribution associated with the memory cell.

[0009] In some embodiments, if the cell current is determined to be greater than the first reference current, then the memory cell is determined to be properly erased.

[0010] In some embodiments, if the cell current is greater than the second reference current and the first reference current is greater than the cell current, then the memory cell is determined to be under-erased.

[0011] In some embodiments, if the cell current is greater than the third reference current, and each of the first reference current and the second reference current is greater than the cell current, the memory cell is determined to be badly erased.

[0012] In some embodiments, if the cell current is less than each of the first reference current, the second reference current, and the third reference current, it is determined that the memory cell is programmed.

[0013] In some embodiments, the method further includes generating a final output signal corresponding to a primary state of the memory cell based on one or more of the first comparison output signal, the second comparison output signal, or the third comparison output signal.

[0014] In some embodiments, the method further includes outputting one or more of a first comparison output signal, a second comparison output signal, a third comparison output signal, or a final output signal.

[0015] According to one aspect of the present disclosure, a robust read circuit system for reading a memory cell is provided. In some embodiments, the robust read circuit system includes a sense amplifier. The sense amplifier may include: one or more current generators configured to generate multiple reference currents; a comparator coupled to the one or more current generators, wherein the comparator is configured to receive a cell current of the memory cell; receive multiple reference currents; and determine the granular state of the memory cell based on comparing the cell current with at least two of the multiple reference currents.

[0016] In some embodiments, the multiple reference currents include a first reference current corresponding to a minimum erased cell current based on a voltage threshold distribution associated with the memory cell; a second reference current corresponding to a maximum original cell current based on a voltage threshold distribution associated with the memory cell; and a third reference current corresponding to a minimum original cell current based on a voltage threshold distribution associated with the memory cell.

[0017] In some embodiments, the sense amplifier is configured to determine that the memory cell is properly erased if the cell current is determined to be greater than a first reference current.

[0018] In some embodiments, the sense amplifier is configured to determine that the memory cell is under-erased if the cell current is determined to be greater than the second reference current and the first reference current is determined to be greater than the cell current.

[0019] In some embodiments, the sense amplifier is configured to determine that the memory cell is badly erased if the cell current is determined to be greater than a third reference current and each of the first reference current and the second reference current is determined to be greater than the cell current.

[0020] In some embodiments, the sense amplifier is configured to determine that the memory cell is programmed if the cell current is determined to be less than the first reference current, the second reference current, and the third reference current.

[0021] In some embodiments, the robust read circuitry is further configured to output a primary state of the memory cell.

[0022] In some embodiments, the sense amplifier is a single-ended sense amplifier.

[0023] In some embodiments, the memory cell is a two level memory cell that is electrically programmable and erasable.

[0024] In some embodiments, the sense amplifier further includes a bias circuit configured to bias a bit line associated with the memory cell.

[0025] The foregoing illustrative summary as well as other exemplary objects and / or advantages of the present disclosure and embodiments thereof are further explained in the following detailed description and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The description of the illustrative embodiments may be read in conjunction with the accompanying drawings. It should be appreciated that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale unless otherwise described. For example, unless otherwise described, the dimensions of some elements may be exaggerated relative to other elements. Embodiments incorporating the teachings of the present disclosure are shown and described with respect to the drawings presented herein, in which: Figure 1 An example set of memory cell voltage threshold distributions in accordance with at least one embodiment of the present disclosure is illustrated.

[0027] Figure 2 A block diagram of example robust read circuitry in accordance with at least one embodiment of the present disclosure is provided.

[0028] Figure 3 An example output configuration of a logic stage of a robust read circuit system in accordance with at least one embodiment of the present disclosure is illustrated.

[0029] Figure 4 Schematic diagrams of example sense amplifiers in accordance with at least one embodiment of the present disclosure are provided.

[0030] Figure 5A flowchart depicting the operation of an example process for reading non-volatile memory in accordance with at least one embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0031] Some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. In fact, these disclosures may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. Like reference numerals refer to like elements throughout the text.

[0032] Terms such as "calculate," "determine," "generate," and / or similar words are used interchangeably herein to refer to the creation, modification, or identification of data. Additionally, "based on," "based in part on," "based at least on," "according to," and / or similar words are used interchangeably herein in an open manner such that they do not indicate based solely or solely on the referenced element or elements unless otherwise indicated. Like reference numbers refer to like elements throughout.

[0033] As used herein, terms such as "front", "rear", "top", etc. are used for explanation purposes in the examples provided below to describe the relative positions of certain components or parts of components. In addition, based on this disclosure, it will be apparent to one of ordinary skill in the art that the terms "substantially" and "approximately" indicate that the referenced element or associated description is accurate within applicable engineering tolerances.

[0034] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner in which it is commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and composed essentially of.

[0035] The phrases "in one embodiment," "according to one embodiment," and the like generally mean that a particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases are not necessarily referring to the same embodiment).

[0036] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0037] If the specification states that a component or feature "may", "could", "would", "should", "will", "preferably", "likely", "usually", "optionally", "for example", "often", or "might" (or other such language) be included or have a certain characteristic, then the particular component or feature is not required to be included or have that characteristic. Such a component or feature may optionally be included in some embodiments, or may be excluded.

[0038] As used herein, the term "or" is used in an alternative sense and a connecting sense, unless otherwise indicated. The terms "illustrative" and "example" are used as examples and do not indicate a quality level. Terms such as "calculate", "determine", "generate" and / or similar words are used interchangeably herein to refer to the creation, modification or identification of data. In addition, "based on", "partially based on", "at least based on", "according to" and / or similar words are used interchangeably in an open manner herein, so that they do not indicate that they are based only on or solely on one or more elements cited, unless so indicated. Similar reference numerals refer to similar elements throughout the text.

[0039] Semiconductor memory is commonly used in several applications for temporarily or permanently storing information in a memory cell. For example, a volatile memory device can be configured to temporarily store information in a memory cell. A non-volatile memory device can be configured to permanently store information in a memory cell, where the stored information is preserved in the absence of power (e.g., when the power is disconnected).

[0040] A non-volatile memory may include an array of memory cells (e.g., a memory array) arranged in rows and columns to form a matrix, where the rows represent word lines and the columns represent bit lines. Each memory cell may be configured to store a bit of information. In a semiconductor memory (such as a flash memory), the memory cells in the memory array may include transistors. For example, in a flash memory (e.g., integrated into a chip of semiconductor material), each memory cell may consist of a floating gate MOSFET configured to store one bit of information. In a memory array, a word line may be connected to the gate terminals of the memory cells on the same row, and a bit line may be connected to the drain terminals of the cells on the same column.

[0041] Each memory cell may have a voltage threshold associated with a corresponding logic value. The voltage threshold of a memory cell may depend on the amount of charge trapped in the floating gate of the memory cell. A read operation, a programming operation, and / or an erase operation may be performed on the memory cell. In order to program the memory cell, for example, a high voltage may be applied to the drain of the transistor while the gate is grounded, which reduces the voltage threshold of the memory cell. In order to erase the memory cell, for example, the gate voltage of the transistor may be raised to a high voltage, which increases the voltage threshold of the memory cell. When the memory cell is erased, the voltage threshold may be moved to a lower value, and when the memory cell is programmed, the voltage threshold may be moved to a higher value. In a two-level flash memory, for example, when in an erased state, the memory cell may have a relatively low voltage threshold and may be associated with a low logic value of 0. In a programmed state, the memory cell may have a higher voltage threshold relative to the erased state and may be associated with a high logic value of 1. In this example, in order to program or erase the cell, the voltage threshold of the gate of the MOSFET may be modified to switch between a low logic value of 0 corresponding to the erased state and a high logic value of 1 corresponding to the programmed state. It should be appreciated that in some examples, a low logic value of 0 may correspond to a programmed state, while a high logic value of 1 may correspond to an erased state.

[0042] In some embodiments, a read operation is performed to determine the state of the memory cell (e.g., whether it is erased or programmed). Information stored in the memory cell can be read to determine whether the memory cell is erased or programmed. In some examples, the read operation can include applying a reference voltage to the gate of the MOSFET and sensing a reference current. If the MOSFET conducts current (e.g., based on a voltage threshold that the voltage threshold of the memory cell is greater than the reference voltage threshold), then it can be determined that the memory cell is erased, and if the MOSFET does not conduct current (e.g., based on a voltage threshold that the voltage threshold of the memory cell is less than the reference voltage threshold), then it can be determined that the memory cell is programmed. For example, the reference voltage can be a value between the voltage thresholds of an erased cell (e.g., an erased memory cell) and a programmed cell (e.g., a programmed memory cell).

[0043] The read circuit system can be fully utilized to read the logic value stored in the memory cell to determine the state of the memory cell (e.g., erased or programmed). The logic value stored in the memory cell can be read by comparing the current flowing through the memory cell with the reference cell. The sense amplifier can be used to compare the current flowing through the memory cell and the reference cell. In some examples, the sense amplifier refers to an amplifier configured to sense a low voltage signal from a bit line and amplify a small voltage swing to a recognizable logic level so that the data can be correctly read. The sense amplifier can be connected to the bit lines of the memory cell and the reference cell.

[0044] As described above, there are many technical challenges and difficulties associated with the reading method of the memory cell. Some of these technical challenges and difficulties include low reliability of the reading operation due to voltage shift and area influence, etc. For example, in the eMTP IP, a serial reading method can be used to read data, where one bit is read at a time. In such examples, a differential method based on a comparison between a memory cell and a reference cell can be used to read data from the memory cell. For example, the reference cell can share a gate voltage with the memory cell. In some examples, the voltage threshold of the reference cell can be a fixed value between the voltage threshold of the erased cell and the voltage threshold of the programmed cell. In some examples, the voltage threshold of the reference cell can be complementary to the voltage threshold of the memory cell. Therefore, this differential reading method generally requires the use of at least two memory cells to store one bit of information, resulting in inefficient use of area. For example, based on the use of at least two memory cells to store a single bit of information, a considerable area in the memory device may be utilized.

[0045] When a read operation of a memory cell (particularly a two-level memory cell) is performed by comparing the cell current of the memory cell (e.g., the current flowing through the memory cell) with a single reference current, aging effects, continuous cycling effects, exposure to stress effects, etc. may affect the reliability of the read operation, making it possible to accurately determine the state of the memory cell. For example, due to aging, exposure to stress and / or continuous cycling of the memory cell, the voltage threshold of the memory cell will gradually shift (e.g., the voltage threshold will gradually increase), thereby reducing the cell current and ultimately affecting the reliability of the read operation, especially in erased cells. For example, as the voltage threshold of the erased cell shifts (e.g., increases), it moves toward the voltage threshold of the original cell, thus making it challenging to accurately distinguish between erased cells and programmed cells. For example, the voltage threshold of a particular erased cell may be significantly shifted to a value that falls within the voltage threshold distribution of the original cell and / or the programmed cell, resulting in an inaccurate read operation. In this regard, due to the shift of the voltage threshold of the memory cell, it is difficult and challenging to accurately determine whether the memory cell is under-erased, over-programmed, etc.

[0046] Embodiments of the present disclosure address the challenges and difficulties mentioned above, as well as other challenges and difficulties associated with read operations of non-volatile memory devices. Specifically, embodiments of the present disclosure employ a single-ended sensing approach and compare a cell current with a plurality of reference currents to determine a granular state of a memory cell. For example, some embodiments utilize a single-ended sense amplifier to read a memory cell, which is configured to compare the cell current of the memory cell with a plurality of carefully selected reference currents (e.g., predefined reference currents).

[0047] By comparing the cell current with multiple reference currents while adopting a single-ended approach, embodiments of the present disclosure are able to distinguish between correctly erased cells, under-erased cells, poorly erased cells, and programmed cells. By comparing the cell current with multiple reference currents, embodiments of the present disclosure are able to capture, track, and / or monitor the voltage shift trend of the memory cell over a period of time, thereby allowing corrective actions to be implemented. For example, embodiments of the present disclosure can be configured to determine whether a memory cell is correctly erased, under-erased, poorly erased, or programmed, thereby improving the reliability of the read operation, and being able to determine the aging effects, stress exposure effects, and / or continuous cycling effects of the memory cell at an early stage (e.g., when the voltage threshold of the erased cell begins to shift toward the voltage threshold of the original cell and / or the programmed cell).

[0048] By comparing a memory cell (e.g., its cell current) with a predefined reference current (e.g., instead of a reference cell), embodiments of the present disclosure efficiently utilize the area of ​​the memory device. For example, embodiments of the present disclosure eliminate the need to compare a memory cell with a reference cell to read the memory cell. In this regard, embodiments of the present disclosure can reduce the array area by, for example, half, compared to the case where a reference cell is used. Some embodiments of the present disclosure make full use of a voltage shift distribution to select or otherwise determine a reference current for comparison with the cell current of the memory, so that a voltage shift in a memory cell can be detected as early as possible to allow corrective action (e.g., by a user).

[0049] Figure 1 An example memory cell voltage threshold distribution set 100 of a memory cell according to at least one embodiment of the present disclosure is illustrated. Specifically, Figure 1 FIG. 1 illustrates a non-volatile memory voltage threshold distribution set. Figure 1 As shown in , a memory cell voltage threshold distribution set 100 may include an erased cell voltage threshold distribution 102 (e.g., a voltage threshold distribution of erased memory cells), an original cell voltage threshold distribution 104 (e.g., a voltage threshold distribution of original memory cells), and a programmed cell voltage threshold distribution 106 (e.g., a voltage threshold distribution of programmed memory cells).

[0050] As shown, the erased cell voltage threshold distribution 102 can define a minimum erased cell current 112 corresponding to the maximum voltage threshold represented in the erased cell voltage threshold distribution 102. As shown, the original cell voltage threshold distribution 104 can define a maximum original cell current 114 corresponding to the minimum original cell voltage threshold represented in the original cell voltage threshold distribution 104. As shown, the original cell voltage threshold distribution 104 can define a minimum original cell current 116 corresponding to the maximum original cell voltage threshold represented in the original cell voltage threshold distribution 104. In some embodiments, the original memory cell describes a memory cell that has not undergone any read operation, programming operation, erase operation, and / or other operation associated with the memory cell. For example, the original cell can be a memory cell manufactured using the same technology as the memory cell being read but has not yet undergone any read, programming, or erase operation. For example, the original cell can include a memory cell that has just been manufactured (e.g., directly out of semiconductor manufacturing).

[0051] For example, the memory cell voltage threshold distribution set 100 may represent an ideal voltage threshold distribution, where there is a sufficient window (e.g., gap) between the various voltage threshold distributions (e.g., between the erased cell voltage threshold distribution 102, the original cell voltage threshold distribution 104, and the programmed cell voltage threshold distribution 106). Figure 1 As can be seen, a sizeable voltage threshold shift of a particular erased cell can cause the voltage threshold of the particular erased cell to shift toward the original cell voltage threshold distribution 104 and / or the programmed cell voltage threshold distribution 106, such that the voltage threshold of the particular erased cell may not be distinguishable relative to the original cell and / or the programmed cell by comparing the cell current of the particular erased cell to a single reference current.

[0052] In some embodiments, the robust read method technology of the present disclosure makes full use of the memory cell voltage threshold distribution set 100 to read the memory cell or otherwise determine the state of the memory cell. In some embodiments, to read the memory cell (e.g., to determine the state of the memory cell), the cell current of the memory cell is compared with a plurality of reference currents (e.g., predefined reference currents) determined based on the memory cell voltage threshold distribution set 100 (e.g., based on one or more of the erased cell voltage threshold distribution 102, the original cell voltage threshold distribution 104, and the programmed cell voltage threshold distribution 106).

[0053] In some embodiments, the minimum erased cell current 112 based on the erased cell voltage threshold distribution 102 is selected as a first reference current (e.g., "Iref1 Vt") among a plurality of reference currents. In some embodiments, the maximum original cell current 114 based on the original cell voltage threshold distribution 104 is selected as a second reference current (e.g., "Iref2 Vt") among a plurality of reference currents. In some embodiments, the minimum original cell current 116 based on the original cell voltage threshold distribution 104 is selected as a third reference current among a plurality of reference currents. In this regard, the first reference current, the second reference current, and the third reference current are carefully selected to enable a fine determination of the state of the memory cell (e.g., properly erased, insufficiently erased, poorly erased, programmed, etc.), thereby enabling early detection of the effects of aging, continuous cycling, and / or exposure to stress reflected in the voltage threshold shift of the memory cell. In some embodiments, the memory cell voltage threshold distribution set 100 may be obtained from silicon data associated with the memory cell being read. For example, the memory cell voltage threshold distribution set may be associated with the memory cell being read.

[0054] Figure 2FIG. 2 illustrates an example block diagram of a robust read circuit system 200 according to at least one embodiment of the present disclosure. In some embodiments, the robust read circuit system is implemented as a circuit configured to convert a cell current 204 (eg, “I cell ”) with a sense amplifier 202 that compares with a plurality of reference currents. In some embodiments, the sense amplifier 202 is a single-ended sense amplifier. In some embodiments, the plurality of reference currents include a first reference current 212 corresponding to a minimum erased cell current 112, a second reference current 214 corresponding to a maximum original cell current 114, and / or a third reference current 216 corresponding to a minimum original cell current 116.

[0055] In some embodiments, the sense amplifier 202 includes a bias circuit 210, one or more current generators (not shown), a comparator 230, and a logic stage 240. The bias circuit 210 can be configured to bias the memory cell to a desired voltage level before performing a read operation. For example, the bias circuit can be configured to apply a fixed reference voltage to the gate of the memory cell (e.g., the gate of its transistor). In some embodiments, the reference voltage is selected to be between the erased cell voltage threshold distribution 102 and the programmed cell voltage threshold distribution 106. In some embodiments, the reference voltage is selected to be in a window between the original cell voltage threshold distribution 104 and the programmed cell voltage threshold distribution 106. In some embodiments, the memory cell is implemented as a complementary metal oxide semiconductor (CMOS) based memory cell. For example, the memory cell can be implemented based on CMOS logic.

[0056] The one or more current generators may be configured to generate a first reference current 212, a second reference current 214, and a third reference current 216. In some embodiments, the one or more current generators may include a single current generator configured to output each of the first reference current 212, the second reference current 214, and the third reference current 216. In some embodiments, the one or more current generators may include a plurality of current generators, each of which is configured to output a specific reference current. For example, the first current generator may be configured to output the first reference current 212, the second current generator may be configured to output the second reference current 214, and the third current generator may be configured to output the third reference current 216.

[0057] In some embodiments, comparator 230 is a current comparator. In some embodiments, comparator 230 may be configured to receive cell current 204 and a plurality of reference currents (e.g., first reference current 212, second reference current 214, and third reference current 216). In some embodiments, comparator 230 includes an array-side input terminal configured to receive cell current 204 and a plurality of reference-side input terminals configured to receive a plurality of reference currents (e.g., first reference current 212, second reference current 214, and third reference current 216).

[0058] The array side input terminal can be selectively connected to the memory cell or otherwise connected to the memory array associated with the memory cell to receive the cell current 204. The reference side input terminal can be coupled to one or more current generators (not shown). For example, the reference side input terminal can be configured to receive a first reference current 212, a second reference current 214, and a third reference current 216.

[0059] In some embodiments, the comparator 230 is configured to compare the cell current 204 with one or more of the first reference current 212, the second reference current 214, and the third reference current 216. In some embodiments, the comparator 230 is configured to compare the cell current 204 with each of the first reference current 212, the second reference current 214, and the third reference current 216. For example, the comparator 230 can be configured to compare the cell current 204 with the first reference current 212, compare the cell current 204 with the second reference current 214, and / or compare the cell current 204 with the third reference current 216.

[0060] In some embodiments, the comparator 230 can be configured to compare the cell current 204 with each of the first reference current 212, the second reference current 214, and the third reference current 216 simultaneously. In some embodiments, the comparator 230 can be configured to compare the cell current 204 with each of the first reference current 212, the second reference current 214, and the third reference current 216 sequentially.

[0061] In some embodiments, the comparator 230 includes a comparison output stage 232. In some embodiments, the comparison output stage 232 includes a plurality of comparison output terminals. For example, the plurality of comparison output terminals may be latch output terminals. In some embodiments, the plurality of comparison output terminals of the comparison output stage 232 are configured to output a comparison result between the cell current 204 and a specific reference current (e.g., the first reference current 212, the second reference current 214, or the third reference current 216) among the plurality of reference currents.

[0062] In some embodiments, the comparison output stage 232 includes a first comparison output terminal 234 configured to output a first comparison output signal corresponding to a comparison result of the cell current 204 and the first reference current 212. In some embodiments, the comparison output stage 232 includes a second comparison output terminal 236 configured to output a second comparison output signal corresponding to a comparison result of the cell current 204 and the second reference current 214. In some embodiments, the comparison output stage 232 includes a third comparison output terminal 238 configured to output a third comparison output signal corresponding to a comparison result of the cell current 204 and the third reference current 216.

[0063] In some embodiments, the first comparison output terminal 234, the second comparison output terminal 236, and the third comparison output terminal 238 are configured to each output a high logic value 1 or a low logic value 0 corresponding to a comparison result between the cell current and a corresponding reference current (e.g., one of the first reference current 212, the second reference current 214, or the third reference current 216). In some embodiments, the comparator 230 is configured to output a high logic value 1 at each of the comparison output terminals 234-238 if the corresponding reference current is greater than the cell current 204 (e.g., the cell current 204 is less than the reference current), and to output a low logic value 0 if the cell current 204 is greater than the reference current (e.g., the reference current is less than the cell current 204).

[0064] It should be understood that in some embodiments, the comparator 230 can be configured to output a low logic value of 0 at each of the comparison output terminals 234-238 if the corresponding reference current is greater than the cell current 204 (e.g., the cell current 204 is less than the reference current), and to output a high logic value of 1 if the cell current 204 is greater than the reference current (e.g., the reference current is less than the cell current 204).

[0065] In some embodiments, logic stage 240 is configured to determine a granular state of a memory cell (eg, properly erased, under erased, badly erased, programmed cell, etc.) based on a comparison of cell current 204 to one or more of a plurality of reference currents.

[0066] In some embodiments, the sense amplifier 202 includes a second logic stage 260. The second logic stage 260 can be configured to process one or more of the comparison output signals from one or more of the first comparison output terminal 234, the second comparison output terminal 236, and / or the third comparison output terminal 238 (e.g., the first comparison output terminal 234, the second comparison output terminal 236, and / or the third comparison output terminal 238) to determine the primary state of the memory cell (e.g., the default state is erased or programmed).

[0067] Figure 3 An example output configuration of a logic level of a robust read circuit system according to at least one embodiment of the present disclosure is illustrated. In some embodiments, the logic level 240 is configured to determine the granularity state of the memory cell based on one or more of the comparison results of the cell current and the reference current. As described above, by making full use of three reference currents to read the memory cell, some embodiments can determine the granularity state of the memory cell. For example, a first granularity state may represent a good erase condition, a second granularity state may indicate an insufficient erase condition, a third granularity state may indicate a poor erase condition, and a fourth granularity state may indicate a programmed cell. In some embodiments, the granularity state of the memory cell determined by the robust read method technology described herein may reflect the degree of voltage threshold shift of the memory cell.

[0068] As mentioned above, reference Figure 2 , the sense amplifier 202 may be configured to sense or otherwise receive the cell current 204, and one or more of the first reference current 212, the second reference current 214, and / or the third reference current 216. For example, a comparator of the sense amplifier may be configured to receive the cell current 204, the first reference current 212, the second reference current 214, and the third reference current 216.

[0069] Using a comparator (e.g., comparator 230), the sense amplifier can compare the cell current 204 with each of the first reference current 212, the second reference current 214, and the third reference current 216, and output a first comparison output signal 304 (e.g., "D0"), a second comparison output signal 306 (e.g., "D1"), and a third comparison output signal 308 (e.g., "D2"), wherein each of the comparison output signals 304-308 represents a comparison result of the cell current 204 with a specific reference current (e.g., one of the first, second, and third reference currents 212-216).

[0070] In some embodiments, the comparator is configured to output a low logic value of 0 if it is determined that the cell current is greater than a reference current (e.g., one of the first, second, and third reference currents), and to output a high logic value of 1 if it is determined that the cell current is less than the reference current (e.g., one of the first, second, and third reference currents 212-216).

[0071] In some embodiments, a first granularity state in the plurality of granularity states describes a first condition 322 in which the cell current 204 is greater than each of the first reference current 212, the second reference current 214, and the third reference current 216. In some embodiments, the first granularity state indicates that the voltage threshold of the memory cell is less than the maximum erased cell voltage threshold of the erased cell voltage threshold distribution 102 (see, e.g., Figure 1), thereby indicating that the memory cell is properly erased (e.g., good erase condition). In some embodiments, the first condition 322 indicates that there is no voltage threshold shift or a minimum voltage threshold shift. Alternatively or additionally, in some embodiments, the first condition 322 indicates that aging effects and / or continuous cycling effects are minimal or absent.

[0072] like Figure 3 As shown in , in some embodiments, when the cell current is correctly erased (e.g., associated with a good erase condition), based on the memory cell having a cell current 204 greater than the first reference current 212, a first comparison output signal 304 corresponding to a comparison between the cell current 204 and the first reference current 212 may be a low logic value of 0. Alternatively or additionally, based on the memory cell having a cell current 204 greater than the second reference current 214, a second comparison output signal 306 corresponding to a comparison between the cell current 204 and the second reference current 214 may be a low logic value of 0. Alternatively or additionally, based on the memory cell having a cell current 204 greater than the third reference current 216, a third comparison output signal 308 corresponding to a comparison between the cell current 204 and the third reference current may be a low logic value of 0.

[0073] In some embodiments, a second granularity state in the plurality of granularity states describes a second condition 324, wherein the cell current 204 is greater than the second reference current 214, and the first reference current 212 is greater than the cell current 204. In some embodiments, the second granularity state indicates that the voltage threshold of the memory cell is between the maximum erased voltage threshold and the minimum original voltage threshold of the original cell voltage threshold distribution 104 (see, e.g., Figure 1 ) (e.g., a window between the erased cell voltage threshold distribution and the original cell voltage threshold distribution 104), thereby indicating that the memory cell is under-erased. In this regard, the second granularity state can indicate some degree of voltage shift. Alternatively or additionally, the second granularity state can indicate some aging and / or continuous cycling effects.

[0074] As shown, in some embodiments, when the memory cell is under-erased, the first comparison output signal 304 may be a high logic value 1 based on the memory cell having a cell current 204 less than the first reference current 212. Alternatively or additionally, the second comparison output signal 306 may be a low logic value 0 based on the memory cell having a cell current 204 greater than the second reference current 214. Alternatively or additionally, the third comparison output signal 308 may be a low logic value 0 based on the memory cell having a cell current 204 greater than the third reference current 216.

[0075] In some embodiments, a third granularity state in the plurality of granularity states describes a third condition 326 in which the cell current 204 is greater than the third reference current 216 but less than the first reference current 212 and the second reference current 214. In some embodiments, the third granularity state indicates that the voltage threshold of the memory cell is between the minimum raw voltage threshold and the maximum raw voltage threshold of the raw cell voltage threshold distribution 104 (see, e.g., Figure 1 ), thereby indicating that the memory cell is poorly erased (e.g., a bad erase condition). In this regard, the third granularity state can indicate a considerable degree of voltage shift, where the voltage threshold of the cell can be within the voltage threshold distribution of the original cell, thereby indicating a potential reliability issue. Alternatively or additionally, the third granularity state can indicate considerable aging and / or continuous cycling effects.

[0076] As shown, in some embodiments, when the memory cell is poorly erased (e.g., a bad erase condition), the first comparison output signal 304 may be a high logic value 1 based on the memory cell having a cell current 204 less than the first reference current 212. Alternatively or additionally, the second comparison output signal 306 may be a high logic value 1 based on the memory cell having a cell current 204 less than the second reference current 214. Alternatively or additionally, the third comparison output signal 308 may be a low logic value 0 based on the memory cell having a cell current 204 greater than the third reference current 216.

[0077] In some embodiments, a fourth granularity state in the plurality of granularity states describes a fourth condition 328 where the cell current 204 is less than each of the first reference current 212, the second reference current 214, and the third reference current 216 (e.g., the third reference current is greater than the cell current). In some embodiments, the fourth granularity state indicates that the voltage threshold of the memory cell is greater than the maximum voltage threshold of the original cell, thereby indicating a programmed cell.

[0078] As shown, in some embodiments, when the memory cell is programmed (e.g., a programmed cell), the first comparison output signal 304 may be a high logic value 1 based on the memory cell having a cell current 204 less than the first reference current 212. Alternatively or additionally, the second comparison output signal 306 may be a high logic value 1 based on the memory cell having a cell current 204 less than the second reference current 214. Alternatively or additionally, the third comparison output signal 308 may be a high logic value 1 based on the memory cell having a cell current 204 less than the third reference current 216.

[0079] It will be appreciated that in some embodiments, the logic value associated with the output signal may be reversed. For example, in some embodiments, if the cell current is greater than the reference current, the output signal may be a high logic value of 1, and if the cell current is less than the reference current, the output signal may be a low logic value of 0.

[0080] In some embodiments, the robust read circuit system 200 (e.g., the sense amplifier 202 thereof) can be configured to output, for example, to a user, a first comparison output signal 304, a second comparison output signal 306, and / or a third comparison output signal 308 corresponding to a granularity state determined by the robust read circuit system (e.g., the sense amplifier 202 thereof).

[0081] like Figure 3 As shown in , in some embodiments, alternatively or additionally, the robust read circuit system 200 (e.g., the sense amplifier 202 thereof) can be configured to output a main output signal 310 indicating an erased state or a programmed state. In some embodiments, the main output signal 310 is determined based on the first comparison output signal 304, the second comparison output signal 306, and / or the third comparison output signal 308. In some embodiments, and as Figure 3 As shown in , the robust read circuitry 200 (e.g., its sense amplifier 202) outputs a low logic value 0 corresponding to the erased state for each of the first condition 322 (e.g., properly erased state), the second condition 324 (e.g., under-erased state), and the third condition 326 (e.g., badly erased state). In some embodiments, and as Figure 3 As shown in , the robust read circuitry 200 (eg, the sense amplifier 202 thereof) outputs a high logic value of 1 corresponding to the programmed state for the fourth condition 328 (eg, programmed cell).

[0082] It should be understood that in some embodiments, the logic states may be reversed. For example, the robust read circuitry 200 (e.g., the sense amplifier 202 thereof) may output a high logic value 1 corresponding to the erased state for each of the first condition 322 (e.g., properly erased state), the second condition 324 (e.g., under-erased state), and the third condition 326 (e.g., badly erased state), and output a low logic value 0 corresponding to the programmed state for the fourth condition 328 (e.g., programmed cell).

[0083] Figure 4 A schematic diagram of an example sense amplifier 400 is provided in accordance with at least one embodiment of the present disclosure. The sense amplifier 400 may be a reference Figure 2 An example of the sense amplifier 202 discussed. Specifically, Figure 4 A schematic diagram of a single-ended sense amplifier is illustrated. Figure 4A first portion 404 of the sense amplifier 400 is depicted, which is configured for biasing of the bit line (e.g., during a precharge phase). As depicted, a second portion 406 may be configured for comparing the cell current to a plurality of reference currents (e.g., during an evaluation phase). Figure 4 As further depicted in FIG. 4 , the third portion 408 is configured to generate a primary output signal (erased state or programmed state). In this regard, by utilizing a single-ended sense amplifier configured to compare a cell current of a memory cell with each of a plurality of reference currents, embodiments of the present disclosure reduce the array cell area used (e.g., saves area that would otherwise include a reference cell) by avoiding the need to use a reference cell.

[0084] Figure 5 Flowcharts depicting the operation of example methods / processes of the robust read method technique according to at least one embodiment of the present disclosure are illustrated. It will be appreciated that each flow chart depicts an example computer-implemented method / process that can be performed by one or more of an apparatus, system, device, and / or computer program product (e.g., utilizing one or more of its specifically configured components).

[0085] Although the exemplary method / process depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of the process.

[0086] The box indicates the operation of the method / processing. Such operations can be performed in any of a variety of ways, including but not limited to the order and manner depicted and described herein. In some embodiments, one or more boxes of any process described herein occur between one or more boxes of another process, before one or more boxes of another process, in parallel with one or more boxes of another process, and / or as a sub-process of a second process. Additionally or alternatively, any process in various embodiments includes some or all of the described and / or depicted operational steps, including one or more optional boxes in some embodiments. With respect to the flowcharts shown herein, one or more of the (one or more) boxes depicted in some embodiments are optional in some or all embodiments of the present disclosure. Optional boxes are depicted with broken lines (or "dotted lines"). Similarly, it should be appreciated that one or more of the operations of each flowchart may be combinable, replaceable and / or otherwise modified, as described herein.

[0087] According to some examples, the method includes receiving a cell current of a memory cell and a plurality of reference currents at operation 502. For example, the example method includes sensing a cell current, a first reference current, a second reference current, and / or a third reference current using a sense amplifier. In some embodiments, the sense amplifier is a single-ended sense amplifier. In some embodiments, the cell current and / or the plurality of reference currents may be sensed in response to an indication of a read operation. In some embodiments, a bit line associated with the memory cell is biased to provide a reference voltage applied to a gate of the memory cell. In some embodiments, the memory cell is a nonvolatile memory cell. Alternatively or additionally, in some embodiments, the memory cell is an electrically programmable and erasable two-level memory cell. Alternatively or additionally, the memory cell is a multi-time programmable (MTP) memory. For example, the memory cell may be implemented as an eMTP IP. Alternatively or additionally, in some embodiments, the memory cell is a CMOS-based memory cell. For example, the memory cell may be implemented as a CMOS configuration. For example, the memory cell may be implemented based on CMOS logic so that no additional mask is required.

[0088] In some embodiments, the plurality of reference currents include a first reference current, a second reference current, and a third reference current. In some embodiments, the first, second, and third reference currents are determined based on a voltage threshold distribution associated with the memory cell. In some embodiments, the first reference current corresponds to a minimum erased cell current based on a voltage threshold distribution associated with the memory cell. In some embodiments, the second reference current corresponds to a maximum original cell current based on a voltage threshold distribution associated with the memory cell. In some embodiments, the third reference current corresponds to a minimum original cell current based on a voltage threshold distribution associated with the memory cell.

[0089] According to some examples, the method includes generating a plurality of comparison output signals at operation 504. In some embodiments, a first comparison output signal is generated based on comparing the cell current with a first reference current. In some embodiments, a second comparison output signal is generated based on comparing the cell current with a second reference current. In some embodiments, a third comparison output signal is generated based on comparing the cell current with a third reference current.

[0090] According to some examples, the method includes determining a granularity state of the memory cell at operation 506. For example, the example method includes determining a granularity state of the memory cell in a plurality of granularity states based on one or more of a comparison of the cell current to a first reference current, a comparison of the cell current to a second reference current, or a comparison of the cell current to a third reference current.

[0091] In some embodiments, the granular state of the memory cell is determined based on comparing the cell current to at least two of a plurality of reference currents. In some embodiments, the granular state of the memory cell is determined based on each of a comparison of the cell current to a first reference current, a comparison of the cell current to a second reference current, and a comparison of the cell current to a third reference current.

[0092] In some embodiments, the plurality of granularity states include one or more of a correctly erased state, an insufficiently erased state, a poorly erased state, or a programmed state. In some embodiments, if it is determined that the cell current is greater than the first reference current, then the memory cell is determined to be correctly erased. In some embodiments, if the cell current is greater than the second reference current, and the first reference current is greater than the cell current, then the memory cell is determined to be insufficiently erased. In some embodiments, if the cell current is greater than the third reference current, and each of the first reference current and the second reference current is greater than the cell current, then the memory cell is determined to be poorly erased. In some embodiments, if the cell current is less than each of the first reference current, the second reference current, and the third reference current, then the memory cell is determined to be programmed.

[0093] According to some examples, the method includes generating a final output signal corresponding to a primary state of the memory cell at operation 508. In some embodiments, the example method includes generating the final output signal based on one or more of the first comparison output signal, the second comparison output signal, or the third comparison output signal. In some embodiments, generating the final output may include performing one or more logic operations on one or more of the first comparison output signal, the second comparison output signal, or the third comparison output signal. In some embodiments, the final output signal is generated based on each of the first comparison output signal, the second comparison output signal, and the third comparison output signal.

[0094] According to some examples, the method includes outputting one or more of a first comparison output signal, a second comparison output signal, a third comparison output signal, or a main output signal at operation 510. For example, the first comparison output signal, the second comparison output signal, the third comparison output signal, and the final output signal may be output so that they are accessible to a user.

[0095] in conclusion Those skilled in the art of the present disclosure who benefit from the teachings presented in the foregoing description and the related drawings will think of many modifications and other embodiments of the present disclosure set forth herein. Therefore, it should be understood that the embodiments are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing description and the related drawings describe example embodiments in the context of certain example combinations of elements and / or functions, it should be appreciated that different combinations of elements and / or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, combinations of elements and / or functions different from those explicitly described above may also be envisioned, as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used only in a general and descriptive sense, and not for purposes of limitation.

[0096] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any disclosure or the scope of what can be claimed, but rather as descriptions of features that are peculiar to a particular disclosed specific embodiment. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Moreover, although features may be described above as working in certain combinations, and even initially claimed as such, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0097] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the particular order or sequential order shown or performing all of the operations shown to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous. Moreover, the separation of the various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0098] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing can be advantageous.

[0099] In addition, although this detailed description has set forth some embodiments of the present disclosure, the appended claims may cover other embodiments of the present disclosure that are different from the described embodiments according to various modifications and improvements. For example, in some embodiments, a high logic value of 1 may be associated with an erased cell, and a low logic value of 0 may be associated with a programmed cell. As another example, in some embodiments, the multiple references may include less than three references or more than three references. As yet another example, in some embodiments, the multiple references may be selected based on other criteria that may not be based on a voltage threshold distribution. As yet another example, the sense amplifier may be implemented in different configurations without departing from the scope of the present disclosure.

[0100] Additionally, in the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that 35 USC §112, paragraph (f) be invoked to interpret the claim.

Claims

1. A method for reading a memory cell, the method comprising: receiving a cell current of a memory cell; receiving a first reference current, a second reference current, and a third reference current; generating a first comparison output signal based on comparing the cell current to a first reference current; generating a second comparison output signal based on comparing the cell current to a second reference current; generating a third comparison output signal based on comparing the cell current to a third reference current; as well as A granular state of the memory cell is determined based at least in part on one or more of a comparison of the cell current to a first reference current, a comparison of the cell current to a second reference current, or a comparison of the cell current to a third reference current.

2. The method of claim 1, wherein the first reference current corresponds to a minimum erased cell current based on a voltage threshold distribution associated with the memory cells.

3. The method of claim 2, wherein the second reference current corresponds to a maximum original cell current based on a voltage threshold distribution associated with the memory cell.

4. The method of claim 3, wherein the third reference current corresponds to a minimum original cell current based on a voltage threshold distribution associated with the memory cell.

5. The method of claim 4, wherein if it is determined that the cell current is greater than the first reference current, it is determined that the memory cell is correctly erased.

6. The method of claim 4, wherein if the cell current is greater than the second reference current and the first reference current is greater than the cell current, then determining that the memory cell is under-erased.

7. The method of claim 4, wherein if the cell current is greater than a third reference current, and each of the first reference current and the second reference current is greater than the cell current, it is determined that the memory cell is badly erased.

8. The method of claim 4, wherein if the cell current is less than each of the first reference current, the second reference current, and the third reference current, it is determined that the memory cell is programmed.

9. The method of claim 1, further comprising generating a final output signal corresponding to a primary state of the memory cell based on one or more of the first comparison output signal, the second comparison output signal, or the third comparison output signal. 10 . The method of claim 9 , further comprising outputting one or more of a first comparison output signal, a second comparison output signal, a third comparison output signal, or a final output signal.

11. A robust read circuit system for reading a memory cell, the robust read circuit system comprising: Sense amplifiers, including: one or more current generators configured to generate a plurality of reference currents; a comparator coupled to the one or more current generators, wherein the comparator is configured to: receiving a cell current of a memory cell; receiving the plurality of reference currents; and A granular state of the memory cell is determined based on comparing the cell current to at least two reference currents of the plurality of reference currents.

12. The sense amplifier of claim 11 , wherein the plurality of reference currents comprises: a first reference current corresponding to a minimum erased cell current based on a voltage threshold distribution associated with the memory cell; a second reference current corresponding to a maximum original cell current based on a voltage threshold distribution associated with the memory cell; as well as The third reference current corresponds to a minimum original cell current based on a voltage threshold distribution associated with the memory cell.

13. The robust read circuitry of claim 12, wherein the sense amplifier is configured to determine that the memory cell is properly erased if the cell current is determined to be greater than the first reference current.

14. The robust read circuitry of claim 12, wherein the sense amplifier is configured to determine that the memory cell is under-erased if the cell current is determined to be greater than the second reference current and the first reference current is determined to be greater than the cell current.

15. The robust read circuit system of claim 12, wherein the sense amplifier is configured to determine that the memory cell is badly erased if the cell current is determined to be greater than a third reference current and each of the first reference current and the second reference current is determined to be greater than the cell current.

16. The robust read circuit system of claim 12, wherein the sense amplifier is configured to determine that the memory cell is programmed if the cell current is determined to be less than the first reference current, the second reference current, and the third reference current.

17. The robust read circuitry of claim 11, further configured to output a primary state of the memory cell.

18. The robust read circuitry of claim 11, wherein the sense amplifier is a single-ended sense amplifier.

19. The robust read circuit system of claim 11, wherein the memory cell is an electrically programmable and erasable two-level memory cell.

20. The robust read circuitry of claim 11, wherein the sense amplifier further comprises a bias circuit configured to bias a bit line associated with the memory cell.

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