Storage device, test fixture and test system

Abstract

Embodiments of the present disclosure provide a storage device, a test fixture and a test system. The storage device comprises a main circuit board and a memory controller. The main circuit board comprises a test interface configured to receive first startup data. The memory controller is disposed on the main circuit board and connected to the test interface. The memory controller stores second startup data. The memory controller is configured to obtain the second startup data, obtain the first startup data through the test interface when the obtaining of the second startup data fails, and perform an initialization operation on the storage device according to the first startup data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a storage device, a test fixture, and a test system. Background Technology

[0002] Solid-state drives (SSDs) have gradually become the mainstream in the market due to their advantages such as fast read and write speeds, superior shock resistance, and extremely low power consumption. Furthermore, with the development of cloud computing and big data technologies, SSDs still have a very broad market prospect.

[0003] Solid-state drives (SSDs) undergo activation, a series of tests and adjustments before leaving the factory to ensure they have good storage performance, reliability, and stability. Because SSDs have very sophisticated hardware and complex firmware, they may inevitably fail to boot under certain circumstances, affecting subsequent testing and adjustments. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a storage device, a test fixture, and a test system.

[0005] According to a first aspect of this disclosure, a storage device is provided, comprising:

[0006] The main circuit board includes a test interface for receiving first startup data.

[0007] A memory controller is mounted on the main circuit board and connected to the test interface; the memory controller stores the second startup data.

[0008] The memory controller is configured to: acquire the second boot data; acquire the first boot data through the test interface when acquiring the second boot data fails; and perform an initialization operation on the storage device based on the first boot data.

[0009] In some embodiments, the memory controller is configured to:

[0010] When the acquisition of the second startup data fails, the external storage device that provides the first startup data is enabled based on the selection signal, and a startup data request signal is generated, and the first startup data provided by the external storage device in response to the startup data request signal is received;

[0011] The test interface is also used to output the selection signal and the start data request signal.

[0012] In some embodiments, the memory controller is configured to:

[0013] A clock signal is output through the test interface, and the first startup data is sampled based on the clock signal;

[0014] The external storage device is supplied with power and ground voltage through the test interface.

[0015] In some embodiments, the test interface includes a plurality of test pads;

[0016] The memory controller is connected to the plurality of test pads to output the selection signal, the startup data request signal, the clock signal, the power supply voltage, and the ground voltage through the plurality of test pads, and to receive the first startup data.

[0017] In some embodiments, the test interface includes:

[0018] The first test pad is connected to the power supply pin of the memory controller to output the power supply voltage;

[0019] The second test pad is connected to the ground pin of the memory controller and is used to output the ground voltage;

[0020] The third test pad is connected to the chip select signal pin of the memory controller and is used to output the selection signal;

[0021] The fourth test pad is connected to the clock pin of the memory controller and is used to output the clock signal;

[0022] The fifth test pad is connected to the signal output pin of the memory controller and is used to output the startup data request signal;

[0023] The sixth test pad is connected to the signal input pin of the memory controller and is used to receive the first startup data.

[0024] In some embodiments, the first boot data includes read-only memory program code and bootloader code;

[0025] The memory controller is configured to: run a read-only memory program based on read-only memory program code, verify the bootloader code using the read-only memory program, and run the bootloader based on the verified bootloader code to complete the initialization operation.

[0026] In some embodiments, the memory controller is further configured to:

[0027] After power-on, acquire the second startup data;

[0028] When the second startup data is successfully acquired, an initialization operation is performed on the storage device based on the second startup data.

[0029] In some embodiments, the main circuit board includes a first side and a second side disposed opposite to each other, and the memory controller is disposed on the first side of the main circuit board;

[0030] The test interface is located on the first or second side of the main circuit board.

[0031] In some embodiments, the storage device further includes: an input / output connector disposed at one end of the main circuit board, and the test interface is located between the memory controller and the input / output connector;

[0032] The storage device also includes:

[0033] A non-volatile memory is disposed on the first side of the main circuit board and located on the side of the memory controller away from the input / output connector.

[0034] In some embodiments, the processor is configured to output a startup data loading failure signal through the input / output connector when acquiring the second startup data fails.

[0035] According to a second aspect of this disclosure, a test fixture is provided, comprising:

[0036] Test substrate;

[0037] A startup data storage device is installed on the test substrate, and the startup data storage device stores first startup data.

[0038] A test connector is disposed on the test substrate and connected to the startup data storage device. The test connector is used to make contact with the test interface on the storage device.

[0039] In some embodiments, the startup data storage device includes a read-only memory, wherein the read-only memory stores the first startup data.

[0040] In some embodiments, the test connector includes a plurality of pins, each pin being configured to contact and connect with a test pad in the test interface.

[0041] In some embodiments, the test fixture further includes:

[0042] A signal conversion module is disposed on the test substrate;

[0043] The first conversion interface is connected to the signal conversion module;

[0044] The second conversion interface is connected to the signal conversion module. The second conversion interface is used to connect to the input / output connector of the storage device. The first conversion interface is different from the second conversion interface.

[0045] In some embodiments, a switch is provided between the test connector and the startup data storage device;

[0046] After the storage device outputs a startup data loading failure signal, the switch is closed to enable the startup data storage device.

[0047] According to a third aspect of this disclosure, a test system is provided, comprising: a test fixture and a storage device;

[0048] The test fixture includes: a startup data storage device and a test connector disposed on a test substrate, wherein the startup data storage device stores first startup data and the test connector is connected to the startup data storage device;

[0049] The storage device includes a main circuit board and a memory controller. The main circuit board includes a test interface. The memory controller is disposed on the main circuit board and connected to the test interface. The storage device is mounted on the test fixture, and the test interface and the test connector are in contact connection.

[0050] In some embodiments, the memory controller stores second startup data;

[0051] The memory controller is configured to: acquire the second startup data; when acquiring the second startup data fails, acquire the first startup data in the startup data storage device; and perform an initialization operation on the memory controller according to the first startup data.

[0052] In some embodiments, the memory controller is configured to:

[0053] When acquiring the second startup data fails, the startup data storage device is enabled based on a selection signal, a startup data request signal is sent to the startup data storage device, and the first startup data provided by the startup data storage device in response to the startup data request signal is received.

[0054] In some embodiments, the test interface includes a plurality of test pads, and the memory controller is connected to the plurality of test pads;

[0055] The test connector includes a plurality of pins, the start-up data storage device is connected to the plurality of pins, and each pin is in contact with a test pad.

[0056] In some embodiments, the test interface includes:

[0057] The first test pad is connected to the power pin of the memory controller and is used to supply power voltage to the boot data storage device;

[0058] The second test pad is connected to the ground pin of the memory controller and is used to supply ground voltage to the startup data storage device;

[0059] The third test pad is connected to the chip select signal pin of the memory controller and is used to output the selection signal to the startup data storage device;

[0060] The fourth test pad is connected to the clock pin of the memory controller and is used to provide a clock signal to the startup data storage device;

[0061] The fifth test pad is connected to the signal output pin of the memory controller and is used to output the startup data request signal to the startup data storage device.

[0062] The sixth test pad is connected to the signal input pin of the memory controller and is used to receive the first startup data from the startup data storage device.

[0063] The storage device provided in this embodiment has a test interface on the main circuit board to receive first boot data provided by an external storage device. This allows the first boot data to be used to complete the initialization operation even if the memory controller fails to obtain second boot data from its internal storage. This design firstly avoids situations where corrupted second boot data prevents the storage device from completing initialization; secondly, the location and routing of the test interface are more flexible, and the test interface occupies less area on the main circuit board. These characteristics contribute to reducing the size of the main circuit board, thereby facilitating device miniaturization, reducing layout complexity, and simplifying motherboard design.

[0064] Furthermore, the initial boot data in the external storage device can be pre-programmed, and different storage devices can share the same external storage device. This allows for obtaining the initial boot data by connecting to the external storage device through the test interface, shortening the testing cycle. Especially when multiple storage devices fail to initialize during testing, these devices can share the same external storage device, greatly simplifying the debugging process, improving product debugging efficiency, and reducing costs. Attached Figure Description

[0065] Figure 1A A schematic diagram of an exemplary system provided in this disclosure embodiment;

[0066] Figure 1BAn architecture diagram of a memory card provided in this disclosure embodiment;

[0067] Figure 1C An architecture diagram of an SSD provided in an embodiment of this disclosure;

[0068] Figure 2 This is a schematic diagram of the structure of a storage device provided in an embodiment of the present disclosure;

[0069] Figure 3 This is a schematic diagram of the structure of another storage device provided in an embodiment of the present disclosure;

[0070] Figure 4 for Figure 3 Another partial structural diagram of the storage device shown;

[0071] Figure 5 This is a schematic diagram showing the connection between the memory controller and the test interface provided in an embodiment of the present disclosure;

[0072] Figure 6 This is a schematic diagram of the structure of a test fixture provided in an embodiment of the present disclosure;

[0073] Figure 7 A schematic diagram of the connection between the startup data storage device and the test connector provided in an embodiment of this disclosure;

[0074] Figure 8 This is a schematic diagram of a testing system provided in an embodiment of the present disclosure. Detailed Implementation

[0075] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments.

[0076] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0077] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising” and / or “including,” as used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0078] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0079] like Figure 1A As shown, this disclosure provides an exemplary system 10, which may include a host 20 and a storage device 30. The exemplary system 10 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory 40 therein; the host 20 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)).

[0080] In one embodiment of this disclosure, the host 20 may be configured to send data to or receive data from the storage device 30. Here, the storage device 30 may include a memory controller 300 and one or more memories 40. The memories 40 may include, but are not limited to, NAND flash memory, 3D NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM).

[0081] In one embodiment of this disclosure, a memory controller 300 may be coupled to the memory 40 and the host 20 and is used to control the memory 40. Exemplarily, the memory controller 300 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 300 may also be designed to operate in a high duty cycle environment, such as an SSD or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0082] In one embodiment of this disclosure, the memory controller 300 and one or more memories 40 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 30 can be implemented and packaged into different types of end electronic products. Figure 1B As shown, the memory controller 300 and a single memory 40 can be integrated together to form a memory card 50. The memory card 50 may include a PC card (Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC, RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 50 may also include a connector for connecting the memory card 50 to a host computer (e.g., Figure 1A The host 20) is coupled to the memory card connector 51. In such a way... Figure 1C In another embodiment shown, the memory controller 300 and a plurality of memories 40 may be integrated together to form an SSD 60. The SSD 60 may also include a connection between the SSD 60 and a host (e.g., Figure 1A The host 20 is coupled to the SSD connector 61. In some embodiments, the storage capacity and / or operating speed of the SSD 60 is greater than that of the memory card 50.

[0083] The memory controller 300 can manage the data in the memory 40 and communicate with the host. The memory controller 300 can be configured to control operations such as reading, erasing, and programming of the memory 40; it can also be configured to manage various functions related to data stored or to be stored in the memory 40, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling; it can also be configured to handle error checking and correction (ECC) codes for data read from or written to the memory 40. Furthermore, the memory controller 300 can also be configured to communicate with external devices (e.g., according to a specific communication protocol) according to a specific communication protocol. Figure 1ACommunication with the host 20). For example, the host interface controller can communicate with an external host via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, etc. It should be understood that the memory controller 300 can also perform any other suitable functions, such as formatting the memory 40, initializing the storage device 30, etc.

[0084] In one embodiment, the startup of the storage device 30, also known as the initialization of the storage device 30, mainly includes two stages: the first stage is that the memory controller 300 executes the read-only memory code (ROM code), and the second stage is that the bootloader code is loaded and executed.

[0085] In one embodiment, the memory controller 300 may include a processor, read-only memory (ROM), and tightly-coupled memory (TCM). For example, the tightly-coupled memory may be implemented as random access memory (RAM).

[0086] The ROM code is stored internally in the memory controller 300; specifically, it is permanently stored in the read-only memory (ROM). After the memory controller 300 is powered on, the ROM code is executed first. Generally, after the memory controller 300 is powered on, the processor reads the ROM code from a fixed address stored in the ROM to run the ROM program.

[0087] In some embodiments, the bootloader may be stored in read-only memory.

[0088] When the processor runs the ROM program, the ROM program searches for the Bootloader file in the read-only memory and loads the Bootloader file into the tightly coupled memory. The processor then runs the ROM program to verify the Bootloader file in the tightly coupled memory. If the verification is successful, the processor jumps to and runs the bootloader program according to the Bootloader, completing the initialization of the storage device.

[0089] The memory controller 300 completes the entire system initialization by executing ROM code and the bootloader. During the initialization process, the memory controller 300 configures the storage device so that the host or unlocking device can recognize the storage device after initialization. The unlocking device can then write the firmware required for the storage device (e.g., an SSD) to the storage device.

[0090] Given the important role of ROM code and bootloader in system initialization, in order to prevent the storage device from failing to perform initialization due to damage to the ROM code and bootloader inside the memory controller, in some embodiments, mounting positions for external storage devices and related components can be reserved on the main circuit board of the storage device.

[0091] If, during debugging, an error occurs in the ROM code and / or Bootloader within the memory controller 300, preventing the bootloader from running, the external storage device and related components can be manually mounted, and the ROM code and / or Bootloader file can be burned into the external storage device. The memory controller 300 can then retrieve the ROM code and / or Bootloader file from the external storage device to complete system initialization, thereby enabling debugging of the storage device.

[0092] While this method can remedy the problem of storage devices failing to boot due to internal errors in the memory controller, manually mounting external storage devices and related components is time-consuming and labor-intensive. Furthermore, writing ROM code and / or Bootloader files into the external storage devices after mounting increases testing cycles and costs. Especially when multiple storage devices fail to boot, these operations need to be repeated multiple times, significantly increasing production cycles and costs. Additionally, the mounting space reserved for external storage devices and related components occupies a significant amount of motherboard area, hindering device miniaturization.

[0093] Another embodiment of this disclosure provides a storage device that can solve the problem of storage devices failing to boot due to internal faults in the memory controller, and can also reduce debugging cycle and cost. Figure 2 This is a schematic diagram of the structure of a storage device provided in an embodiment of the present disclosure, such as... Figure 2 As shown, the storage device 30 includes:

[0094] The main circuit board includes a test interface 200, which is used to receive the first startup data;

[0095] The memory controller 300 is mounted on the main circuit board and connected to the test interface 200; the memory controller 300 stores the second startup data.

[0096] The memory controller 300 is configured to: acquire second boot data; acquire first boot data through test interface 200 if acquiring the second boot data fails; and perform initialization operations on the storage device based on the first boot data.

[0097] Figure 3 and Figure 4 This is a schematic diagram of the structure of another storage device provided in the embodiments of this disclosure. The following is in conjunction with... Figure 3 and Figure 4 The storage device provided in the embodiments of this disclosure is described in detail.

[0098] In this embodiment, the main circuit board 100 may be a printed circuit board (PCB). The main circuit board 100 serves as a support for electronic components and a carrier for the electrical interconnection of these components. The main circuit board 100 includes a first surface 101 and a second surface 102 facing each other. Components may be concentrated on one side of the main circuit board 100, such as the first surface 101. Alternatively, components may be disposed on both sides of the main circuit board 100, meaning components are disposed on both the first surface 101 and the second surface 102 of the main circuit board 100.

[0099] The main circuit board 100 has component pads (not shown in the figure) on its surface. Electronic components are soldered onto the component pads on the main circuit board. Metal traces and vias are arranged on the surface and / or inside of the main circuit board. The metal traces are connected to the component pads corresponding to different components, so that the electronic components are electrically connected to each other.

[0100] See also Figure 3 and Figure 4In this embodiment, the storage device 30 includes a memory controller 300 and one or more memory devices, which are integrated on the same main circuit board 100. The memory devices may include non-volatile memory 410, which may include NAND flash memory or other non-volatile memories (e.g., PCRAM, FRAM) as described above. For example, both the memory controller 300 and the non-volatile memory 410 are disposed on the first surface 101 of the main circuit board 100.

[0101] The first surface 101 of the main circuit board 100 is provided with a plurality of first device pads corresponding to the memory controller 300 and a plurality of second device pads corresponding to the memory devices. A plurality of pins of the memory controller 300 are soldered one-to-one with the plurality of first device pads, and a plurality of pins of the memory devices are soldered one-to-one with the plurality of second device pads. The first device pads and the second device pads are connected by metal traces and vias, thereby realizing the electrical connection between the memory controller 300 and the memory devices.

[0102] It should be understood that, in another embodiment, the memory controller 300 and some of the memory devices may be disposed on the first side 101 of the main circuit board 100, and other memory devices may be disposed on the second side 102 of the main circuit board 100.

[0103] The storage device also includes an input / output connector 500 for mounting the storage device on the host and for handling signal transmission between the host and the storage device. During testing of the storage device, the input / output connector 500 is connected to a test device, which then sends signals to the storage device through the input / output connector 500 to test or debug the storage device.

[0104] In some embodiments, such as Figure 3 As shown, the input / output connector 500 is located at one end of the main circuit board 100 for easy installation to the host. The memory controller 300 is located adjacent to the input / output connector 500, and the non-volatile memory 410 is located at the end of the memory controller 300 away from the input / output connector 500.

[0105] In some embodiments, the input / output connector 500 in the SSD is typically a gold finger. The gold finger is used to insert into a corresponding slot on the host to install the SSD into the host and establish an electrical connection. The specific structure of the gold finger is determined by the interface protocol between the memory controller 300 and the host.

[0106] In addition, the storage device may also include DRAM 420, which is connected to the memory controller 300 and serves as a data relay station between the host and the memory controller 300. Data sent from the host to the storage device 30 can be cached in the DRAM 420 first, and then written to the non-volatile memory 410 by the memory controller 300. That is, setting up DRAM 420 can improve the data transfer efficiency between the host and the storage device 30.

[0107] See also Figure 3 In this embodiment, the main circuit board 100 also includes a test interface 200, which is connected to the memory controller 300. The test interface 200 receives the first startup data sent by the external storage device and transmits it to the memory controller 300.

[0108] In other words, in this embodiment, the test interface 200 replaces the component pads reserved for external storage devices and related components on the main circuit board 100, and the external storage devices and related components are placed on a structure outside the storage device. For example, the "external storage devices and related components" can be placed on the test fixture as a boot data storage device. During the test, when the storage device fails to initialize, the test interface 200 is connected to the external boot data storage device to provide the memory controller 300 with the first boot data, so that the storage device can complete system initialization.

[0109] This disclosure does not limit the specific structure of the test interface 200. In this embodiment, as shown... Figure 3 and Figure 4 As shown, the test interface 200 may include one or more test pads 210 (also referred to as test points). The test pads 210 may be formed simultaneously with the device pads and have a similar structure. For example, the test pads may be flat metal pads.

[0110] This disclosure does not limit the shape of the test pad 210. For example, the test pad 210 can be circular, elliptical, square, polygonal (e.g., hexagonal), teardrop-shaped, etc.

[0111] Compared to component pads, which require dimensions, spacing, and arrangement to match component pins, test pads 210 offer greater flexibility in size, spacing, and arrangement. The arrangement of multiple test pads can be adjusted based on the size of the main circuit board 100 or the layout of other components, and the size and spacing of the test pads can also be adjusted (e.g., reduced). Furthermore, when not involved in related testing, test pads can be covered with solder resist ink (commonly known as solder mask) to reduce the probability of oxidation. When needed, the solder mask covering the test pads can be removed.

[0112] It should be understood that in other embodiments, the test interface 200 may also be a connector or similar device commonly used in the art for testing.

[0113] In some embodiments, such as Figure 4 As shown, the test interface 200 and the memory controller 300 can be located on the same side of the main circuit board 100. That is, the test interface 200 is also located on the first side 101 of the main circuit board. In other embodiments, the test interface 200 and the memory controller 300 can be located on opposite sides of the main circuit board, that is, the test interface 200 is located on the second side 102 of the main circuit board.

[0114] It should be understood that if the test interface 200 is a test pad, then the test interface 200 can be located on either side of the main circuit board without affecting the thickness of the storage device. If the test interface 200 is a connector, then the test interface 200 can be located on the same side as other components (such as the memory controller 300) to avoid increasing the thickness of the storage device.

[0115] Furthermore, this disclosure does not limit the electrical connection method between the test interface 200 and the memory controller 300. Taking the test interface 200 including multiple test pads 210 as an example, the multiple test pads and the multiple first device pads corresponding to the memory controller 300 may be electrically connected in a one-to-one correspondence, that is, one test pad is electrically connected to one first device pad, but they may not be electrically connected in a one-to-one correspondence. The connection method between the multiple first device pads and the multiple test pads 210 depends on the signal interaction between the memory controller 300 and the external boot data storage device. In actual use, the connection relationship between the first device pads and the test pads 210 is set according to the signal between the memory controller 300 and the external boot data storage device.

[0116] In some embodiments, the first device pad and the test pad 210 are connected via metal traces, or vias and metal traces. For example, the memory controller 300 and the test pad 210 are disposed on a first surface 101 of the main circuit board 100, and the first device pad and the test pad 210 can be connected via metal traces routed on the first surface 101 of the main circuit board 100. In other embodiments, the first device pad and the test pad 210 can be connected to the inner layer circuitry or the second surface 102 circuitry of the main circuit board 100 via vias, interconnected using metal traces in the inner layer circuitry or the second surface 102 circuitry, thereby electrically connecting the memory controller 300 and the test pad 210.

[0117] See also Figure 3In this embodiment of the present disclosure, the memory controller 300 includes a processor 310 and a first memory 320. The processor 310 and the first memory 320 are integrated inside the memory controller 300 chip and can be considered as a processor module and a storage module inside the memory controller 300.

[0118] The first memory 320 is a memory whose data is not lost after power failure, i.e., a non-volatile memory. In this embodiment, the first memory 320 can be a read-only memory (ROM), which may include a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), etc. The first memory 320 stores second boot data. The second boot data may include ROM code and bootloader code.

[0119] As described above, when the memory controller 300 is powered on, the processor 310 first retrieves the ROM code from the internal first memory 320 (e.g., read-only memory) to run the ROM program. The ROM program then searches for the bootloader file in the first memory 320 to run the bootloader program to complete the initialization. In other words, the memory controller 300 can only complete the device initialization after loading and executing the ROM code and the bootloader.

[0120] If the processor 310 fails to obtain the second boot data, it will obtain the first boot data stored in the external boot data storage device through the test interface 200, and perform an initialization operation on the storage device based on the first boot data.

[0121] In some embodiments, the processor 310 may fail to acquire the second boot data due to: a corrupted internal ROM program or a corrupted bootloader, ultimately preventing the initialization operation from being completed. The cause of a corrupted ROM program or bootloader may be an error in the ROM code or the bootloader itself, or physical damage to the first memory 320, preventing the ROM code and / or bootloader file from being retrieved.

[0122] In some embodiments, the first boot data and the second boot data can be the same. That is, the first boot data also includes read-only memory program code (ROM code) and bootloader code. Regardless of the reason why the processor 310 fails to obtain the second boot data, the processor 310 can obtain the ROM code and / or bootloader from an external boot data storage device as needed to complete the initialization.

[0123] For example, if the ROM program inside the memory controller 300 is corrupted, preventing initialization from being completed, the processor 310 retrieves the ROM code from the boot data storage device and runs the ROM program. The ROM program retrieves the bootloader from the first memory 320. Alternatively, the processor 310 can also retrieve the ROM code and bootloader from the boot data storage device to complete the initialization. This simplifies the code writing, improves initialization efficiency, and avoids the need to access the external boot data storage device again if the bootloader program inside the memory controller 300 also malfunctions.

[0124] As another example, if the bootloader inside the memory controller 300 is damaged, making initialization impossible, the ROM program can obtain the bootloader from the boot data storage device to complete the initialization.

[0125] For example, regardless of the reason why the processor 310 fails to acquire the second boot data, the processor 310 acquires the ROM code and bootloader from the external boot data storage device to complete the initialization.

[0126] In other embodiments, the first boot data may differ from the second boot data. It should be understood that, in some examples, after the processor 200 fails to acquire the second boot data, it will output a boot data loading failure signal through the input / output connector 500. The boot data loading failure signal can be presented in code form on the host computer's display screen. Therefore, by analyzing the boot data loading failure signal, the reason for the processor's failure to acquire the second boot data can be determined, allowing for targeted solutions such as burning ROM code or a bootloader into the external boot data storage device. For example, the first boot data may only include a bootloader, used when the ROM program runs normally but the bootloader file cannot be retrieved from the first memory 320, or when the retrieved bootloader file is corrupted and cannot run the bootloader program.

[0127] In some embodiments, the second boot data may only include read-only memory (ROM) code, while the bootloader code may be stored in non-volatile memory 410. Correspondingly, the first boot data may include ROM code. Alternatively, the first boot data may also include both ROM code and bootloader; that is, after the processor obtains the ROM code from an external boot data storage device to run the ROM program, the ROM program may obtain the bootloader file from non-volatile memory 410 or the boot data storage device to complete initialization.

[0128] In summary, during the testing process, if the memory controller 300 fails to complete initialization due to an internal fault, an external boot data storage device is activated. The boot data storage device is connected to the test interface to provide the memory controller 300 with the first boot data to help the memory controller 300 complete initialization.

[0129] The storage device provided in this embodiment uses a test interface 200 to replace the reserved positions for external storage devices and related components on the main circuit board 100. Compared with the device pads of external storage devices and related components, the test interface 200 has more flexible positioning and routing, and the test interface 200 occupies a smaller area on the main circuit board. These characteristics are conducive to reducing the size of the main circuit board 100, thereby facilitating device miniaturization and reducing layout difficulty, thus shortening the design cycle.

[0130] Furthermore, by placing the external storage devices and related components outside the storage device and electrically connecting them to the memory controller 300 via the test interface 200, it is unnecessary to mount the external storage devices and related components onto the storage device, thereby shortening the testing cycle. Especially when multiple storage devices fail to initialize during testing, these storage devices can connect to the same boot data storage device to obtain the first boot data, without having to mount and write the first boot data to each storage device individually. In other words, once the first boot data is written to the external storage device, it can be applied to multiple storage devices, eliminating the need to repeatedly mount and write the first boot data to the faulty storage device, thus greatly simplifying the debugging process and improving product debugging efficiency.

[0131] In some embodiments, the processor 310 of the memory controller 300 is configured to:

[0132] When the acquisition of the second boot data fails, the external storage device that provides the first boot data is enabled based on the selection signal, and a boot data request signal is generated, and the first boot data provided by the external storage device in response to the boot data request signal is received;

[0133] Test interface 200 is also used to output selection signals and start data request signals.

[0134] The selection signal is also known as the chip select enable signal. The memory controller 300 includes multiple chip select pins, which can lead out multiple chip select enable signal lines to connect to multiple chips. The chip select enable signal is typically controlled by the master device (here, the memory controller 300). For example, the chip select enable signal is active low. When the memory controller 300 accesses a chip, it pulls the level of the chip select pin connected to that chip low to select the chip.

[0135] In this embodiment, as Figure 5 As shown, a chip select pin SPI CS (Serial Peripheral Interface Chip Select) of the memory controller 300 is connected to the test interface 200. When the processor 310 fails to acquire the second boot data, the memory controller 300 changes the level of the chip select pin SPI CS from high to low, that is, changes the selection signal from high level to low level, in order to select the external boot data storage device, that is, to enable the boot data storage device.

[0136] The memory controller 300 also includes a Master Output Slave Input (MOSI) pin, connected to the test interface. The MOSI pin (also referred to herein as the signal output pin) is used by the master device to send signals or data to the slave device. In this embodiment, the memory controller 300 sends a startup data request signal to the startup data storage device via the MOSI pin and the test interface 200, requesting to obtain the first startup data.

[0137] The memory controller 300 also includes a Master Input Slave Output (MISO) pin, connected to the test interface. The MISO pin (also referred to herein as the signal input pin) is used by the master device to receive data sent by the slave device. Upon receiving a boot data request signal from the memory controller 300, the external boot data storage device provides first boot data in response to the boot data request signal. This first boot data is sent to the memory controller 300 via the test interface 200 and the MISO pin.

[0138] In some embodiments, the memory controller 300 is further configured to:

[0139] The clock signal is output through the test interface 200, and the first start-up data is sampled based on the clock signal;

[0140] The test interface 200 provides power and ground voltage to the external storage device.

[0141] The clock signal is generated by the memory controller 300 and used to synchronize the timing of data transmission. Correspondingly, the memory controller also includes a clock pin SPI CLK, connected to a test interface. The memory controller sends a clock signal to the external boot data storage device via the clock pin and the test interface 200 to control the timing of data transmission.

[0142] When communication between the memory controller 300 and the external boot data storage device begins, the memory controller 300 pulls the select signal of the connection test interface 200 low to enable the boot data storage device. Then, the memory controller 300 sends a clock signal to the boot data storage device via the SPI CLK clock pin and a boot data request signal via the MOSI pin. Upon receiving the boot data request signal, the boot data storage device sends the first boot data to the memory controller 300 via the MISO pin, based on the clock signal sent by the memory controller 300. After communication ends, the memory controller 300 pulls the select signal high from low to release the external boot data storage device.

[0143] In some embodiments, the external boot data storage device is powered by the memory controller 300 during communication with the memory controller 300. Correspondingly, the memory controller 300 also includes a power supply pin (SPI VCC) and a ground pin (GND), both connected to the test interface 200. During communication between the memory controller 300 and the boot data storage device, the memory controller 300 provides power to the boot data storage device via the power supply pin (SPI VCC) and the test interface 200, and provides a reference ground to the boot data storage device via the ground pin (GND) and the test interface 200, enabling the boot data storage device to operate.

[0144] It should be understood that in other embodiments, power and reference ground may also be provided to the boot data storage device by other means. For example, power and reference ground may be provided to the boot data storage device by a test device, such as a host computer. Alternatively, the boot data storage device may be equipped with a power module for separate power supply.

[0145] As described above, the test interface 200 may include multiple test pads 210. Multiple pins of the memory controller 300 may be connected one-to-one with the multiple test pads 210 to output selection signals, start data request signals, clock signals, power supply voltages and ground voltages, and to receive first start data.

[0146] In some embodiments, such as Figure 5As shown, corresponding to the signal interaction between the memory controller 300 and the external startup data storage device, the test interface 200 may include:

[0147] The first test pad 211 is connected to the power supply pin SPI VCC of the memory controller for outputting the power supply voltage;

[0148] The second test pad 212 is connected to the ground pin GND of the memory controller and is used to output ground voltage;

[0149] The third test pad 213 is connected to the chip select signal pin SPI CS of the memory controller and is used to output the select signal;

[0150] The fourth test pad 214 is connected to the clock pin SPI CLK of the memory controller for outputting a clock signal;

[0151] The fifth test pad 215 is connected to the MOSI pin of the memory controller and is used to output the startup data request signal;

[0152] The sixth test pad 216 is connected to the MISO pin of the memory controller to receive the first boot data.

[0153] Here, the first test pad 211, the second test pad 212, the third test pad 213, the fourth test pad 214, the fifth test pad 215, and the sixth test pad 216 all belong to test pad 210. This disclosure does not limit the arrangement of the above six test pads. For example, as shown... Figure 2 As shown, the six test pads can be arranged in a 2×3 array. Alternatively, they can be arranged in a 3×2 array. They can also be arranged in a row or a column. The six test pads can be arranged in any configuration according to layout and routing requirements.

[0154] In some embodiments, see continue to see Figure 4 The memory controller 300 also includes a second memory 330, which is connected to the test interface 200 and the processor 310. The second memory 330 is configured to receive and store at least a portion of the first startup data.

[0155] For example, the second memory 330 may be a random access memory (RAM), and the second memory 330 may be defined as a tightly coupled memory (TCM). In some embodiments, the processor 310 directly obtains ROM code from an external boot data storage device to run the ROM program, and the second memory 330 can at least be used to receive and store bootloader code. In some embodiments, the second memory 330 may be configured to receive and store ROM code and bootloader, and the processor 310 obtains first boot data from the second memory 330 to complete initialization.

[0156] In some embodiments, the memory controller 300 is configured to automatically retrieve the first boot data from an external storage device when the memory controller 300 fails to retrieve the second boot data. That is, after failing to retrieve the second boot data, the memory controller 300 will by default prioritize retrieving the first boot data from an external boot data storage device.

[0157] The initialization process of a memory controller 300 is described in detail below with a specific embodiment. Specifically,

[0158] After detecting that the memory controller 300 is powered, the processor 310 reads the ROM code from a fixed address stored in the first memory 320 (read-only memory) to run the ROM program. Next, the ROM program searches for the bootloader file in the first memory 320 and loads it into the second memory 330 (closely coupled memory). The processor 310 runs the ROM program to verify the bootloader file in the second memory 330. Upon successful verification, the processor 310 jumps to and executes the bootloader file, i.e., runs the bootloader program, completing the initialization operation.

[0159] If the ROM program and / or Bootloader program encounter errors that prevent initialization from being completed, the memory controller 300 will send a boot data failure signal to the test device via the input / output connector. It will also, by default, pull the SPI CS chip select pin connected to the test interface 200 low to select the external boot data storage device. Subsequently, the memory controller 300 sends a clock signal to the boot data storage device via the SPI CLK clock pin, simultaneously sending a boot data request signal via the MOSI pin and supplying power to the boot data storage device via the SPI VCC power pin and the GND ground pin. Upon receiving the boot data request signal, the external boot data storage device, based on the clock signal sent by the memory controller 300, sends the first boot data to the memory controller 300 via the MISO pin. This first boot data can be stored in the second memory 330 of the memory controller 300.

[0160] After communication is completed, the memory controller 300 pulls the selection signal high from low level to release the external boot data storage device. The memory controller 300 initializes according to the first boot data in the second memory 330.

[0161] This disclosure also provides a test fixture for testing or debugging the storage device 30. Figure 6 This is a schematic diagram of the structure of a test fixture provided in an embodiment of this disclosure, as shown below. Figure 6 As shown, the test fixture 70 includes: a test substrate 610, and a first conversion interface 630, a second conversion interface 640, and a signal conversion module 620 disposed on the test substrate 610. The signal conversion module 620 is connected to the first conversion interface 630 and the second conversion interface 640 respectively. The first conversion interface 630 is used to connect to a host computer, and the second conversion interface 640 is used to connect to the input / output connector 500 of the storage device. The first conversion interface 630 is different from the second conversion interface 640. The signal conversion module 620 is used to convert the signal of the first conversion interface 630 and the signal of the second conversion interface 640.

[0162] The input / output connectors 500 in the aforementioned storage devices typically conform to the PCIe or SATA protocols, and can be presented in the form of gold fingers. The host computer, however, is usually a computer that uses a USB interface for communication. That is, the input / output connectors 500 in the storage device and the USB interface of the host computer have different interface types and cannot be directly plugged in. Therefore, an interface conversion module and a signal conversion module 620 are needed to achieve the connection and signal transmission between the storage device and the host computer.

[0163] In some embodiments, the first conversion interface 630 may be a USB plug, which is used to insert into the USB interface of the host computer.

[0164] Depending on the interface protocol followed by the storage device, the second conversion interface 640 can be a PCIe interface or a SATA interface, and the specific structure of the PCIe or SATA interface can be a slot. The gold fingers of the storage device can be inserted into the slot of the test fixture.

[0165] In some embodiments, the signal conversion module 620 converts the signals from the first conversion interface 630 and the second conversion interface 640 according to the PCIe protocol (or SATA protocol) and the USB protocol. Furthermore, the test substrate 610 may also be provided with a power conversion module, connected to the first conversion interface 630 and the signal conversion module 620, to increase the power supply voltage required by the storage device. For example, the power conversion module is used to convert the 5V voltage received by the first conversion interface 630 (USB plug) to a 3.3V voltage.

[0166] In this embodiment of the disclosure, the test substrate 610 may be a printed circuit board. The test substrate 610 is provided with metal traces and vias for connecting the first conversion interface 630, the second conversion interface 640, and the signal conversion module 620.

[0167] See also Figure 6 In this embodiment, a startup data storage device 700 and a test connector 800 are further provided on the test fixture 70. Specifically, the test fixture also includes:

[0168] A startup data storage device 700 is installed on the test substrate 610, and the startup data storage device 700 stores the first startup data.

[0169] A test connector 800 is disposed on the test substrate 610 and connected to the startup data storage device 700. The test connector 800 is used to make contact with the test interface 200 on the aforementioned storage device.

[0170] The boot data storage device 700 includes non-volatile memory. The non-volatile memory can be a read-only memory (ROM), which may include a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The non-volatile memory can also be NAND flash memory, phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), etc. In this embodiment, the boot data storage device 700 includes an EEPROM. Furthermore, the boot data storage device 700 may also include some related components that enable the EEPROM to function properly.

[0171] The boot data storage device 700 stores first boot data. As shown above, the first boot data may include read-only memory program code (ROM code) and bootloader code. It should be understood that in actual use, the first boot data can be burned into the boot data storage device 700 according to the failure of the storage device or as needed.

[0172] A test connector 800 is disposed on the test substrate 610 and connected to the startup data storage device 700. The test connector 800 is disposed corresponding to the test interface 200 on the storage device, and the test connector 800 is used to make physical contact with the test interface 200.

[0173] In some embodiments, when the test interface 200 includes a plurality of test pads 210, the test connector 800 may include a plurality of pins 810. The number of pins is equal to the number of test pads. The arrangement of the plurality of pins and the spacing between adjacent pins are equal to the arrangement of the plurality of test pads and the spacing between adjacent test pads, so that each pin can contact and connect with one test pad.

[0174] In one embodiment of this disclosure, the test interface 200 includes six test pads 210 (211 to 216), and correspondingly, the test connector 800 may include six pins 810, each pin 810 being connected to a test pad 210. For example, as... Figure 7 As shown, the test connector 800 includes:

[0175] The first pin 811 is connected to the power supply pin SPI VCC' of the EEPROM 710. The first pin is used to make contact with the first test pad 211. The power supply pin SPI VCC' of the EEPROM is used to receive the power supply voltage provided by the memory controller.

[0176] The second pin 812 is connected to the ground pin GND' of the EEPROM. The second pin is used to make contact with the second test pad 212. The ground pin GND' of the EEPROM is used to receive the ground voltage provided by the memory controller.

[0177] The third pin 813 is connected to the chip select signal pin SPI CS' of the EEPROM. The third pin is used to make contact with the third test pad 213. The chip select signal pin SPI CS' of the EEPROM is used to receive the selection signal from the memory controller.

[0178] The fourth pin 814 is connected to the EEPROM clock pin SPI CK'. The fourth pin is used to make contact with the fourth test pad 214. The EEPROM clock pin SPI CK' is used to receive the clock signal provided by the memory controller.

[0179] The fifth pin 815 is connected to the signal input pin MISO' of the EEPROM. The fifth pin is used to make contact with the fifth test pad 215. The signal input pin MISO' of the EEPROM is used to receive the start data request signal provided by the memory controller.

[0180] The sixth pin 816 is connected to the signal output pin MOSI' of the EEPROM. The sixth pin is used to make contact with the sixth test pad 216. The signal output pin MOSI' of the EEPROM is used to output the first start data to the memory controller.

[0181] Here, the first ejector pin 811, the second ejector pin 812, the third ejector pin 813, the fourth ejector pin 814, the fifth ejector pin 815, and the sixth ejector pin 816 all belong to ejector pin 810. For example, ejector pin 810 can be a spring ejector pin, so that the ejector pin can abut against the test pad, thereby improving the reliability of the connection between the ejector pin and the test pad.

[0182] For example, the ejector pin 810 is soldered onto the test substrate 610. For instance, the ejector pin 810 can be mounted onto the test substrate 610 using SMT (Surface Mount Technology) or soldered onto the test substrate 610 using a wave soldering process.

[0183] It should be understood that when the test interface 200 on the storage device is a connector, the test connector 800 on the test fixture should be a connector that matches the connector.

[0184] During the testing process (e.g., the card activation process), when the input / output connector 500 of the storage device is inserted into the second adapter interface 640 on the test fixture, the test connector 800 on the test fixture makes physical contact with the test interface 200 of the storage device, thus establishing a connection between the memory controller 300 and the boot data storage device 700. After the test begins, the host computer supplies power to the memory controller 300, and the memory controller 300 begins acquiring internal second boot data for initialization. If the memory controller 300 fails to acquire the second boot data, it supplies power to the boot data storage device 700 via the link between the test interface 200 and the test connector 800, and sends a selection signal, a boot data request signal, and a clock signal to acquire first boot data from the boot data storage device 700, and performs initialization based on the first boot data. After the storage device completes initialization, the test device (e.g., the card activation device) flashes firmware to the storage device through the host computer to complete the card activation of the storage device.

[0185] In some embodiments, if the memory controller 300 fails to acquire the second boot data, the memory controller will by default prioritize acquiring the first boot data from the boot data storage device 700. That is, the memory controller can choose the boot data storage device 700 and acquire the first boot data on its own, without waiting for instructions.

[0186] In some embodiments, when the memory controller 300 fails to acquire the second boot data, it also sends a boot data loading failure signal to the host computer via the input / output connector 500. The boot data loading failure signal can be presented in code form, illustrating the process of the memory controller failing to acquire the second boot data. Based on the boot data loading failure signal displayed on the host computer screen, testers can determine the reason why the memory controller 300 cannot initialize the device.

[0187] For example, while the memory controller 300 sends a second startup data loading failure signal to the host computer, it can automatically retrieve the first startup data from the startup data storage device 700 for initialization. The advantage of this setup is that it does not interrupt the storage device initialization process, thus accelerating testing efficiency.

[0188] In other embodiments, the memory controller 300 is not allowed to retrieve the first startup data from the startup data storage device 700 on its own. For example, after the memory controller 300 sends a startup data loading failure signal to the host computer, the host computer needs to control or manually control the memory controller 300 to retrieve the first startup data from the startup data storage device. This setting allows for targeted provision of the first startup data after the cause of the memory controller 300's failure is clearly identified.

[0189] In some embodiments, the host computer can send instructions to the memory controller 300 via software, instructing the memory controller 300 to retrieve the first boot data from the boot data storage device.

[0190] In some embodiments, a switch 720 is provided between the test connector 800 and the storage device; when the host computer receives a startup data loading failure signal output by the storage device, the switch 720 is closed to enable the startup data storage device 700. The memory controller can then retrieve the first startup data from the startup data storage device 700. For example, the switch 720 can be closed manually or controlled by the host computer. For example, the switch 720 can be located between any pin of the startup data storage device 700 and a pin 810. For instance, the switch 720 can be located between the EEPROM's power supply pin SPIVCC' and the first pin, or the switch 720 can be located between the EEPROM's signal input pin MISO' and the fifth pin.

[0191] In some embodiments, if the memory controller 300 fails to acquire the second boot data, after the memory controller 300 completes initialization based on the first boot data (i.e., after the storage device 30 starts), it can also rewrite the ROM code and / or bootloader into the first memory 320 based on the fault information of the second boot data displayed by the boot data loading failure signal. This ensures that if the storage device needs to be re-initialized later (including after leaving the factory), it can be initialized based on the second boot data in the memory controller 300. For example, the first memory 320 may include a PROM, EPROM, or EEPROM.

[0192] In this embodiment, a startup data storage device and a test connector are provided on the test fixture. After writing the first startup data to the startup data storage device once, it can be applied to multiple storage devices, which can greatly improve testing efficiency. Moreover, test interfaces can be reserved in the same location on different models of storage devices, so the test fixture can be applied to more storage devices. That is, the test interfaces of different products can be set in the same coordinate position, so multiple projects can share a set of test fixtures, reducing testing costs.

[0193] It should be understood that in some embodiments, a startup data storage device and a test connector can be added to the existing test fixture (such as a card opening fixture) to complete the storage device initialization and card opening using a single test fixture. For example, the test fixture provided in this disclosure is a card opening fixture, and the card opening device includes a host computer and the card opening fixture, which is connected to the host computer and the storage device. In this embodiment, after powering on the storage device, the storage device is first initialized. After initialization, the host computer is used to burn the firmware (FW) program required for the solid-state drive to run on the storage device, thus completing the card opening of the storage device.

[0194] In other embodiments, a test fixture may also be provided to install the boot data storage device and the test connector, so that when the memory controller fails to initialize due to failure to acquire the second boot data, the test fixture can be used to perform initialization.

[0195] This disclosure also provides a testing system. Figure 8 A schematic diagram of the test system provided in the embodiments of this disclosure, such as... Figure 8 As shown, the testing system 80 includes: a test fixture 70 and a storage device 30;

[0196] The test fixture 70 includes a startup data storage device 700 and a test connector 800 disposed on the test substrate 610. The startup data storage device 700 stores first startup data, and the test connector 800 is connected to the startup data storage device 700.

[0197] The storage device 30 includes a main circuit board and a memory controller 300. The main circuit board includes a test interface 200. The memory controller 300 is disposed on the main circuit board and connected to the test interface 200. The storage device 30 is mounted on the test fixture 70, and the test interface 200 and the test connector 800 are in contact connection.

[0198] Furthermore, the testing system 90 also includes a host computer 900, and the host computer 900 and the testing fixture 70 belong to the testing equipment. In this embodiment, the testing equipment can be a card opening device, the host computer 900 is also used to burn firmware to the storage device 30, and the testing fixture 70 is a card opening fixture.

[0199] See also Figure 8 The test fixture 70 further includes a first conversion interface 630 and a second conversion interface 640, both connected to the signal conversion module 620. The first conversion interface 630 is connected to the host computer 900 and can communicate using the USB protocol. The second conversion interface 640 is connected to the input / output connector 500 on the storage device 30 and can communicate using the PCIe or SATA protocol. For example, firmware program code output by the host computer 900 is sent to the storage device 30 via the first conversion interface 630, the signal conversion module 620, and the second conversion interface 640.

[0200] Furthermore, the memory controller 300 includes a first memory and a processor connected to the first memory, wherein the first memory stores second boot data, and the processor is configured to: acquire the second boot data in the first memory; when acquiring the second boot data fails, acquire the first boot data in the boot data storage device 700 via the test interface 200 and the test connector 800; and perform an initialization operation on the storage device 30 according to the first boot data.

[0201] For example, the memory controller 300 is configured to: when acquiring second startup data fails, select the startup data storage device 700 in the test fixture based on a selection signal and supply power to the startup data storage device 700; then, send a clock signal and a startup data request signal to the startup data storage device 700; subsequently, sample the first startup data provided by the startup data storage device 700 in response to the startup data request signal based on the clock signal; finally, perform an initialization operation on the memory controller 300 according to the first startup data.

[0202] In some embodiments, the test interface 200 may include a plurality of test pads, and the memory controller 300 is connected to each test pad;

[0203] The test connector 800 includes a plurality of pins, each pin being connected to the boot data storage device 700 and each pin being contacted with a test pad to form a conductive line between the memory controller 300 and the boot data storage device 700.

[0204] The connection relationships between the multiple test pads and the pins of the memory controller 300, as well as the connection relationships between the multiple ejector pins and the test pads and the pins of the start data storage device 700, can be found above and will not be repeated here.

[0205] In the testing system provided in this embodiment, a startup data storage device providing the first startup data is mounted on a test fixture. When the memory controller in the storage device fails to complete system initialization due to a failure to acquire its internal second startup data, the startup data storage device on the test fixture is activated to provide the first startup data to the memory controller. In this embodiment, a test interface replaces the installation location reserved for external storage devices and related components on the storage device. Firstly, it has virtually no impact on the layout of other devices on the storage device. Secondly, the test interface has a smaller footprint and more flexible wiring, simplifying the design of the main circuit board and facilitating device miniaturization. Furthermore, when initialization problems occur, there is no need to manually solder external storage devices and related components, nor is it necessary to burn the first startup data into the external storage device, greatly improving debugging efficiency. Moreover, different models of storage devices can have test interfaces reserved in the same location, allowing for the unified fabrication of test fixtures. That is, several test fixtures 70 can be deployed at once, and each project can use the same test fixture, saving testing costs.

[0206] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The above description is only a specific implementation of this disclosure, but the protection scope of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure.

Claims

1. A storage device, characterized in that, include: The main circuit board includes a test interface for receiving first startup data. A memory controller is mounted on the main circuit board and connected to the test interface; The memory controller stores the second startup data; The memory controller is configured to: acquire the second boot data; acquire the first boot data through the test interface when acquiring the second boot data fails; and perform an initialization operation on the storage device based on the first boot data.

2. The storage device according to claim 1, characterized in that, The memory controller is configured to: When the acquisition of the second startup data fails, the external storage device that provides the first startup data is enabled based on the selection signal, and a startup data request signal is generated, and the first startup data provided by the external storage device in response to the startup data request signal is received; The test interface is also used to output the selection signal and the start data request signal.

3. The storage device according to claim 2, characterized in that, The memory controller is configured to: A clock signal is output through the test interface, and the first startup data is sampled based on the clock signal; The external storage device is supplied with power and ground voltage through the test interface.

4. The storage device according to claim 3, characterized in that, The test interface includes multiple test pads; The memory controller is connected to the plurality of test pads to output the selection signal, the startup data request signal, the clock signal, the power supply voltage, and the ground voltage through the plurality of test pads, and to receive the first startup data.

5. The storage device according to claim 4, characterized in that, The test interface includes: The first test pad is connected to the power supply pin of the memory controller to output the power supply voltage; The second test pad is connected to the ground pin of the memory controller and is used to output the ground voltage; The third test pad is connected to the chip select signal pin of the memory controller and is used to output the selection signal; The fourth test pad is connected to the clock pin of the memory controller and is used to output the clock signal; The fifth test pad is connected to the signal output pin of the memory controller and is used to output the startup data request signal; The sixth test pad is connected to the signal input pin of the memory controller and is used to receive the first startup data.

6. The storage device according to claim 1, characterized in that, The first boot data includes read-only memory program code and bootloader code; The memory controller is configured to: run a read-only memory program based on read-only memory program code, verify the bootloader code using the read-only memory program, and run the bootloader based on the verified bootloader code to complete the initialization operation.

7. The storage device according to claim 1, characterized in that, The memory controller is also configured to: After power-on, acquire the second startup data; When the second startup data is successfully acquired, an initialization operation is performed on the storage device based on the second startup data.

8. The storage device according to claim 1, characterized in that, The main circuit board includes a first side and a second side disposed opposite to each other, and the memory controller is disposed on the first side of the main circuit board; The test interface is located on the first or second side of the main circuit board.

9. The storage device according to claim 8, characterized in that, The storage device further includes: an input / output connector disposed at one end of the main circuit board, and the test interface located between the memory controller and the input / output connector; The storage device also includes: A non-volatile memory is disposed on the first side of the main circuit board and located on the side of the memory controller away from the input / output connector.

10. The storage device according to claim 9, characterized in that, The memory controller is configured to output a startup data loading failure signal through the input / output connector when the acquisition of the second startup data fails.

11. A test fixture, characterized in that, include: Test substrate; A startup data storage device is installed on the test substrate, and the startup data storage device stores first startup data. The startup data storage device is configured to: provide the first startup data to the storage device in response to a startup data request signal; wherein the startup data request signal is issued by the storage device after it fails to obtain the second startup data stored therein; A test connector is disposed on the test substrate and connected to the startup data storage device. The test connector is used to make contact with the test interface on the storage device.

12. The test fixture according to claim 11, characterized in that, The startup data storage device includes a read-only memory, which stores the first startup data.

13. The test fixture according to claim 11, characterized in that, The test connector includes a plurality of pins, each pin being used to make contact with a test pad in the test interface.

14. The test fixture according to claim 11, characterized in that, The test fixture also includes: A signal conversion module is disposed on the test substrate; The first conversion interface is connected to the signal conversion module; The second conversion interface is connected to the signal conversion module. The second conversion interface is used to connect to the input / output connector of the storage device. The second conversion interface is different from the first conversion interface.

15. The test fixture according to claim 14, characterized in that, A switch is provided between the test connector and the startup data storage device; After the storage device outputs a startup data loading failure signal, the switch is closed to enable the startup data storage device.

16. A testing system, characterized in that, include: Test fixtures and storage devices; The test fixture includes: a startup data storage device and a test connector disposed on a test substrate, wherein the startup data storage device stores first startup data and the test connector is connected to the startup data storage device; The storage device includes a main circuit board and a memory controller. The main circuit board includes a test interface. The memory controller is disposed on the main circuit board and connected to the test interface. The storage device is mounted on the test fixture, and the test interface and the test connector are in contact connection. The memory controller stores second startup data; the memory controller is configured to: acquire the second startup data, and when acquiring the second startup data fails, acquire the first startup data in the startup data storage device; and perform an initialization operation on the storage device according to the first startup data.

17. The testing system according to claim 16, characterized in that, The memory controller is configured to: When acquiring the second startup data fails, the startup data storage device is enabled based on a selection signal, a startup data request signal is sent to the startup data storage device, and the first startup data provided by the startup data storage device in response to the startup data request signal is received.

18. The testing system according to claim 17, characterized in that, The test interface includes multiple test pads, and the memory controller is connected to the multiple test pads. The test connector includes a plurality of pins, the start-up data storage device is connected to the plurality of pins, and each pin is in contact with a test pad.

19. The testing system according to claim 18, characterized in that, The test interface includes: The first test pad is connected to the power pin of the memory controller and is used to supply power voltage to the boot data storage device; The second test pad is connected to the ground pin of the memory controller and is used to supply ground voltage to the startup data storage device; The third test pad is connected to the chip select signal pin of the memory controller and is used to output the selection signal to the startup data storage device; The fourth test pad is connected to the clock pin of the memory controller and is used to provide a clock signal to the startup data storage device; The fifth test pad is connected to the signal output pin of the memory controller and is used to output the startup data request signal to the startup data storage device. The sixth test pad is connected to the signal input pin of the memory controller and is used to receive the first startup data from the startup data storage device.

Images