Packaging Method and System for Memory Chips Based on Wire Bonding

Abstract

The present invention relates to the technical field of chip packaging, and discloses a packaging method and system for a storage chip based on wire bonding, including: performing front-end processing on the storage chip to obtain a target storage chip; evaluating the expected application performance corresponding to the target storage chip, calculating the bond matching coefficient between the target storage chip and the wire bonding material, and screening out the corresponding optimal bonding material from the wire bonding materials; collecting the initial chip image corresponding to the target storage chip, identifying the wire bonding origin, wire bonding end point and intermediate solder joints in the chip solder joints, and calculating the circularity of the intermediate solder joints; determining the optimal solder joints from the intermediate solder joints, planning the wire bonding path corresponding to the target storage chip, and analyzing the physical characterization attributes corresponding to each solder joint in the optimal solder joints; performing bond packaging processing on the target storage chip to obtain a packaged storage chip. The main purpose of the present invention is to solve the problem of reduced packaging quality of the storage chip.

Description

Technical Field

[0001] The present invention relates to a packaging method and system for a storage chip based on wire bonding, belonging to the technical field of chip packaging. Background Art

[0002] In the current era of the rapid development of the electronic information industry, as the core storage component of various electronic devices, the market demand for storage chips has shown an explosive growth trend. In order to meet the growing market demand and ensure the high performance and high reliability of storage chips, the packaging technology of storage chips has become one of the key links.

[0003] In the traditional packaging process of storage chips, first, the wafer needs to be cut to obtain individual storage chips. Subsequently, the chips are placed on a specific lead frame or substrate, and then wire bonding operations are carried out. In the wire bonding process, mainly relying on the operator's past experience to determine some basic bonding parameters, such as bonding temperature, bonding pressure, and bonding time, etc. After that, a professional wire bonding device is used to connect the metal wires to the pads of the chip and the pins on the lead frame or substrate according to the established parameters. After the bonding is completed, encapsulation treatment is carried out to protect the chip and the wires, and finally, the final packaged product is obtained through trimming and forming. However, this traditional packaging method relies on experience to determine the bonding parameters, lacking accurate quantitative analysis and optimization mechanisms, resulting in difficulty in quickly and accurately adjusting the bonding parameters for different types and specifications of storage chips, and thus reducing the packaging quality of storage chips. Therefore, a method capable of improving the packaging quality of storage chips is needed. Summary of the Invention

[0004] The present invention provides a packaging method and system for a storage chip based on wire bonding, and its main purpose is to solve the problem of reduced packaging quality of storage chips.

[0005] To achieve the above object, a packaging method for a storage chip based on wire bonding provided by the present invention includes:

[0006] Obtain the storage chip to be processed and its corresponding chip specification data, and combine the chip specification data and a preset specification threshold to perform front-end processing on the storage chip to obtain a target storage chip;

[0007] Query the chip application scenario and wire bonding material corresponding to the target storage chip, evaluate the expected application performance corresponding to the target storage chip according to the chip application scenario, calculate the bonding matching coefficient between the target storage chip and the wire bonding material based on the expected application performance, and screen out the corresponding optimal bonding material from the wire bonding materials based on the bonding matching coefficient;

[0008] Collect the initial chip image corresponding to the target storage chip, mark the chip solder joints in the initial chip image, identify the wire bonding origin, wire bonding end point and intermediate solder joints in the chip solder joints according to the preset bonding requirements, and calculate the circularity of the solder joints corresponding to the intermediate solder joints based on the initial chip image;

[0009] Determine the optimal solder joints from the intermediate solder joints according to the circularity of the solder joints, combine the wire bonding origin, the wire bonding end point and the optimal solder joints to plan the wire bonding path corresponding to the target storage chip, analyze the physical characterization attributes corresponding to each solder joint in the optimal solder joints according to the initial chip image, and set the bonding process parameters corresponding to the target storage chip based on the physical characterization attributes;

[0010] Combine the wire bonding path, the most suitable bonding material and the bonding process parameters to perform the bonding and packaging process on the target storage chip to obtain a packaged storage chip.

[0011] Optionally, the front-end processing of the storage chip by combining the chip specification data and the preset specification threshold to obtain the target storage chip includes:

[0012] Identify the specification indicators corresponding to the specification threshold, and perform data filtering processing on the chip specification data based on the specification indicators to obtain filtered specification data;

[0013] Perform data calibration processing on the filtered specification data to obtain calibrated specification data;

[0014] Perform standardization processing on the calibrated specification data to obtain standard specification data;

[0015] Combine the standard specification data and the specification threshold to calculate the chip yield rate corresponding to the storage chip;

[0016] Perform front-end processing on the storage chip according to the chip yield rate to obtain the target storage chip.

[0017] Optionally, the calculation of the chip yield rate corresponding to the storage chip by combining the standard specification data and the specification threshold includes:

[0018] Read the specification reference value in the standard specification data and calculate the specification weight corresponding to the specification reference value;

[0019] Combine the specification reference value, the specification threshold and the specification weight, and the chip yield rate corresponding to the storage chip can be calculated by the following formula:

[0020]

[0021] Among them, A represents the chip yield rate corresponding to the storage chip, and B a represents the a-th reference value in the specification reference values, a represents the serial number of the specification reference values, Q represents the number of specification reference values, and B , a represents the specification threshold corresponding to the a-th reference value in the specification reference values, and D a represents the specification weight corresponding to the a-th reference value in the specification reference values.

[0022] Optionally, evaluating the expected application performance corresponding to the target storage chip according to the chip application scenario includes:

[0023] Scheduling the chip load data corresponding to the target storage chip in the chip application scenario;

[0024] Performing label extraction on the chip load data to obtain load labels;

[0025] Calculating the chip load rate corresponding to the load labels based on the chip load data;

[0026] Evaluating the actual application performance corresponding to the target storage chip based on the chip load rate.

[0027] Optionally, calculating the bond matching coefficient between the target storage chip and the wire bonding material based on the expected application performance includes:

[0028] Performing index splitting on the expected application performance to obtain performance indicators, and screening out key performance indicators from the performance indicators;

[0029] Analyzing the index factors corresponding to the key performance indicators and querying the material characteristic attributes corresponding to the wire bonding material;

[0030] Calculating the coupling index between the index factors and the material characteristic attributes;

[0031] Combining the coupling index and the material characteristic attributes to calculate the bond matching coefficient between the target storage chip and the wire bonding material.

[0032] Optionally, calculating the coupling index between the index factors and the material characteristic attributes includes:

[0033] Performing vectorization processing on the index factors and the material characteristic attributes respectively to obtain an index factor vector and a characteristic attribute vector;

[0034] Calculating the means corresponding to the index factors and the material characteristic attributes respectively according to the index factor vector and the characteristic attribute vector to obtain a factor vector mean and an attribute vector mean;

[0035] Combining the index factor vector, the characteristic attribute vector, the mean of the factor vectors, and the mean of the attribute vectors, the coupling index between the index factor and the material characteristic attribute can be calculated by the following formula:

[0036]

[0037] where E represents the coupling index between the index factor and the material characteristic attribute, and F b represents the b-th vector in the index factor vector, represents the mean of the factor vectors, b represents the serial number corresponding to the index factor vector, n represents the number of vectors corresponding to the index factor vector, and H d represents the d-th vector in the characteristic attribute vector, represents the mean of the attribute vectors, d represents the serial number corresponding to the characteristic attribute vector, and m represents the number of vectors corresponding to the characteristic attribute vector.

[0038] Optionally, calculating the circularity of the solder joint corresponding to the intermediate solder joint based on the initial chip image includes:

[0039] Marking the solder joint image corresponding to the intermediate solder joint from the initial chip image;

[0040] Identifying the solder joint edge pixels in the solder joint image and calculating the pixel distance between the solder joint edge pixels;

[0041] Determining the solder joint perimeter corresponding to the intermediate solder joint based on the pixel distance;

[0042] Counting the number of solder joint pixels corresponding to the intermediate solder joint based on the solder joint image;

[0043] Determining the solder joint area corresponding to the intermediate solder joint based on the number of solder joint pixels;

[0044] Combining the solder joint perimeter and the solder joint area, the circularity of the solder joint corresponding to the intermediate solder joint can be calculated by the following formula:

[0045]

[0046] where γ represents the circularity of the solder joint corresponding to the intermediate solder joint, Se represents the solder joint area corresponding to the e-th solder joint in the intermediate solder joint, e represents the serial number corresponding to the intermediate solder joint, and Ge represents the solder joint perimeter corresponding to the e-th solder joint in the intermediate solder joint.

[0047] Optionally, determining the optimal solder joint from the intermediate solder joints according to the circularity of the solder joint includes:

[0048] Identify the set of candidate solder joints corresponding to each solder joint in the intermediate solder joints, and count the number of solder joints corresponding to the set of candidate solder joints;

[0049] Based on the set of candidate solder joints, calculate the candidate welding travel corresponding to the intermediate solder joint;

[0050] Combining the number of solder joints and the total distance of the solder joints, set the solder joint priority corresponding to the intermediate solder joint;

[0051] Combining the circularity of the solder joint and the solder joint priority, determine the optimal solder joint from the intermediate solder joints.

[0052] Optionally, according to the initial chip image, analyze the physical characterization attributes corresponding to each solder joint in the optimal solder joints, including:

[0053] Extract the image corresponding to the optimal solder joint from the initial chip image to obtain the optimal solder joint image;

[0054] Perform denoising processing on the optimal solder joint image to obtain a denoised solder joint image;

[0055] Perform gray-scale processing on the denoised solder joint image to obtain a gray-scale solder joint image;

[0056] Based on the gray-scale solder joint image, calculate the solder joint gloss corresponding to the optimal solder joint;

[0057] Construct the solder joint gray-level co-occurrence matrix corresponding to the gray-scale solder joint image, and based on the solder joint gray-level co-occurrence matrix, analyze the solder joint texture characterization corresponding to the optimal solder joint;

[0058] Combining the solder joint gloss and the solder joint texture characterization, generate the physical characterization attributes corresponding to each solder joint in the optimal solder joints.

[0059] A packaging system for realizing the packaging of a storage chip based on wire bonding, characterized in that the system includes:

[0060] A chip processing module, configured to obtain a storage chip to be processed and its corresponding chip specification data, and combine the chip specification data and a preset specification threshold to perform front-end processing on the storage chip to obtain a target storage chip;

[0061] A material screening module, configured to query the chip application scenario and wire bonding material corresponding to the target storage chip, evaluate the expected application performance corresponding to the target storage chip according to the chip application scenario, calculate the bond matching coefficient between the target storage chip and the wire bonding material based on the expected application performance, and screen out the corresponding optimal bonding material from the wire bonding materials based on the bond matching coefficient;

[0062] A solder joint roundness calculation module, which is used to collect the initial chip image corresponding to the target storage chip, mark the chip solder joints in the initial chip image, identify the lead bonding origin, lead bonding end point and intermediate solder joints in the chip solder joints according to the preset bonding requirements, and calculate the solder joint roundness corresponding to the intermediate solder joints based on the initial chip image;

[0063] A process parameter setting module, which is used to determine the optimal solder joint from the intermediate solder joints according to the solder joint roundness, plan the lead bonding path corresponding to the target storage chip in combination with the lead bonding origin, the lead bonding end point and the optimal solder joint, analyze the physical characterization attributes corresponding to each solder joint in the optimal solder joint according to the initial chip image, and set the bonding process parameters corresponding to the target storage chip based on the physical characterization attributes;

[0064] A packaging processing module, which is used to perform bonding and packaging processing on the target storage chip in combination with the lead bonding path, the most suitable bonding material and the bonding process parameters to obtain a packaged storage chip.

[0065] Compared with the problems in the background art, the present invention combines the chip specification data and the preset specification threshold to perform front-end processing on the storage chip, can process the chips that do not meet the requirements in the storage chip, improve the chip yield of the storage chip, and provide accuracy for subsequent analysis of the storage chip. The present invention evaluates the expected application performance corresponding to the target storage chip according to the chip application scenario, can understand the performance requirements that the target storage chip needs to achieve during actual use through the expected application performance, and thus lays an important basis for the subsequent calculation of the bonding matching coefficient between the target storage chip and the lead bonding material. The present invention can obtain the visual image of the target storage chip by collecting the initial chip image corresponding to the target storage chip, mark the chip solder joints in the initial chip image, and then accurately obtain the coordinate positions of each solder joint in the initial chip image. Identify the lead bonding origin, lead bonding end point and intermediate solder joints in the chip solder joints according to the preset bonding requirements, which provides convenience for the subsequent calculation of the solder joint roundness corresponding to the intermediate solder joints. The present invention can obtain the most suitable welding point position in the intermediate solder joints by determining the optimal solder joint from the intermediate solder joints according to the solder joint roundness, thereby improving the overall quality and reliability after chip packaging. The present invention can improve the bonding and packaging quality of the target storage chip and enhance the reliability and stability of the target storage chip by performing bonding and packaging processing on the target storage chip in combination with the lead bonding path, the most suitable bonding material and the bonding process parameters. Therefore, the present invention proposes a method and system for packaging a storage chip based on lead bonding to improve the packaging quality of the storage chip. Brief Description of the Drawings

[0066] Figure 1 FIG. 1 is a schematic flow chart of a packaging method for a storage chip implemented based on wire bonding according to an embodiment of the present invention;

[0067] Figure 2 FIG. 2 is a functional module diagram of a packaging system for a storage chip implemented based on wire bonding according to an embodiment of the present invention.

[0068] The implementation, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed Embodiments

[0069] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0070] The embodiments of the present application provide a packaging method for a storage chip implemented based on wire bonding. The execution subject of the packaging method for a storage chip implemented based on wire bonding includes, but is not limited to, at least one of electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiments of the present application. In other words, the packaging method for a storage chip implemented based on wire bonding can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0071] Embodiment 1:

[0072] Referring to Figure 1 FIG. 1, which is a schematic flow chart of a packaging method for a storage chip implemented based on wire bonding according to an embodiment of the present invention. In this embodiment, the packaging method for a storage chip implemented based on wire bonding includes:

[0073] S1. Obtain the storage chip to be processed and its corresponding chip specification data, and perform front-end processing on the storage chip in combination with the chip specification data and a preset specification threshold to obtain a target storage chip.

[0074] The present invention combines the chip specification data and a preset specification threshold to perform front-end processing on the storage chip, which can process the chips in the storage chip that do not meet the requirements, improve the chip yield rate of the storage chip, and provide accuracy for subsequent analysis of the storage chip. It should be noted that the storage chip is a semiconductor device with specific storage functions and circuit structures, the chip specification data is the quantitative characteristic information of the storage chip in terms of physical size, pin layout, storage capacity, operating voltage, read / write speed, etc., and the target storage chip is the chip obtained after processing the chips in the storage chip that do not meet the specification threshold.

[0075] Specifically, the combination of the chip specification data and the preset specification threshold to perform front-end processing on the storage chip to obtain a target storage chip includes:

[0076] Identify the specification indicators corresponding to the specification threshold, and based on the specification indicators, perform data filtering processing on the chip specification data to obtain filtered specification data;

[0077] Perform data calibration processing on the filtered specification data to obtain calibrated specification data;

[0078] Perform standardization processing on the calibrated specification data to obtain standard specification data;

[0079] Combine the standard specification data and the specification threshold to calculate the chip yield rate corresponding to the storage chip;

[0080] According to the chip yield rate, perform front-end processing on the storage chip to obtain a target storage chip.

[0081] It should be noted that the specification indicators are the specification types corresponding to the specification threshold, the filtered specification data is the data obtained after removing the data in the chip specification data that is not relevant to the specification indicators, the calibrated specification data is the data obtained after repairing the data corresponding to the acquisition error in the filtered specification data, the standard specification data is the unified standard specification data of the calibrated specification data, and the chip yield rate represents the proportion of the number of storage chips that meet the production standard conditions.

[0082] Further, the specification indicators corresponding to the specification thresholds can be recognized through OCR recognition technology; the data filtering process of the chip specification data can be implemented through a filtering function, and the filtering function is compiled by a programming language; the data calibration process of the filtered specification data can be implemented through the average value substitution method; the standardization process of the calibrated specification data can be implemented through the Z-score standardization method; when the chip yield rate is lower than the set value, the storage chip is subjected to front-end processing to obtain a target storage chip, and the set value can be set to 80%, or can be set according to the actual application scenario.

[0083] Further, as an alternative embodiment of the present invention, combining the standard specification data and the specification threshold to calculate the chip yield rate corresponding to the storage chip includes:

[0084] Read the specification reference value in the standard specification data and calculate the specification weight corresponding to the specification reference value;

[0085] Combining the specification reference value, the specification threshold and the specification weight, the chip yield rate corresponding to the storage chip can be calculated through the following formula:

[0086]

[0087] where A represents the chip yield rate corresponding to the storage chip, B a represents the a-th reference value in the specification reference value, a represents the serial number of the specification reference value, Q represents the number of specification reference values, B , a represents the specification threshold corresponding to the a-th reference value in the specification reference value, D a represents the specification weight corresponding to the a-th reference value in the specification reference value.

[0088] It should be explained that the specification reference value is the specific value in the standard specification data, and the specification weight represents the importance degree corresponding to the specification reference value. Further, the specification reference value in the standard specification data can be read through a data interface, such as HTTP, TCP, etc.; the calculation of the specification weight corresponding to the specification reference value can be implemented through factor analysis.

[0089] S2. Query the chip application scenario and wire bonding material corresponding to the target storage chip, evaluate the expected application performance corresponding to the target storage chip according to the chip application scenario, (scenario conditions) based on the expected application performance, calculate the bond matching coefficient between the target storage chip and the wire bonding material (performance parameters of the material, material proportion), and based on the bond matching coefficient, screen out the corresponding optimal bonding material from the wire bonding materials.

[0090] According to the chip application scenario of the present invention, the expected application performance corresponding to the target storage chip is evaluated. The performance requirements that the target storage chip needs to achieve during actual use can be understood through the expected application performance, thereby laying an important basis for the subsequent calculation of the bonding matching coefficient between the target storage chip and the wire bonding material. It should be noted that the chip application scenario is the usage environment and conditions corresponding to the target storage chip, including but not limited to the specific devices and systems to which it is applied, as well as the functions it undertakes, the performance requirements it needs to meet, the working temperature range, the power supply conditions, the data transmission rate requirements, the storage capacity requirements, and other various relevant factors in these devices or systems. The expected application performance is a comprehensive description of the various performance indicators and performances that the target storage chip should achieve. Further, the query of the chip application scenario corresponding to the target storage chip and the wire bonding material can be realized through the official website of the packaged chip. Based on the bonding matching coefficient, the corresponding optimal bonding material is selected from the wire bonding materials. For example, the material with the largest bonding matching coefficient is selected as the optimal bonding material because this material has the highest degree of adaptation to the target storage chip in terms of expected application performance.

[0091] Specifically, evaluating the expected application performance corresponding to the target storage chip according to the chip application scenario includes:

[0092] Scheduling the chip load data corresponding to the target storage chip in the chip application scenario;

[0093] Performing label extraction on the chip load data to obtain load labels;

[0094] Based on the chip load data, calculating the chip load rate corresponding to the load label;

[0095] Based on the chip load rate, evaluating the actual application performance corresponding to the target storage chip.

[0096] It should be noted that the chip load data is the historical usage data corresponding to the target storage chip in the chip application scenario. The load label is the load type corresponding to the chip load data, such as read / write speed and operation speed, etc. The chip load rate represents the degree of use corresponding to the load label.

[0097] Further, the chip load data corresponding to the target storage chip in the chip application scenario can be scheduled through the chip data repository, where the chip data repository is a library for storing the usage data of the target storage chip; the label extraction of the chip load data can be realized through a label extraction tool; based on the chip load data, the chip load rate corresponding to the load label can be calculated by the data traffic statistics method, and the calculation formula is: chip load rate = (actual data traffic / rated data traffic) × 100%; based on the chip load rate, the actual application performance corresponding to the target storage chip can be evaluated, and according to the performance characteristics of the chip and the requirements of the application scenario, the chip load rate is divided into different levels, such as low load (0% - 30%), medium load (30% - 70%), high load (70% - 100%), etc., so as to divide the actual application performance of the target storage chip into low load performance, medium load performance, high load performance, etc.

[0098] In the present invention, by calculating the bonding matching coefficient between the target storage chip and the wire bonding material based on the expected application performance, the matching degree between the target storage chip and the wire bonding material can be understood, which further lays a foundation for subsequently screening out the corresponding optimal bonding material from the wire bonding materials. It should be noted that the bonding matching coefficient represents the matching degree between the target storage chip and the wire bonding material.

[0099] Specifically, calculating the bonding matching coefficient between the target storage chip and the wire bonding material based on the expected application performance includes:

[0100] Splitting the indexes of the expected application performance to obtain performance indexes, and screening out the key performance indexes from the performance indexes;

[0101] Analyzing the index factors corresponding to the key performance indexes, and querying the material characteristic attributes corresponding to the wire bonding material;

[0102] Calculating the coupling index between the index factors and the material characteristic attributes;

[0103] Combining the coupling index and the material characteristic attributes, calculating the bonding matching coefficient between the target storage chip and the wire bonding material.

[0104] It should be noted that the performance indicators are specific breakdown manifestations of the expected application performance, such as storage capacity. The key performance indicators are the parts of the performance indicators that play a key role in the overall application. The indicator factors are the specific conditions or elements corresponding to the key performance indicators that affect their achievement, such as external or internal conditions like working temperature and signal frequency that affect the read-write speed. The material characteristic attributes are the inherent nature characteristics of the wire bonding material, such as conductivity, thermal conductivity, mechanical strength, etc., which are the internal traits determining the material performance. The coupling index represents the degree of mutual correlation and mutual influence between the indicator factors and the material characteristic attributes. Further, the breakdown of the indicators of the expected application performance can be achieved through the analytic hierarchy process; the key performance indicators can be screened out from the performance indicators through the principal component analysis method; the analysis of the indicator factors corresponding to the key performance indicators can be achieved through the causal analysis method; the query of the material characteristic attributes corresponding to the wire bonding material can be achieved through the query of the material performance database; multiplying the coupling index and the quantified values corresponding to the material characteristic attributes and summing them up to obtain the key matching coefficient between the target storage chip and the wire bonding material.

[0105] Further, as an optional embodiment of the present invention, calculating the coupling index between the indicator factors and the material characteristic attributes includes:

[0106] Perform vectorization processing on the indicator factors and the material characteristic attributes respectively to obtain an indicator factor vector and a characteristic attribute vector;

[0107] According to the indicator factor vector and the characteristic attribute vector, calculate the means corresponding to the indicator factors and the material characteristic attributes respectively to obtain a factor vector mean and an attribute vector mean;

[0108] Combining the indicator factor vector, the characteristic attribute vector, the factor vector mean, and the attribute vector mean, the coupling index between the indicator factors and the material characteristic attributes can be calculated through the following formula:

[0109]

[0110] where E represents the coupling index between the indicator factors and the material characteristic attributes, F b represents the b-th vector in the indicator factor vector, represents the factor vector mean, b represents the serial number corresponding to the indicator factor vector, n represents the number of vectors corresponding to the indicator factor vector, H d represents the d-th vector in the characteristic attribute vector, represents the attribute vector mean, d represents the serial number corresponding to the characteristic attribute vector, and m represents the number of vectors corresponding to the characteristic attribute vector.

[0111] It should be noted that the index factor vector and the characteristic attribute vector are respectively the expression vectors corresponding to the index factor and the material characteristic attribute; further, the vectorization processing of the index factor and the material characteristic attribute can be realized by the word vector model method; the mean value corresponding to the index factor and the material characteristic attribute can be realized by the average function.

[0112] S3. Collect the initial chip image corresponding to the target storage chip, mark the chip solder joints in the initial chip image, identify the lead bonding origin, lead bonding end point and intermediate solder joints in the chip solder joints according to the preset bonding requirements, and calculate the circularity of the intermediate solder joints based on the initial chip image.

[0113] By collecting the initial chip image corresponding to the target storage chip, the present invention can obtain the visual image of the target storage chip, mark the chip solder joints in the initial chip image, and then accurately obtain the coordinate positions of each solder joint in the initial chip image. According to the preset bonding requirements, the lead bonding origin, lead bonding end point and intermediate solder joints are identified in the chip solder joints, which provides convenience for the subsequent calculation of the circularity of the intermediate solder joints. It should be noted that the initial chip image is the visual image corresponding to the target storage chip, the chip solder joints are the points for welding in the initial chip image, the preset bonding requirements are a series of conditions and standards for the bonding process and bonding effect that are preset in advance according to factors such as specific application scenarios, chip performance requirements, process standards and relevant technical specifications before the bonding operation of components such as chips and leads, the lead bonding origin and the lead bonding end point are the starting and ending welding points in the chip solder joints, and the intermediate solder joints are the solder joints between the lead bonding origin and the lead bonding end point. Further, the collection of the initial chip image corresponding to the target storage chip can be realized by an industrial camera device; the marking of the chip solder joints in the initial chip image can be realized by an X-ray detection device; the lead bonding origin and the lead bonding end point can be identified in the chip solder joints through manual processing.

[0114] Specifically, calculating the circularity of the intermediate solder joints based on the initial chip image includes:

[0115] Mark the solder joint image corresponding to the intermediate solder joint in the initial chip image;

[0116] Identify the solder joint edge pixels in the solder joint image and calculate the pixel distance between the solder joint edge pixels;

[0117] Determine the solder joint perimeter corresponding to the intermediate solder joint based on the pixel distance;

[0118] Based on the solder joint image, count the number of solder joint pixels corresponding to the middle solder joint;

[0119] Based on the number of solder joint pixels, determine the solder joint area corresponding to the middle solder joint;

[0120] Combining the solder joint perimeter and the solder joint area, the circularity of the solder joint corresponding to the middle solder joint can be calculated by the following formula:

[0121]

[0122] Where γ represents the circularity of the solder joint corresponding to the middle solder joint, Se represents the solder joint area corresponding to the e-th solder joint in the middle solder joint, e represents the serial number corresponding to the middle solder joint, and Ge represents the solder joint perimeter corresponding to the e-th solder joint in the middle solder joint.

[0123] It should be explained that the solder joint image is the image corresponding to the middle solder joint in the initial chip image, the solder joint edge pixels are the pixels at the edge position of the middle solder joint in the solder joint image, and the number of solder joint pixels is the number of area pixels corresponding to the middle solder joint. Further, the solder joint edge pixels in the solder joint image can be identified by an edge detection algorithm, such as the Canny edge detection algorithm; the pixel distance between the solder joint edge pixels can be calculated by the Euclidean distance algorithm; the pixel distances are summed to obtain the solder joint perimeter corresponding to the middle solder joint; the number of solder joint pixels in the solder joint image can be counted by image processing software, such as Adobe Photoshop software; the number of solder joint pixels is the solder joint area corresponding to the middle solder joint.

[0124] S4. According to the circularity of the solder joint, determine the optimal solder joint from the middle solder joints, combine the lead bonding origin, the lead bonding end point and the optimal solder joint, plan the lead bonding path corresponding to the target memory chip, analyze the physical characterization attributes corresponding to each solder joint in the optimal solder joint according to the initial chip image, and set the bonding process parameters corresponding to the target memory chip based on the physical characterization attributes.

[0125] In the present invention, by determining the optimal solder joint from the middle solder joints according to the circularity of the solder joint, the most suitable welding point position in the middle solder joints can be obtained, thereby improving the overall quality and reliability after chip packaging. It should be explained that the optimal solder joint is the optimal welding point position in the middle solder joints.

[0126] Specifically, determining the optimal solder joint from the middle solder joints according to the circularity of the solder joint includes:

[0127] Identify the set of candidate solder joints corresponding to each solder joint in the intermediate solder joints, and count the number of solder joints corresponding to the set of candidate solder joints;

[0128] Based on the set of candidate solder joints, calculate the candidate welding travel corresponding to the intermediate solder joints;

[0129] Combine the number of solder joints and the total distance of the solder joints to set the solder joint priority corresponding to the intermediate solder joints;

[0130] Combine the circularity of the solder joints and the solder joint priority to determine the optimal solder joint from the intermediate solder joints.

[0131] It should be explained that the set of candidate solder joints is the set of candidate solder joints corresponding to each solder joint in the intermediate solder joints, the number of solder joints is the total number of candidate solder joints corresponding to the set of candidate solder joints, the candidate welding travel is the sum of the distances from the intermediate solder joints to each point in the set of candidate solder joints, and the solder joint priority indicates the priority level corresponding to the intermediate solder joints.

[0132] Further, the candidate solder joint sets corresponding to each solder joint in the intermediate solder joints can be identified by a method based on circuit connection relationships. By examining the detailed circuit diagram of the chip, other solder joints that have similar functions or are in the same signal path in terms of electrical connection with each intermediate solder joint are determined. These solder joints can form the candidate solder joint sets. For example, in a digital circuit, if an intermediate solder joint is a connection point of a certain data bus, then other solder joints on the same bus can serve as candidate solder joints when this intermediate solder joint fails. Through the analysis of the circuit connection and signal flow in the circuit diagram, this candidate solder joint relationship based on circuit functions can be clearly identified; calculate the distance between the intermediate solder joint and each solder joint in the candidate solder joint set, and sum the distances to obtain the corresponding candidate welding travel; combine the number of solder joints and the total solder joint distance to set the solder joint priority corresponding to the intermediate solder joint. For example, if the number of solder joints of the intermediate solder joint 1 is 4 and the total solder joint distance is 10 meters, the corresponding priority score is 14; if the number of solder joints of the intermediate solder joint 2 is 5 and the total solder joint distance is 12 meters, the corresponding priority score is 17; if the number of solder joints of the intermediate solder joint 3 is 5 and the total solder joint distance is 14 meters, the corresponding priority score is 19. Then the solder joint priorities corresponding to the intermediate solder joint 1, the intermediate solder joint 2, and the intermediate solder joint 3 are low, medium, and high respectively; combine the solder joint roundness and the solder joint priority to determine the optimal solder joint from the intermediate solder joints. For example, for a group of intermediate solder joints, first screen according to the solder joint roundness. The roundness of solder joint A is 0.9, which is relatively close to the ideal circle among these solder joints, initially highlighting its shape advantage. At the same time, its solder joint priority is relatively high. Considering the roundness and priority comprehensively, solder joint A stands out and is determined as the optimal solder joint. It achieves a better balance in terms of shape regularity, functional importance, connection stability, etc., and can provide a better basis for subsequent operations such as wire bonding.

[0133] The present invention plans the wire bonding path corresponding to the target memory chip by combining the wire bonding origin, the wire bonding end point, and the optimal solder joint, thereby providing an accurate, efficient, and reliable connection blueprint and process implementation guidance for subsequent chip packaging; analyzing the physical characterization attributes corresponding to each solder joint in the optimal solder joint can understand the physical state, structure, performance, and other characteristic properties corresponding to the optimal solder joint, thereby improving the setting accuracy of the subsequent wire bonding process parameters for the target memory chip. It should be noted that the wire bonding path is a specific connection trajectory corresponding to the target memory chip that starts from the wire bonding origin, passes through the optimal solder joint, and finally reaches the wire bonding end point. The physical characterization attribute is the physical characteristic property of each solder joint in the optimal solder joint. Further, by combining the wire bonding origin, the wire bonding end point, and the optimal solder joint, the wire bonding path corresponding to the target memory chip can be planned through a path planning algorithm, such as the Dijkstra algorithm.

[0134] Specifically, analyze the physical characterization attributes corresponding to each solder joint in the optimal solder joints according to the initial chip image, including:

[0135] Extract the image corresponding to the optimal solder joint from the initial chip image to obtain the optimal solder joint image;

[0136] Perform denoising processing on the optimal solder joint image to obtain the denoised solder joint image;

[0137] Perform grayscale processing on the denoised solder joint image to obtain the grayscale solder joint image;

[0138] Calculate the solder joint gloss corresponding to the optimal solder joint based on the grayscale solder joint image;

[0139] Construct the solder joint gray-level co-occurrence matrix corresponding to the grayscale solder joint image, and analyze the solder joint texture characterization corresponding to the optimal solder joint based on the solder joint gray-level co-occurrence matrix;

[0140] Combine the solder joint gloss and the solder joint texture characterization to generate the physical characterization attributes corresponding to each solder joint in the optimal solder joints.

[0141] It should be explained that the optimal solder joint image is the image corresponding to the optimal solder joint in the initial chip image, the denoised solder joint image is the image obtained after removing the noise interference in the optimal solder joint image, the grayscale solder joint image is the image expressed only in a single color of the denoised solder joint image, the solder joint gloss represents the smoothness corresponding to the optimal solder joint, the solder joint gray-level co-occurrence matrix is the texture description matrix corresponding to the grayscale solder joint image, and the solder joint texture characterization is the texture characteristic corresponding to the optimal solder joint.

[0142] Furthermore, the image corresponding to the optimal solder joint can be extracted from the initial chip image through a segmentation tool to obtain the optimal solder joint image. The segmentation tool is compiled by a scripting language, such as the JS scripting language. The denoising process of the optimal solder joint image can be achieved through a low-pass filter. The grayscale processing of the denoised solder joint image can be achieved through the average method. The pixel values of the red, green, and blue channels of the color image are added respectively, and then divided by 3. The obtained average value is used as the corresponding grayscale value, and the grayscale value is used to replace the corresponding pixel value to obtain the grayscale solder joint image. Calculate the grayscale standard deviation corresponding to the grayscale solder joint image, and determine the solder joint gloss corresponding to the optimal solder joint according to the grayscale standard deviation. The smaller the grayscale standard deviation, the higher the solder joint gloss. The solder joint gray-level co-occurrence matrix corresponding to the grayscale solder joint image can be constructed through a matrix function, such as the zero matrix function. The characteristic parameters corresponding to the solder joint gray-level co-occurrence matrix can be calculated through corresponding calculation formulas, and the solder joint texture characterization corresponding to the optimal solder joint can be analyzed according to the characteristic parameters, such as characteristic parameters like contrast, energy, and homogeneity.

[0143] In the present invention, by setting the bonding process parameters corresponding to the target storage chip based on the physical characterization attributes, the bonding process can be better adapted to the target storage chip, improving the chip packaging quality and performance. It should be noted that the bonding process parameters are a series of key factors that need to be controlled and adjusted during the wire bonding process of the target storage chip, such as bonding speed and bonding pressure, etc. Further, based on the physical characterization attributes, when setting the bonding process parameters corresponding to the target storage chip, if the solder joint gloss in the physical characterization attributes is high and the texture characterization shows uniform and fine, it indicates good welding quality, and the bonding temperature and pressure can be appropriately reduced to reduce potential damage to the chip while ensuring connection reliability. If the gloss is low and the texture is rough and disorderly, it may be necessary to increase the bonding power and time to promote the full fusion of the bonding material to improve the connection effect and stability.

[0144] S5. Combine the wire bonding path, the most suitable bonding material, and the bonding process parameters to perform the bonding and packaging process on the target storage chip to obtain the packaged storage chip.

[0145] In the present invention, by combining the wire bonding path, the most suitable bonding material, and the bonding process parameters to perform the bonding and packaging process on the target storage chip, the bonding and packaging quality of the target storage chip can be improved, and the reliability and stability of the target storage chip can be enhanced.

[0146] Compared with the problems described in the background art, the present invention combines the chip specification data and preset specification thresholds to perform front-end processing on the storage chip, which can process the chips that do not meet the requirements in the storage chip, improve the chip yield rate of the storage chip, and provide accuracy for subsequent analysis of the storage chip. According to the chip application scenario, the present invention evaluates the expected application performance corresponding to the target storage chip, and can understand the performance requirements that the target storage chip needs to achieve during actual use through the expected application performance, thereby laying an important basis for the subsequent calculation of the bonding matching coefficient between the target storage chip and the wire bonding material. By collecting the initial chip image corresponding to the target storage chip, the present invention can obtain the visual image of the target storage chip, mark the chip solder joints in the initial chip image, and then accurately obtain the coordinate positions of each solder joint in the initial chip image. According to the preset bonding requirements, the wire bonding origin, wire bonding end point, and intermediate solder joints are identified in the chip solder joints, which provides convenience for the subsequent calculation of the circularity of the solder joints corresponding to the intermediate solder joints. By determining the optimal solder joint from the intermediate solder joints according to the circularity of the solder joints, the present invention can obtain the most suitable welding position in the intermediate solder joints, thereby improving the overall quality and reliability after the chip packaging is completed. By combining the wire bonding path, the most suitable bonding material, and the bonding process parameters, the present invention performs bonding and packaging processing on the target storage chip, which can improve the bonding and packaging quality of the target storage chip and enhance the reliability and stability of the target storage chip. Therefore, the present invention proposes a method for packaging a storage chip based on wire bonding to improve the packaging quality of the storage chip.

[0147] Embodiment 2:

[0148] As Figure 2 shown, it is a functional module diagram of a system for packaging a storage chip based on wire bonding provided by an embodiment of the present invention.

[0149] The packaging system 100 for a storage chip based on wire bonding according to the present invention can be installed in an electronic device. According to the functions achieved, the packaging system 100 for a storage chip based on wire bonding can include a chip processing module 101, a material screening module 102, a solder joint circularity calculation module 103, a process parameter setting module 104, and a packaging processing module 105. The modules in the present invention can also be referred to as units, which refer to a series of computer program segments that can be executed by a processor of an electronic device and can complete fixed functions, and are stored in the memory of the electronic device.

[0150] In this embodiment, the functions of each module / unit are as follows:

[0151] The chip processing module 101 is configured to obtain a storage chip to be processed and its corresponding chip specification data, and perform front-end processing on the storage chip in combination with the chip specification data and a preset specification threshold to obtain a target storage chip;

[0152] The material screening module 102 is configured to query the chip application scenario and wire bonding material corresponding to the target storage chip, evaluate the expected application performance corresponding to the target storage chip according to the chip application scenario, calculate the bond matching coefficient between the target storage chip and the wire bonding material based on the expected application performance, and screen out the corresponding optimal bonding material from the wire bonding materials based on the bond matching coefficient;

[0153] The solder joint roundness calculation module 103 is configured to collect an initial chip image corresponding to the target storage chip, mark the chip solder joints in the initial chip image, identify the wire bonding origin, wire bonding end point, and intermediate solder joints in the chip solder joints according to a preset bonding requirement, and calculate the solder joint roundness corresponding to the intermediate solder joints based on the initial chip image;

[0154] The process parameter setting module 104 is configured to determine the optimal solder joint from the intermediate solder joints according to the solder joint roundness, plan the wire bonding path corresponding to the target storage chip in combination with the wire bonding origin, the wire bonding end point, and the optimal solder joint, analyze the physical characterization attributes corresponding to each solder joint in the optimal solder joint according to the initial chip image, and set the bonding process parameters corresponding to the target storage chip based on the physical characterization attributes;

[0155] The packaging processing module 105 is configured to perform bonding and packaging processing on the target storage chip in combination with the wire bonding path, the optimal bonding material, and the bonding process parameters to obtain a packaged storage chip.

[0156] Specifically, each module in the packaging system 100 for implementing the storage chip based on wire bonding in the embodiments of the present application adopts the same technical means as those in the Figure 1 a packaging method for implementing a storage chip based on wire bonding described above, and can produce the same technical effects, which will not be elaborated here.

[0157] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for packaging a memory chip based on wire bonding, characterized in that: The method comprises: Acquire a memory chip to be processed and its corresponding chip specification data, combine the chip specification data and a preset specification threshold, perform front-end processing on the memory chip, and obtain a target memory chip; Querying the chip application scenario and wire bonding material corresponding to the target memory chip, evaluating the expected application performance corresponding to the target memory chip according to the chip application scenario, calculating the bonding matching coefficient between the target memory chip and the wire bonding material based on the expected application performance, and selecting the corresponding most suitable bonding material from the wire bonding materials based on the bonding matching coefficient; Collecting an initial chip image corresponding to the target memory chip, marking chip solder joints in the initial chip image, identifying wire bonding origins, wire bonding endpoints, and middle solder joints in the chip solder joints according to preset bonding requirements, and calculating solder joint circularity corresponding to the middle solder joint based on the initial chip image; According to the roundness of the solder joint, determine the best solder joint from the middle solder joints, plan the wire bonding path corresponding to the target memory chip in combination with the wire bonding origin, the wire bonding endpoint and the best solder joint, analyze the physical characterization property corresponding to each solder joint in the best solder joint according to the initial image of the chip, and set the bonding process parameters corresponding to the target memory chip based on the physical characterization property; In combination with the wire bonding path, the most suitable bonding material and the bonding process parameters, a bonding packaging process is performed on the target memory chip to obtain a packaged memory chip.

2. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The combining the chip specification data and the preset specification threshold to perform front-end processing on the memory chip to obtain a target memory chip includes: Identify the specification index corresponding to the specification threshold, and perform data filtering processing on the chip specification data based on the specification index to obtain filtered specification data; Performing data calibration processing on the filtering specification data to obtain calibration specification data; Performing standardization processing on the calibration specification data to obtain standard specification data; Calculate the chip yield rate corresponding to the memory chip by combining the standard specification data and the specification threshold; According to the chip yield rate, the memory chip is processed at the front end to obtain a target memory chip.

3. The method for packaging a memory chip based on wire bonding according to claim 2, characterized in that: The step of combining the standard specification data and the specification threshold to calculate the chip yield rate corresponding to the memory chip includes: Read the specification reference value in the standard specification data, and calculate the specification weight corresponding to the specification reference value; In combination with the specification reference value, the specification threshold value and the specification weight, the chip yield rate corresponding to the memory chip can be calculated by the following formula: Among them, A represents the chip yield rate corresponding to the memory chip, B a represents the ath reference value in the specification reference value, a represents the serial number of the specification reference value, Q represents the number of specification reference values, B , a Indicates the specification threshold corresponding to the ath benchmark value in the specification benchmark value, D a Indicates the specification weight corresponding to the ath benchmark value in the specification benchmark value.

4. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The step of evaluating the expected application performance corresponding to the target storage chip according to the chip application scenario includes: Scheduling chip load data corresponding to the target storage chip in the chip application scenario; Extracting labels from the chip load data to obtain load labels; Based on the chip load data, calculating the chip load rate corresponding to the load tag; Based on the chip load rate, the actual application performance corresponding to the target storage chip is evaluated.

5. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The step of calculating a bonding fit coefficient between the target memory chip and the wire bonding material based on the expected application performance includes: Decomposing the expected application performance into indicators to obtain performance indicators, and screening out key performance indicators from the performance indicators; Analyzing the indicator factors corresponding to the key performance indicators, and querying the material characteristic attributes corresponding to the wire bonding material; Calculating a coupling index between the index factor and the material characteristic attribute; The bonding fit coefficient between the target memory chip and the wire bonding material is calculated in combination with the coupling index and the material characteristic attribute.

6. The method for packaging a memory chip based on wire bonding according to claim 5, characterized in that: The calculating of the coupling index between the index factor and the material characteristic attribute comprises: Performing vector processing on the index factors and the material characteristic attributes respectively to obtain an index factor vector and a characteristic attribute vector; According to the indicator factor vector and the characteristic attribute vector, respectively calculating the mean values ​​corresponding to the indicator factors and the material characteristic attributes, to obtain the factor vector mean and the attribute vector mean; Combining the index factor vector, the characteristic attribute vector, the factor vector mean and the attribute vector mean, the coupling index between the index factor and the material characteristic attribute can be calculated by the following formula: Among them, E represents the coupling index between the index factor and the material characteristic property, F b represents the bth vector in the indicator factor vector, represents the mean of the factor vector, b represents the serial number corresponding to the indicator factor vector, n represents the number of vectors corresponding to the indicator factor vector, H d represents the dth vector in the feature attribute vector, represents the mean of the attribute vector, d represents the serial number corresponding to the feature attribute vector, and m represents the number of vectors corresponding to the feature attribute vector.

7. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The calculating the solder joint circularity corresponding to the middle solder joint based on the chip initial image includes: Marking a solder joint image corresponding to the middle solder joint from the initial chip image; Identify the edge pixels of the welding spot in the welding spot image, and calculate the pixel distance between the edge pixels of the welding spot; Based on the pixel distance, determining a perimeter of a welding spot corresponding to the middle welding spot; Based on the welding point image, counting the number of welding point pixels corresponding to the middle welding point; Based on the number of pixels of the welding points, determining the welding point area corresponding to the middle welding point; Combining the solder joint perimeter and the solder joint area, the solder joint circularity corresponding to the middle solder joint can be calculated by the following formula: Among them, γ represents the roundness of the solder joint corresponding to the middle solder joint, Se represents the solder joint area corresponding to the e-th solder joint in the middle solder joints, e represents the serial number corresponding to the middle solder joint, and Ge represents the solder joint circumference corresponding to the e-th solder joint in the middle solder joints.

8. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: Determining the optimal welding point from the intermediate welding points according to the welding point circularity includes: Identify a candidate welding point set corresponding to each welding point in the intermediate welding points, and count the number of welding points corresponding to the candidate welding point set; Based on the candidate welding point set, calculating the candidate welding stroke corresponding to the intermediate welding point; In combination with the number of solder joints and the total distance between solder joints, setting the solder joint priority corresponding to the middle solder joint; The optimal welding spot is determined from the intermediate welding spots in combination with the welding spot circularity and the welding spot priority.

9. The method for packaging a memory chip based on wire bonding according to claim 1, characterized in that: The step of analyzing the physical characterization property corresponding to each solder joint in the optimal solder joint according to the initial chip image includes: Extracting the image corresponding to the optimal solder joint from the initial chip image to obtain the optimal solder joint image; Performing denoising processing on the optimal solder joint image to obtain a denoised solder joint image; Performing grayscale processing on the denoised solder joint image to obtain a grayscale solder joint image; Based on the grayscale solder joint image, calculating the solder joint glossiness corresponding to the optimal solder joint; Constructing a solder joint grayscale co-occurrence matrix corresponding to the grayscale solder joint image, and analyzing a solder joint texture representation corresponding to the optimal solder joint based on the solder joint grayscale co-occurrence matrix; The glossiness of the weld point and the texture characterization of the weld point are combined to generate a physical characterization attribute corresponding to each weld point in the optimal weld point.

10. A packaging system for memory chips based on wire bonding, characterized in that: The system comprises: A chip processing module is used to obtain a memory chip to be processed and its corresponding chip specification data, and to perform front-end processing on the memory chip in combination with the chip specification data and a preset specification threshold to obtain a target memory chip; A material screening module, used to query the chip application scenario and wire bonding material corresponding to the target memory chip, evaluate the expected application performance corresponding to the target memory chip according to the chip application scenario, calculate the bonding matching coefficient between the target memory chip and the wire bonding material based on the expected application performance, and screen out the corresponding most suitable bonding material from the wire bonding material based on the bonding matching coefficient; A solder joint circularity calculation module is used to collect an initial chip image corresponding to the target memory chip, mark the chip solder joints in the initial chip image, identify the wire bonding origin, wire bonding endpoint and middle solder joint in the chip solder joints according to preset bonding requirements, and calculate the solder joint circularity corresponding to the middle solder joint based on the initial chip image; A process parameter setting module, for determining an optimal solder joint from the intermediate solder joints according to the solder joint circularity, planning a wire bonding path corresponding to the target memory chip in combination with the wire bonding origin, the wire bonding endpoint and the optimal solder joint, analyzing the physical characterization attribute corresponding to each solder joint in the optimal solder joint according to the chip initial image, and setting the bonding process parameters corresponding to the target memory chip based on the physical characterization attribute; The packaging processing module is used to perform bonding packaging processing on the target memory chip in combination with the wire bonding path, the most suitable bonding material and the bonding process parameters to obtain a packaged memory chip.

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