Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is provided with a first region and a second region, and the second region is disposed at the periphery of the first region; forming a first isolation groove in the substrate in the first region, and forming a second isolation groove in the substrate in the second region; wherein in the direction parallel to the surface of the substrate, the opening size of the second isolation groove is larger than that of the first isolation groove; forming a first dielectric layer and a second dielectric layer which at least fill the second isolation groove; wherein the second dielectric layer is located above the first dielectric layer, and the second dielectric layer is generated towards the side wall of the first dielectric layer along the bottom of the first dielectric layer; and removing the first dielectric layer and the second dielectric layer which are higher than the top of the second isolation groove, and taking the rest part of the first dielectric layer and the rest part of the second dielectric layer as an isolation structure. By adopting the technical scheme, the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As the integration of semiconductor devices increases, a large number of semiconductor elements are formed on a single chip. In order for each semiconductor element to perform its own function, the semiconductor elements need to be electrically insulated from each other.

[0003] Shallow trench isolation (STI) is a commonly used electrical isolation technology that achieves isolation between semiconductor components by forming an insulating material in a substrate.

[0004] However, the electrical performance of semiconductor devices formed so far still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which can improve the electrical performance of the semiconductor structure.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate having a first area and a second area, wherein the second area is disposed at the periphery of the first area;

[0008] Forming a first isolation trench in the substrate of the first region, and forming a second isolation trench in the substrate of the second region; wherein, along a direction parallel to the surface of the substrate, an opening size of the second isolation trench is larger than an opening size of the first isolation trench;

[0009] Forming a first dielectric layer and a second dielectric layer that at least fill the second isolation groove; wherein the second dielectric layer is located above the first dielectric layer, and the second dielectric layer is formed along the bottom of the first dielectric layer toward the side wall of the first dielectric layer;

[0010] The first dielectric layer and the second dielectric layer that are higher than the top of the second isolation trench are removed, and the remaining portions of the first dielectric layer and the second dielectric layer are used as isolation structures.

[0011] Optionally, in the same process step, forming the first isolation trench in the substrate of the first region and forming the second isolation trench in the substrate of the second region are achieved.

[0012] Optionally, in the same process step, the step of forming the first isolation trench in the substrate of the first region and the step of forming the second isolation trench in the substrate of the second region comprises:

[0013] forming a mask layer having an opening above the substrate, wherein, along the surface direction of the substrate, the size of the opening of the mask layer located in the first region is smaller than the size of the opening of the mask layer located in the second region;

[0014] A portion of the thickness of the substrate exposed by the opening is removed along the sidewall of the mask layer to form the first isolation trench in the substrate in the first region and the second isolation trench in the substrate in the second region.

[0015] Optionally, along a direction parallel to the surface of the substrate, an opening size of the second isolation groove is 0.23 μm to 0.28 μm;

[0016] Along the depth direction of the substrate, the depth of the second isolation groove is 0.2 μm to 0.4 μm.

[0017] Optionally, the step of forming a first dielectric layer and a second dielectric layer that at least fill the second isolation trench comprises:

[0018] forming a first dielectric layer in the first isolation trench and the second isolation trench, wherein the first dielectric layer located in the first region at least fills the first isolation trench; and the first dielectric layer located in the second isolation trench has a groove;

[0019] A second dielectric layer is formed on the first dielectric layer, and the second dielectric layer is grown along the bottom of the first dielectric layer toward the sidewall of the first dielectric layer, so that the first dielectric layer and the second dielectric layer at least fill the second isolation groove.

[0020] Optionally, the step of forming a first dielectric layer in the first isolation trench and the second isolation trench includes:

[0021] forming a first sub-dielectric layer in the first isolation trench and the second isolation trench, wherein the first sub-dielectric layer in the first isolation trench has a groove along the normal direction of the substrate;

[0022] A second sub-dielectric layer is formed in the first isolation groove on the first sub-dielectric layer to at least fill up the remaining space of the first isolation groove; wherein the first sub-dielectric layer and the second sub-dielectric layer serve as the first dielectric layer.

[0023] Optionally, the thickness of the first sub-dielectric layer is 570 angstroms to 700 angstroms;

[0024] The thickness of the second dielectric layer is 2400 angstroms to 3000 angstroms.

[0025] Optionally, the first dielectric layer is formed by using a HARP process.

[0026] Optionally, the second dielectric layer is formed by a high-density plasma chemical vapor deposition process.

[0027] Optionally, the second dielectric layer has a thickness of 2500 angstroms to 3100 angstroms.

[0028] Optionally, the first dielectric layer and the second dielectric layer are made of the same material.

[0029] Optionally, materials of the first dielectric layer and the second dielectric layer include silicon oxide.

[0030] Optionally, before the step of forming the first dielectric layer, the method further comprises:

[0031] A liner layer is formed to cover the bottom and sidewalls of the first isolation trench and the second isolation trench.

[0032] This embodiment also provides a semiconductor structure, including:

[0033] A substrate, the substrate having a first area and a second area, wherein the second area is disposed at a periphery of the first area;

[0034] The isolation structure is located in the substrate of the first region and the substrate of the second region respectively, and along the surface direction of the substrate, the opening size of the isolation structure located in the substrate of the second region is larger than the opening size of the isolation structure located in the substrate of the first region.

[0035] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0036] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a substrate has a first region and a second region, a first isolation groove is formed in the substrate of the first region, a second isolation groove is formed in the substrate of the second region, and an opening size of the second isolation groove is larger than an opening size of the first isolation groove along a surface direction parallel to the substrate, and in the step of forming a first dielectric layer and a second dielectric layer in the first isolation groove and the second isolation groove, the second dielectric layer is formed after the first dielectric layer, and the second dielectric layer is generated along the bottom of the first dielectric layer toward the side wall of the first dielectric layer, that is, the second dielectric layer is generated from the middle to both sides along the normal direction of the substrate, so that the first dielectric layer and the second dielectric layer can at least fill the second isolation groove, and then the isolation structure formed subsequently can completely fill the first isolation and the second isolation grooves, reduce or avoid the generation of holes in the isolation structure, and thus improve the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1 to 8 A schematic cross-sectional structure diagram of a semiconductor device forming process provided by an embodiment of the present invention; Fig. 9 It is a schematic cross-sectional structure diagram corresponding to an embodiment of a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0038] The performance of the current semiconductor structure needs to be improved. Specifically, during the formation of the semiconductor, at the 55nm and 65nm nodes, after the isolation trenches are planarized, voids exist in some isolation trenches.

[0039] After analyzing the causes of the above situation, the inventors found that in the process of filling the isolation grooves, there are some isolation grooves with larger opening sizes along the direction parallel to the substrate surface. During the deposition process, when the dielectric layer is formed in the isolation grooves, when the isolation grooves with smaller opening sizes are fully filled with the dielectric layer, the filling thickness of the dielectric layer in the isolation grooves with larger opening sizes is insufficient, which leads to the formation of grooves in the dielectric layer in the isolation grooves. When the subsequent planarization process is performed, holes will be generated in the isolation grooves with larger opening sizes.

[0040] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a first region and a second region, the second region being arranged at the periphery of the first region; forming a first isolation groove in the substrate of the first region, and forming a second isolation groove in the substrate of the second region; wherein, along a surface direction parallel to the substrate, the opening size of the second isolation groove is larger than the opening size of the first isolation groove; forming a first dielectric layer and a second dielectric layer that at least fill the second isolation groove; wherein the second dielectric layer is located above the first dielectric layer, and the second dielectric layer is generated along the bottom of the first dielectric layer toward the side wall of the first dielectric layer; removing the first dielectric layer and the second dielectric layer that are higher than the top of the second isolation groove, and using the remaining parts of the first dielectric layer and the second dielectric layer as an isolation structure.

[0041] The present invention generates the second dielectric layer along the bottom of the first dielectric layer toward the side wall of the first dielectric layer, that is, the second dielectric layer is generated from the middle to both sides along the normal direction of the substrate, so that the first dielectric layer and the second dielectric layer can at least fill the second isolation groove, and then the isolation structure formed subsequently can completely fill the first isolation groove and the second isolation groove, reduce or avoid the generation of holes in the isolation structure, and thus improve the electrical performance of the semiconductor structure.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below in conjunction with the accompanying drawings.

[0043] Figures 1 to 8 A schematic cross-sectional structural diagram of a semiconductor device formation process provided by an embodiment of the present invention.

[0044] refer to Figure 1 , providing a substrate 100, the substrate 100 has a first region I and a second region II, and the second region II is arranged on the periphery of the first region I.

[0045] The substrate 100 is used to provide a process platform for subsequently forming a semiconductor structure.

[0046] In this embodiment, the semiconductor structure is a planar transistor, and the corresponding substrate 100 is a planar substrate. In other embodiments, the semiconductor structure can also be a fin field effect transistor as an example, and the substrate 100 also includes a fin.

[0047] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0048] In this embodiment, the first region I of the substrate 100 is used to form a memory device (eg, a static memory SRAM).

[0049] In this embodiment, the second region II of the substrate 100 is used to form a logic device (eg, a capacitor).

[0050] In this case, the semiconductor device structure in this embodiment may be a logic chip.

[0051] See also Figures 2 to 3 , a first isolation trench 102 is formed in the substrate 100 in the first region I, and a second isolation trench 104 is formed in the substrate 100 in the second region II.

[0052] The first isolation trench 102 and the second isolation trench 104 provide a process space for an isolation structure to be formed subsequently.

[0053] In this embodiment, along a direction parallel to the surface of the substrate 100 , the opening size of the second isolation trench 104 is larger than the opening size of the first isolation trench 102 .

[0054] In a specific embodiment, along a direction parallel to the surface of the substrate 100 , the opening size of the second isolation trench 104 is 0.23 μm to 0.28 μm; along a depth direction of the substrate 100 , the depth of the second isolation trench 104 is 0.2 μm to 0.4 μm.

[0055] In this embodiment, in the same process step, the first isolation trench 102 is formed in the substrate 100 in the first region I, and the second isolation trench 104 is formed in the substrate 100 in the second region II.

[0056] By forming the first isolation trench 102 and the second isolation trench 104 in the same process step, the process steps can be simplified.

[0057] In this embodiment, in the same process step, the first isolation trench 102 is formed in the substrate 100 in the first region I, and the second isolation trench 104 is formed in the substrate 100 in the second region II.

[0058] In this embodiment, see Figure 2 , a mask layer 106 having an opening is formed above the substrate 100 .

[0059] The mask layer 106 is used as a mask in the process of forming the first isolation trench 102 and the second isolation trench 104 .

[0060] In this embodiment, the mask layer 106 is a single-layer structure. In other embodiments, the mask layer 106 may also be a stacked-layer structure.

[0061] In this embodiment, the step of forming a mask layer 106 having an opening above the substrate 100 includes: forming a mask layer 106 on the substrate 100, forming a photoresist (not shown) having a pattern opening on the mask layer 106, wherein the pattern opening exposes a portion of the mask layer 106, and removing the exposed mask layer 106 along the pattern opening to form a mask layer 106 having an opening (e.g., a first opening K1 and a second opening K2).

[0062] In this embodiment, along a direction parallel to the surface of the substrate 100 , the size of the first opening K1 of the mask layer 106 located in the first region I is smaller than the size of the second opening K2 of the mask layer 106 located in the second region II.

[0063] In a specific embodiment, along the surface direction of the substrate 100 , the size of the opening K2 of the mask layer 106 in the second region II is 0.23 μm to 0.28 μm.

[0064] See also Figure 3 , along the sidewalls of the mask layer 106, a portion of the thickness of the substrate 100 exposed by the openings (e.g., the first opening K1 and the second opening K2) is removed, a first isolation trench 102 is formed in the substrate 100 in the first region I, and a second isolation trench 104 is formed in the substrate 100 in the second region II.

[0065] As an example, along the side wall of the mask layer 106, a portion of the thickness of the substrate 100 exposed by the first opening K1 is removed to form a first isolation trench 102 in the substrate 100 in the first region I; and a portion of the thickness of the substrate 100 exposed by the second opening K2 is removed to form a second isolation trench 104 in the substrate 100 in the second region II.

[0066] In this embodiment, in order to improve the formation quality of the first isolation trench 102 and the second isolation trench 104 , a dry etching process is used to etch the partial thickness of the substrate 100 exposed by the first opening K1 and the second opening K2 .

[0067] In this embodiment, along the normal direction of the surface of the substrate 100 , the first isolation trench 102 and the second isolation trench 104 have the same depth in the substrate 100 .

[0068] After the first isolation trench 102 and the second isolation trench 104 are formed, the mask layer 106 may be removed.

[0069] In this embodiment, at least one of an ashing process, a planarization process, or an etch-back process may be used to remove the mask layer 106 on the substrate 100 .

[0070] In this embodiment, see Figure 2 and Figure 3 Before forming the mask layer 106 , a protection layer 108 is formed on the substrate 100 .

[0071] The protection layer 108 is used to protect the surface of the substrate 100 and reduce or avoid damage to the surface of the substrate 100 .

[0072] In this embodiment, the material of the protective layer 108 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride oxycarbon, boron nitride and boron carbonitride.

[0073] As an example, the material of the protection layer 108 is silicon nitride.

[0074] See also Figure 3 In the step of removing the portion of the thickness of the substrate 100 exposed by the first opening K1 and the second opening K2 , the protection layer 108 exposed by the first opening K1 and the second opening K2 is also removed.

[0075] In an optional example, after forming the first isolation trench 102 and the second isolation trench 104 in the substrate 100, Figure 4 , a liner layer 110 is formed to cover the bottom and sidewalls of the first isolation trench 102 and the second isolation trench 104 .

[0076] The liner layer 110 can protect the first isolation trench 102 and the second isolation trench 104, and prevent impurities, moisture or chemicals in the external environment from contaminating or damaging the surfaces of the first isolation trench 102 and the second isolation trench 104; and by forming the liner layer 110 before forming the first dielectric layer, the liner layer 110 can serve as a buffer layer to reduce the stress caused by poor lattice matching or difference in thermal expansion coefficient between the first dielectric layer and the substrate 100, thereby reducing structural deformation or damage of the first isolation trench 102 and the second isolation trench 104.

[0077] See also Figures 5 to 8 , forming a first dielectric layer 116 and a second dielectric layer 118 that at least fill the second isolation trench 104 .

[0078] The first dielectric layer 116 is used as an isolation structure to be filled in the first isolation trench 102 , and the first dielectric layer 116 and the second dielectric layer 118 are used as an isolation structure to be filled in the second isolation trench 104 .

[0079] It can be understood that, along the direction parallel to the surface of the substrate 100, the opening size of the first isolation groove 102 is smaller than the opening size of the second isolation groove 104. When the first dielectric layer 116 and the second dielectric layer 118 fill the second isolation groove 104, the first isolation groove 102 must have been filled.

[0080] In this embodiment, the second dielectric layer 118 is located above the first dielectric layer 116, and the second dielectric layer 118 is generated along the bottom of the first dielectric layer 116 toward the side wall of the first dielectric layer 116, that is, the second dielectric layer 118 is generated from the middle to both sides along the normal direction of the substrate 100, so that the second dielectric layer 118 can completely fill the remaining space of the second isolation groove 104 in the first dielectric layer 116.

[0081] In this embodiment, the steps of forming the first dielectric layer 116 and the second dielectric layer 118 that at least fill the second isolation trench 104 include:

[0082] A first dielectric layer 116 is formed in the first isolation trench 102 and the second isolation trench 104 .

[0083] For some examples, see Figure 5 and Figure 6 The step of forming the first dielectric layer 116 in the first isolation trench 102 and the second isolation trench 104 includes:

[0084] See also Figure 5 A first sub-dielectric layer 112 is formed in the first isolation trench 102 and the second isolation trench 104 .

[0085] The first sub-dielectric layer 112 serves as an isolation structure that is subsequently formed in the first isolation trench 102 and the second isolation trench 104 .

[0086] In this embodiment, the HARP process is used to form the first sub-dielectric layer 112 in the first isolation trench 102 and the second isolation trench 104 .

[0087] In this embodiment, the thickness of the first sub-dielectric layer 112 is 570 angstroms to 700 angstroms.

[0088] In this embodiment, the material of the first sub-dielectric layer 112 is an insulating material, including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride and boron carbonitride.

[0089] See also Figure 5 In the step of forming the first sub-dielectric layer 112 , the first sub-dielectric layer 112 located in the first isolation trench has a groove, that is, the first sub-dielectric layer 112 does not fill the entire space in the first isolation trench 102 .

[0090] It can be understood that, along the direction parallel to the surface of the substrate 100 , the opening size of the first isolation groove 102 is smaller than the opening size of the second isolation groove. When the first sub-dielectric layer 112 does not fill the entire space in the first isolation groove 102 , the first sub-dielectric layer 112 will inevitably not fill the second isolation groove 104 .

[0091] See also Figure 6 A second sub-dielectric layer 114 is formed in the first isolation trench 102 on the first sub-dielectric layer 112 to at least fill up the remaining space of the first isolation trench 102 .

[0092] The second sub-dielectric layer 114 serves as an isolation structure that is subsequently formed in the first isolation trench 102 and the second isolation trench 104 .

[0093] In this embodiment, the second sub-dielectric layer 114 is formed on the first sub-dielectric layer 112 by adopting the HARP process.

[0094] In this embodiment, the thickness of the second sub-dielectric layer 114 is 2400 angstroms to 3000 angstroms.

[0095] In this embodiment, the material of the second sub-dielectric layer 114 is an insulating material, including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride and boron carbonitride.

[0096] See also Figure 6 In the step of forming the second sub-dielectric layer 114, the first dielectric layer 116 composed of the second sub-dielectric layer 114 and the first sub-dielectric layer 112 completely fills the first isolation trench 102; and the first dielectric layer 116 located in the second isolation trench 104 has a groove, that is, the first dielectric layer 116 does not fill the entire space in the second isolation trench 102.

[0097] See also Figure 7 , a second dielectric layer 118 is formed on the first dielectric layer 116 .

[0098] The second dielectric layer 118 serves as an isolation structure that is subsequently formed in the second isolation trench 104 .

[0099] In this embodiment, the second dielectric layer 118 is formed by a high density plasma chemical vapor deposition process.

[0100] In this embodiment, the thickness of the second dielectric layer 118 is 2500 angstroms to 3100 angstroms.

[0101] In this embodiment, the second dielectric layer 118 and the first dielectric layer 116 are made of the same material, both of which are insulating materials, specifically including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride and boron carbonitride.

[0102] In this embodiment, in the step of forming the second dielectric layer 118, the second dielectric layer 118 can be generated along the bottom of the first dielectric layer 116 toward the side wall of the first dielectric layer 116, that is, the second dielectric layer 118 is generated from the middle to both sides along the normal direction of the substrate 100, so that the second dielectric layer 118 can fill the remaining space of the second isolation groove 104 in the first dielectric layer 116, and then the first dielectric layer 116 and the second dielectric layer 118 can at least fill the second isolation groove 104.

[0103] In other words, along the normal direction of the substrate 100 , the first dielectric layer 116 and the second dielectric layer 118 located on the second region II fill up all the space in the second isolation trench 104 .

[0104] It should be noted that the reason why the first sub-dielectric layer 112 and the second sub-dielectric layer 114 are formed first and then the second dielectric layer 118 is formed in the present embodiment is that if the HARP process is adopted, the first dielectric layer 116 is formed at one time, which takes a long time and is costly, while if the HARP process is adopted twice, the rate of the first deposition process is low, but its filling ability is strong, and the second deposition rate is high, thereby reducing the formation time of the first dielectric layer 116 while satisfying the requirement of being able to completely fill the first isolation groove 102; further, in forming the second dielectric layer 118, the second dielectric layer 118 has the characteristic of being generated along the bottom of the first dielectric layer 116 toward the side wall of the first dielectric layer 116, so that the second isolation groove 104 can be filled to avoid the formation of holes in the second isolation groove 104.

[0105] In some other examples, the process time of the second dielectric layer 118 may be prolonged so that the first dielectric layer 116 and the second dielectric layer 118 at least fill the second isolation trench 104 .

[0106] See also Figure 8 , the first dielectric layer 116 and the second dielectric layer 118 that are higher than the top of the second isolation trench 104 are removed, and the remaining portions of the first dielectric layer 116 and the second dielectric layer 118 are used as the isolation structure 120 .

[0107] The isolation structure 120 may be used to isolate adjacent devices.

[0108] In some examples, the step of forming the isolation structure 120 may include: taking the top layer of the substrate 100 as the stopping position, using a planarization process (e.g., a chemical mechanical polishing process) to remove the first dielectric layer 116 and the second dielectric layer 118 above the second isolation groove 104, and retaining the first dielectric layer 116 and the second dielectric layer 118 to the second isolation groove 104 as the isolation structure 120, and retaining the first dielectric layer 116 to the first isolation groove 102 as the isolation structure 120.

[0109] In some embodiments, the isolation structure 120 may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbon oxynitride.

[0110] In this embodiment, the material of the isolation structure 120 may be silicon oxide.

[0111] In some embodiments, the substrate 100 may further have a gate structure, and the substrate at both sides of the gate structure has source and drain doping regions, and the gate structure exposes the source and drain doping regions.

[0112] When the device is working, the gate structure is used to control the opening and closing of the conductive channel. In this embodiment, the gate structure is a metal gate structure, and the gate structure may include a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0113] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.

[0114] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0115] In this embodiment, the gate electrode layer may include one or both of a work function layer and an electrode layer.

[0116] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and silicon titanium nitride.

[0117] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0118] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0119] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0120] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0121] In this embodiment, the gate structure is described by taking a metal gate structure as an example. In other embodiments, based on actual process requirements, the gate structure may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0122] In some embodiments, a gate sidewall is formed on the sidewall of the gate structure, and the gate sidewall can be used to protect the gate structure.

[0123] In this embodiment, the material of the gate spacer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride or boron carbonitride.

[0124] As an example, the material of the gate spacer is silicon nitride.

[0125] In this embodiment, the source-drain doped region can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the source-drain doped region can provide a carrier source.

[0126] The process of forming the source-drain doped regions includes: forming grooves in the substrate on both sides of the gate structure; forming a stress layer that fills the grooves; in the process of forming the stress layer, in-situ doping the stress layer to form the source-drain doped regions; or, after forming the stress layer, doping the stress layer to form the source-drain doped regions.

[0127] Fig. 9 1 is a schematic diagram of a structure corresponding to an embodiment of a semiconductor structure of the present invention. Fig. 9As shown, in this embodiment, the semiconductor structure includes: a substrate 200, the substrate 200 has a first region I and a second region II, and the second region II is arranged at the periphery of the first region I; an isolation structure 220, which is respectively located in the substrate 200 of the first region I and in the substrate 200 of the second region II, and along the surface direction of the substrate 200, the opening size of the isolation structure 220 located in the substrate 200 of the second region II is larger than the opening size of the isolation structure 220 located in the substrate 200 of the first region I.

[0128] In this embodiment, the substrate 200 is used to provide a process platform for subsequently forming a semiconductor structure.

[0129] In this embodiment, the semiconductor structure is a planar transistor, and the corresponding substrate 200 is a planar substrate. In other embodiments, the semiconductor structure can also be a fin field effect transistor as an example, and the substrate 200 also includes a fin.

[0130] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0131] In this embodiment, the first region I of the substrate 200 is used to form a memory device (eg, a static memory SRAM).

[0132] In this embodiment, the second region II of the substrate 200 is used to form a logic device (eg, a capacitor).

[0133] In this case, the semiconductor device structure in this embodiment may be a logic chip.

[0134] In this embodiment, the isolation structure 220 can be used to isolate adjacent devices.

[0135] In some embodiments, the isolation structure 220 may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

[0136] In this embodiment, the material of the isolation structure 220 may be silicon oxide.

[0137] In this embodiment, along the depth direction of the substrate 200 , the depth of the isolation structure 220 is 0.2 μm to 0.4 μm.

[0138] As an optional example, the semiconductor structure may further include a liner layer 210 located in the substrate 200 and covering the bottom and sidewalls of the isolation structure 220 .

[0139] The liner layer 210 can play a buffering role and reduce the stress caused by poor lattice matching or difference in thermal expansion coefficient between the isolation structure 220 and the substrate 200, thereby causing structural deformation or damage to the substrate 200.

[0140] In this embodiment, the semiconductor structure may further include: a gate structure. When the device is working, the gate structure is used to control the opening and closing of the conductive channel.

[0141] In this embodiment, the gate structure is a metal gate structure, and the gate structure includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0142] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.

[0143] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0144] In this embodiment, the gate electrode layer includes one or both of a work function layer and an electrode layer.

[0145] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an Å-MOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride and silicon titanium nitride.

[0146] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0147] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0148] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0149] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0150] In this embodiment, the gate structure is described by taking a metal gate structure as an example. In other embodiments, based on actual process requirements, the gate structure may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0151] In this embodiment, the semiconductor structure may further include: source and drain doping layers located on the substrate at both sides of the gate structure.

[0152] The source-drain doped layer can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the source-drain doped layer can be used to provide a carrier source.

[0153] In this embodiment, the source-drain doping layer may include a stress layer doped with ions, and the stress layer may be used to provide stress for the channel region, thereby improving the mobility of carriers.

[0154] Specifically, when forming an ÅMOS transistor, the source and drain doping layers may include a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when forming a PMOS transistor, the source and drain doping layers may include a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.

[0155] It should be noted that the semiconductor structure described in this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0156] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a first area and a second area, wherein the second area is disposed at the periphery of the first area; Forming a first isolation trench in the substrate of the first region, and forming a second isolation trench in the substrate of the second region; wherein, along a direction parallel to the surface of the substrate, an opening size of the second isolation trench is larger than an opening size of the first isolation trench; Forming a first dielectric layer and a second dielectric layer that at least fill the second isolation groove; wherein the second dielectric layer is located above the first dielectric layer, and the second dielectric layer is formed along the bottom of the first dielectric layer toward the side wall of the first dielectric layer; The first dielectric layer and the second dielectric layer that are higher than the top of the second isolation trench are removed, and the remaining portions of the first dielectric layer and the second dielectric layer are used as isolation structures.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the same process step, the first isolation trench is formed in the substrate of the first region, and the second isolation trench is formed in the substrate of the second region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming the first isolation trench in the substrate of the first region and the step of forming the second isolation trench in the substrate of the second region in the same process step comprises: forming a mask layer having an opening above the substrate, wherein, along the surface direction of the substrate, the size of the opening of the mask layer located in the first region is smaller than the size of the opening of the mask layer located in the second region; A portion of the thickness of the substrate exposed by the opening is removed along the sidewall of the mask layer to form the first isolation trench in the substrate in the first region and the second isolation trench in the substrate in the second region.

4. The method for forming a semiconductor structure according to claim 1, wherein: Along a direction parallel to the surface of the substrate, an opening size of the second isolation groove is 0.23 μm to 0.28 μm; Along the depth direction of the substrate, the depth of the second isolation groove is 0.2 μm to 0.4 μm.

5. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a first dielectric layer and a second dielectric layer that at least fills the second isolation trench comprises: forming a first dielectric layer in the first isolation trench and the second isolation trench, wherein the first dielectric layer located in the first region at least fills the first isolation trench; and the first dielectric layer located in the second isolation trench has a groove; A second dielectric layer is formed on the first dielectric layer, and the second dielectric layer is grown along the bottom of the first dielectric layer toward the sidewall of the first dielectric layer, so that the first dielectric layer and the second dielectric layer at least fill the second isolation groove.

6. The method for forming a semiconductor structure according to claim 5, characterized in that: The step of forming a first dielectric layer in the first isolation trench and the second isolation trench comprises: forming a first sub-dielectric layer in the first isolation trench and the second isolation trench, wherein the first sub-dielectric layer in the first isolation trench has a groove along the normal direction of the substrate; A second sub-dielectric layer is formed in the first isolation groove on the first sub-dielectric layer to at least fill up the remaining space of the first isolation groove; wherein the first sub-dielectric layer and the second sub-dielectric layer serve as the first dielectric layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The thickness of the first sub-dielectric layer is 570 angstroms to 700 angstroms; The thickness of the second dielectric layer is 2400 angstroms to 3000 angstroms.

8. The method for forming a semiconductor structure according to any one of claims 1, 5 to 7, characterized in that: The first dielectric layer is formed by adopting a HARP process.

9. The method for forming a semiconductor structure according to claim 1, wherein: The second dielectric layer is formed by adopting a high-density plasma chemical vapor deposition process.

10. The method for forming a semiconductor structure according to claim 1 or 9, characterized in that: The thickness of the second dielectric layer is 2500 angstroms to 3100 angstroms.

11. The method for forming a semiconductor structure according to claim 1, wherein: The first dielectric layer and the second dielectric layer are made of the same material.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: The materials of the first dielectric layer and the second dielectric layer include silicon oxide.

13. The method for forming a semiconductor structure according to claim 1, wherein: Before the step of forming the first dielectric layer, the method further includes: A liner layer is formed to cover the bottom and sidewalls of the first isolation trench and the second isolation trench.

14. A semiconductor structure, characterized in that: include: A substrate, the substrate having a first area and a second area, wherein the second area is disposed at a periphery of the first area; The isolation structure is located in the substrate of the first region and the substrate of the second region respectively, and along the surface direction of the substrate, the opening size of the isolation structure located in the substrate of the second region is larger than the opening size of the isolation structure located in the substrate of the first region.

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