Trench isolation structure and method of making the same, semiconductor device
By forming gaps on the trench sidewalls and removing the sacrificial layer, the problem of filling oxide layers in deep trenches was solved, achieving the effects of simplifying the process, reducing costs, and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU FULLSEMI SEMICON CO LTD
- Filing Date
- 2024-12-09
- Publication Date
- 2026-05-12
AI Technical Summary
Existing DTI processes present significant challenges in filling oxide layers in deep trenches, leading to increased internal stress in devices, which negatively impacts performance. Furthermore, these processes are complex and costly.
By combining a sacrificial layer and a low-temperature oxide film layer, a gap is first formed on the sidewall of the trench. Then, anisotropic etching is used to form a window to remove the sacrificial layer. Finally, a second oxide film layer is filled to seal the opening, forming a sealing structure. This simplifies the process and reduces internal stress.
It reduces capacitance and internal stress, simplifies process steps, lowers production costs, and improves device performance and fabrication yield.
Smart Images
Figure CN119650510B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically to a trench isolation structure and its preparation method, and a semiconductor device. Background Technology
[0002] With the development of semiconductor technology, the feature size of devices in integrated circuits is getting smaller and smaller, and the speed of devices and systems is increasing accordingly. In particular, after semiconductor processes entered the deep submicron stage, isolation technology has become increasingly important.
[0003] Currently, Deep Trench Isolation (DTI) technology is widely used in microelectronic devices, integrated circuits, sensors, and optoelectronic devices to improve chip performance, reduce chip power consumption, and increase chip integration density and reliability. A typical DTI structure includes trenches or gaps formed in the isolation region of a semiconductor substrate. These trenches or gaps need to be completely filled with an oxide layer to prevent electrical coupling between adjacent device structures. However, due to the high aspect ratio of deep trenches, completely filling the interior of deep trenches with an oxide layer presents significant technological challenges, making it difficult to complete the filling without creating random voids or gaps. Furthermore, completely filling the deep trench with an oxide layer can increase the internal stress of the device, affecting its performance. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench isolation structure and its preparation method, as well as a semiconductor device, so as to simplify the preparation process of the trench isolation structure, reduce the preparation difficulty and cost, and improve the performance of the semiconductor device.
[0005] To achieve the above and other related objectives, the present invention provides a method for preparing a trench isolation structure, comprising:
[0006] A semiconductor substrate is provided, the semiconductor substrate including trenches;
[0007] At least the interior of the trench is filled with a sacrificial layer, wherein the filled sacrificial layer is exposed on the trench sidewall at a certain height from the trench port toward the depth of the trench interior;
[0008] A first oxide film layer is formed at least on the sidewall of the trench and above the sacrificial layer within the trench. The first oxide film layer includes a first portion and a second portion. The first portion is formed on the sidewall of the trench, and a gap is formed within the first portion that extends through the first portion along the depth direction of the trench. The second portion is formed at the bottom of the gap and on the sacrificial layer.
[0009] A window is formed on the second part, and the window exposes part of the sacrificial layer;
[0010] Remove the sacrificial layer within the trench based on the window;
[0011] A second oxide film layer is filled into the gap within the first part until the second oxide film layer completely fills the gap, forming a seal at the end of the trench.
[0012] According to one aspect of the present invention, a trench isolation structure is also provided, which is formed by the above-described method for preparing the trench isolation structure.
[0013] According to one aspect of the present invention, a semiconductor device is also provided, the semiconductor device including the above-described trench isolation structure.
[0014] Compared with the prior art, the trench isolation structure, its fabrication method, and the semiconductor device described in this invention have at least the following characteristics:
[0015] Beneficial effects:
[0016] The method for fabricating a trench isolation structure according to the present invention includes providing a semiconductor substrate, the semiconductor substrate including a trench. A sacrificial layer is filled at least inside the trench, wherein the filled sacrificial layer exposes a portion of the trench sidewall at a depth direction from the trench port into the trench interior. A first oxide film layer is formed at least on the trench sidewall and above the sacrificial layer inside the trench. The first oxide film layer includes a first portion and a second portion. The first portion is formed on the trench sidewall, and a gap extending through the first portion along the depth direction of the trench is formed within the first portion; the second portion is formed at the bottom of the gap and on the sacrificial layer. A window is formed on the second portion, the window exposing a portion of the sacrificial layer. The sacrificial layer inside the trench is removed based on the window. A second oxide film layer is filled into the gap within the first portion until the second oxide film layer completely fills the gap, forming a seal at the trench port. Thus, since the present invention forms a seal only at the trench port, leaving a partial void structure below, the trench isolation structure formed in the present invention can not only reduce capacitance and improve device operating speed, but also reduce internal stress in the device, resulting in superior device performance. Compared to the traditional DTI trench-filling oxide layer process, this void structure process avoids the process challenges posed by the filling capacity of the oxide layer during trench filling and the effects of stress-induced wafer warpage, resulting in a simpler process. Furthermore, the trench isolation structure of this invention has a simpler fabrication process, lower cost, lower internal stress in the sealing structure, and better device performance.
[0017] Furthermore, in this invention, the port of the formed trench isolation structure includes a first oxide film layer formed using a low-temperature oxide film process. This oxide film layer makes it easier to etch windows in subsequent processes, simplifying the fabrication process. Moreover, the oxide film layer formed by this process is more uniform, reduces capacitance and internal stress, and exhibits superior structural performance.
[0018] Furthermore, in this invention, the sacrificial layer is made of a non-oxide film material with high fluidity and filling capacity. The sacrificial layer formed by this material has fewer defects, which is beneficial to the formation quality of the first oxide film layer subsequently formed on it, and further reduces structural stress.
[0019] Furthermore, in this invention, by controlling the proportion of the back-etching depth to the trench depth to be 1% to 4%, it is possible to ensure the thickness of the first oxide film layer formed subsequently, which facilitates the subsequent etching window, while also taking into account the sealing height and avoiding the increase in structural stress caused by excessive sealing height.
[0020] Furthermore, in this invention, anisotropic etching is used to etch the window, which increases the etching rate of the window and reduces the etching loss of the first oxide film layer located on the annular sidewall. This avoids the large size of the gap formed between the subsequent first oxide film layers, which would make it difficult for subsequent rapid filling. As a result, it saves subsequent filling materials and filling time, which reduces production costs and improves production efficiency.
[0021] Furthermore, during anisotropic etching, self-aligned etching windows are formed within the trenches, eliminating the need for a patterned mask on the semiconductor substrate. This saves one mask and one photolithography process, and also eliminates the need for resist removal, thus simplifying the process and reducing fabrication difficulty. Simultaneously, it avoids pattern misalignment issues caused by overlay precision limitations introduced by the photolithography process, improving device fabrication yield.
[0022] The trench isolation structure and semiconductor device in this invention are formed using the above-described trench isolation structure fabrication method, and thus possess the same technical effects. Attached Figure Description
[0023] Figure 1 This is a flowchart illustrating the preparation method of the trench isolation structure in an embodiment of the present invention;
[0024] Figure 2 This is a schematic diagram of the structure after trenches are formed inside the semiconductor substrate in an embodiment of the present invention;
[0025] Figure 3 This is a schematic diagram of the structure after an oxide layer is formed on the surface of the semiconductor substrate and the inner wall of the trench in an embodiment of the present invention;
[0026] Figure 4 This is a schematic diagram of the structure after filling the trench and re-etching the sacrificial layer in an embodiment of the present invention;
[0027] Figure 5 This is a schematic diagram of the structure after the first oxide film layer is formed on the oxide layer and the sacrificial layer in the trench in an embodiment of the present invention;
[0028] Figure 6 This is a schematic diagram of the structure after a window is formed on the first oxide film layer in the trench in an embodiment of the present invention;
[0029] Figure 7 This is a schematic diagram of the structure after removing the sacrificial layer based on window etching in an embodiment of the present invention;
[0030] Figure 8 This is a schematic diagram of the structure after the second oxide film layer is formed inside the window and above the second oxide film layer in an embodiment of the present invention;
[0031] Figure 9 This is a schematic diagram of the structure after planarization of the interface after the formation of the second oxide film layer in an embodiment of the present invention.
[0032] List of reference numerals in the attached diagram:
[0033] 100 Semiconductor Substrate
[0034] 200 trench
[0035] 300 Oxide Layer
[0036] 301 Trench sidewall
[0037] 400 Sacrificial Layers
[0038] 500 First oxide film layer
[0039] 501 Part 1
[0040] 502 Part Two
[0041] 503 gap
[0042] 504 Window
[0043] 600 Second oxide film layer
[0044] 700 sealed
[0045] 800 porosity structure Detailed Implementation
[0046] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0047] It should be understood that the illustrations provided in the embodiments of this invention are merely schematic representations of the basic concept of the invention. Although the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this application.
[0048] To simplify the fabrication process of trench isolation structures, reduce fabrication difficulty and cost, and improve the performance of semiconductor devices, this embodiment provides a trench isolation structure, its fabrication method, and a semiconductor device.
[0049] Example 1
[0050] This embodiment provides a method for preparing a trench isolation structure, referring to... Figure 1 The preparation method includes:
[0051] S1: A semiconductor substrate is provided, the semiconductor substrate including trenches;
[0052] Specifically, refer to Figure 2 A semiconductor substrate 100 is provided, which can be made of silicon (Si), germanium (Ge), silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. When the semiconductor substrate 100 is made of silicon, it can be one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor substrate 100 can be a wafer or a structure containing an epitaxial layer. Optionally, the semiconductor substrate 100 includes a wafer and an epitaxial layer, which refers to a layer structure formed by N-type doping or P-type doping with at least a partial thickness on the surface of the wafer. Optionally, the semiconductor substrate 100 can also be only a P-type substrate, and a conductive layer can be formed by N-type ion doping in subsequent processes. Of course, the semiconductor substrate 100 can also be only an N-type substrate, and a conductive layer can be formed by P-type ion doping in subsequent processes. This embodiment uses a silicon substrate as an example for illustration.
[0053] A trench 200 is formed within the semiconductor substrate 100. Specifically, dry etching can be used to etch the semiconductor substrate 100, with the etching depth controlled between 25 μm and 40 μm. After dry etching, damage to the silicon lattice at the sidewalls of the trench 200 is inevitable. Therefore, in this embodiment, referring to… Figure 3After the trench 200 is formed, an oxide layer 300 can be formed on the sidewall of the trench 200.
[0054] S2: At least the interior of the trench is filled with a sacrificial layer, wherein the filled sacrificial layer is exposed on the trench sidewall at a certain height from the port of the trench in the depth direction inside the trench;
[0055] Specifically, refer to Figure 4 A sacrificial layer 400 is filled inside the trench 200. This sacrificial layer 400 fills the interior of the trench 200 and exposes a portion of the inner wall of the trench 200's port in the inward direction. This exposed inner wall forms the trench sidewall 301. The sacrificial layer 400 is made of a non-oxide film material with good flowability and strong filling capacity. This material selection allows for the formation of a relatively dense filling layer with fewer structural defects, ensuring that subsequent layers formed on top of it will not have significant structural defects that could affect device performance. For example, the sacrificial layer 400 can be a photoresist layer (PR) or a bottom anti-reflective coating (BARC). Of course, the sacrificial layer 400 can also be other non-oxide film materials with high flowability; this embodiment does not limit this.
[0056] In this embodiment, the material of the sacrificial layer 400 is a photoresist layer as an example. During fabrication, the sacrificial layer 400, i.e., the photoresist layer, can first be completely filled inside the trench 200. Then, the completely filled sacrificial layer 400 is etched back along the port of the trench 200 towards the depth of the trench 200 to expose the trench sidewall 301. During the back etching, a mixture of oxygen and nitrogen gas can be used to etch the sacrificial layer 400. This mixture of gas has selective etching properties for the oxide layer 300 formed earlier in the trench 200 and will not etch the previously formed oxide layer 300. Optionally, the oxygen to nitrogen gas flow rate is between 20 and 30:1.
[0057] Reference Figure 4 and 5 Considering that a first oxide film 500 needs to be deposited on the trench sidewall 301 exposed by the etchback and the sacrificial layer 400 at the bottom of the trench sidewall 301, and that the etchback depth has a significant impact on the thickness of the first oxide film 500 subsequently formed on the trench sidewall 301 and above the sacrificial layer 400 within the trench 200, a shallower etchback depth results in a shallower trench formed by the sacrificial layer 400 and the trench sidewall 301, leading to a thicker first oxide film 500, which is less conducive to subsequent etching. Figure 6 The window 504 is shown in the diagram. Furthermore, the etch-back depth also affects the performance of subsequent device structures; for example, a shallower etch-back depth results in more difficult-to-form components within the trench 200. Figure 9The smaller the height of the seal 700 shown, the lower the structural capacitance, which is more beneficial to device performance. To balance subsequent device performance and the ease of opening the window 504, this embodiment controls the etch-back depth to be 1% to 4% of the trench 200 depth, for example, 1.25% to 4%. This etch-back depth ratio ensures that the first oxide film layer 500 deposited on the trench sidewall 301 and above the sacrificial layer 400 within the trench 200 is not too thick, facilitating the subsequent etching of the window 504, while also preventing the seal 700 height from being too large and affecting the performance of the subsequently formed device. In a specific example, the etch-back depth is approximately 0.5 μm to 1 μm.
[0058] S3: A first oxide film layer is formed at least on the sidewall of the trench and above the sacrificial layer in the trench. The first oxide film layer includes a first part and a second part. The first part is formed on the sidewall of the trench, and a gap is formed in the first part that extends through the first part along the depth direction of the trench. The second part is formed at the bottom of the gap and on the sacrificial layer.
[0059] Specifically, refer to Figure 5 A first oxide film layer 500 is formed at least above the trench sidewall 301 and the sacrificial layer 400 within the trench 200. In actual process, due to the difficulty in controlling the deposition rate, the first oxide film layer 500 may also form on the surface of the semiconductor substrate 100 between adjacent trenches 200. This first oxide film layer 500 formed above the semiconductor substrate 100 can be removed by subsequent processes. During implementation, it is sufficient to ensure that the first oxide film layer 500 is formed above the trench sidewall 301 and the sacrificial layer 400 within the trench 200.
[0060] To facilitate the formation of the window 504 on the first oxide film layer 500 formed within the trench 200, this embodiment employs a low-temperature oxide film deposition (LTO) process to form the first oxide film layer 500. This low-temperature oxide film deposition process typically deposits the oxide film layer at relatively low temperatures, such as 200°C to 300°C, which is lower than high-temperature oxidation processes. The non-dense nature of the first oxide film layer 500 formed by this deposition process makes it easier to etch the window 504, improving production efficiency and reducing production costs. Simultaneously, this deposition process allows for more precise control of the oxidation rate during oxide film formation, resulting in a more uniform oxide film layer with lower stress, which helps reduce structural stress in the device and improve device performance. In this embodiment, the deposition of the first oxide film layer 500 is as follows: For example
[0061] In this embodiment, the first oxide film layer 500 includes a first portion 501 and a second portion 502. The first portion 501 is formed on the trench sidewall 301, and a gap 503 is formed within the first portion 501, extending through the first portion 501 along the depth direction of the trench 200. The second portion 502 is formed at the bottom of the gap 503 and on the sacrificial layer 400. Because the etching depth in step S3 is properly controlled, the overall thickness of the formed first oxide film layer 500 is relatively small, and the thickness of the second portion 502 is less than the thickness of the first portion 501. When etching to form the window 504, less etching gas and etching time can be used, which helps to save production costs and improve production efficiency. Since the low-temperature oxide film deposition process has a lower process temperature, it avoids damage to the already formed structure caused by high temperatures, and also consumes less energy.
[0062] S4: A window is formed on the second part, and the window exposes part of the sacrificial layer;
[0063] Specifically, refer to Figure 6 A window 504 is formed on the second portion 502, exposing a portion of the sacrificial layer 400. To increase the etching rate of the window 504 and reduce the etching loss of the first oxide film layer 500 located on the annular sidewall, this method avoids excessively large gaps 503 formed between the subsequent first oxide film layers 500, which could hinder rapid subsequent filling and save on filling material and time. In this embodiment, an anisotropic dry etching method is used to form the window 504 on the second portion 502 of the first oxide film layer 500. During dry etching, the ratio of the longitudinal etching rate to the transverse etching rate is 20–50:1, meaning the etching rate of the first portion 501 is much lower than the etching rate of the second portion 502. This allows for the rapid formation of the window 504 on the second portion 502 while preventing over-etching of the first portion 501 and avoiding excessively large gaps 503 in the filling process.
[0064] To simplify the process and reduce manufacturing costs, this embodiment employs a self-aligned method for anisotropic dry etching. This eliminates the need for a patterned mask on the semiconductor substrate 100, saving one mask and one photolithography process, and also eliminates the need for resist removal, thereby simplifying the process steps and reducing fabrication difficulty. Simultaneously, it avoids pattern misalignment issues caused by overlay precision limitations introduced by the photolithography process, improving device fabrication yield.
[0065] S5: Remove the sacrificial layer within the trench based on the window;
[0066] Specifically, refer to Figure 7The sacrificial layer 400 within the trench 200 is removed based on the window 504 formed in step S4. For example, a wet etching process and / or an ashing process can be used to remove the sacrificial layer 400 within the trench 200. During the removal process, either a wet etching process or an ashing process can be used to remove the sacrificial layer 400. In order to effectively remove the sacrificial layer 400 within the trench 200 and reduce costs, this embodiment first uses a time-enhanced ashing process to remove most of the sacrificial layer 400, and then uses a wet etching process to remove the remaining sacrificial layer 400 within the trench 200. This effectively removes the sacrificial layer 400 within the trench 200 and avoids the production cost incurred by using wet etching to remove the entire sacrificial layer 400. If the sacrificial layer 400 is made of other materials, a corresponding removal method can be selected for removal, but the removal method must ensure that it does not damage the oxide layer 300.
[0067] S6: Fill the gaps in the first part with a second oxide film layer until the second oxide film layer completely fills the gaps, forming a seal at the end of the trench.
[0068] Specifically, refer to Figure 8 Alternatively, after removing the sacrificial layer 400, a second oxide film layer 600 is formed in the gap 503 within the first portion 501 until the second oxide film layer 600 completely fills the gap 503, forming a seal 700 at the port of the trench 200. In this embodiment, a chemical vapor deposition process is used to fill the gap 503 in the first portion 501 with the second oxide film layer 600, eliminating the need for composite films such as nitride films, thus offering greater freedom in process selection. For example, the chemical vapor deposition process can be plasma-enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (SACVD) performed under sub-atmospheric pressure conditions. When using plasma-enhanced chemical vapor deposition, a plasma-enhanced oxidation (PE-OX) process can be used to form the oxide film layer. During deposition, the deposition rate of the second oxide film layer 600 is controlled between... The second oxide film layer 600 quickly fills the gap 503 between the first part 501 of the first oxide film layer 500, avoiding a slow deposition rate that would cause the deposited material to fill the gap at the bottom of the trench 200, affecting the structure and performance of subsequent devices. Moreover, due to the small gap size, the filling rate is fast and the cost is lower.
[0069] Optionally, refer to Figure 8During the filling process, if the second oxide film layer 600 is also formed above the semiconductor substrate 100 between adjacent trenches 200, due to the difference in deposition coverage between deposition on a plane and deposition within the trenches 200, the thickness of the second oxide film layer 600 formed above the trenches 200 and the second oxide film layer 600 formed above the semiconductor substrate 100 may be inconsistent, affecting the planarization of the structure. Therefore, this embodiment also includes a step of planarizing the interface after the formation of the second oxide film layer 600. Optionally, referring to... Figure 9 The structure can be planarized by chemical mechanical polishing to remove the excess oxide film layer on the structure until the oxide layer 300 above the trench 200 is exposed.
[0070] Example 2
[0071] This embodiment provides a trench isolation structure, which is formed using the preparation method of the trench isolation structure in Embodiment 1 above.
[0072] Specifically, refer to Figure 9 The trench isolation structure includes a semiconductor substrate 100, a trench 200, a seal 700, and a void structure 800. Optionally, the semiconductor substrate 100 includes a wafer and an epitaxial layer formed on the wafer, the epitaxial layer including the trench 200. In this embodiment, the wafer refers to a bare wafer, and the epitaxial layer can be formed by performing at least a partial thickness of N-type doping or P-type doping on the bare wafer, and the trench 200 is formed within the epitaxial layer. The trench 200 extends from the surface of the semiconductor substrate 100 toward the interior of the semiconductor substrate 100. A first oxide film layer 500 is formed on the trench sidewall 301 at the port of the trench 200. The seal 700 is located at the port of the trench 200 to close the port of the trench 200. The seal 700 includes a second oxide film layer 600 filling the gaps between the first oxide film layers 500. The void structure 800 is located within the trench 200 and below the seal 700.
[0073] Since the trench isolation structure in this embodiment is formed using the same preparation method as the trench isolation structure in Embodiment 1, its preparation process is simpler and its production cost is lower. Furthermore, the sealing height within the trench isolation structure occupies 1% to 4% of the trench depth, resulting in lower internal stress and reduced capacitance. The trench ends contain an oxide film layer formed using a low-temperature oxidation process, which further reduces internal stress, lowers capacitance, and enhances structural performance.
[0074] Example 3
[0075] This embodiment provides a semiconductor device comprising a semiconductor substrate, at least two functional device structures disposed on the semiconductor substrate, and a trench isolation structure disposed between adjacent functional device structures. The trench isolation structure is fabricated using the trench isolation structure of Embodiment 1 or the trench isolation structure of Embodiment 2, which has a simpler fabrication process and lower production cost. Furthermore, the sealing height within the trench isolation structure occupies 1% to 4% of the trench depth, resulting in lower internal stress. The trench ports contain an oxide film layer formed using a low-temperature oxide film process, further reducing internal stress, lower capacitance, and superior device performance.
[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a trench isolation structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including trenches; Filling the interior of the trench with a sacrificial layer includes: completely filling the interior of the trench with the sacrificial layer, etching back the sacrificial layer into the trench, and controlling the etching back depth to occupy a proportion of 1% to 4% of the trench depth to expose part of the trench sidewall at the port of the trench; A first oxide film layer is formed at least on the sidewall of the trench and above the sacrificial layer within the trench. The first oxide film layer includes a first portion and a second portion. The first portion is formed on the sidewall of the trench, and a gap is formed within the first portion that extends through the first portion along the depth direction of the trench. The second portion is formed at the bottom of the gap and on the sacrificial layer. A window is formed on the second portion, the window exposing a portion of the sacrificial layer; Remove the sacrificial layer within the trench based on the window; A second oxide film layer is filled into the gap within the first portion until the second oxide film layer completely fills the gap, forming a seal at the port of the trench.
2. The method for preparing the trench isolation structure according to claim 1, characterized in that, Before filling at least the interior of the trench with a sacrificial layer, the method further includes: An oxide layer is formed on the inner wall of the trench and on the surface of the semiconductor substrate.
3. The method for preparing the trench isolation structure according to claim 1, characterized in that, The sacrificial layer is a photoresist layer or a bottom anti-reflective coating.
4. The method for preparing the trench isolation structure according to claim 1, characterized in that, The step of forming a first oxide film layer at least over the exposed trench sidewalls and the sacrificial layer within the trench includes: The first oxide film layer is deposited using a low-temperature oxide film deposition process.
5. The method for preparing the trench isolation structure according to claim 1 or 4, characterized in that, The step of forming a first oxide film layer at least on the sidewalls of the trench and above the sacrificial layer within the trench includes: The thickness of the first part is greater than the thickness of the second part.
6. The method for preparing the trench isolation structure according to claim 1, characterized in that, The step of forming a window on the second part includes: The first oxide film layer located in the trench is etched using anisotropic etching, such that the lateral etching rate is less than the longitudinal etching rate, in order to remove at least a portion of the second portion and form the window.
7. The method for preparing the trench isolation structure according to claim 6, characterized in that, The step of etching the first oxide film layer located within the trench using anisotropic etching includes: Anisotropic etching of the first oxide film layer located in the trench is performed using a self-aligned method.
8. The method for preparing the trench isolation structure according to claim 1, characterized in that, The step of removing the sacrificial layer within the trench based on the window includes: The sacrificial layer is removed using wet etching and / or ashing processes.
9. The method for preparing the trench isolation structure according to claim 1, characterized in that, The step of filling the gaps within the first portion with the second oxide film layer until the second oxide film layer completely fills the gaps includes: The second oxide film layer is filled into the gaps within the first portion using a chemical vapor deposition process.
10. The method for preparing the trench isolation structure according to claim 1 or 9, characterized in that, The step of filling the gaps within the first portion with the second oxide film layer until the second oxide film layer completely fills the gaps includes: The deposition rate of the second oxide film is controlled to be between 2000 Å / min and 4000 Å / min.
11. The method for preparing the trench isolation structure according to claim 1, characterized in that, After the step of filling the gaps within the first portion with the second oxide film layer until the second oxide film layer completely fills the gaps, the method further includes: Planarize the interface where the second oxide film layer is located.
12. The method for preparing the trench isolation structure according to claim 1, characterized in that, The semiconductor substrate includes a wafer and an epitaxial layer formed on the wafer, the epitaxial layer including the trench.
13. A trench isolation structure, characterized in that, The trench isolation structure is formed by the method for preparing the trench isolation structure according to any one of claims 1 to 12, and the trench isolation structure comprises: Semiconductor substrate; The trench extends from the surface of the semiconductor substrate toward the interior of the semiconductor substrate; a first oxide film layer is formed on the trench sidewall at the port of the trench; A seal is located at the port of the trench to close the port of the trench; the seal includes a second oxide film layer filling the gaps between the first oxide film layers; A void structure is located below the seal within the trench.
14. The trench isolation structure according to claim 13, characterized in that, The height of the seal occupies 1% to 4% of the depth of the trench.
15. A semiconductor device, characterized in that, The semiconductor device includes the trench isolation structure according to any one of claims 13 to 14.