Micro-channel packaging structure based on cooling liquid cooling and packaging method thereof

Abstract

The application belongs to the technical field of integrated circuit packaging, and particularly relates to a micro-flow channel packaging structure based on cooling liquid cooling and a packaging method thereof. The packaging structure comprises a packaging body, a plurality of recesses are symmetrically arranged on the upper and lower surfaces of the packaging body, functional chips are attached in the recesses, and the active pads of the functional chips are directed to the outside; a metal wiring layer is arranged on the surface of each functional chip; a through silicon via is vertically arranged on the left and right sides of the packaging body, and the through silicon via is filled with a copper layer to form a through silicon via structure, and the metal wiring layers on the upper and lower sides are connected through the through silicon via structure; and a micro-flow channel groove is arranged between the functional chips on the upper and lower sides along the left-right direction, and the two ends of the micro-flow channel groove extend in the vertical direction and are exposed to the outside. The application introduces liquid helium to increase the heat dissipation effect of double-sided chips, and realizes double-sided interconnection through the through silicon via structure, thereby improving the integration degree and effectively solving the heat dissipation problem of high-performance chips.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit packaging technology, and particularly relates to a micro-channel packaging structure based on cooling liquid cooling and a packaging method thereof. BACKGROUND

[0002] With the rapid development of modern electronic equipment, miniaturization has become the mainstream trend of the development of modern electronic equipment, and the feature size of electronic devices is continuously reduced. As a core component, the size of the chip is continuously reduced, and the performance is continuously improved, and the heat dissipation problem is increasingly prominent. Efficient heat dissipation technology has become one of the key factors to ensure stable operation and prolong the service life of the chip. The commonly used heat dissipation scheme is micro-channel. This heat dissipation structure is to prepare a micro-channel on the back of the packaging structure, and to realize chip heat dissipation by increasing the heat dissipation area. Under the current condition of high-density integration, the conventional micro-channel heat dissipation is not suitable for high heat flux chips. SUMMARY

[0003] The purpose of the present application is to provide a micro-channel packaging structure based on cooling liquid cooling and a packaging method thereof, which forms a closed micro-channel passage through wafer bonding, increases the heat dissipation effect of double-sided chips by passing in liquid helium, and realizes double-sided interconnection by using a through-silicon via structure, thereby effectively solving the heat dissipation problem of high-performance chips while improving the integration level.

[0004] To solve the above technical problems, the present application provides a micro-channel packaging structure based on cooling liquid cooling, comprising:

[0005] a packaging body, a plurality of grooves are symmetrically formed on the upper and lower surfaces of the packaging body, and functional chips are attached in the grooves, with the active pads of the functional chips facing the outside;

[0006] a metal wiring layer, which is arranged on the surfaces of the functional chips on the upper and lower sides, respectively;

[0007] a through-silicon via, which is vertically formed on the left and right sides of the packaging body, respectively, and is filled with a copper layer to form a through-silicon via structure, and the metal wiring layers on the upper and lower sides are connected through the through-silicon via structure;

[0008] a micro-channel groove, which is formed between the functional chips on the upper and lower sides along the left-right direction, and the two ends of the micro-channel groove extend vertically to the outside to form an inlet and an outlet for the circulation of liquid helium cooling liquid;

[0009] wherein the distance between the micro-channel groove and the functional chips on the upper and lower sides in the vertical direction is 10-50 microns, and the opening width and opening distance of the micro-channel groove are 10-500 microns.

[0010] Preferably, the groove is a straight groove or an inclined groove, the cross section of the groove is rectangular or trapezoidal, and the depth of the groove is adapted to the size of the packaged chip.

[0011] Preferably, an insulating layer is further included, which is deposited on the inner wall surface of the groove, the upper and lower surfaces of the package, and the inner wall surface of the through silicon via, respectively.

[0012] Preferably, an adhesive layer is further included, by which the functional chip is attached and mounted in the groove.

[0013] Preferably, a filling layer is further included, which fills the gap between the groove and the functional chip, and covers the insulating layer on the upper and lower surfaces of the package; the filling layer is a polyamide, or a polyimide and a resin high polymer.

[0014] Preferably, the functional chip is a high-density I / O interface chip, the metal wiring layer is a multi-layer wiring structure, the cross section of the micro-channel groove is rectangular, triangular, trapezoidal, semicircular, drop-shaped or needle-shaped, and the groove wall of the micro-channel groove further includes turbulence protrusions uniformly arranged along an S-shaped path.

[0015] Preferably, a metal layer pad and a bump are further included, which are arranged on the upper and lower metal wiring layers, respectively, and the metal layer pad and the bump are arranged one by one in the vertical direction.

[0016] Preferably, a solder resist layer is further included, which covers the upper and lower surfaces of the package, and has a plurality of openings, so that the metal layer pad and the bump are exposed at the openings.

[0017] Preferably, the package is assembled by wafer-level bonding process using two silicon substrates arranged in upper and lower positions.

[0018] The application further provides a packaging method of the micro-channel packaging structure based on cooling liquid cooling.

[0019] Step S1: etching a groove on the surface of the silicon substrate one, and depositing an insulating layer on the inner wall of the groove;

[0020] Step S2: etching a through silicon via on the surface of the silicon substrate one, and depositing an insulating layer on the inner wall of the through silicon via;

[0021] Step S3: mounting a functional chip in the groove through an adhesive layer, and the active pad of the functional chip faces outward;

[0022] Step S4: filling of the filling layer in the groove, opening the position of the active pad and the through silicon via by a photolithography process;

[0023] Step S5: after filling copper in the through silicon via, metal wiring is formed to form a metal wiring layer;

[0024] Step S6: the metal wiring layer is temporarily bonded to the carrier through temporary bonding glue;

[0025] Step S7: the back through silicon via is exposed by back thinning, etching and chemical mechanical polishing processes;

[0026] Step S8: a micro-channel groove is etched on the surface away from the metal wiring layer by dry etching;

[0027] Step S9: the carrier is removed, the temporary bonding glue is cleaned, and the bump is made on the metal wiring layer by disassembling and bonding;

[0028] Step S10: steps S1 to S7 are repeated to expose the back through silicon via of another silicon substrate two;

[0029] Step S11: the micro-channel groove of the silicon substrate two is etched by dry etching, and the position corresponds to the micro-channel groove on the silicon substrate one;

[0030] Step S12: the carrier is removed, the temporary bonding glue is cleaned, and the metal layer pad corresponding to the bump is made on the metal wiring layer by disassembling and bonding;

[0031] Step S13: the silicon substrate one and the silicon substrate two are assembled by wafer-level bonding process, and the packaging structure is finally completed.

[0032] Compared with the prior art, the present application has the following beneficial effects:

[0033] 1. The present invention further enhances the heat dissipation effect by circulating liquid helium coolant in a microfluidic structure that increases the specific surface area to achieve heat dissipation. Furthermore, the present invention shortens the path for heat conduction from the chip interior to the cooling fluid by providing a vertical spacing of 10 μm to 50 μm between the microfluidic grooves and the upper and lower functional chips. This inventive range of values ​​improves heat conduction efficiency and reduces temperature gradients, which is beneficial for chip heat dissipation and avoids local overheating. Simultaneously, the microfluidic grooves have a width and spacing of 10 μm to 500 μm, which optimizes the flow state of the fluid within the grooves, reduces fluid resistance, and increases fluid flow rate, thereby enhancing the heat dissipation effect, thereby ensuring sufficient heat dissipation area while avoiding excessive fluid resistance. Furthermore, the cross-sectional shape of the microfluidic grooves is rectangular, triangular, trapezoidal, semicircular, teardrop-shaped, or needle-like, and the microfluidic groove walls further include flow-disturbing protrusions evenly distributed along an S-shaped path. In the microfluidic grooves, the fluid temperature gradually increases along the length of the channel, forming a thermal boundary layer. By controlling the size and shape of the grooves, the fluid boundary layer can be broken and the turbulence of the fluid flow can be increased to enhance the convective heat transfer effect.

[0034] 2. The present invention connects double-sided chips through a through-silicon via structure to achieve double-sided wiring, thereby improving device integration and reliability and reducing package size.

[0035] 3. The microchannel structure of the present invention is located on the back of the double-sided active chip, which has high heat dissipation efficiency and does not require an additional heat dissipation structure. It reduces the package volume while increasing the chip integration and reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a schematic diagram of etching a groove on a surface of a silicon substrate according to the present invention.

[0037] Figure 2 It is a schematic diagram of etching a through silicon via on a surface of a silicon substrate according to the present invention.

[0038] Figure 3 This is a schematic diagram of mounting a chip in a groove according to the present invention.

[0039] Figure 4 This is a schematic diagram of filling a filling layer in a groove according to the present invention.

[0040] Figure 5 Schematic diagram of copper filling of through silicon vias according to the present invention.

[0041] Figure 6 This is a schematic diagram of temporarily bonding the metal wiring layer to the carrier according to the present invention.

[0042] Figure 7 This is a schematic diagram of thinning the back surface until the through-silicon vias are exposed according to the present invention.

[0043] Figure 8 Schematic diagram of etching microchannel grooves according to the present invention.

[0044] Figure 9 This is a schematic diagram of the present invention's method of removing bonds and making bumps on a metal wiring layer.

[0045] Figure 10 This is a schematic diagram of the present invention completing the exposure of the through silicon via on the back side of the silicon substrate.

[0046] Figure 11 This is a schematic diagram of etching microchannel grooves on a silicon substrate by dry etching according to the present invention.

[0047] Figure 12 This is a schematic diagram of manufacturing a metal layer pad according to the present invention.

[0048] Figure 13 This is a schematic diagram of the packaging structure completed by wafer bonding assembly in the present invention.

[0049] In the figure: 1-package, 101-silicon substrate 1, 102-silicon substrate 2, 2-groove, 3-functional chip, 31-active pad, 4-metal wiring layer, 5-through silicon via, 6-microchannel groove, 61-liquid inlet, 62-liquid outlet, 7-insulating layer, 8-adhesive layer, 9-filling layer, 10-metal layer pad, 11-bump, 12-solder mask layer, 13-carrier, 14-temporary bonding glue. DETAILED DESCRIPTION

[0050] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention. Example 1

[0051] like Figure 13 As shown, an embodiment of the present invention provides a microfluidic package structure based on coolant cooling, including:

[0052] The package body 1 has a plurality of grooves 2 symmetrically formed on the upper and lower surfaces of the package body 1. The functional chip 3 is mounted in the groove 2 with the active pads 31 of the functional chip 3 facing outwards.

[0053] Metal wiring layers 4 are respectively arranged on the surfaces of the upper and lower functional chips 3;

[0054] Through-silicon vias 5 are vertically opened on the left and right sides of the package body 1, and the through-silicon vias 5 are filled with a copper layer to form a through-silicon via structure, through which the metal wiring layers 4 on the upper and lower sides are connected;

[0055] Micro-channel grooves 6 are provided between the upper and lower functional chips 3 in the left-right direction, and the two ends of the micro-channel grooves 6 extend in the vertical direction to be exposed to the outside to form a liquid inlet 61 and a liquid outlet 62 for circulating liquid helium cooling liquid.

[0056] The narrower the width of the micro-channel grooves 6, the faster the cooling liquid flows, and the better the heat dissipation effect, but at the same time, the flow resistance is increased, resulting in an increase in pump work. The groove width is too wide, which will also affect the temperature distribution. Similarly, the groove spacing also has an effect on the flow characteristics and heat transfer performance of the cooling liquid. The smaller the groove spacing, the higher the flowability and heat transfer performance of the cooling liquid. Therefore, the width and spacing of the micro-channel grooves 6 are 10-500 μm. The smaller the spacing between the micro-channel grooves 6 and the functional chips 3, the higher the heat conduction efficiency and the smaller the temperature gradient, which is beneficial to chip heat dissipation and avoids local overheating. However, reducing the spacing will increase the difficulty and cost of the manufacturing process. The relationship between heat dissipation performance and manufacturing cost needs to be balanced, and the optimal spacing value is selected. Therefore, the spacing between the micro-channel grooves 6 and the upper and lower functional chips 3 in the vertical direction is 10-50 μm.

[0057] The groove 2 is a straight groove or an inclined groove structure, and the cross section of the groove 2 is rectangular or trapezoidal. The depth of the groove 2 is matched with the size of the packaged chip, and the range is within 10 μm.

[0058] The insulating layer 7 is further included, which is deposited on the inner wall surface of the groove 2, the upper and lower surfaces of the package 1, and the inner wall surface of the through silicon via 5.

[0059] The adhesive layer 8 is further included, which is used to adhere and mount the functional chip 3 in the groove 2.

[0060] The filling layer 9 is further included, which is filled in the gap between the groove 2 and the functional chip 3, and covers the insulating layer 7 on the upper and lower surfaces of the package 1. The filling layer 9 is a polyamide, or a polyimide and a resin high polymer.

[0061] The functional chip 3 is a high-density I / O interface chip, and the metal wiring layer 4 is a multi-layer wiring structure. For high-density I / O interface chips, multi-layer wiring can be used, that is, an additional passivation layer is added, and a second metal redistribution layer is redistributed on the passivation layer. This can effectively reduce the package size.

[0062] The cross-sectional shape of the micro-channel groove 6 is rectangular, triangular, trapezoidal, semicircular, water-drop-shaped or needle-imitated-shaped, different shapes have different effects on heat dissipation and fluid pressure drop, and need to be considered comprehensively. The groove wall of the micro-channel groove 6 further includes turbulence protrusions uniformly arranged along the S-shaped path. In the micro-channel groove, the fluid temperature gradually rises along the length direction of the channel, forming a thermal boundary layer. By controlling the size and shape of the groove, the fluid boundary layer can be broken, and the turbulence degree of fluid flow can be enhanced to strengthen the convective heat transfer effect.

[0063] The metal layer pad 10 and the bump 11 are arranged on the upper and lower metal wiring layers 4 respectively, and the metal layer pad 10 and the bump 11 are arranged one by one in the vertical direction.

[0064] The solder resist layer 12 is further included, which covers the upper and lower surfaces of the package 1, and the solder resist layer 12 has a plurality of openings so that the metal layer pad 10 and the bump 11 are exposed at the openings.

[0065] The package 1 is assembled by wafer-level bonding process of two upper and lower silicon substrates 101 and 102. Embodiment two

[0066] As shown in Figures 1 to 13 The application further provides a packaging method of the micro-channel packaging structure based on cooling liquid cooling, which prepares the micro-channel packaging structure based on cooling liquid cooling as described above, and includes the following steps:

[0067] Step S1: etching the groove 2 on the surface of the silicon substrate 101, and depositing the insulating layer 7 on the inner wall of the groove 2;

[0068] Step S2: etching the through silicon via 5 on the surface of the silicon substrate 101, and depositing the insulating layer 7 on the inner wall of the through silicon via 5;

[0069] Step S3: attaching the functional chip 3 in the groove 2 through the adhesive layer 8, and the active pad 31 of the functional chip 3 faces outward;

[0070] Step S4: filling the filling layer 9 in the groove 2, and opening the positions of the active pad 31 and the through silicon via 5 through the photoetch process;

[0071] Step S5: after filling copper in the through silicon via 5, forming the metal wiring layer 4 by metal wiring;

[0072] Step S6: temporarily bonding the end face of the metal wiring layer 4 with the carrier 13 through the temporary bonding glue 14; the material of the carrier 13 can be silicon or glass, and the size can be wafer level or board level;

[0073] Step S7: expose the backside through hole 5 by backside thinning, etching and chemical mechanical polishing process;

[0074] Step S8: then deposit an insulating layer 7 on the surface, etch the micro channel groove 6 on the surface away from the metal wiring layer 4 by dry etching;

[0075] Step S9: disassemble the bonding, remove the carrier 13, clean the temporary bonding glue 14, and make the bump 11 on the metal wiring layer 4;

[0076] Step S10: repeat the above steps S1 to S7 to expose the backside through hole 5 of the other silicon substrate two 102;

[0077] Step S11: etch the micro channel groove 6 of the silicon substrate two 102 by dry etching, and correspond to the position of the micro channel groove 6 on the silicon substrate one 101;

[0078] Step S12: disassemble the bonding, remove the carrier 13, clean the temporary bonding glue 14, and make the metal layer pad 10 corresponding to the bump 11 on the metal wiring layer 4; for connecting capacitor, resistor and other electrical components;

[0079] Step S13: assemble the silicon substrate one 101 and the silicon substrate two 102 by wafer level bonding process, connect the through hole structure and the double-sided micro channel groove 6 by wafer bonding, realize the transmission of electrical signal and the in and out and circulation of cooling liquid, and finally complete the packaging structure.

[0080] The above description is only a description of the preferred embodiment of the present application, and is not any limitation on the scope of the present application. Any modification or modification made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A microfluidic packaging structure based on coolant cooling, characterized in that: include: A package body, wherein a plurality of grooves are symmetrically formed on the upper and lower surfaces of the package body, and a functional chip is mounted in the groove with the active pads of the functional chip facing outward; Metal wiring layers are respectively arranged on the surfaces of the functional chips on the upper and lower sides; Through-silicon vias (TSVs) are vertically opened on the left and right sides of the package body, and the TSVs are filled with a copper layer to form a TSV structure, through which the metal wiring layers on the upper and lower sides are connected; A microfluidic groove is formed in an S-shaped path along the left-right direction and is opened between the functional chips on the upper and lower sides, and both ends of the microfluidic groove extend in the vertical direction and are exposed to the outside to form a liquid inlet and a liquid outlet for the circulation of liquid helium coolant; The vertical distance between the microchannel groove and the functional chips on the upper and lower sides is 10 μm to 50 μm; the width and spacing of the microchannel groove are 10 μm to 500 μm.

2. The microfluidic package structure based on coolant cooling according to claim 1, characterized in that: The groove is a straight groove or an oblique groove structure, and the cross-sectional shape of the groove is a rectangle or a trapezoid; and the depth of the groove is adapted to the size of the packaged chip.

3. The micro-channel packaging structure based on coolant cooling according to claim 1, characterized in that: The invention also includes an insulating layer, which is deposited on the inner wall surface of the groove, the upper and lower surfaces of the package body, and the inner wall surface of the through silicon via.

4. The micro-channel packaging structure based on coolant cooling according to claim 1, characterized in that: It also includes an adhesive layer, through which the functional chip is bonded and mounted in the groove.

5. The micro-channel packaging structure based on coolant cooling according to claim 3, characterized in that: It also includes a filling layer, which fills the gap between the groove and the functional chip, and covers the insulating layer at the upper and lower surfaces of the package body; wherein the filling layer is a polyamide, or polyimide and resin polymer.

6. The micro-channel packaging structure based on coolant cooling according to claim 1, characterized in that: The functional chip is a high-density I / O interface chip, and the metal wiring layer is a multi-layer wiring structure. The cross-sectional shape of the microchannel groove is rectangular, triangular, trapezoidal, semicircular, teardrop-shaped or needle-shaped, and the groove wall of the microchannel groove also includes flow-disturbing protrusions evenly distributed along an S-shaped path.

7. The micro-channel packaging structure based on coolant cooling according to claim 1, characterized in that: It also includes metal layer pads and bumps, which are respectively arranged on the upper and lower sides of the metal wiring layer, and the metal layer pads and the bumps are arranged in a one-to-one correspondence in the vertical direction.

8. The micro-channel packaging structure based on coolant cooling according to claim 7, characterized in that: The package further comprises a solder resist layer, which covers the upper and lower surfaces of the package body and has a plurality of openings, so that the metal layer pads and the bumps are exposed at the openings.

9. The micro-channel packaging structure based on coolant cooling according to claim 1, characterized in that: The package body is assembled by a wafer-level bonding process using two silicon substrates, a first silicon substrate and a second silicon substrate, which are arranged one above the other.

10. A packaging method for a microfluidic packaging structure based on coolant cooling, characterized in that: Preparation of a microfluidic package structure based on coolant cooling according to any one of claims 1 to 9 comprises the following steps: Step S1: etching a groove on a surface of a silicon substrate and depositing an insulating layer on the inner wall of the groove; Step S2: etching a through-silicon via on a surface of the silicon substrate and depositing an insulating layer on the inner wall of the through-silicon via; Step S3: mounting the functional chip in the groove through the adhesive layer, with the active pad of the functional chip facing outward; Step S4: Filling the groove with a filling layer, and opening the positions of the active pad and the through-silicon via by a photolithography process; Step S5: After the through silicon via is filled with copper, metal wiring is performed to form a metal wiring layer; Step S6: temporarily bonding the metal wiring layer to the carrier using a temporary bonding adhesive; Step S7: exposing the back-side through-silicon vias through back-side thinning, etching, and chemical mechanical polishing processes; Step S8: etching a microchannel groove on the surface away from the metal wiring layer by dry etching; Step S9: Debonding, removing the carrier, cleaning the temporary bonding glue, and making bumps on the metal wiring layer; Step S10: repeating the above steps S1 to S7 to complete the exposure of the back side through silicon via of another silicon substrate 2; Step S11: dry-etching the microchannel grooves on the second silicon substrate so that the positions thereof correspond to the microchannel grooves on the first silicon substrate; Step S12: Debonding, removing the carrier, cleaning the temporary bonding glue, and making metal layer pads corresponding to the bumps on the metal wiring layer; Step S13: Assemble the first silicon substrate and the second silicon substrate through a wafer-level bonding process to finally complete the packaging structure.

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