Interconnection structure, preparation method thereof and passive device

Abstract

The invention provides an interconnection structure, a preparation method thereof and a passive device, belongs to the technical field of semiconductor packaging, and can solve the problem that a substrate of an existing interconnection structure is easy to crack. The interconnection structure disclosed by the invention comprises a substrate and a plurality of conductive columns, a plurality of through holes penetrating through the substrate are formed in the substrate; the conductive columns are filled in the through holes; the height of the conductive column is smaller than the depth of the through hole; the interconnection structure further comprises a first buffer layer and a first conductive layer. The first buffer layer is positioned on one side of the substrate and is filled in the through hole; the first conductive layer is located on the side, away from the substrate, of the first buffer layer; the first conductive layer is connected with the conductive column through a first via hole penetrating through the first buffer layer.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor packaging technology, specifically relating to an interconnect structure and its fabrication method, and passive devices. Background Technology

[0002] As semiconductor manufacturing processes advance towards deep submicron and nanometer scales, traditional photolithography is gradually approaching its limits. Increasing the number of transistors and shrinking feature sizes in integrated circuits is becoming increasingly slow and difficult, posing a significant challenge to the continuation of Moore's Law. Simultaneously, the interconnection delay problem caused by long signal transmission distances in traditional packaging is becoming increasingly severe, making it difficult to meet the requirements of high-speed and low-power chips. To overcome the challenges faced by integrated circuits and traditional packaging, 3D integration technology has emerged.

[0003] Through Silicon Via (TSV) technology is considered one of the most promising technologies for achieving 3D integration. TSV technology enables direct interconnection between chips by creating vertical through-holes between chips and wafers. It maximizes chip stacking density in three dimensions, minimizes interconnect lines, and reduces overall size, significantly improving chip speed and reducing power consumption, thus becoming one of the most attractive technologies in electronic packaging. However, silicon is a semiconductor material, and charge carriers around TSVs can move freely under the influence of electric or magnetic fields, affecting nearby circuits or signals and impacting chip performance. Glass, on the other hand, has no freely moving charges, excellent dielectric properties, and a coefficient of thermal expansion (CTE) close to that of silicon. Through Glass Via (TGV) technology, which uses glass instead of silicon, avoids the problems of TSVs and is an ideal solution for 3D integration. Furthermore, TGV technology eliminates the need for an insulating layer, reducing process complexity and manufacturing costs. TGV and related technologies have broad application prospects in optical communication, radio frequency, microwave, microelectromechanical systems (MEMS), microfluidic devices, and 3D integration.

[0004] However, copper is generally used as the conductive pillar in TGS. Since the coefficient of thermal expansion of copper differs from that of glass by a factor of 6, the difference in volume expansion during heat treatment or process at temperatures above 200°C can lead to cracking, especially at stress concentration points. This can result in process failure, damage to equipment hardware, low yield, and device failure. Summary of the Invention

[0005] This disclosure aims to at least solve one of the technical problems existing in the prior art, and provides an interconnect structure and its fabrication method, as well as a passive device.

[0006] In a first aspect, embodiments of this disclosure provide an interconnect structure, wherein the interconnect structure includes: a substrate and a plurality of conductive pillars; a plurality of through-holes are formed on the substrate; the conductive pillars fill the through-holes; the height of the conductive pillars is less than the depth of the through-holes; the interconnect structure further includes: a first buffer layer and a first conductive layer;

[0007] The first buffer layer is located on one side of the substrate and fills the through-hole;

[0008] The first conductive layer is located on the side of the first buffer layer that is away from the substrate.

[0009] The first conductive layer is connected to the conductive post through a first through-hole penetrating the first buffer layer.

[0010] In some embodiments, the interconnect structure further includes: a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, and a third insulating layer located on the side of the first conductive layer opposite to the substrate.

[0011] The first conductive layer is connected to the third conductive layer through a second via that penetrates the first insulating layer and the second insulating layer;

[0012] The second conductive layer is connected to the third conductive layer through a third via penetrating the second insulating layer;

[0013] The third conductive layer is exposed through a fourth via that penetrates the third insulating layer.

[0014] In some embodiments, the interconnect structure further includes: a second buffer layer and a fourth conductive layer;

[0015] The second buffer layer is located on the side of the substrate away from the first conductive layer and fills the via.

[0016] The fourth conductive layer is located on the side of the second buffer layer that is away from the substrate.

[0017] The fourth conductive layer is connected to the conductive post through a fifth through-hole that penetrates the second buffer layer.

[0018] In some embodiments, the interconnect structure further includes: a fourth conductive layer;

[0019] The fourth conductive layer is located on the side of the substrate opposite to the first conductive layer and is connected to the conductive pillar.

[0020] In some embodiments, the first via includes: a plurality of first sub-vias;

[0021] The first conductive layer is connected to the conductive pillar through a plurality of first sub-vias.

[0022] In some embodiments, the fifth via includes: a plurality of fifth sub-vias;

[0023] The fourth conductive layer is connected to the conductive pillar through multiple fifth sub-vias.

[0024] Secondly, embodiments of this disclosure provide a passive device, wherein the passive device includes the interconnection structure provided above.

[0025] Thirdly, embodiments of this disclosure provide a method for fabricating an interconnect structure, wherein the method for fabricating the interconnect structure includes:

[0026] Forming through-holes on the substrate;

[0027] The through hole is filled with a conductive pillar; the height of the conductive pillar is less than the depth of the through hole.

[0028] A buffer layer is formed on one side of the substrate.

[0029] At the via, the buffer layer is etched to form a first via to expose the conductive pillar;

[0030] A first conductive layer is formed on the buffer layer, such that the first conductive layer is connected to the conductive post through the first via.

[0031] In some embodiments, forming a through-hole on the substrate includes:

[0032] A first etching is performed on the first surface of the substrate to form a pre-via on the first surface;

[0033] A second etching is performed on the second surface of the substrate to form a through hole at the position corresponding to the pre-via; the second surface is disposed opposite to the first surface.

[0034] In some embodiments, the through-hole is filled with a conductive pillar, including:

[0035] A seed layer is formed by sputtering a first metal inside the through-hole, on the first surface and the second surface;

[0036] A second metal is deposited on the seed layer within the through-hole to form a conductive pillar; the conductive pillar is at a certain distance from both the first surface and the second surface;

[0037] The seed layers on the first surface and the second surface are ground to remove the seed layers on the first surface and the second surface.

[0038] In some embodiments, forming a through-hole on the substrate includes:

[0039] A first etching is performed on the first surface of the substrate to form a pre-via.

[0040] The second surface of the substrate is ground to expose the pre-via to form the via; the second surface is disposed opposite to the first surface.

[0041] In some embodiments, the through-hole is filled with a conductive pillar, including:

[0042] A seed layer is formed by sputtering a first metal inside the through-hole and on the first surface;

[0043] A second metal is deposited on the seed layer within the through-hole to form a conductive pillar; the conductive pillar is located at a certain distance from the first surface.

[0044] The seed layer on the first surface is ground to remove the seed layer on the first surface. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of an exemplary interconnection structure.

[0046] Figure 2 This is a schematic diagram of another exemplary interconnection structure.

[0047] Figure 3 This is a schematic diagram of an interconnection structure provided in an embodiment of the present disclosure.

[0048] Figure 4 This is a schematic diagram of another interconnection structure provided in an embodiment of the present disclosure.

[0049] Figure 5 This is a schematic diagram of another interconnection structure provided in an embodiment of the present disclosure.

[0050] Figure 6 This is a schematic diagram of another interconnection structure provided in an embodiment of the present disclosure.

[0051] Figure 7 This is a schematic flowchart illustrating a method for fabricating an interconnect structure according to an embodiment of the present disclosure.

[0052] Figures 8a to 8i This is a schematic diagram of the intermediate structure of each step in the preparation method of an interconnect structure provided in this embodiment.

[0053] Figures 9a to 9j This is a schematic diagram of the intermediate structure of each step in another method for preparing an interconnect structure provided in this embodiment. Detailed Implementation

[0054] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0056] Figure 1 This is a schematic diagram of an exemplary interconnection structure. Figure 2 Here is a schematic diagram of another exemplary interconnection structure, such as... Figure 1 and Figure 2 As shown, the interconnect structure includes: a substrate 101 and a plurality of conductive pillars 102; a plurality of through holes V are formed on the substrate 101, penetrating the substrate 101; the conductive pillars 102 fill the through holes V. The conductive pillars 102 generally fill the entire through hole V, that is, the two ends of the conductive pillars 102 are respectively flush with the two surfaces of the substrate 101, so that the two ends of the conductive pillars 102 are exposed to connect with other signal lines and electronic devices.

[0057] Figure 2 and Figure 1 The difference in the interconnection structure shown is that, Figure 1 In the interconnect structure shown, the via V is formed by simultaneously etching the upper and lower surfaces, and its overall shape is such that the diameter is smaller in the middle and larger at both ends. Figure 2 In the interconnect structure shown, the via V is formed by single-sided etching, and the overall shape layer has a larger aperture at one end and a smaller aperture at the other end.

[0058] It should be noted that in the above interconnect structure, the substrate 101 can be a silicon substrate or a glass substrate, both of which have essentially the same coefficient of thermal expansion. The conductive pillars 102 generally use copper as the filler material. In the following description, an interconnect structure composed of a glass substrate and copper will be used as an example; the implementation principle of an interconnect structure composed of a silicon substrate and copper is similar and will not be detailed further.

[0059] Because the coefficients of thermal expansion of copper and glass differ by a factor of 6, during heat treatment or manufacturing processes at temperatures above 200°C, the difference in volume expansion can lead to cracking, especially at stress concentration points (the edges of through-holes V), which can cause the process to fail, damage equipment hardware, or result in low yield and device failure.

[0060] Understandable Figure 1 In the interconnect structure shown, because the diameters at both ends of the through-hole V are relatively large, the stress concentration points are located at the edges of both ends. Figure 2 In the interconnection structure shown, since the diameter of the other end of the through hole V is smaller, the stress concentration is not obvious, and the stress concentration is mainly located at the edge of one end.

[0061] To at least solve one of the above-mentioned technical problems, this disclosure provides an interconnect structure and its fabrication method, as well as a passive device. The interconnect structure, its fabrication method, and the passive device provided in this disclosure will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0062] Firstly, embodiments of this disclosure provide an interconnection structure. Figure 3 This is a schematic diagram of an interconnection structure provided in an embodiment of the present disclosure, such as... Figure 3 As shown, the interconnect structure includes: a substrate 101 and a plurality of conductive pillars 102; a plurality of through holes V are formed on the substrate 101; the conductive pillars 102 are filled in the through holes V; the height of the conductive pillars 102 is less than the depth of the through holes V; the interconnect structure also includes: a first buffer layer 103 and a first conductive layer 104; the first buffer layer 103 is located on the substrate 101 and is filled in the through holes V; the first conductive layer 104 is located on the side of the first buffer layer 103 away from the substrate 101; the first conductive layer 104 is connected to the conductive pillars 102 through a first via V1 penetrating the first buffer layer 103.

[0063] The substrate 101 can be a glass substrate, which can effectively support other structures on it. Simultaneously, the glass substrate is transparent, allowing clear observation of the location where the via V is formed. When etching the via V on both sides, it helps avoid misalignment that could cause the via V to fail. It is understood that the substrate 101 can also be made of other insulating materials such as silicon substrates; the implementation principle is similar and will not be detailed further. The depth of the via V is the thickness of the substrate 101.

[0064] The conductive post 102 can be made of copper. It can connect different electrical devices on both sides of the substrate 101 to transmit signals and achieve interconnection. Since the conductive post 102 directly fills the via V, the trace distance between different devices on both sides of the substrate 101 can be reduced, avoiding interconnection delay problems caused by excessive trace distance. It is understood that the conductive post 102 can also be made of other metal materials or alloy materials with good conductivity, which will not be listed here.

[0065] The height of the conductive post 102 is less than the depth of the via V, that is, less than the thickness of the substrate 101. The conductive post 102 cannot fill the entire via V. This can prevent the conductive post 102 from contacting the edge of the via V and prevent the problem of excessive stress concentration.

[0066] The first buffer layer 103 can be made of organic materials such as optical adhesives and resins, and has strong buffering properties. The first buffer layer 103 is located on the substrate 101 and fills the through-hole V. It can cover the edge of the through-hole V, which can alleviate the stress generated during preparation and transportation, and avoid stress concentration at the edge of the through-hole V. To facilitate the formation of the first via V1 on the first buffer layer 103, the first buffer layer 103 can be made of photosensitive materials such as optical adhesives.

[0067] The first conductive layer 104 can be connected to the conductive pillar 102 through a first via V1 penetrating the first buffer layer 103. Since the height of the conductive pillar 102 is less than the depth of the via V, the first conductive layer 104 can act as a lead to guide the conductive pillar 102 out to connect with other electrical devices on the substrate 101. Simultaneously, the first buffer layer 103 can be disposed between the first conductive layer 104 and the substrate 101 to prevent the substrate 101 from cracking due to a large difference in thermal expansion coefficients between the first conductive layer 104 and the substrate 101, thus affecting signal transmission and semiconductor packaging performance. The first conductive layer 104 can be formed as a copper metal layer using electrochemical deposition. When applied in a display substrate, the first conductive layer 104 can specifically be the first gate conductive layer in the display substrate, which can be used as a gate line and the first electrode of a storage capacitor.

[0068] In the interconnect structure provided in this disclosure, the height of the conductive post 102 is less than the depth of the via V, which avoids direct contact between the conductive post 102 and the edge of the via V in the substrate 101, thus preventing stress concentration at the edge of the via V. Simultaneously, the first buffer layer 103 covers the edge of the via V, and the conductive post 102 is led out through the first conductive layer 104. The first buffer layer 103 can be disposed between the first conductive layer 104 and the substrate 101, preventing the substrate 101 from cracking due to a large difference in thermal expansion coefficients between the first conductive layer 104 and the substrate 101. This improves signal transmission and semiconductor packaging performance.

[0069] like Figure 3 As shown, the interconnect structure further includes: a first insulating layer 105, a second conductive layer 106, a second insulating layer 107, a third conductive layer 108, and a third insulating layer 109 located on the side of the first conductive layer 104 facing away from the substrate 101; the first conductive layer 104 is connected to the third conductive layer 108 through a second via V2 penetrating the first insulating layer 105 and the second insulating layer 107; the second conductive layer 106 is connected to the third conductive layer 108 through a third via V3 penetrating the second insulating layer 107; and the third conductive layer 108 is exposed through a fourth via V4 penetrating the third insulating layer 109.

[0070] The first insulating layer 105 can cover the first conductive layer 104, preventing short circuits between the first conductive layer 104 and other electrical components. The first insulating layer 105 can be made of one or more materials such as silicon nitride, silicon oxide, and silicon oxynitride. When applied in a display substrate, the first insulating layer 105 can specifically be the first gate insulating layer in the display substrate.

[0071] The second conductive layer 106 can be made of the same material and have the same fabrication process as the first conductive layer 104 to reduce the complexity of the process and save on fabrication costs. For example, a copper metal layer can be formed by electrochemical deposition. When applied in a display substrate, the second conductive layer 106 can be the second gate conductive layer in the display substrate, which can be used as the second electrode of a storage capacitor. The second conductive layer 106 and the first conductive layer 104 are not connected, but their orthogonal projections on the substrate 101 overlap to form a storage capacitor.

[0072] The second insulating layer 107 can cover the second conductive layer 106, preventing short circuits between the second conductive layer 106 and other electrical components. The second insulating layer 107 can be made of organic materials such as polyimide (PI), or one or more of materials such as silicon nitride, silicon oxide, and silicon oxynitride. When applied in a display substrate, the second insulating layer 107 can specifically be the second gate insulating layer in the display substrate.

[0073] The third conductive layer 108 can be made of the same material and have the same fabrication process as the first conductive layer 104 to reduce the complexity of the process and save on fabrication costs. For example, a copper metal layer can be formed by electrochemical deposition. When applied in a display substrate, the third conductive layer 108 can be the source / drain conductive layer in the display substrate, and it can be used as a signal line such as a data line. The third conductive layer 108 is connected to the first conductive layer 104 and the second conductive layer 106 through the second via V2 and the third via V3, respectively, and introduces the signal to the first conductive layer 104 and the second conductive layer 106.

[0074] The third insulating layer 109 can cover the third conductive layer 108, preventing short circuits between the third conductive layer 108 and other electrical components. The third insulating layer 109 can be made of organic materials such as polyimide (PI), or one or more of materials such as silicon nitride, silicon oxide, and silicon oxynitride. When applied in a display substrate, the third insulating layer 109 can specifically be an interlayer insulating layer in the display substrate. A fourth through-hole V4 is formed on the third insulating layer 109, exposing the third conductive layer 108 for connection to other electrical components on the substrate 101.

[0075] like Figure 3 As shown, the interconnect structure further includes: a second buffer layer 110 and a fourth conductive layer 111; the second buffer layer 110 is located on the side of the substrate 101 away from the first conductive layer 104 and is filled in the via V; the fourth conductive layer 111 is located on the side of the second buffer layer 110 away from the substrate 101; the fourth conductive layer 111 is connected to the conductive pillar 102 through a fifth via V5 penetrating the second buffer layer 110.

[0076] The second buffer layer 110 can be formed using the same material and process as the first buffer layer 103 to save on manufacturing costs. The fourth conductive layer 111 can be formed using the same material and process as the first conductive layer 104 to save on manufacturing costs.

[0077] The fourth conductive layer 111 can be connected to the conductive pillar 102 through the fifth via V5 penetrating the second buffer layer 110. Since the height of the conductive pillar 102 is less than the depth of the via V, the fourth conductive layer 111 can act as a lead to bring out the conductive pillar 102 for connection with other electrical devices on the back side of the substrate 101. Simultaneously, the second buffer layer 110 can be disposed between the fourth conductive layer 111 and the substrate 101 to prevent the substrate 101 from cracking due to a large difference in thermal expansion coefficients between the fourth conductive layer 111 and the substrate 101, thus affecting signal transmission and semiconductor packaging performance.

[0078] Figure 4 A schematic diagram of another interconnection structure provided in this disclosure embodiment is shown below. Figure 4 As shown, the interconnect structure also includes a fourth conductive layer 111; the fourth conductive layer 111 is located on the side of the substrate 101 away from the first conductive layer 104 and is connected to the conductive pillar 102.

[0079] Figure 4 and Figure 3 The difference in the interconnection structure shown is that, Figure 3 In the interconnect structure shown, the via V is formed by simultaneously etching the upper and lower surfaces, and its overall shape is such that the diameter is smaller in the middle and larger at both ends. Figure 2 In the interconnect structure shown, the via V is formed by single-sided etching, and the overall shape layer has a larger aperture at one end and a smaller aperture at the other end.

[0080] Figure 3 In the interconnect structure shown, since the diameter of the two ends of the through hole V is large, the stress concentration point is located at the edge of the two ends. A first buffer layer 103 and a second buffer layer 110 are respectively provided at the two ends of the through hole V and the two surfaces of the substrate 101. Figure 4 In the interconnect structure shown, since the aperture of the other end of the via V is small, the stress concentration is not obvious. The stress concentration is mainly located at the edge of one end. The first buffer layer 103 is only provided at one end of the via V and on the upper surface of the substrate 101.

[0081] like Figure 4 As shown, the fourth conductive layer 111 can be directly connected to the other end of the conductive post 102. The fourth conductive layer 111 can be used as a lead to lead out the conductive post 102 to connect with other electrical devices on the back side of the substrate 101.

[0082] Figure 5 This is a schematic diagram of another interconnection structure provided in an embodiment of the present disclosure. Figure 6 A schematic diagram of another interconnection structure provided in this disclosure embodiment is shown below. Figure 5 and Figure 6 As shown, the first via V1 includes: a plurality of first sub-vias V11; the first conductive layer 104 is connected to the conductive post 102 through the plurality of first sub-vias V11.

[0083] The first via V1 can be formed by multiple first sub-vias V11, which can turn a single hole into multiple holes. The first conductive layer 104 can be filled in the multiple first sub-vias V11. Without affecting the conductivity of the first conductive layer 104, the amount of material used in the first conductive layer 104 can be reduced, thereby reducing the amount of thermal expansion and further preventing the substrate 101 from cracking due to stress concentration.

[0084] like Figure 5As shown, the fifth via V5 includes: a plurality of fifth sub-vias V51; the fourth conductive layer 111 is connected to the conductive post 102 through the plurality of fifth sub-vias V51.

[0085] The fifth via V5 can be formed by multiple fifth sub-vias V51, which can turn a single hole into multiple holes. The fourth conductive layer 111 can be filled in the multiple fifth sub-vias V51. Without affecting the conductivity of the fourth conductive layer 111, the amount of material used in the fourth conductive layer 111 can be reduced, thereby reducing the amount of thermal expansion and further preventing the substrate 101 from cracking due to stress concentration.

[0086] Secondly, this disclosure provides a passive device, which includes the interconnect structure provided in any of the above embodiments. Its implementation principle is similar to that of the interconnect structure described above, and will not be repeated here.

[0087] Thirdly, embodiments of this disclosure provide a method for preparing an interconnect structure, used to prepare an interconnect structure as provided in any of the above embodiments. Figure 7 This is a schematic flowchart illustrating a method for fabricating an interconnect structure according to an embodiment of the present disclosure, as shown below. Figure 7 As shown, the method for preparing the interconnect structure includes the following steps S701 to S705.

[0088] S701 forms a through-hole on the substrate.

[0089] S702, a conductive post is filled inside the through hole; the height of the conductive post is less than the depth of the through hole.

[0090] S703, a buffer layer is formed on one side of the substrate.

[0091] S704, at the via, the buffer layer is etched to form the first via to expose the conductive pillar.

[0092] S705, a first conductive layer is formed on the buffer layer, such that the first conductive layer is connected to the conductive post through the first via.

[0093] Figures 8a to 8i This is a schematic diagram of the intermediate structure of each step in the fabrication method of an interconnect structure provided in this embodiment. The following will, in conjunction with the accompanying drawings, describe the process. Figure 3 The interconnect structure shown provides a further detailed description of each step in the fabrication method of the aforementioned interconnect structure.

[0094] like Figure 8a As shown, a glass of appropriate thickness (0.1 to 0.7 mm) is selected as the substrate 101, such as AF32 / BF33 / EXG / quartz, which are commonly found on the market.

[0095] like Figure 8b As shown, the first surface (front side) of the substrate 101 is modified or ablated using appropriate laser energy.

[0096] like Figure 8c As shown, the modified substrate 101 is etched with HF or NaOH / KOH to create or enlarge vias, forming pre-through holes with a diameter ranging from 10µm to 100µm. During etching, the etching ability of HF or NaOH / KOH differs between the bottom and top of the hole as the hole depth increases, easily leading to inconsistent hole diameters at the top and bottom, resulting in a structure that is larger at the top and smaller at the bottom. To ensure more uniform hole diameters, a double-sided etching method can be used. That is, following the steps described above, the same operation is performed on the second surface (back side) of the substrate 101, i.e., a second etching or enlargement is performed to form an integral through-hole V.

[0097] like Figure 8d As shown, a first metal is sputtered into the via V and onto the first and second surfaces of the substrate 101 using a physical vapor deposition (PVD) process to form a seed layer. Specifically, the first metal can be a titanium (Ti) / copper (Cu) or tantalum (Ta) / copper (Cu) alloy, with a thickness of approximately 1 μm.

[0098] like Figure 8e As shown, a second metal is deposited on the seed layer inside the via V using the chemical vapor deposition (CVD) process to fill the via with the second metal, which can be copper (Cu). The second metal is filled to a certain depth from the top of the via V, about 5 μm to 20 μm, thus forming a conductive pillar 102.

[0099] like Figure 8f As shown, the first metal of the seed layer on the first and second surfaces of the substrate 101 is removed by chemical mechanical polishing (CMP).

[0100] like Figure 8g As shown, a high-temperature resistant organic photosensitive material, such as HD4100 or BL301, is coated on both surfaces of the substrate 101 using a uniform coating or spray coating method to form a first buffer layer 103 and a second buffer layer 110.

[0101] like Figure 8hAs shown, the two surfaces of the substrate 101 are exposed and developed to expose the metal of the conductive pillar 102 in the through hole V, or the polymer material on both surfaces of the substrate 101 is exposed at the same time, leaving only a thin ring of photosensitive material on the inner sidewall of the through hole V, forming the first through hole V1 and the fifth through hole V5.

[0102] like Figure 8i As shown, seed layers are deposited on the first and second surfaces of the substrate 101, and a first conductive layer 104 and a fourth conductive layer 111 are formed by electrochemical deposition. Then, a first insulating layer 105, a second conductive layer 106, a second insulating layer 107, a third conductive layer 108, and a third insulating layer 109 are formed using the same process described above.

[0103] Figures 9a to 9j The following is a schematic diagram of the intermediate structure of each step in the preparation method of another interconnect structure provided in the embodiments of this disclosure. The diagram will be described below with reference to the accompanying drawings. Figure 4 The interconnect structure shown provides a further detailed description of each step in the fabrication method of the aforementioned interconnect structure.

[0104] like Figure 9a As shown, a glass of appropriate thickness (0.1 to 0.7 mm) is selected as the substrate 101, such as AF32 / BF33 / EXG / quartz, which are commonly found on the market.

[0105] like Figure 9b As shown, a suitable laser energy is used to modify or ablate the first surface (front side) of the substrate 101. Of course, the above steps can also be performed on the second surface (back side) of the substrate 101. Here, the modification or ablation of the first surface of the substrate 101 will be used as an example for explanation.

[0106] like Figure 9c As shown, the modified substrate 101 is etched with HF or NaOH / KOH to create or enlarge pre-through holes, with a hole diameter of 10µm to 100µm.

[0107] like Figure 9d As shown, a first metal is sputtered into the via V and onto the first surface of the substrate 101 using a physical vapor deposition (PVD) process to form a seed layer. Specifically, the first metal can be a titanium (Ti) / copper (Cu) or tantalum (Ta) / copper (Cu) alloy, with a thickness of approximately 1 μm.

[0108] like Figure 9eAs shown, a second metal is deposited on the seed layer inside the via V using the chemical vapor deposition (CVD) process to fill the via with the second metal, which can be copper (Cu). The second metal is filled to a certain depth from the top of the via V, about 5 μm to 20 μm, thus forming a conductive pillar 102.

[0109] like Figure 9f As shown, the second surface of the substrate 101 is polished and ground using a chemical mechanical polishing (CMP) process, so that the pre-through hole penetrates the entire substrate 101 to form a through hole V, and the conductive pillar 102 is exposed through the through hole V.

[0110] like Figure 9g As shown, the first metal of the seed layer on the first surface of the substrate 101 is polished and removed using a chemical mechanical polishing (CMP) process.

[0111] like Figure 9h As shown, a high-temperature resistant organic photosensitive material, such as HD4100 or BL301, is coated onto the upper surface of the substrate 101 using a homogenizing or spraying method to form a first buffer layer 103.

[0112] like Figure 9i As shown, the upper surface of the substrate 101 is exposed and developed to expose the metal of the conductive pillar 102 inside the through hole V, or the polymer material on the upper surface of the substrate 101 is exposed at the same time, leaving only a thin ring of photosensitive material on the inner sidewall of the through hole V, forming the first through hole V1.

[0113] like Figure 9j As shown, a seed layer is deposited on the upper surface of the substrate 101, and a first conductive layer 104 and a fourth conductive layer 111 are formed by electrochemical deposition. Then, a first insulating layer 105, a second conductive layer 106, a second insulating layer 107, a third conductive layer 108, and a third insulating layer 109 are formed using the same process described above.

[0114] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. An interconnection structure, wherein, The interconnect structure includes: a substrate and a plurality of conductive pillars; a plurality of through-holes are formed on the substrate; the conductive pillars fill the through-holes; the height of the conductive pillars is less than the depth of the through-holes; the interconnect structure further includes: a first buffer layer and a first conductive layer; The first buffer layer is located on one side of the substrate and fills the through-hole; The first conductive layer is located on the side of the first buffer layer that is away from the substrate. The first conductive layer is connected to the conductive post through a first through-hole penetrating the first buffer layer.

2. The interconnection structure according to claim 1, wherein, The interconnect structure further includes: a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, and a third insulating layer located on the side of the first conductive layer opposite to the substrate. The first conductive layer is connected to the third conductive layer through a second via that penetrates the first insulating layer and the second insulating layer; The second conductive layer is connected to the third conductive layer through a third via penetrating the second insulating layer; The third conductive layer is exposed through a fourth via that penetrates the third insulating layer.

3. The interconnection structure according to claim 1, wherein, The interconnect structure further includes: a second buffer layer and a fourth conductive layer; The second buffer layer is located on the side of the substrate away from the first conductive layer and fills the via. The fourth conductive layer is located on the side of the second buffer layer that is away from the substrate. The fourth conductive layer is connected to the conductive post through a fifth through-hole that penetrates the second buffer layer.

4. The interconnection structure according to claim 1, wherein, The interconnect structure further includes: a fourth conductive layer; The fourth conductive layer is located on the side of the substrate opposite to the first conductive layer and is connected to the conductive pillar.

5. The interconnection structure according to claim 3 or 4, wherein, The first via includes: a plurality of first sub-vias; The first conductive layer is connected to the conductive pillar through a plurality of first sub-vias.

6. The interconnection structure according to claim 3, wherein, The fifth via includes: a plurality of fifth sub-vias; The fourth conductive layer is connected to the conductive pillar through multiple fifth sub-vias.

7. A passive device, wherein, The passive device includes the interconnect structure as described in any one of claims 1 to 6.

8. A method for fabricating an interconnect structure, wherein, The method for preparing the interconnect structure includes: Forming through-holes on the substrate; The through hole is filled with a conductive pillar; the height of the conductive pillar is less than the depth of the through hole. A buffer layer is formed on one side of the substrate. At the via, the buffer layer is etched to form a first via to expose the conductive pillar; A first conductive layer is formed on the buffer layer, such that the first conductive layer is connected to the conductive post through the first via.

9. The method for preparing the interconnect structure according to claim 8, wherein, Forming through-holes on the substrate includes: A first etching is performed on the first surface of the substrate to form a pre-via on the first surface; A second etching is performed on the second surface of the substrate to form a through hole at the position corresponding to the pre-via; the second surface is disposed opposite to the first surface.

10. The method for preparing the interconnect structure according to claim 9, wherein, The through-hole is filled with conductive pillars, including: A seed layer is formed by sputtering a first metal inside the through-hole, on the first surface and the second surface; A second metal is deposited on the seed layer within the through-hole to form a conductive pillar; the conductive pillar is at a certain distance from both the first surface and the second surface; The seed layers on the first surface and the second surface are ground to remove the seed layers on the first surface and the second surface.

11. The method for preparing the interconnect structure according to claim 8, wherein, Forming through-holes on the substrate includes: A first etching is performed on the first surface of the substrate to form a pre-via. The second surface of the substrate is ground to expose the pre-via to form the via; the second surface is disposed opposite to the first surface.

12. The method for fabricating the interconnect structure according to claim 11, wherein, The through-hole is filled with conductive pillars, including: A seed layer is formed by sputtering a first metal inside the through-hole and on the first surface; A second metal is deposited on the seed layer within the through-hole to form a conductive pillar; the conductive pillar is located at a certain distance from the first surface. The seed layer on the first surface is ground to remove the seed layer on the first surface.

Images