Capacitor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a capacitor device and a manufacturing method thereof, and electronic equipment, relates to the field of capacitors, and can improve the capacitance density of an MIM capacitor. The capacitor device comprises a substrate, and a first electrode layer, a second electrode layer and a first dielectric layer which are arranged on the substrate. Wherein the first electrode layer is of a groove structure, an opening of the groove structure faces the side away from the substrate, and the bottom of the groove structure is arranged on the substrate. The second electrode layer covers the inner surface and the outer surface of the trench structure. The first dielectric layer is located between the first electrode layer and the second electrode layer. By arranging the second electrode layer to cover the inner surface and the outer surface of the first electrode layer (namely the groove structure), the effective capacitance area can be increased, and then the capacitance density is improved.

Description

Technical Field

[0001] The present application relates to the field of capacitors, and in particular to a capacitor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] MIM (metal insulator metal) capacitors are usually integrated in the back-end metal interconnect layer of CMOS (complementary metal oxide semiconductor). MIM capacitors include a lower metal electrode layer, a dielectric layer, and an upper metal electrode layer stacked in sequence. Its capacitance density is determined by the dielectric constant of the dielectric layer and the effective contact area between the electrode layer and the dielectric layer.

[0003] At present, there are two main structures of MIM capacitors: flat MIM ( Figure 1 ) and traditional 3D MIM ( Figure 2 ). A planar MIM capacitor is a sandwich-type MIM structure formed by depositing a bottom electrode, a dielectric layer, and a top electrode on a planar layer in sequence. A conventional 3D MIM capacitor is a 3D MIM structure formed by first forming a trench on a planar layer, and then depositing a bottom electrode, a dielectric layer, and a top electrode in the trench in sequence. The conventional 3D MIM capacitor can increase the effective area of ​​the capacitor, and its capacitance density can be increased to more than three times that of a planar MIM.

[0004] However, with the rapid development of the integrated circuit industry and market demand, there is an increasing need to integrate more functions on smaller chips, so the design method and manufacturing of chips are also facing greater challenges. MIM capacitors are commonly used in circuits such as radio frequency (RF) and image sensors (CMOS image sensor, CIS). They usually need to occupy a large area to achieve the target capacitance, which is not conducive to the design of back-end circuits and the miniaturization of chips. Therefore, it is necessary to design MIM capacitors with higher capacitance density to meet the needs of chip miniaturization. Summary of the invention

[0005] The present application provides a capacitor device and a manufacturing method thereof, and an electronic device, which can improve the capacitance density of a MIM capacitor.

[0006] The present application provides a capacitor device, which includes: a substrate, at least one first electrode layer arranged on the substrate, a second electrode layer, and a first dielectric layer. The first electrode layer is a groove structure, the opening of the groove structure is facing the side away from the substrate, and the bottom of the groove structure is arranged on the substrate. The second electrode layer covers the inner surface and the outer surface of the groove structure. The first dielectric layer is located between the first electrode layer and the second electrode layer. In this case, the first electrode layer, the first dielectric layer, and the second electrode layer can form a 3D MIM capacitor.

[0007] Compared with the top electrode of the MIM capacitor in the technology that only covers the inner surface of the bottom electrode, in the capacitor device provided in the present application, by setting the inner and outer surfaces of the first electrode layer (i.e., the bottom electrode) to be covered by the second electrode layer (i.e., the top electrode), the inner and outer surfaces of the first electrode layer in the MIM capacitor can form a capacitor with the second electrode layer, thereby increasing the effective capacitor area and further improving the capacitance density of the MIM capacitor.

[0008] In some possible implementations, the capacitor device includes a plurality of first electrode layers that are spaced apart from each other. In this case, a plurality of MIM capacitors are formed in the device.

[0009] In some possible implementations, the capacitor device further includes an etch stop layer, wherein the etch stop layer covers an area on the substrate surface where the first electrode layer is not provided. During the manufacturing process of the capacitor device, the etch stop layer can protect the substrate surface to avoid damage to the substrate surface due to the etching process, so as to ensure the performance of the capacitor device.

[0010] In some possible implementations, the etch stop layer includes one or more of silicon carbon nitride SiCN and silicon nitride SiN.

[0011] In some possible implementations, the capacitor device further includes a second dielectric layer; wherein the second dielectric layer covers the second electrode layer, and the second dielectric layer fills the inner region and the outer region of the trench structure.

[0012] In some possible implementations, the second dielectric layer includes one or more of silicon carbon oxyhydride SiCOH, silicon oxyfluoride SiOF, and silicon oxycarbide SiOC.

[0013] In some possible implementations, the substrate includes a silicon substrate and a metal wiring layer disposed on the silicon substrate. The first electrode layer is disposed on a side of the metal wiring layer away from the silicon substrate, and the first electrode layer is connected to the metal wiring layer at the bottom of the trench structure. That is, the 3D MIM capacitor can be compatible with the back-end process.

[0014] In some possible implementations, the substrate includes a silicon substrate and a metal wiring layer disposed on the silicon substrate. The first electrode layer is disposed on a side of the silicon substrate away from the metal wiring layer, and the first electrode layer is connected to the metal wiring layer at the bottom of the trench structure through a silicon through-hole disposed in the silicon substrate. That is, the 3D MIM capacitor is disposed on the back side of the silicon substrate.

[0015] In some possible implementations, the capacitor device further includes a support structure; the support structure is connected between the tops of two adjacent first electrode layers, and the top of the support structure is flush with the top of the first electrode layer. The support structure provides a supporting force to the first electrode layer from the side to prevent the first electrode layer from collapsing during the manufacturing process of the device.

[0016] The present application also provides a method for manufacturing a capacitor device, the manufacturing method comprising: forming a sacrificial layer on a substrate, and etching the sacrificial layer to form at least one first groove. Depositing a first electrode layer in the first groove and filling a dielectric material, exposing the top of the sacrificial layer by grinding. Removing the sacrificial layer and the dielectric material filled in the first groove, retaining the first electrode layer of the groove structure on the substrate. Depositing a first dielectric layer and a second electrode layer on the inner surface and the outer surface of the groove structure in sequence.

[0017] The manufacturing method of the present application is used to manufacture a capacitor device, by first forming a first electrode layer with a groove structure on the surface of the sacrificial layer, and then removing the sacrificial layer, thereby exposing the inner surface and outer surface of the first electrode layer. On this basis, the second electrode layer is formed to cover the inner surface and outer surface of the first electrode layer as a whole, so that the inner surface and outer surface of the first electrode layer in the MIM capacitor can form a capacitor with the second electrode layer, thereby increasing the effective capacitor area, and then improving the capacitance density of the MIM capacitor.

[0018] In some possible implementations, a sacrificial layer is formed on the surface of a substrate, and at least one first groove is formed by etching the sacrificial layer, including: first forming an etch stop layer on the surface of the substrate, then forming a sacrificial layer, and forming at least one first groove by etching the sacrificial layer and the etch stop layer.

[0019] In some possible implementations, before removing the sacrificial layer and the dielectric material filled in the first groove, the manufacturing method further includes: thinning the sacrificial layer in a partial area between two adjacent first electrode layers to form a second groove. Depositing dielectric material in the second groove to form a support structure connected between the two first electrode layers. The support structure provides a support force to the first electrode layer from the side to prevent the first electrode layer from collapsing during the manufacturing process of the device.

[0020] The present application also provides an electronic device, which includes a circuit board and any possible capacitor device as described above, wherein the capacitor device is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of a planar MIM capacitor provided in the prior art;

[0022] Figure 2 A schematic diagram of the structure of a traditional 3D MIM capacitor provided in the prior art;

[0023] Figure 3 A schematic diagram of a three-dimensional structure of a capacitor device provided in an embodiment of the present application;

[0024] Figure 4 for Figure 3 Side view of

[0025] Figure 5 for Figure 4 Schematic diagram of the first electrode layer;

[0026] Figure 6 A schematic diagram of a capacitor device provided in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of a support structure in a capacitor device provided in an embodiment of the present application;

[0028] Figure 8 A schematic diagram of a capacitor device provided in an embodiment of the present application;

[0029] Fig. 9 A schematic diagram of a capacitor device provided in an embodiment of the present application;

[0030] Fig.10 A flow chart of a method for manufacturing a capacitor device provided in an embodiment of the present application;

[0031] Fig.11 A schematic diagram of a capacitor device during the manufacturing process provided in an embodiment of the present application;

[0032] Fig.12 A schematic diagram of a capacitor device during the manufacturing process provided in an embodiment of the present application;

[0033] Fig.13 A schematic diagram of a capacitor device during the manufacturing process provided in an embodiment of the present application;

[0034] Fig.14 A schematic diagram of a capacitor device during the manufacturing process provided in an embodiment of the present application;

[0035] Fig.15A schematic diagram of a capacitor device during the manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or it can be indirect through an intermediate medium, or it can be the internal connection of two elements. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.

[0038] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc., and the present application does not impose any restrictions on this.

[0039] Indicatively, the above-mentioned consumer electronic products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products can be smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products can be car-mounted navigators, car-mounted displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service transactions, etc. Communication electronic products can be servers, storage devices, radars, base stations, and other communication equipment.

[0040] The electronic device includes a printed circuit board (PCB) and a capacitor device electrically connected to the circuit board. The capacitor device uses a new type of 3D MIM capacitor, which can increase the effective capacitor area and the capacitance density of the MIM without changing the trench depth-to-width ratio, thereby being more conducive to the miniaturization of the device and providing a margin for the design.

[0041] The present application does not impose any restrictions on the configuration of the above-mentioned capacitor device. The capacitor device can be any device with a MIM capacitor disposed inside, such as an artificial intelligence chip, a server logic chip, a radio frequency chip, an image sensor (CMOS image sensor, CIS), etc.

[0042] Indicatively, in a CIS chip using global shutter technology and dual conversion gain (DCG) technology, the MIM capacitor will occupy a larger area in the pixel unit. When such a CIS chip uses the new 3D MIM capacitor provided by the present application, it can increase the capacitance density by increasing the effective capacitance area, thereby being more conducive to the miniaturization requirements of the image sensor chip and providing a margin for the design. Another point is that a higher capacitance density is conducive to reducing the LCG (low conversion gain) in the DCG, which can further improve the dynamic range of the CIS.

[0043] The structure of the novel 3D MIM capacitor provided in the embodiments of the present application is described below.

[0044] Figure 3 A schematic diagram of the three-dimensional structure of a capacitor device provided in an embodiment of the present application. Figure 4 for Figure 3 Side view of.

[0045] Indicative, reference Figure 3 and Figure 4 As shown, an embodiment of the present application provides a capacitive device, which includes a substrate 10 and a plurality of first electrode layers 21 disposed on the substrate 10 . Figure 3 and Figure 4 The description is only schematically illustrated by taking two first electrode layers 21 as an example. In some possible implementations, a first electrode layer 21 may also be provided in the capacitor device. The following embodiments are all described by taking the example of a plurality of first electrode layers 21 being provided at intervals on the substrate 10.

[0046] Figure 5 for Figure 4 Schematic diagram of the first electrode layer 21.

[0047] refer to Figure 5 As shown, the first electrode layer 21 is in a groove structure, the opening of the groove structure is upward (that is, toward the side away from the substrate 10), and the bottom of the groove structure is arranged on the substrate 10. The groove structure has an inner surface a1 and an outer surface a2. Schematically, in some possible implementations, the first electrode layer 21 can be in a strip-shaped U-shaped groove structure.

[0048] On this basis, combined with Figure 4 and Figure 5 As shown, the capacitor device further includes a second electrode layer 22 and a first dielectric layer 30. The second electrode layer 22 covers the inner surface a1 and the outer surface a2 of the groove structure (21). The first dielectric layer 30 is arranged between the first electrode layer 21 and the second electrode layer 22, that is, the first dielectric layer 30 also covers the inner surface and the outer surface of the groove structure (21). In this case, the first electrode layer 21, the first dielectric layer 30, and the second electrode layer 22 are stacked in sequence to form a 3D MIM capacitor.

[0049] The above-mentioned “coverage” refers to the coverage of a certain area, and does not impose any restriction on whether the two film layers are in contact with each other. Whether the film layers are in contact with each other can be determined according to the functional requirements of the device.

[0050] In the existing 3D MIM capacitors ( Figure 2 ), the top electrode is arranged on the inner side of the bottom electrode (groove structure), that is, the top electrode only covers the inner surface area of ​​the bottom electrode, that is, the inner surface area of ​​the bottom electrode (groove structure) will form an effective capacitance area with the top electrode.

[0051] In contrast, in the capacitor device provided in the embodiment of the present application, the inner and outer surface areas of the first electrode layer (i.e., the bottom electrode) are covered by the second electrode layer (i.e., the top electrode), that is, capacitance is formed between the inner and outer surfaces of the first electrode layer and the second electrode layer, thereby increasing the effective capacitance area and further improving the capacitance density.

[0052] When the layout area and the trench depth are the same, the effective capacitance area of ​​the new 3D MIM of the present application can be increased to that of the traditional 3D MIM ( Figure 2 ) is about twice as much.

[0053] Of course, in some possible implementations, a third electrode layer, a fourth electrode layer, etc. can be made on the second electrode layer 22 according to actual needs, and adjacent electrode layers are isolated by a dielectric layer, thereby further increasing the effective capacitance area and improving the capacitance density.

[0054] The present application does not limit the specific materials used for the first electrode layer 21 , the second electrode layer 22 , and the first dielectric layer 30 , and they can be set as needed in practice.

[0055] Schematically, the first electrode layer 21 and the second electrode layer 22 can be made of one or more metal materials such as Cu (copper), TiN (titanium nitride), TaN (tantalum nitride), etc. The metal materials used by the first electrode layer 21 and the second electrode layer 22 can be the same or different.

[0056] Illustratively, the first dielectric layer 30 may be made of one or more dielectric materials such as Al2O3 (aluminum oxide), TaO (tantalum oxide), HfO (hafnium oxide), and ZrO (zirconium oxide).

[0057] The thickness of the first electrode layer 21 , the second electrode layer 22 , and the first dielectric layer 30 can be set according to actual needs, and the present application does not impose any limitation thereto.

[0058] After completing the production of MIM capacitors, refer to Figure 6 As shown, a second dielectric layer 50 can be formed on the second electrode layer 22, and the inner area and the outer area of ​​the groove structure (21) are filled and leveled as a whole by the second dielectric layer 50, and the entire MIM capacitor is covered. In this case, the upper surface S1 of the second dielectric layer 50 (i.e., the surface on the side away from the groove structure) is a planar structure or a nearly planar structure, so that the subsequent metal layer process can be performed on the upper surface S1 of the second dielectric layer 50. Schematically, the upper surface S1 of the second dielectric layer 50 can be prepared by grinding using a CMP (chemical mechanical polishing) process.

[0059] Illustratively, the second dielectric layer 50 may be made of one or more low dielectric constant materials (ie, low-k materials) such as SiCOH (silicon carbon oxyhydride), SiOF (silicon oxyfluoride), and SiOC (silicon oxycarbide), but the present application is not limited thereto.

[0060] In addition, as shown in reference 6, in some possible implementations, a metal via V may be formed in the second dielectric layer 50 on the side of the first electrode layer 21, and the second electrode layer 22 may be led out through the metal via V. The first electrode layer 21 may be led out through the bottom substrate 10, and this application does not limit this, and it may be set as needed in practice.

[0061] In addition, in the present application, since the first dielectric layer 30 and the second electrode layer 22 cover the outer side of the first electrode layer 21, the film layers on the outer side and the inner side of the first electrode layer 21 need to be removed before the first dielectric layer 30 and the second electrode layer 22 are formed. In this case, there are the following two technical problems:

[0062] Technical Problem 1: When the film layer outside the first electrode layer 21 is removed, it is easy to cause damage to the surface of the substrate 10, thereby affecting the performance of the capacitor device.

[0063] Technical Problem 2: After the film layers on the outer and inner sides of the first electrode layer 21 are removed, the first electrode layer 21 loses support and is prone to collapse.

[0064] In order to solve the above technical problem, Figure 5 As shown, in some possible implementations, the etching stop layer 40 may be covered on part or all of the area on the surface of the substrate 10 where the first electrode layer 21 is not provided, and the surface of the substrate 10 is protected by the etching stop layer 40. For details, please refer to the corresponding part of the manufacturing method below, which will not be repeated here.

[0065] The present application does not impose any limitation on the material and thickness of the etching stop layer 40 , and the material and thickness can be set as required in practice.

[0066] Illustratively, in some possible implementations, the etch stop layer 40 may be made of one or more dielectric materials such as SiCN (silicon carbon nitride) and SiN (silicon nitride).

[0067] In order to solve the above technical problem 2, Figure 7As shown, in some possible implementations, a support structure 60 can be set between the tops of two adjacent first electrode layers 21, and the support structure 60 is in contact with the outer side surfaces of the tops of the two first electrode layers 21, so that the support structure 60 can provide supporting force to the first electrode layer 21 from the side to prevent the first electrode layer 21 from collapsing.

[0068] Considering the actual production process, some possible implementation methods are as follows: Figure 7 As shown, the top of the support structure 60 can be set flush with the top of the first electrode layer 21, and there is a certain distance between the bottom of the support structure 60 and the substrate 10, that is, the thickness of the support structure 60 is less than the height of the first electrode layer 21. For details, please refer to the corresponding part of the manufacturing method below, which will not be repeated here.

[0069] The present application does not impose any restrictions on the material and thickness of the support structure 60 , and the materials and thickness can be set as required in practice.

[0070] As shown, in some possible implementations, the support structure 60 may be made of one or more dielectric materials such as SiN (silicon nitride) and SiCN (silicon carbon nitride).

[0071] In addition, it should be understood by those skilled in the art that the manufacturing process of integrated circuits includes the front end of line (FEOL) and the back end of line (BEOL). The manufacturing of transistors is realized on a silicon substrate through the front end of line (FEOL). Among them, the transistor can be a fin field effect transistor (FinFET), a gate-all-around field effect transistor (FET), etc., but is not limited to this. The back end of line (BEOL) is to establish several metal interconnection layers, and the conductive metal wires of different layers are connected by columnar metal vias. The transistors in the front end of line (FEOL) are electrically connected to the metal interconnection layers of the back end of line (BEOL).

[0072] The novel 3D MIM capacitor provided in the embodiment of the present application can be compatible with the back-end-of-line (BEOL) process. In this case, refer to Figure 8As shown, the substrate 10 may include: a silicon substrate 101 formed with a semiconductor device (such as a transistor T, etc.), and a metal wiring layer 102 disposed on the silicon substrate 101. The first electrode layer 21 is disposed on the metal wiring layer 102 (i.e., the side away from the silicon substrate), and the bottom of the first electrode layer 21 (i.e., the bottom of the trench structure) is electrically connected to the metal wiring layer 102. The second electrode layer 22 may be led upward through a metal via V.

[0073] Of course, as another possible implementation method, Fig. 9 As shown, the novel 3D MIM capacitor provided in the embodiment of the present application can also be arranged on the back side of the silicon substrate 101, that is, the side of the silicon substrate 101 where no semiconductor device (such as transistor T, etc.) is arranged. In this case, the first electrode layer 21 is arranged on the side of the silicon substrate 101 away from the metal wiring layer 102, and the bottom of the first electrode layer 21 (that is, the bottom of the trench structure) can be electrically connected to the metal wiring layer 102 through a silicon via TSV (through silicon via) arranged in the silicon substrate 101. The second electrode layer 22 can also be electrically connected to the metal wiring layer 102 through the silicon via TSV.

[0074] The present application also provides a method for manufacturing a capacitor device as described above. Fig.10 As shown, the production method may include:

[0075] Step 01: Reference Fig.11 As shown, a sacrificial layer 41 is formed on the substrate 10 , and the sacrificial layer 41 is etched to form at least one first trench 42 .

[0076] In some possible implementations, step 01 may include: Fig.11 As shown in (a), a substrate 10 is provided. Figure 8 As shown, the substrate 10 may include a silicon substrate 101 on which a semiconductor device (such as a transistor T, etc.) is fabricated, and a metal wiring layer 102 disposed on the silicon substrate 101. Then, an etching stop layer 40 with a thickness of about 20 nm is formed on the substrate 10 using SiCN. Fig.11 As shown in (b), a sacrificial layer 41 with a thickness of about 350 nm is formed on the etch stop layer 40 using SiO2, and a hard mask layer HM with a thickness of about 20 nm is formed on the sacrificial layer 41 using SiN. Then, the pattern of the first trench 42 is first transferred to the hard mask layer HM through processes such as photolithography and etching, and then the first trench 42 is formed by etching after stripping. After that, the hard mask layer HM can be removed by rinsing using a wet process.

[0077] Illustratively, in some possible implementations, the etch stop layer 40 may be a wet etch stop layer, which is used to protect the surface of the substrate 10 when the sacrificial layer 41 is removed by wet etching in the subsequent step 03, thereby preventing the wet etching process from damaging the surface of the substrate 10 and affecting the performance of the device.

[0078] Step 02: Reference Fig.12 As shown, the first electrode layer 21 is deposited in the first trench 42 and filled with a dielectric material, and the top of the sacrificial layer 41 is exposed by grinding.

[0079] In some possible implementations, step 02 may include: Fig.12 As shown in (a), a CVD (chemical vapor deposition) or ALD (atomic layer deposition) process can be used to deposit TiN or TaN in the first trench 42 as the first electrode layer 21; then, referring to Fig.12 As shown in (b), a dielectric material (such as SiO 2 ) is filled in the first trench 42 , and the first electrode layer 21 is polished by a CMP (chemical mechanical polishing) process to expose the top of the sacrificial layer 41 .

[0080] Step 03: Reference Fig.13 As shown, the sacrificial layer 41 and the dielectric material filled in the first groove 42 are removed, and the first electrode layer 21 with a groove structure is retained on the substrate 10 .

[0081] In some possible implementations, step 03 may include: Fig.13 As shown, the sacrificial layer 41 and the dielectric material filled in the first groove 42 can be rinsed and removed by a wet etching process, so that the first electrode layer 21 with a strip groove structure is retained on the substrate 10. The material of the sacrificial layer 41 can be the same as the dielectric material filled in the first groove 42, so that the sacrificial layer 41 and the dielectric material filled in the first groove 42 can be removed at the same time by one wet etching.

[0082] Step 04: Reference Fig.14 As shown, the first dielectric layer 30 and the second electrode layer 22 are sequentially deposited on the inner surface and the outer surface of the groove structure (the first electrode layer 21).

[0083] In some possible implementations, step 04 may include: Fig.14As shown in (a), a dielectric material such as Al2O3 (aluminum oxide), TaO (tantalum oxide), HfO (hafnium oxide), and ZrO (zirconium oxide) can be used to deposit a first dielectric layer 30 with a thickness of about 20 nm on the surface of the first electrode layer 21 through an ALD process; then, Fig.14 As shown in (b), TiN (titanium nitride) or TaN (tantalum nitride) is used to deposit the second electrode layer 22 with a thickness of about 20 nm on the first dielectric layer 30 through a CVD or ALD process.

[0084] After step 04, other production steps may be performed as needed, and this application does not impose any restrictions on this.

[0085] For example, in some possible implementations, the process of step 04 may be repeated after the second electrode layer 22 to form a dielectric layer and an electrode layer again, thereby forming a MIM capacitor having three or more electrode layers.

[0086] For example, in some possible implementations, reference Figure 6 As shown, after the second electrode layer 22, a second dielectric layer 50 can be made of a low dielectric constant material (i.e., low k material) such as SiCOH (carbon silicon oxyhydride), SiOF (silicon oxyfluoride), and SiOC (silicon oxycarbon), etc., to fill the inside and outside of the first electrode layer 21 and cover the entire MIM capacitor. After the first dielectric layer 50 is completed, a metal via V and subsequent metal wiring layers can be made.

[0087] In addition, refer to Fig.13 As shown, after the dielectric material on the outer and inner sides of the first electrode layer 21 is removed in step 03, the first electrode layer 21 loses support and is prone to collapse. Therefore, in order to prevent the first electrode layer 21 from collapsing, before removing the sacrificial layer 41 in step 03, the manufacturing method may further include: Fig.15 As shown in (a), the sacrificial layer 41 in a part of the region between two adjacent first electrode layers 21 is etched and thinned to form a second groove 43. Then, referring to Fig.15 As shown in (b) and (c), a dielectric material 44 (such as a SiN layer with a thickness of 100 nm) is deposited in the second groove 43, and the dielectric material 44 is polished to be flush with the first electrode layer 21 through a CMP process. At this time, the dielectric material 44 filled in the second groove 43 forms a support structure 60, and the support structure 60 is connected between the two first electrode layers 21, so that it can play a certain supporting role for the first electrode layer 21 and prevent the first electrode layer 21 from collapsing.

[0088] After forming the support structure 60, refer to Fig.15As shown in (d), the sacrificial layer 41 and the dielectric material filled in the first trench 42 can be removed through step 03. The subsequent steps can refer to the above and will not be repeated here.

[0089] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by the device function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0090] For other related contents in the above-mentioned manufacturing method, you can refer to the corresponding parts in the above-mentioned capacitor device embodiment, which will not be repeated here; for other setting structures in the above-mentioned capacitor device embodiment, you can refer to the above-mentioned manufacturing method and related manufacturing methods for adjustment, which will not be repeated here one by one.

[0091] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A capacitor device, characterized in that: include: substrate; at least one first electrode layer, the first electrode layer being disposed on the substrate and being in a groove structure, wherein an opening of the groove structure faces a side away from the substrate; a second electrode layer, the second electrode layer covering the inner surface and the outer surface of the groove structure; A first dielectric layer is located between the first electrode layer and the second electrode layer.

2. The capacitive device according to claim 1, characterized in that: The capacitive device includes a plurality of first electrode layers arranged at intervals.

3. The capacitive device according to claim 1 or 2, characterized in that: The capacitor device further includes an etch stop layer; The etching stop layer covers an area on the surface of the substrate where the first electrode layer is not disposed.

4. The capacitive device according to claim 3, characterized in that: The etch stop layer includes one or more of silicon carbon nitride SiCN and silicon nitride SiN.

5. The capacitive device according to any one of claims 1 to 4, characterized in that: The capacitor device further includes a second dielectric layer; The second dielectric layer covers the second electrode layer, and the second dielectric layer fills the inner area and the outer area of ​​the trench structure.

6. The capacitive device according to claim 5, characterized in that: The second dielectric layer includes one or more of silicon carbon oxyhydride SiCOH, silicon oxyfluoride SiOF, and silicon oxycarbide SiOC.

7. The capacitive device according to any one of claims 1 to 6, characterized in that: The base comprises a silicon substrate and a metal wiring layer arranged on the silicon substrate; The first electrode layer is disposed on a side of the metal wiring layer away from the silicon substrate, and the first electrode layer is connected to the metal wiring layer at the bottom of the trench structure.

8. The capacitive device according to any one of claims 1 to 6, characterized in that: The base comprises a silicon substrate and a metal wiring layer arranged on the silicon substrate; The first electrode layer is disposed on a side of the silicon substrate away from the metal wiring layer, and the first electrode layer is connected to the metal wiring layer through a through silicon via disposed in the silicon substrate at the bottom of the trench structure.

9. The capacitive device according to any one of claims 1 to 8, characterized in that: The capacitive device also includes a support structure; The supporting structure is connected between top ends of two adjacent first electrode layers, and the top of the supporting structure is flush with the top of the first electrode layer.

10. A method for manufacturing a capacitor device, characterized in that: include: forming a sacrificial layer on a substrate, and etching the sacrificial layer to form at least one first groove; Depositing a first electrode layer in the first groove and filling the first groove with a dielectric material, and exposing the top of the sacrificial layer by grinding; removing the sacrificial layer and the dielectric material filled in the first groove, and retaining the first electrode layer of the groove structure on the substrate; A first dielectric layer and a second electrode layer are sequentially deposited on the inner surface and the outer surface of the groove structure.

11. The method for manufacturing a capacitive device according to claim 10, characterized in that: The method of forming a sacrificial layer on the surface of the substrate and forming at least one first groove by etching the sacrificial layer comprises: An etch stop layer is first formed on the surface of the substrate, and then a sacrificial layer is formed. At least one first groove is formed by etching the sacrificial layer and the etch stop layer.

12. The method for manufacturing a capacitive device according to claim 10 or 11, characterized in that: Before removing the sacrificial layer and the dielectric material filled in the first trench, the manufacturing method further includes: Thinning the sacrificial layer in a partial area between two adjacent first electrode layers to form a second groove; A dielectric material is deposited in the second groove to form a support structure connected between the two first electrode layers.

13. An electronic device, characterized in that: The invention comprises a circuit board and a capacitive device as claimed in any one of claims 1 to 9, wherein the capacitive device is electrically connected to the circuit board.

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