Semiconductor device

Abstract

The invention realizes miniaturization of a semiconductor device. The semiconductor device includes: an interposer substrate including a plurality of wiring layers therein; a first semiconductor chip disposed on the interposer substrate; and a power supply circuit that transforms a voltage supplied from the outside and supplies the transformed voltage to the first semiconductor chip. The power supply circuit includes: an inductor configured from a plurality of coil patterns respectively formed in at least two wiring layers of a plurality of wiring layers of an interposer substrate; and a capacitor.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] A semiconductor device having a semiconductor memory chip and a semiconductor controller chip built therein is known.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-142084 Summary of the invention

[0006] Problems to be solved by the invention

[0007] Embodiments of the present disclosure achieve miniaturization of semiconductor devices.

[0008] Means for solving problems

[0009] A semiconductor device of an embodiment includes: an interposer substrate including a plurality of wiring layers inside; a first semiconductor chip arranged on the interposer substrate; and a power supply circuit that transforms a voltage supplied from an external source and supplies the voltage to the first semiconductor chip. The power supply circuit includes: an inductor composed of a plurality of coil patterns formed at at least two wiring layers among the plurality of wiring layers of the interposer substrate; and a capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a front view showing the front structure of the semiconductor device according to the first embodiment.

[0011] Figure 2 It is a plan view showing the planar structure of the semiconductor device according to the first embodiment.

[0012] Figure 3 It means along Figure 2 A cross-sectional view of the cross-sectional structure taken along line III-III.

[0013] Figure 4 This is a circuit diagram showing the configuration of a power supply circuit according to the first embodiment.

[0014] Figure 5 (A) to (D) are diagrams schematically showing the planar structures of the plurality of coil patterns included in the inductor according to the first embodiment.

[0015] Figure 6 It is a perspective view schematically showing the three-dimensional structure of the inductor according to the first embodiment.

[0016] Figure 7 (A) to (D) are diagrams schematically showing the planar structures of the plurality of coil patterns included in the inductor according to the modified example of the first embodiment.

[0017] Figure 8 It is a front view showing the front structure of the semiconductor device according to the second embodiment.

[0018] Fig. 9 This is a circuit diagram showing the configuration of a power supply circuit according to the third embodiment.

[0019] Fig.10 It is a front view showing the front structure of the semiconductor device according to the third embodiment.

[0020] Fig.11 It is a plan view showing the planar structure of the semiconductor device according to the third embodiment.

[0021] Description of Reference Numerals

[0022] 1: semiconductor device; 9: power supply circuit; 50: interposer substrate; 51: control chip (first semiconductor chip); 52: memory chip; 56: power supply IC (second semiconductor chip); 80: inductor (first inductor); 81, 81a, 81b: capacitor; 83: second inductor; 801-804, 831-834: coil pattern; 821, 822: switch element (first switch element); 823, 824: switch element (second switch element). DETAILED DESCRIPTION

[0023] In order to facilitate the understanding of the description, the same components are denoted by the same reference numerals as much as possible in the drawings, and repeated descriptions are omitted.

[0024] 1 First Embodiment

[0025] A semiconductor device according to a first embodiment will be described. The semiconductor device according to this embodiment is a semiconductor package including a NAND flash memory chip. The semiconductor device according to this embodiment is, for example, a universal flash storage (UFS) device mounted on a smartphone.

[0026] 1.1 Structure of semiconductor devices

[0027] Figure 1FIG. 2 is a front view showing the front structure of the semiconductor device 1 according to the present embodiment. Figure 1 As shown, the semiconductor device 1 can be mounted on a substrate 3 .

[0028] The substrate 3 is, for example, a printed circuit board (PCB). The semiconductor device 1 can be mounted on the surface 30 of the substrate 3. Hereinafter, the direction perpendicular to the surface 30 of the substrate 3 is referred to as the Z direction. In addition, the axial directions perpendicular to the Z direction and perpendicular to each other are referred to as the X direction and the Y direction. The Z direction is an example of the first direction.

[0029] The semiconductor device 1 includes an interposer substrate 50, a control chip 51, a plurality of memory chips 52, a single or a plurality of spacers 53, and a sealant 54. The semiconductor device 1 is a so-called semiconductor package obtained by integrally sealing the control chip 51 and the plurality of memory chips 52 with the sealant 54. Figure 1 Although a cut-away cross-sectional structure of a portion of the seal 54 is shown, hatching indicating the cross section of the seal 54 is omitted. Hatching indicating the cross section of the seal 54 is also omitted in other drawings.

[0030] The interposer substrate 50 is disposed between the substrate 3 and the control chip 51. The interposer substrate 50 has a multilayer structure 500 and a plurality of external terminals 501. The interposer substrate 50 is used to achieve conduction among the substrate 3, the control chip 51, and the memory chip 52.

[0031] The multilayer structure 500 includes a plurality of insulating layers, a plurality of wiring layers, and vias. The multilayer structure 500 has a structure in which insulating layers and wiring layers are alternately stacked in the Z direction. The multilayer structure 500 of this embodiment has four wiring layers. The plurality of wiring layers are electrically connected via vias in a manner that penetrates a single or a plurality of insulating layers in the Z direction. The insulating layer is formed of an insulating material such as a resin with glass added. The wiring layer and the via are formed of a conductive material such as copper (Cu).

[0032] The multilayer structure 500 has a bottom surface 500a. The bottom surface 500a faces the substrate 3. A plurality of external terminals 501 are provided on the bottom surface 500a. The plurality of external terminals 501 are electrically connected to at least one wiring layer among a plurality of wiring layers formed inside the multilayer structure 500 via electrodes formed on the bottom surface 500a. The external terminals 501 are protruding terminals formed by solder balls, solder plating, etc. The bottom of each of the plurality of external terminals 501 contacts the electrode provided on the substrate 3. Thus, the circuit inside the substrate 3 is electrically connected to the wiring layer inside the multilayer structure 500.

[0033] The multilayer structure 500 has an upper surface 500b. The upper surface 500b faces the control chip 51. The upper surface 500b contacts a plurality of external terminals 510 formed on the control chip 51. A plurality of electrodes are provided on the upper surface 500b for the plurality of external terminals 510 of the control chip 51 to contact respectively. The control chip 51 is electrically connected to the circuit inside the substrate 3 via the external terminals 510, the electrodes formed on the upper surface 500b, the wiring layer formed inside the multilayer structure 500, the electrodes formed on the bottom surface 500a, the external terminals 501, and the electrodes provided on the substrate 3.

[0034] In addition, hereinafter, the bottom surface 500a of the multilayer structure 500 is also referred to as “the bottom surface 500a of the interposer substrate 50”, and the top surface 500b of the multilayer structure 500 is also referred to as “the top surface 500b of the interposer substrate 50”. In the present embodiment, the top surface 500b of the interposer substrate 50 corresponds to the main surface of the interposer substrate 50.

[0035] The control chip 51 has a plurality of external terminals 510. The control chip 51 is, for example, a system on a chip (SoC) or an application specific integrated circuit (ASIC). In addition, the control chip 51 may also be another integrated circuit (IC) or circuit. The control chip 51 is an example of a first semiconductor chip.

[0036] A plurality of memory chips 52 are stacked on the control chip 51. The memory chips 52 are spaced apart from the upper surface 500b of the interposer substrate 50 in the Z direction. The arrangement of the control chip 51 and the memory chip 52 is an example, and the arrangement can be changed arbitrarily.

[0037] Figure 2 It is a plan view showing the planar structure of the semiconductor device 1 . Figure 3 It means along Figure 2 A cross-sectional view of the cross-sectional structure taken along line III-III.

[0038] like Figure 2 and Figure 3 As shown, the semiconductor device 1 further includes bonding wires 55 connecting the plurality of memory chips 52 to the interposer substrate 50 . The plurality of memory chips 52 are electrically connected to the control chip 51 via the bonding wires 55 , the wiring layer inside the interposer substrate 50 , and the external terminals 510 .

[0039] like Figure 1 and Figure 3As shown, the spacer 53 is arranged between the lower end memory chip 52a arranged at the position closest to the interposer substrate 50 among the plurality of memory chips 52 and the upper surface 500b of the interposer substrate 50. The upper surface 500b of the interposer substrate 50 is bonded to the bottom surface 530 of the spacer 53 in the Z direction via an adhesive layer. The bottom surface of the lower end memory chip 52a is bonded to the upper surface 531 of the spacer 53 in the Z direction via an adhesive layer.

[0040] The sealing member 54 is formed of a synthetic resin, etc. The sealing member 54 seals the control chip 51 , the plurality of memory chips 52 , the plurality of bonding wires 55 , and the spacer 53 .

[0041] 1.2 Composition of power supply circuit

[0042] The semiconductor device 1 of the present embodiment further includes Figure 4 The power supply circuit 9 is shown. Figure 4 : is a circuit diagram showing the structure of the power supply circuit 9 of the present embodiment. The power supply circuit 9 adjusts the voltage supplied from the outside, and supplies the adjusted voltage to the control chip 51. The power supply circuit 9 transforms (e.g., steps down) the voltage supplied from the outside. For example, the power supply circuit 9 is a DC / DC converter. The stepped-down voltage is supplied to a low-voltage system such as a logic power supply and an I / O power supply of the control chip 51. For example, when the voltage supplied from the outside is 2.5V, the power supply circuit 9 steps down the voltage to, for example, 1.2V.

[0043] Next, the specific structure of the power supply circuit 9 is described. Figure 4 As shown, the power supply circuit 9 includes an inductor 80 , a capacitor 81 , and a power device 82 .

[0044] The power device 82 is built in the control chip 51. The power device 82 includes a control circuit 820 and two switching elements 821 and 822.

[0045] The two switch elements 821 and 822 are, for example, N-channel MOS transistors. The source terminal of the switch element 821 and the drain terminal of the switch element 822 are connected to each other. Therefore, the two switch elements 821 and 822 are electrically connected in series. A voltage Vcc supplied from the outside is applied to the drain terminal of the switch element 821. The external voltage Vcc is supplied from Figure 1 The substrate 3 shown in the figure supplies the control chip 51 with the ground voltage Vss via the external terminal 501 , the wiring layer of the interposer substrate 50 , and the external terminal 510 . The source terminal of the switching element 822 is supplied with the ground voltage Vss.

[0046] like Figure 1 and Figure 3As shown, the inductor 80 is composed of a plurality of coil patterns 801 to 804 formed on the interposer substrate 50. The coil patterns 801 to 804 are formed on each of the four wiring layers of the interposer substrate 50. The coil patterns 801 to 804 are formed of a conductive material such as copper (Cu).

[0047] Figure 5 (A) to (D) are plan views showing the planar structures of the coil patterns 801 to 804. Figure 5 As shown in (A), the coil pattern 801 is formed to be bent and extended in a rectangular shape with the axis m10 as the center. The axis m10 is an axis parallel to the Z direction. Figure 4 As shown, the first end 801a of the coil pattern 801 is connected to the middle portion 825 of the switch elements 821 and 822 via the wiring layer of the interposer substrate 50. Figure 5 As shown in FIG. 8(A) , the second end portion 801 b of the coil pattern 801 is formed so as to protrude inward (in the Y direction).

[0048] like Figure 5 As shown in (B), the coil pattern 802 is formed to be bent and extended in a rectangular shape with the axis m10 as the center, similarly to the coil pattern 801. The first end 802a and the second end 802b of the coil pattern 802 are formed to protrude inward. The first end 802a of the coil pattern 802 is arranged in the Z direction with respect to the Figure 5 The first end 802a of the coil pattern 802 is connected to the second end 801b of the coil pattern 801 via the through hole 205, and the through hole 205 is formed to extend in the Z direction in the interposer substrate 50. The second end 802b of the coil pattern 802 is offset in the X direction relative to the first end 802a.

[0049] like Figure 5 As shown in (C), the coil pattern 803 is also formed to be bent and extended in a rectangular shape with the axis m10 as the center, similarly to the coil pattern 801. The first end 803a and the second end 803b of the coil pattern 803 are formed to protrude inward. The first end 803a of the coil pattern 803 is arranged in the Z direction with respect to the Figure 5 The first end 803a of the coil pattern 803 is connected to the second end 802b of the coil pattern 802 via the through hole 206, and the through hole 206 is formed to extend in the Z direction in the interposer substrate 50. The second end 803b of the coil pattern 803 is staggered in the X direction relative to the first end 803a.

[0050] like Figure 5As shown in (D), the coil pattern 804 is also formed to be bent and extended in a rectangular shape with the axis m10 as the center, similarly to the coil pattern 801. The first end 804a of the coil pattern 804 is formed to protrude inward. The first end 804a of the coil pattern 804 is arranged in the Z direction with respect to Figure 5 The first end 804a of the coil pattern 804 is electrically connected to the second end 803b of the coil pattern 803 via the through hole 207, and the through hole 207 is formed to extend in the Z direction in the interposer substrate 50. Figure 4 As shown, the second end portion 804 b of the coil pattern 804 is electrically connected to the control chip 51 and the capacitor 81 via the wiring layer of the interposer substrate 50 .

[0051] Figure 6 801 to 804 are three-dimensional diagrams schematically showing the three-dimensional structure of coil patterns 801 to 804. Figure 6 As shown, the coil patterns 801 to 804 are formed so that the portions other than the first end portions 801a to 804a and the second end portions 801b to 804b of each overlap when viewed from the Z direction. Therefore, the coil patterns 801 to 804 have substantially the same pattern shape.

[0052] By making Figure 3 The switch element 821 shown in FIG. 8 is turned on, and a voltage Vcc is applied to the first end 801a of the coil pattern 801. Figure 5 (A)~(D) and Figure 6 As shown by the arrow I in the middle, the current flowing in each coil pattern 801 to 804 increases. Specifically, the current flows in the order from the first end 801a of the coil pattern 801 to the second end 801b, the through hole 205, from the first end 802a of the coil pattern 802 to the second end 802b, the through hole 206, from the first end 803a of the coil pattern 803 to the second end 803b, the through hole 207, and from the first end 804a of the coil pattern 804 to the second end 804b.

[0053] like Figure 1 As shown, the coil patterns 801 to 804 are formed in the interposer substrate 50 below the spacer 53. Figure 2 As shown, coil patterns 801 to 804 are arranged at positions different from (ie, not overlapping) wiring regions A11 and A12 of the interposer substrate 50 when viewed from the Z direction. The wiring regions A11 and A12 are, for example, regions where the following (a1) to (a3) ​​are arranged.

[0054] (a1) A portion of the wiring layer of the interposer substrate 50 that functions as wiring for electrically connecting the external terminals 501 on the bottom surface 500 a of the interposer substrate 50 and the control chip 51 .

[0055] (a2) A portion of the wiring layer of the interposer substrate 50 that functions as wiring for electrically connecting the control chip 51 and the memory chip 52 .

[0056] (a3) A portion where bonding wires 55 connecting the interposer substrate 50 and the memory chip 52 are arranged.

[0057] By arranging the coil patterns 801 to 804 at positions different from the wiring areas A11 and A12 of the interposer substrate 50 in this manner, interference between the coil patterns 801 to 804 and various wirings can be easily avoided.

[0058] Figure 1 and Figure 2 The capacitor 81 shown is disposed on the interposer substrate 50. Figure 2 As shown, the capacitor 81 may be arranged at a position different from the wiring areas A11 and A12 of the interposer substrate 50 when viewed from the Z direction. In addition, the capacitor 81 has a predetermined height in the Z direction, and is therefore arranged so as not to interfere with the memory chip 52 and the bonding wire 55. The capacitor 81 is arranged in a manner aligned with the inductor 80 in the Y direction.

[0059] like Figure 4 As shown, the output voltage of the inductor 80 is applied to the control circuit 820 via the wiring layer of the interposer substrate 50. The control circuit 820 controls the gate voltages of the switch elements 821 and 822 to turn on / off the switch elements 821 and 822, thereby stepping down the external voltage Vcc and supplying it to the control chip 51. At this time, the control circuit 820 controls the voltage supplied to the control chip 51 to be a predetermined voltage (e.g., 1.2V), for example.

[0060] 1.3 Functions and Effects of the Semiconductor Device of the Present Embodiment

[0061] As described above, the semiconductor device 1 of the present embodiment includes an interposer substrate 50, a control chip 51, and a power supply circuit 9. The interposer substrate 50 includes a plurality of wiring layers inside. The control chip 51 is disposed on the interposer substrate 50. The power supply circuit 9 transforms the external voltage Vcc and supplies it to the control chip 51. The power supply circuit 9 includes an inductor 80 and a capacitor 81. The inductor 80 is composed of a plurality of coil patterns 801 to 804 formed at a plurality of wiring layers of the interposer substrate 50, respectively.

[0062] According to this configuration, the inductor 80 can be disposed inside the interposer substrate 50 , so that the semiconductor device 1 can be miniaturized compared to a case where a component corresponding to the inductor 80 is disposed, for example, on the upper surface 500 b of the interposer substrate 50 .

[0063] Four wiring layers are formed on the interposer substrate 50. Coil patterns 801 to 804 are formed on all the wiring layers of the four wiring layers. Figure 6 As shown, the plurality of coil patterns 801 to 804 are arranged at positions overlapping each other when viewed from the Z direction.

[0064] According to this configuration, high magnetic coupling can be achieved through the coil patterns 801 to 804. Therefore, high inductance can be obtained even with a small area.

[0065] The inductance is proportional to the square of the number of turns of the coil pattern included in the inductor 80. Considering the inductance required of the inductor 80 in the power supply circuit 9, it is beneficial to form four or more wiring layers on the interposer substrate 50 and to form four or more coil patterns (i.e., to set the number of turns to four or more).

[0066] The control chip 51 incorporates the switch elements 821 , 822 of the power supply circuit 9 and a control circuit 820 for controlling the switch elements 821 , 822 .

[0067] According to this configuration, the structure of the semiconductor device 1 can be simplified compared to a case where the switch elements 821 and 822 and the control circuit 820 are provided separately from the control chip 51 .

[0068] like Figure 2 and Figure 3 As shown, the plurality of coil patterns 801 to 804 are arranged at positions overlapping the memory chip 52 and the spacer 53 and not overlapping the control chip 51 when viewed from the Z direction.

[0069] According to this configuration, interference between the wiring connected to the control chip 51 formed in the interposer substrate 50 and the coil patterns 801 to 804 can be avoided.

[0070] like Figure 6 As shown, in the plurality of coil patterns 801 to 804 , current flows in the same rotation direction around a predetermined axis m10 .

[0071] According to this configuration, since the directions of magnetic fluxes formed by the coil patterns 801 to 804 are the same when current flows through the coil patterns 801 to 804, high magnetic coupling can be formed by the coil patterns 801 to 804. Therefore, high inductance can be achieved.

[0072] 1.4 Variations

[0073] Next, a modification of the semiconductor device 1 according to the first embodiment will be described.

[0074] Figure 7 (A) to (D) are plan views showing the planar structures of the coil patterns 801 to 804 of the modification examples. Figure 7 As shown in (A) to (D), the coil patterns 801 to 804 of this modification are formed into a spiral shape with the axis m10 as the center. In more detail, the coil patterns 801 and 803 are formed to be rolled into a vortex counterclockwise with the axis m10 as the center. The coil patterns 802 and 804 are formed to be rolled into a vortex clockwise with the axis m10 as the center. In addition, hereinafter, the respective ends located at the periphery of each coil pattern 801 to 804 are referred to as outer ends 801c, 802c, 803c, and 804c. In addition, the respective ends located near the center of each coil pattern 801 to 804 are referred to as inner ends 801d, 802d, 803d, and 804d.

[0075] like Figure 7 As shown in (A), the outer end portion 801c of the coil pattern 801 is Figure 4 The middle parts 825 of the switch elements 821 and 822 are connected. Figure 7 As shown in (A) and (B) of FIG. 8 , the inner end 801d of the coil pattern 801 is connected to the inner end 802d of the coil pattern 802 via the through hole 208. Figure 7 As shown in (B) and (C) of FIG. 8 , the outer end 802c of the coil pattern 802 is connected to the outer end 803c of the coil pattern 803 via the through hole 209. Figure 7 As shown in (C) and (D), the inner end 803d of the coil pattern 803 is connected to the inner end 804d of the coil pattern 804 via the through hole 210. The outer end 804c of the coil pattern 804 is connected to the wiring layer of the interposer substrate 50, as shown in FIG. Figure 4 It is connected to the control chip 51 and the capacitor 81 as shown.

[0076] In the inductor 80 of this modification, when the switch element 821 is turned on and a voltage Vcc is applied to the outer end 801c of the coil pattern 801, Figure 7 As indicated by arrows I in (A) to (D), the current flowing in the counterclockwise direction around the axis m10 in each coil pattern 801 to 804 increases.

[0077] According to this configuration, since the directions of the magnetic fluxes formed in the coil patterns 801 to 804 are the same, high magnetic coupling can be formed through the coil patterns 801 to 804. Therefore, the performance of the inductor 80 can be improved.

[0078] 2. Second Embodiment

[0079] Next, a semiconductor device according to a second embodiment will be described. The following description will focus on differences from the semiconductor device 1 according to the first embodiment.

[0080] 2.1 Structure of semiconductor devices

[0081] like Figure 8 As shown in FIG. 1 , the semiconductor device 1 of the present embodiment further includes a power supply IC 56. The power supply IC 56 is sealed together with the control chip 51 and the memory chip 52 by a sealing member 54. The power supply IC 56 is a Figure 3 The power device 82 shown is obtained by converting it into a semiconductor chip. The power IC 56 is an example of a second semiconductor chip.

[0082] 2.2 Functions and Effects of the Semiconductor Device of the Present Embodiment

[0083] The power IC 56 of this embodiment is provided separately from the control chip 51 , and includes switch elements 821 , 822 and a control circuit 820 .

[0084] According to this configuration, the power IC 56 can be manufactured by a process suitable for the power circuit 9 , so that the characteristics of the power circuit 9 can be improved and the manufacturing cost can be reduced.

[0085] 3. Third Embodiment

[0086] Next, a semiconductor device according to a third embodiment will be described. The following description will focus on differences from the semiconductor device 1 according to the first embodiment.

[0087] 3.1 Composition of power supply circuit

[0088] Fig. 9 is a circuit diagram showing the configuration of the power supply circuit 9 of this embodiment. Fig. 9 As shown, the power supply circuit 9 of the present embodiment further includes an inductor 83. Hereinafter, the inductor 80 is referred to as a "first inductor 80" and the inductor 83 is referred to as a "second inductor 83." The second inductor 83 is electrically connected to the first inductor 80 in parallel.

[0089] The power device 82 further includes two switching elements 823 and 824 connected in series. The switching elements 823 and 824 are connected to the second inductor 83. Since the switching elements 823 and 824 have the same or similar configuration as the switching elements 821 and 822, their detailed description is omitted. The switching elements 823 and 824 are controlled by the control circuit 820.

[0090] Fig.10 It is a front view showing the front structure of the semiconductor device 1 according to the present embodiment. Fig.11is a plan view showing the planar structure of the semiconductor device 1 according to the present embodiment. Fig.10 and Fig.11 In FIG. 1 , one of the X directions is represented by an X1 direction, and the other of the X directions is represented by an X2 direction. The X1 direction is an example of the second direction. The X2 direction is an example of the third direction.

[0091] like Fig.10 and Fig.11 As shown, the second inductor 83 is arranged on the opposite side of the first inductor 80 relative to the control chip 51 in the X direction. The second inductor 83 is composed of coil patterns 831 to 834 respectively formed at the wiring layer of the interposer substrate 50. Since the coil patterns 831 to 834 of the second inductor 83 have the same or similar shapes as the coil patterns 801 to 804 of the first inductor 80, their detailed description is omitted. The coil patterns 801 to 804 are examples of the first coil pattern. The coil patterns 831 to 834 are examples of the second coil pattern.

[0092] In addition to the capacitor 81a corresponding to the first inductor 80, a capacitor 81b corresponding to the second inductor 83 is provided on the upper surface 500b of the interposer substrate 50. Hereinafter, the capacitor 81a is referred to as the "first capacitor 81a" and the capacitor 81b is referred to as the "second capacitor 81b". Fig.11 As shown in FIG. 8 , the second capacitor 81 b is arranged so as to be aligned with the second inductor 83 in the Y direction.

[0093] In addition, Fig. 9 In the circuit diagram of the power supply circuit 9 shown, the first capacitor 81 a and the second capacitor 81 b are collectively shown as one capacitor 81 .

[0094] The control circuit 820 operates the switching elements 821 and 822 and the switching elements 823 and 824 with a phase difference of 180 degrees, thereby interleaving the switching elements 821 and 822 connected to the first inductor 80 and the switching elements 823 and 824 connected to the second inductor 83. The switching elements 821 and 822 are examples of the first switching elements, and the switching elements 823 and 824 are examples of the second switching elements.

[0095] 3.2 Functions and Effects of the Semiconductor Device of the Present Embodiment

[0096] A plurality of inductors 80 and 83 are formed on the interposer substrate 50. The first inductor 80 is arranged offset in the X1 direction with respect to the control chip 51. The second inductor 83 is arranged offset in the X2 direction opposite to the X1 direction with respect to the first inductor 80 via the control chip 51.

[0097] According to this configuration, the fluctuation of the output voltage can be suppressed by the two-interleaved operation. In addition, by increasing the distance between the inductor 80 and the inductor 83, the degradation of the characteristics due to the magnetic coupling can be suppressed.

[0098] 4 Other Implementation Methods

[0099] The present disclosure is not limited to the above-mentioned specific examples.

[0100] For example, the coil pattern constituting the inductor 80 does not need to be formed on all of the four wiring layers of the interposer substrate 50 , and may be formed on only three wiring layers, for example.

[0101] exist Figure 5 In (A), the second end 801b of the coil pattern 801 and the first end 802a of the coil pattern 802 are shown to protrude inward (in the +Y direction), but the second end 801b of the coil pattern 801 and the first end 802a of the coil pattern 802 may also be formed to protrude outward (in the -Y direction). The same is true for the second protruding portion 802b of the coil pattern 802, the first protruding portion 803a and the second protruding portion 803b of the coil pattern 803, and the first protruding portion 804a of the coil pattern 804.

[0102] Although the interposer substrate 50 of each embodiment includes four wiring layers, the number of wiring layers included in the interposer substrate 50 can be changed arbitrarily. In addition, the number of coil patterns used to constitute the inductor 80 can also be changed arbitrarily according to the number of wiring layers. For example, when the interposer substrate 50 is formed with four or more wiring layers, the inductor 80 can be composed of four or more coil patterns respectively formed at the four or more wiring layers of the interposer substrate 50.

[0103] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: an interposer substrate including a plurality of wiring layers internally; a first semiconductor chip disposed on the interposer substrate; and The power supply circuit transforms the voltage supplied from the outside and supplies it to the first semiconductor chip. The power supply circuit has: an inductor composed of a plurality of coil patterns respectively formed on at least two wiring layers among the plurality of wiring layers of the interposer substrate; and Capacitor.

2. The semiconductor device according to claim 1, The interposer substrate includes four or more wiring layers as the plurality of wiring layers, The inductor is composed of four or more coil patterns respectively formed on the four or more wiring layers of the interposer substrate.

3. The semiconductor device according to claim 1, The plurality of coil patterns are respectively formed on all of the plurality of wiring layers of the interposer substrate.

4. The semiconductor device according to claim 1, The plurality of wiring layers are stacked in a first direction inside the interposer substrate. The plurality of coil patterns do not include a portion overlapping the first semiconductor chip when viewed from the first direction.

5. The semiconductor device according to claim 1, The plurality of wiring layers are stacked in a first direction inside the interposer substrate. The plurality of coil patterns are arranged at positions overlapping each other when viewed from the first direction.

6. The semiconductor device according to claim 1, The first semiconductor chip includes a switching element of the power supply circuit and a control circuit for controlling the switching element.

7. The semiconductor device according to claim 1, The semiconductor device further includes a second semiconductor chip that includes a switching element of the power supply circuit and a control circuit that controls the switching element and is different from the first semiconductor chip.

8. The semiconductor device according to claim 1, The semiconductor device further includes a memory chip. The first semiconductor chip is a control chip configured to control the memory chip.

9. The semiconductor device according to claim 8, The plurality of wiring layers are stacked in a first direction inside the interposer substrate. The plurality of coil patterns are arranged at positions overlapping the memory chip when viewed from the first direction.

10. The semiconductor device according to claim 1, The semiconductor device further comprises: Memory chips; and a spacer, disposed between the memory chip and the interposer substrate, The first semiconductor chip is a control chip configured to control the memory chip. The plurality of wiring layers are stacked in a first direction inside the interposer substrate. The memory chip is arranged to be separated from the main surface of the interposer substrate in the first direction. The plurality of coil patterns are arranged at positions overlapping the spacer when viewed from the first direction.

11. The semiconductor device according to claim 1, The power supply circuit is configured to allow current to flow in the same rotation direction through the plurality of coil patterns.

12. The semiconductor device according to claim 1, The plurality of coil patterns are respectively formed in a rectangular shape.

13. The semiconductor device according to claim 1, The plurality of coil patterns are respectively formed in a spiral shape.

14. The semiconductor device according to claim 1, The power supply circuit has at least two of the inductors.

15. The semiconductor device according to claim 14, The plurality of wiring layers are stacked in a first direction inside the interposer substrate. The power supply circuit includes a first inductor and a second inductor as the at least two inductors. The first inductor is arranged to be offset with respect to the first semiconductor chip in a second direction orthogonal to the first direction, and is composed of a plurality of first coil patterns. The second inductor is arranged to be offset with respect to the first inductor in a third direction opposite to the second direction via the first semiconductor chip, and is formed of a plurality of second coil patterns.

16. The semiconductor device according to claim 15, The semiconductor device further includes at least two switching elements including a first switching element and a second switching element. The first switching element and the second switching element are connected to the first inductor and the second inductor, respectively. The power supply circuit operates the first switching element and the second switching element alternately.

17. The semiconductor device according to claim 1, The plurality of wiring layers are stacked in a first direction inside the interposer substrate. One of the plurality of coil patterns and another one of the plurality of coil patterns are connected to each other via a through hole formed inside the interposer substrate so as to extend in the first direction.

18. The semiconductor device according to claim 17, The semiconductor device further comprises: A first switching element to which a voltage supplied from the outside is applied; and The second switching element is applied with a ground voltage. The one coil pattern among the plurality of coil patterns has a first end and a second end, The first end of the one coil pattern among the plurality of coil patterns is connected to the other one coil pattern among the plurality of coil patterns via the through hole. The second end portion of the one coil pattern among the plurality of coil patterns is connected to a portion between the first switching element and the second switching element.

19. The semiconductor device according to claim 18, The other one of the plurality of coil patterns has a third end and a fourth end, the third end of the other one of the plurality of coil patterns is connected to the first end of the one of the plurality of coil patterns via the through hole, The fourth end portion of the other one of the plurality of coil patterns is connected to the capacitor.

20. The semiconductor device according to claim 19, The fourth end portion of the other one of the plurality of coil patterns is further connected to the first semiconductor chip.

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