Ceramic-packaged digital isolator product structure and chip isolation structure manufacturing method

Abstract

This invention relates to a ceramic-packaged digital isolator product structure and a method for manufacturing a chip isolation structure. The digital isolator product structure specifically addresses the high-voltage isolation problem of ceramic-packaged digital isolators, improving their reliability. It includes a digital isolator chip and a housing. The digital isolator chip's substrate is a semiconductor silicon wafer, and the chip has metal bonding pads for the input and output terminals of a receiver chip and a transmitter chip. The housing and the digital isolator chip are bonded with insulating adhesive. In the digital isolator product structure of this invention, the chip design only increases the spacing between the chip pads, solving the withstand voltage problem between the input and output terminals of isolators manufactured using existing semiconductor silicon wafer processes. Furthermore, the insufficient insulation withstand voltage of digital isolators manufactured using existing silicon wafer processes can be solved using existing silicon wafer process lines and chips.

Description

Technical Field

[0001] This invention relates to the technical field of digital isolator packaging, and in particular to a ceramic-packaged digital isolator product structure and a method for manufacturing a chip isolation structure. Background Technology

[0002] Most existing digital isolators use epoxy molding compound for plastic encapsulation. In humid environments or under temperature cycling and high temperatures, the difference in thermal expansion coefficients between the molding compound and different materials (chip, frame, bonding wire) can lead to device delamination, resulting in problems such as leakage and reduced isolation withstand voltage. Some products use ceramic encapsulation. To improve the isolation withstand voltage, potting compound is introduced to wrap the PAD of the digital isolator chip and the surrounding area of ​​the chip, which solves the problem of use in humid environments. However, in environments with large changes such as aviation, aerospace, and missile applications, the high mechanical stress can lead to bonding reliability issues.

[0003] To meet the isolation withstand voltage requirements, if the air-sealed ceramic packaged digital isolator chip is manufactured using a mature silicon wafer process line, the distance from the input and output terminals of all digital isolators to the side of the chip (the exposed part of the semiconductor silicon wafer) needs to be increased to eliminate surface creep, leakage, and substrate breakdown through the semiconductor silicon. However, this leads to problems such as the digital isolator chip becoming too large to meet design requirements and thus unable to be received. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a ceramic-encapsulated digital isolator product structure. This structure specifically solves the high-voltage isolation problem of ceramic-encapsulated digital isolators, improving their reliability. The structure includes a digital isolator chip and a housing. The substrate of the digital isolator chip is a semiconductor silicon wafer. The digital isolator chip has metal bonding pads for the input and output terminals of a receiver chip and a transmitter chip. The spacing between the metal bonding pads at the input and output terminals is increased, i.e., the PAD spacing is increased, to meet preset isolation withstand voltage requirements. Furthermore, the size of the digital isolator chip remains constant and is adapted to the sizes of the receiver chip and the transmitter chip.

[0005] The outer casing and the digital isolator chip are provided with insulating adhesive for bonding and connection. The receiver chip and transmitter chip are also bonded to the digital isolator chip with insulating adhesive.

[0006] In one embodiment of the present invention, the digital isolator chip is made of semiconductor silicon wafer, thinned by 100μm, and the digital isolator chip is bonded to the outer shell with insulating adhesive. At the same time, the insulating adhesive is required to overflow and wrap the side of the digital isolator chip, which is located in the empty sealed cavity, ultimately replacing the method of increasing the distance between the chip sides to prevent surface creep.

[0007] In one embodiment of the present invention, after the digital isolator chip is attached to the outer casing, the top of the outer casing is equipped with a cover plate to form an airtight structure.

[0008] In one embodiment of the present invention, the receiver chip and the transmitter chip are connected to the digital isolator chip by bonding wires, and then capped to form the digital isolator product.

[0009] This invention also provides a method for fabricating an isolation structure for a digital isolator chip, comprising the following steps:

[0010] Step S1: First, according to the product isolation withstand voltage requirement technical document, without increasing the size of the digital isolator chip, design and increase the spacing between the metal bonding pads of the input and output terminals on the digital isolator chip; use a semiconductor silicon wafer based on a polyimide process line to fabricate the digital isolator chip with the specified spacing; that is, design the primary and secondary PAD spacing of the isolator chip, and use a semiconductor silicon wafer based on a polyimide process line to fabricate a digital isolator chip with the PAD spacing;

[0011] Step S2: Next, the digital isolator disc is thinned to 100μm and diced with a 30μm thick blade;

[0012] Step S3: Then, the digital isolator chip is bonded to the housing using insulating adhesive, wherein the insulating adhesive overflows and surrounds the digital isolator chip; the receiver chip and transmitter chip are bonded to the digital isolator chip using insulating adhesive, and then the chips are interconnected using bonding wire, and then baked.

[0013] Step S4: Seal the cover plate and the outer shell to form a vacuum seal structure, so that the digital isolator chip is sealed in the vacuum seal cavity formed by the outer shell and the cover plate, and the product is formed.

[0014] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: In the digital isolator product structure of the present invention, the chip design of the isolator only increases the chip PAD spacing, which solves the withstand voltage problem between the input and output terminals of the isolator manufactured by the existing semiconductor silicon wafer process. It does not require redesigning the receiver isolator chip and the transmitter chip, and meets the requirements of ceramic packaging. At the same time, the insulation withstand voltage of the digital isolator manufactured by the semiconductor silicon wafer process can be solved by using the existing silicon wafer process line and chip, which reduces the investment and production cost of digital isolator manufacturing. At the same time, ceramic packaging does not require potting, and the digital isolator can work stably for a long time in harsh environments. Attached Figure Description

[0015] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0016] Figure 1 This is a top view of the digital isolator chip described in this invention;

[0017] Figure 2 This is a schematic diagram of the ceramic-encapsulated digital isolator product structure in this invention;

[0018] Figure 3 This is a top view bonding diagram of the ceramic-encapsulated digital isolator product structure of the present invention.

[0019] In the diagram: 1. Outer shell; 2. Insulating adhesive; 3. Digital isolator chip; 4. Receiver chip; 5. Transmitter chip; 6. Bonding wire; 7. Cover plate. Detailed Implementation Example 1

[0020] like Figure 1 and Figure 2 As shown, this embodiment provides a ceramic-encapsulated digital isolator product structure. The digital isolator product structure specifically solves the high-voltage isolation problem of ceramic-encapsulated digital isolators and improves the reliability of ceramic-encapsulated digital isolators. It includes a digital isolator chip 3 and a housing 1. The substrate of the digital isolator chip 3 is a semiconductor silicon wafer. The digital isolator chip 3 is provided with input and output metal bonding pads for a receiver chip 4 and a transmitter chip 5. The housing 1 and the digital isolator chip 3 are provided with insulating adhesive 2 for bonding and connection. The receiver chip 4 and the transmitter chip 5 are also bonded to the digital isolator chip 3 using insulating adhesive 2.

[0021] The digital isolator chip 3 is fabricated using a semiconductor silicon wafer, thinned by 100μm. Insulating adhesive 2 is used to bond the isolator chip 3 to the outer casing 1, ensuring the adhesive overflows to completely surround the digital isolator chip 3. The digital isolator chip 3 is designed according to product requirements, increasing the spacing between the PADs between the isolator's input and output terminals.

[0022] Specifically, the isolator chip 3 is thinned to 100μm, and insulating glue 2 is used to bond the isolator chip to the inside of the housing cavity. The insulating glue 2 overflows and surrounds the isolator chip 3 to prevent the isolator chip 3 from being broken through the substrate.

[0023] like Figure 2 and Figure 3 As shown, after the digital isolator chip 3 is attached to the outer casing 1, the top of the outer casing 1 is equipped with a cover plate 7.

[0024] The receiver chip 4 and transmitter chip 5 are connected to the digital isolator chip 3 by a bonding wire 6, and then capped to form the digital isolator product.

[0025] In this embodiment, the isolator chip design only increases the chip PAD spacing, solving the voltage withstand problem between the input and output terminals of isolators manufactured using existing semiconductor silicon wafer processes. It does not require redesigning the receiver isolator chip and transmitter chip, and meets the requirements of ceramic packaging.

[0026] The digital isolator product structure described in this embodiment includes a digital isolator chip fabricated using semiconductor silicon wafer technology and a digital isolator circuit package. This invention solves the problem of insufficient insulation withstand voltage in digital isolators fabricated using existing silicon wafer technology by utilizing existing silicon wafer process lines and chips, reducing investment and production costs. Furthermore, the ceramic packaging eliminates the need for potting, allowing the digital isolator to operate stably for extended periods in harsh environments. Example 2

[0027] This embodiment provides a method for fabricating an isolation structure for a digital isolator chip, including the following steps:

[0028] Step S1: First, according to the product isolation withstand voltage requirement technical document, design the primary and secondary PAD spacing of the isolator chip, and use semiconductor silicon wafers based on polyimide process line to fabricate digital isolator chips;

[0029] Step S2: Next, the digital isolator disc is thinned to 100μm and diced with a 30μm thick blade;

[0030] Step S3: Then, the digital isolator chip 3 is bonded to the housing 1 using insulating adhesive 2, wherein the insulating adhesive 2 overflows and wraps around the digital isolator chip 3; the receiver chip 4 and the transmitter chip 5 are bonded to the digital isolator chip 3 using insulating adhesive 2, and then the chips are interconnected using bonding wire 6 and baked.

[0031] Step S4: Seal the cover plate 7 and the outer shell 1 to form a vacuum seal structure, so that the digital isolator chip 3 is sealed in the vacuum seal cavity formed by the outer shell 1 and the cover plate 7, and the product is formed.

[0032] In the chip isolation structure fabrication method described in this embodiment, only the PAD spacing of the digital isolator chip is increased, without the need to redesign the receiver chip and transmitter chip. The digital isolator chip is wrapped around by the overflow of insulating glue, which prevents the isolator chip from being broken through the substrate. There is no need to use potting glue to wrap the bonding wire and PAD, which solves the high voltage isolation problem of ceramic packaged digital isolators and improves the reliability of ceramic packaged digital isolators.

[0033] Furthermore, in practical applications, the pad spacing is 1.5mm, and the substrate spacing within the pad is 200um. If a die-mounting method is used, the withstand voltage can be increased from the original 1000V to over 2000V.

[0034] In summary, by utilizing the above-mentioned technical solution of the present invention, the present invention solves the problem of insufficient withstand voltage between the input and output terminals of an empty-sealed digital isolator chip caused by semiconductor silicon by using insulating adhesive to bond the digital isolator chip to the casing and by allowing the insulating adhesive to overflow and wrap around the isolator chip.

[0035] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A ceramic-encapsulated digital isolator product structure, wherein the digital isolator product structure specifically solves the high-voltage isolation problem of ceramic-encapsulated digital isolators and improves the reliability of ceramic-encapsulated digital isolators, characterized in that, Includes a digital isolator chip (3) and a housing (1). The substrate of the digital isolator chip (3) is a semiconductor silicon wafer. The digital isolator chip (3) is provided with metal bonding pads for the input and output ends of the receiver chip (4) and the transmitter chip (5). The spacing between the metal bonding pads of the input and output ends is increased, that is, the PAD spacing is increased. The size of the digital isolator chip (3) is adapted to the size of the receiver chip (4) and the transmitter chip (5) and remains unchanged. The outer casing (1) and the digital isolator chip (3) are provided with insulating glue (2) for bonding and connecting, and the receiver chip (4) and transmitter chip (5) are also bonded to the digital isolator chip (3) with insulating glue (2); The digital isolator chip (3) is made of semiconductor silicon wafer and thinned by 100μm. The digital isolator chip (3) is bonded to the outer shell (1) with insulating glue (2). At the same time, the insulating glue (2) is required to overflow to cover the side of the digital isolator chip (3) and be placed in the empty sealed cavity.

2. The digital isolator product structure according to claim 1, characterized in that: The digital isolator chip (3) is attached to the outer shell (1), and the top of the outer shell (1) is equipped with a cover plate (7) to form an airtight structure.

3. The digital isolator product structure according to claim 1, characterized in that: The receiver chip (4) and transmitter chip (5) are connected to the digital isolator chip (3) by a bonding wire (6), and then capped to form the digital isolator product.

4. A method for fabricating an isolation structure for a digital isolator chip, wherein the digital isolator product structure according to any one of claims 1 to 3 is characterized in that: Includes the following steps: Step S1: First, according to the product isolation withstand voltage requirement technical document, design and increase the spacing between the metal bonding pads of the input and output terminals on the digital isolator chip without increasing the size of the digital isolator chip; The digital isolator chip with the aforementioned spacing is fabricated using a semiconductor silicon wafer based on a polyimide process line; that is, the primary and secondary PAD spacing of the isolator chip is designed, and the digital isolator chip with the PAD spacing is fabricated using a semiconductor silicon wafer based on a polyimide process line. Step S2: Next, the digital isolator disc is thinned to 100μm and diced with a 30μm thick blade; Step S3: Then, the digital isolator chip (3) is bonded to the housing (1) using insulating glue (2), wherein the insulating glue (2) overflows to cover the side of the digital isolator chip (3); the receiver chip (4) and the transmitter chip (5) are bonded to the digital isolator chip (3) using insulating glue (2), and then the chips are interconnected using bonding wire (6), and then baked. Step S4: Seal the cover plate (7) and the outer shell (1) to form an air-sealed structure, so that the digital isolator chip (3) is sealed in the air-sealed cavity composed of the outer shell (1) and the cover plate (7), and the product is formed.

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