Protection structure for enhancement mode FET of circuit and corresponding method

Abstract

The invention relates to a circuit comprising a self-conducting transistor, referred to as a power transistor, a further transistor, referred to as a control transistor, a further transistor, referred to as a first protection transistor, and a string, referred to as a Zener string, comprising at least one Zener diode, wherein the power transistor is coupled between a first end of the circuit and a first node of the circuit, the control transistor is coupled between the first node and a second end of the circuit, and a gate end of the control transistor is coupled to a third end of the circuit. Wherein the first protection transistor is coupled between the first node and the second terminal, and wherein the Zener string is coupled between the first terminal and a gate terminal of the first protection transistor.

Description

Technical Field

[0001] The present disclosure relates to a circuit and a method for a circuit. Background Art

[0002] The inverter can be used to convert a DC voltage into an AC voltage. The inverter can include a half-bridge or full-bridge circuit, for example in an H configuration. The full-bridge circuit can include four electronically controllable switching units. Each switching unit can include at least one transistor. The switching units can be controlled via a control unit so that an AC voltage can be generated from a DC voltage via a full-bridge circuit, or a DC voltage can be generated from an AC voltage. For example, the inverter can be used by a solar panel to generate an AC voltage from a DC voltage of the solar panel. In another example, the inverter can be used to power an electric motor of an electric vehicle.

[0003] The load at the output of the inverter generally has an inductive component, a capacitive component, and an impedance component. The inductive component of the load may cause the following technical effect: even after the switching unit of the inverter is turned off, the current continues to flow through the load at the output of the inverter, at least for a short time. Due to the aforementioned technical effect, a very high voltage may drop across the switching unit of the inverter. In this regard, it is desirable that the inverter is robust to such high voltages. Summary of the invention

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0005] Aspects of the disclosure are defined in the following claims.

[0006] According to a first aspect of the present disclosure, there is provided a circuit comprising: a self-conducting transistor referred to as a power transistor, a further transistor referred to as a control transistor, a further transistor referred to as a first protection transistor, and a string referred to as a Zener string, the string comprising at least one Zener diode, wherein the power transistor is coupled between a first end of the circuit and a first node of the circuit, wherein the control transistor is coupled between the first node and a second end of the circuit, wherein a gate terminal of the control transistor is coupled to a third end of the circuit, wherein the first protection transistor is coupled between the first node and the second end, and wherein the Zener string is coupled between the first end and the gate terminal of the first protection transistor.

[0007] In one or more embodiments, the power transistor is a gallium nitride transistor, a silicon carbide transistor, or another compound semiconductor transistor.

[0008] In one or more embodiments, the control transistor and the first protection transistor are monolithic.

[0009] In one or more embodiments, the control transistor, the first protection transistor and the at least one Zener diode are monolithic.

[0010] In one or more embodiments, a drain terminal of the power transistor is coupled to the first terminal, and wherein a source terminal of the power transistor is coupled to the first node.

[0011] In one or more embodiments, the gate terminal of the power transistor is coupled to the second terminal.

[0012] In one or more embodiments, the drain terminal of the control transistor is coupled to the first node, and wherein the source terminal of the control transistor is coupled to the second terminal.

[0013] In one or more embodiments, at least one of the control transistor and the first protection transistor is a self-blocking transistor, in particular a silicon Si self-blocking transistor.

[0014] In one or more embodiments, a drain terminal of the first protection transistor is coupled to the first node, and wherein a source terminal of the first protection transistor is coupled to the second terminal.

[0015] In one or more embodiments, the source terminal of the first protection transistor is coupled to the second terminal via at least the first electrical impedance.

[0016] In one or more embodiments, the gate terminal of the first protection transistor is coupled to the second terminal via at least the second electrical impedance.

[0017] In one or more embodiments, the circuit includes a further transistor referred to as a second protection transistor, wherein the second protection transistor is coupled between the first node and the second terminal, and wherein a gate terminal of the second protection transistor is coupled to a source terminal of the first protection transistor.

[0018] In one or more embodiments, a drain terminal of the second protection transistor is coupled to the first node, and wherein a source terminal of the second protection transistor is coupled to the second terminal.

[0019] In one or more embodiments, the second protection transistor is a self-blocking transistor, in particular a self-blocking silicon Si transistor.

[0020] According to a second aspect of the present disclosure, a method for a circuit, the circuit comprising a self-conducting power transistor, a further transistor referred to as a control transistor, a further transistor referred to as a first protection transistor, and a string referred to as a Zener string comprising at least one Zener diode, wherein the power transistor is a gallium nitride transistor or a silicon carbide transistor, wherein the power transistor is coupled between a first end of the circuit and a first node of the circuit, wherein the control transistor is coupled between the first node and a second end of the circuit, wherein a gate terminal of the control transistor is coupled to a third end of the circuit, wherein the first protection transistor is coupled between the first node and the second end, and wherein the Zener string is coupled between the first end and the between the gate terminals of a first protection transistor, and wherein the method comprises the following steps: (a) driving the gate terminal of the control transistor via the third terminal so that the control transistor becomes conductive and sets the circuit in a state referred to as an on-state; (b) driving the gate terminal of the control transistor via the third terminal so that the control transistor becomes blocked and sets the circuit in a state referred to as an off-state; and (c) if the voltage across the Zener string exceeds a reverse voltage predefined by the at least one Zener diode, driving the gate terminal of the protection transistor via the Zener string so that the protection transistor becomes conductive and sets and / or maintains the circuit in a state referred to as a protection state.

[0021] According to a third aspect of the present disclosure, a device is disclosed, the device comprising the circuit of the first aspect of the present disclosure. The device may be an integrated circuit device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered to limit the scope of the present disclosure, such that other equally effective embodiments may be implemented. The advantages of the claimed subject matter will become apparent to those skilled in the art upon reading this specification in conjunction with the accompanying drawings, in which like reference numerals are used to designate like elements, and in which:

[0023] Figure 1 A simplified block diagram of the circuit is shown.

[0024] Figures 2 to 4 Each shows a simplified block diagram of a circuit according to the present disclosure.

[0025] Figures 5 to 7 Each shows a simplified signal flow.

[0026] Figure 8 A simplified block diagram of a system according to the present disclosure is shown.

[0027] Fig. 9 A simplified flow chart is shown. DETAILED DESCRIPTION

[0028] Figure 1 An example embodiment of a circuit 100 is schematically shown. In an example, the circuit 100 may be understood as an apparatus. The circuit 100 comprises a transistor 102 referred to as a power transistor 102 , another transistor 104 referred to as a control transistor 104 and a further transistor 106 referred to as a first protection transistor 106 .

[0029] The power transistor 102 may be a self-conducting transistor. In addition, the power transistor 102 may be configured as a field effect transistor FET. In an example, the power transistor 102 is configured as and / or referred to as a depletion transistor or a depletion FET. The power transistor 102 may also be referred to as a "normally on" transistor. In an example of a self-conducting transistor, conductivity between the source terminal 134 of the power transistor 102 and the drain terminal of the power transistor 102 is possible even without a (positive) gate voltage. The drain-source voltage between the drain terminal 132 and the source terminal 134 may be sufficient to provide a current between the drain terminal and the source terminal. In an example, the self-conducting transistor is configured to block the current between the drain terminal 132 and the source terminal 134 if the gate voltage at the gate terminal 130 is lower than the source voltage at the source terminal 134. Therefore, the current between the drain terminal 132 and the source terminal 134 of the power transistor 102 may be controlled by the gate voltage at the gate terminal 130 and / or the source voltage at the source terminal 134.

[0030] The power transistor 102 is coupled between a first terminal 112 of the circuit 100 and a first node 116 of the circuit 100. The first terminal 112 may be configured as a terminal of the circuit 100 or another node of the circuit 100. In one example, the circuit 100 may form a part of a larger circuit (not shown) such that the circuit 100 may be integrated into the larger circuit. In another example, the circuit 100 may include a device used as a switch unit in the example. In this example, the first terminal 112 may form an end of the switch unit. Figure 8 , an example of a device 153 is schematically shown. The device 153 may form part of an inverter. The device 153 comprises a bridge circuit 154, which is particularly configured as a full bridge and / or an H bridge. The bridge circuit 154 may include a plurality of branches 172, 174, 176, 178. In addition, the bridge circuit 154 may include a plurality of switching units 156, 158, 160, 162. Each branch 172, 174, 176, 178 may include one of the switching units 156, 158, 160, 162. Each switching unit 156, 158, 160, 162 may be formed by a circuit according to the circuit 100.

[0031] In an example, coupling may be understood as a direct electrical connection or an indirect electrical connection, specifically a direct electrical connection or an indirect electrical connection via at least one other electrical component such as a resistor, a capacitor and / or an inductor. If an indirect electrical connection is used, in an example, several components may be electrically connected to each other in a predefined circuit arrangement. A direct electrical connection or an indirect electrical connection may include parasitic components.

[0032] The control transistor 104 may be a self-blocking transistor, specifically a silicon self-blocking transistor. In addition, the control transistor 104 may be configured as a field effect transistor. In an example, the control transistor 104 is configured as and / or referred to as an enhancement transistor or an enhancement FET. The control transistor 104 may also be referred to as a "normally disconnected" transistor. In an example, the control transistor 104 is configured so that in the absence of a positive gate voltage at the gate terminal 118 of the control transistor 104, no conduction electrons (or conduction carriers) are available. In other words, in the absence of a positive gate voltage at the gate terminal 118 of the control transistor 104, no conductivity (and / or conductive channel) is established between the drain terminal 120 and the source terminal 122 of the control transistor 104. In the absence of a positive gate voltage applied to the gate terminal 118 of the control transistor 104, the control transistor 104 is disconnected. On the other hand, if a positive gate voltage is applied to the gate terminal 118 of the control transistor 104, a conductive channel is formed between the drain terminal 120 and the source terminal 122. Therefore, current may flow between the drain terminal 120 and the source terminal 122 via the conductive channel.

[0033] The control transistor 104 is coupled between the first node 116 and the second end 114 of the circuit 100. The second end 114 may be configured as another end of the circuit 100 or another node of the circuit 100. As previously discussed, in an example, the circuit 100 may include a device, such as a switch unit. The switch unit may be a switch unit 156, 158, 160, 162 of a bridge circuit 154. The bridge circuit 154 may form a part of the device 153. In this regard, reference is made to the previous explanations and Figure 8 In this example, the second end 114 may also form a terminal of the switch units 156 , 158 , 160 , 162 .

[0034] The circuit 100 further includes a third terminal 115. The gate terminal 118 of the control transistor 104 is coupled to the third terminal 115. The third terminal 115 may be configured as another terminal of the circuit 100 or another node of the circuit 100. In an example, the third terminal 115 may also form a terminal of the switch units 156, 158, 160, 162.

[0035] In the example, the control transistor 104 is coupled to the power transistor 102 via the first node 116 such that the control transistor 104 can control a gate-source voltage between a gate terminal 130 of the power transistor 102 and a source terminal 134 of the power transistor 102. The control transistor 104 can be controlled via the gate terminal 118 and thus via the third terminal 115. The effect is that the gate-source voltage between the gate terminal 130 of the power transistor 102 and the source terminal 134 of the power transistor 102 can be controlled at least indirectly via the third terminal 115.

[0036] In an example, a drain terminal 132 of the power transistor 102 is coupled to the first terminal 112. The drain terminal 132 may be directly electrically connected to the first terminal 112 via a signal connection.

[0037] The source terminal 134 of the power transistor 102 may be coupled to the first node 116 of the circuit 100. Additionally, the drain terminal 120 of the control transistor 104 may be coupled to the first node 116 of the circuit 100. In an example, the source terminal 134 of the power transistor 102 may be directly coupled to the first node 116 via a signal connection. Additionally, the drain terminal 120 may be directly coupled to the node 116 via a signal connection. The signal connection from the source terminal 134 to the first node 116 and the signal connection from the node 116 to the drain terminal 120 may be configured to include a common signal connection of the first node 116.

[0038] In an example, a source terminal 122 of the control transistor 104 is coupled to the second terminal 114. The source terminal 122 may be directly electrically connected to the second terminal 114 via a signal connection.

[0039] In an example, the gate terminal 130 of the power transistor 102 is coupled to the second terminal 114. The gate terminal 130 of the power transistor 102 may be directly electrically connected to the second terminal 114 via a signal connection. Thus, both the source terminal 122 of the control transistor 104 and the gate terminal 130 of the power transistor 102 may be directly connected to the second terminal 114 via respective signal connections. The signal connections may be at least partially formed together.

[0040] In an example, the control transistor 104 may be controlled via the third terminal 115 to set the control transistor 104 in a conductive state in which a conductive connection is configured between the drain terminal 120 of the control transistor 104 and the source terminal 122 of the control transistor 104. The effect is that the gate-source voltage between the gate terminal 130 and the source terminal 134 is reduced to about 0V or a value such that the self-turning power transistor 102 is set in a conductive state in which a conductive connection is configured between the drain terminal 132 and the source terminal 134. Another effect is that both the power transistor 102 and the control transistor 104 are in a conductive state, so that in an example, the circuit 100 is set in a conductive state in which a conductive connection is configured between the first terminal 112 and the second terminal 114. In an example, the circuit 100 may be controlled via the third terminal 115 to set the circuit 100 in a conductive state. For example, if the voltage generated at the third terminal 115 is greater than the voltage at the second terminal 114, a positive gate-source voltage is generated between the gate terminal 118 and the source terminal 122 of the control transistor 104. The positive gate-source voltage turns on the control transistor 104 at least when the positive gate-source voltage is greater than a predefined threshold voltage.

[0041] In an example, the control transistor 104 may be controlled via the third terminal 115 to set the control transistor 104 in a blocking state in which a current flow between the drain terminal 120 and the source terminal 122 is prevented. The effect is that, in an example, a negative gate-source voltage may be generated between the gate terminal 130 and the source terminal 134 of the power transistor 102, so that the power transistor 102 is set in a blocking state in which a current flow between the drain terminal 132 and the source terminal 134 of the power transistor 102 is prevented.

[0042] exist Figure 5 , an example of a signal waveform of a voltage referred to as control voltage V1 is schematically shown. Control voltage V1 is applied to third terminal 115. At time T0, control voltage V1 has a value C1, so that control transistor 104 is in a blocking state. In an example, value C1 of control voltage V1 may be less than a predefined threshold voltage of control transistor 104. In an example, power transistor 102 is controlled by control transistor 104, so that power transistor 102 is also in a blocking state.

[0043] exist Figure 6 , an example of a waveform of a voltage referred to as transistor voltage V2 is schematically shown, said voltage being between the drain terminal 132 and the source terminal 134 of the power transistor 102. At time T0, the transistor voltage has a value K2.

[0044] In addition to schematically illustrating an example embodiment of circuit 100, Figure 1Also shown is an example where the circuit 100 is included in an example of a larger circuit arrangement 180. In the example, the circuit arrangement 180 includes the circuit 100, an inductor 150 referred to as load inductor 150, an impedance 148 referred to as load impedance 148, and a voltage source 152. The load inductor 150, the load impedance 148, and the voltage source 152 are coupled in series between a first end 112 of the circuit 100 and a second end 114 of the circuit 100.

[0045] Figure 5 The time points T0, T1, T2, T3 indicated in Figure 6 and 7 . Previously, it was explained that the control transistor 104 and the power transistor 102 are each in a blocking state at the time point T0. The effect is that the transistor voltage V2 at the time point T0 will have a value K2, which in the example is at least 80% of the voltage of the voltage source 152. The value of the voltage of the voltage source 152 may be 600V. For example, if both the control transistor 104 and the power transistor 102 are each in a blocking state at the time T0, the transistor voltage V2 may have 500V (as the value K2) at the time T0.

[0046] At time T1, the control voltage V1 changes from value C1 to value C2, which is preferably greater than a predefined threshold voltage of the control transistor 104. The effect is that the control transistor 104 changes from a blocking state to a conducting state, in which a conductive channel is formed between the drain terminal 120 and the source terminal 122. Another effect is that the power transistor 102 changes from a blocking state to a conducting state, thereby forming a conductive channel between the drain terminal 132 and the source terminal 134. Due to the rapid transition of the control voltage V1 from value C1 to value C2, an oscillatory behavior of the transistor voltage V2 occurs at and immediately after time T1. This oscillatory behavior is caused, for example, by the load inductance 150. Due to the oscillatory behavior, the transistor voltage V2 may have a value K3, at least for a short time after time T1. After a short transition phase after time T1, the transistor voltage V2 reaches a value K1. The value K1 is significantly smaller than the value K2.

[0047] At time T2, the control voltage V1 changes from value C2 to value C1, which is preferably less than a predefined threshold voltage of the control transistor 104. The effect is that the control transistor 104 changes from a conducting state to a blocking state, in which a current flow between the drain terminal 120 and the source terminal 122 is prevented. Another effect is that the power transistor 102 changes from a conducting state to a blocking state, thereby preventing a current flow between the drain terminal 132 and the source terminal 134. Due to the fast transition of the control voltage from value C2 to value C1, there is a (further) oscillation of the transistor voltage V2 at and immediately after time T2. This (further) oscillatory behavior is caused, for example, by the load inductance 150. Due to the (further) oscillatory behavior, the transistor voltage V2 may have a value K4 that is significantly greater than value K2 and / or greater than value K3, at least for a short time after time C2. After a short transition phase after time T2, the transistor voltage V2 reaches value K2.

[0048] The value K4 of the transistor voltage V2 causes high stress on the power transistor 102. Therefore, in particular if the transistor voltage V2 has the value K4, measures are required to prevent avalanche breakdown in the power transistor 102. However, these measures lead to increased costs and a larger size of the power transistor 102. Both increased costs and larger size are undesirable and are to be avoided.

[0049] According to the present disclosure, a circuit 100 is therefore provided comprising a string 108 , referred to as Zener string 108 , and a further transistor 106 , referred to as first protection transistor 106 . Figure 2 An example of an embodiment of the circuit 100 is schematically shown in FIG.

[0050] The first protection transistor 106 is coupled between the first node 116 and the second terminal 114. In an example, a drain terminal 126 of the protection transistor 106 is directly or indirectly connected to the first node 116. A source terminal 128 of the first protection transistor 106 may be directly or indirectly connected to the second terminal 114.

[0051] The first protection transistor 106 may be a self-blocking transistor, specifically a silicon self-blocking transistor. In addition, the first protection transistor 106 may be configured as a field effect transistor. In an example, the first protection transistor 106 is configured as and / or referred to as an enhancement transistor or an enhancement FET. The first protection transistor 106 may also be referred to as a "normally disconnected" transistor. In an example, the first protection transistor 106 is configured so that in the absence of a positive gate voltage at the gate terminal 124 of the first protection transistor 106, no conduction electrons (or conduction carriers) are available. In other words, in the absence of a positive gate voltage at the gate terminal 124 of the first protection transistor 106, no conductivity (and / or conductive channel) is established between the drain terminal 126 and the source terminal 128 of the first protection transistor 106. In the absence of a positive gate voltage applied to the gate terminal 124 of the first protection transistor 106, the first protection transistor 106 is disconnected. On the other hand, if a positive gate voltage is applied to the gate terminal 124 of the first protection transistor 106, a conductive channel is formed between the drain terminal 126 and the source terminal 128. Therefore, current may flow between the drain terminal 126 and the source terminal 128 via the conductive channel.

[0052] The Zener string 108 is coupled between the first terminal 112 and the gate terminal 124 of the first protection transistor 106. The Zener string 108 includes at least one Zener diode 110. Along the direction of the Zener string 108 from the first terminal 112 to the gate terminal 124 of the first protection transistor 106 (referred to as the string direction), the at least one Zener diode 110 may be arranged and / or integrated in the Zener string 108 in a reverse direction.

[0053] In an example, the Zener string 108 and / or the at least one Zener diode 110 are configured such that there is a predefined breakdown voltage. The breakdown voltage may be 600V or have a value between 400V and 800V. If a voltage referred to as the string voltage having at least the value of the breakdown voltage is applied across the Zener string 108 (in the string direction), the at least one Zener diode 110 changes from a blocking state to a conducting state. The greater the value of the string voltage above the breakdown voltage, the more conductive the at least one Zener diode 110 becomes.

[0054] In an example, the Zener string 108 and / or the at least one Zener diode 110 are configured such that the predefined breakdown voltage is defined such that if a voltage between the first terminal 112 and the second terminal 114, referred to as the circuit voltage, reaches and / or exceeds a predefined circuit voltage reference value, the Zener string 108 changes to a conducting state (in the reverse direction). The effect is that the conducting Zener string 108 (in the reverse direction) can control the gate terminal 124 of the first protection transistor 106, such that the first protection transistor 106 changes to a conducting state. In an example, the Zener string 108 and / or the at least one Zener diode 110 are configured such that if the circuit voltage between the first terminal 112 and the second terminal 114 reaches and / or exceeds a predefined circuit voltage reference value, the breakdown voltage is defined such that the first protection transistor 106 is controlled to a conducting state via the Zener string 108.

[0055] In an example, the Zener string 108 and / or the at least one Zener diode 110 are configured such that a breakdown voltage is defined such that if a circuit voltage between the first terminal 112 and the second terminal 114 drops below a predefined reference value, the Zener string 108 changes to a blocking state in a blocking direction. The effect is that the reverse blocking Zener string 108 can control the gate terminal 124 of the first protection transistor 106 such that the first protection transistor 106 changes to a blocking state. In an example, the Zener string 108 and / or the at least one Zener diode 110 are configured such that if a circuit voltage between the first terminal 112 and the second terminal 114 drops below a predefined circuit voltage reference value, the breakdown voltage is defined such that the first protection transistor 106 is controlled to a blocking state via the Zener string 108.

[0056] refer to Figure 2 In the circuit arrangement 180 , the circuit voltage reference value may be set to, for example, the voltage value of the voltage source 152 and / or to a voltage value that is, for example, at most 20%, at most 15% or at most 10% greater than the voltage value of the voltage source 152 .

[0057] about Figure 2 The circuit 100 is similarly referred to as for Figure 1 The foregoing explanations, preferred features, technical effects and / or advantages explained by the circuit 100 are as follows. However, Figure 2 The circuit 100 includes a Zener string 108 and a first protection transistor 106 , which together cause the oscillatory response of the transistor voltage V2 to be significantly reduced after time T1 and / or after time T2 . Figure 7 It is schematically shown in Figure 2 1 is an example of a signal waveform of the transistor voltage V2 of the circuit 100.

[0058] If combined Figure 1As explained, the control voltage V1 may change from the value C2 to the value C1 at time T2, so that the control transistor 104 changes from the on state to the off state at time T2. Figure 7 It can be seen that the signal waveform of the transistor voltage V2 immediately after time T2 does not exhibit a particularly large oscillation response. On the contrary, the maximum value K6 of the transistor voltage V2 after time T2 is only slightly greater than the value K2 of the transistor voltage V2. Immediately after time T2, the transistor voltage V2 increases, so that the circuit voltage between the first terminal 112 and the second terminal 114 also increases. In an example, the Zener string 108 and / or at least one Zener diode 110 can be configured so that if the transistor voltage V2 becomes greater than the value K2, the string voltage reaches a predefined breakdown voltage of at least one Zener diode 110. The effect is that when the breakdown voltage is reached, the first protection transistor 106 is set in a conductive state. The first protection transistor 106 causes conduction between the first node 116 and the second terminal 114, and at the same time, the first control transistor 104 can be in a blocking state. Although the first control transistor 104 is in a blocking state, the conductive connection established by the first protection transistor 106 between the first node 116 and the second terminal 114 can cause the power transistor 102 to be (or continue to be) set in a conductive state. Therefore, a conductive connection is established between the first terminal 112 and the second terminal 114, so that the transistor voltage V2 between the drain terminal 132 and the source terminal 134 is limited to a value of K6. Due to the conductive connection between the first terminal 112 and the second terminal 114, the transistor voltage V2 decreases again after reaching the value K6. In a similar manner, the circuit voltage between the first terminal 112 and the second terminal 114 will also decrease again. In an example, reducing the circuit voltage can also reduce the string voltage and reach a value less than the predefined breakdown voltage of the at least one Zener diode 110. The effect is that the at least one Zener diode 110 is turned back to the blocking state. Another effect is that when the at least one Zener diode 110 reaches the blocking state, the first protection transistor 106 is also driven back to the blocking state. The conductive connection between the first node 116 and the second terminal 114 previously caused by the first protection transistor 106 is disconnected again due to the blocking state of the first protection transistor 106. Assuming that the control transistor 104 is still in the blocking state, both the first protection transistor 106 and the control transistor 104 are in the blocking state. Depending on the oscillatory behavior of the transistor voltage V2 and / or depending on the circuit voltage (between the first terminal 112 and the second terminal 114), the first protection transistor 106 can be changed in a controlled manner between a blocking state and a conducting state via the Zener string 108 in order to attenuate possible oscillatory behavior of the transistor voltage V2 and / or the circuit voltage. In a similar manner, the Zener string 108 and the first protection transistor 106 can be used to attenuate the oscillatory behavior of the transistor voltage and / or the circuit voltage immediately after the time T1.

[0059] Since the oscillatory behavior of the transistor voltage V2 and / or the circuit voltage is advantageously weakened by means of the Zener string 108 and the first protection transistor 106, the cost and size of the power transistor 102 can be reduced. Specifically, it is no longer necessary to ensure a large overvoltage rating of the power transistor 102. Alternatively, a small overvoltage rating may be sufficient for the power transistor 102, thereby reducing the cost and size of the power transistor 102. Due to the smaller size of the power transistor 102, a higher control speed of the power transistor 102 from the on state to the blocking state, as well as a higher control speed of the power transistor 102 from the blocking state to the on state can be achieved. Simply put, the power transistor 102 becomes faster as its size decreases.

[0060] In an example, the size of the first protection transistor 106 is less than 50%, 40%, 10%, or 5% of the size of the control transistor 104 .

[0061] exist Figure 3 , another example of an embodiment of the circuit 100 is schematically shown. Figure 3 Circuit 100, in a similar manner, reference is made to the aforementioned explanations, preferred features, technical effects and advantages, which have been combined Figure 2 The circuit 100 is explained.

[0062] and Figure 2 Compared with the circuit 100, Figure 3 The difference of the circuit 100 of the embodiment of the present invention lies specifically in the Zener string 108. The Zener string 108 includes a plurality of Zener diodes 110, 166. Specifically, the plurality of Zener diodes 110, 166 are connected in series. Due to the series connection of the plurality of Zener diodes 110, 166, a common breakdown voltage of the Zener string 108 may be generated, above which all Zener diodes 110, 166 change from a blocking state to a conducting state at the same time. In the string direction from the first end 112 to the gate terminal 124, each Zener diode 110, 166 may be reverse biased and / or integrated into the Zener string 108. The Zener string 108 may further include at least one (conventional) diode 168. In an example, the Zener string 108 may include one (conventional) diode 168 specifically associated with each Zener diode 110, 166. Each (conventional) diode may have its respective forward direction in the string direction.

[0063] In an example, the Zener string 108 may include a plurality of Zener diodes 110, 166 arranged monolithically integrated with each other. Specifically, each Zener diode 110, 166 is configured as a polysilicon Zener diode 110, 166 and / or is made of and / or with polysilicon.

[0064] In an example, the circuit 100 includes a first electrical impedance 136. The first electrical impedance 136 can be coupled between the first protection transistor 106 and the second terminal 114. In an example, the first impedance 136 is coupled between the gate terminal 124 and the second terminal 114. The first electrical impedance 136 supports an attenuation characteristic of the Zener string 108 and / or the first protection transistor 106.

[0065] In an example, the control transistor 104 and the first protection transistor 106 are monolithically integrated into a single semiconductor chip of the circuit 100. Specifically, the monolithic integration may be achieved by coupling a drain terminal 126 of the first protection transistor 106 and a drain terminal 120 of the control transistor to each other and / or to the first node 116. The monolithic integration of the two transistors 104, 106 may enable a particularly small size of the circuit 100.

[0066] In an example, the control transistor 104, the first protection transistor 106, and the at least one Zener diode 110, 166 of the Zener string 108 are monolithically integrated in a single semiconductor chip of the circuit 100. The at least one Zener diode 110, 166 may be isolated from the control transistor 104 and / or the first protection transistor 106 in the semiconductor chip. By monolithically integrating the two transistors 104, 106 and the at least one Zener diode 110, 166, an even smaller size of the circuit 100 may be achieved.

[0067] However, it is also possible that the at least one Zener diode 110 , 166 of the Zener string 108 is not monolithically integrated into the semiconductor chip, but that the at least one Zener diode 110 , 166 is a discrete component.

[0068] In an example, the power transistor 102 is configured as a compound semiconductor transistor. The compound semiconductor may be selected and / or used in the transistor such that the power transistor 102 allows for a high transistor voltage and a high drain-source current.

[0069] In an example, the power transistor 102 is configured as a gallium nitride (GaN) transistor. The power transistor 102 configured as a GaN transistor provides the following advantages: the power transistor 102 allows a high transistor voltage and / or a high drain-source current while providing very fast switching times. In addition, the GaN transistor provides a smaller channel resistance. The small channel resistance allows the power transistor 102 to have a small package size, which also allows the circuit 100 to include a small package size.

[0070] In an example, the power transistor 102 is configured as a silicon carbide SiC transistor. The power transistor 102 configured as a SiC transistor provides the following advantages: the power transistor 102 allows for a high transistor voltage and / or drain-source current while also providing very fast switching times. In addition, the SiC transistor provides a small channel resistance. The small channel resistance allows the size of the power transistor 102 to be smaller, which also allows the circuit 100 to include a small package size.

[0071] exist Figure 4 , schematically illustrates an example of a further embodiment of the circuit 100. Figure 4 The circuit 100 is similarly referred to for Figure 3 Advantageous explanations, advantageous features, technical effects and / or advantages explained by the circuit 100.

[0072] In an example, the circuit 100 includes another transistor 140 referred to as a second protection transistor 140. The second protection transistor 140 may be coupled between the first node 116 and the second terminal 114. In an example, a drain terminal 144 of the second protection transistor 140 is directly or indirectly electrically connected to the first node 116. In an example, a source terminal 146 of the second protection transistor 140 is directly or indirectly electrically connected to the second terminal 114. In an example, a gate terminal 142 of the second protection transistor 140 is directly or indirectly electrically connected to the source terminal 128 of the first protection transistor 106. The circuit 100 may further include a second electrical impedance 138. The second electrical impedance 138 may be coupled between the source terminal 128 (or gate terminal 142) and the second terminal 114. In an example, the source terminal 128 and the gate terminal 142 may be directly electrically connected to each other. Both the source terminal 128 and the gate terminal 142 may be electrically connected to the second terminal 114 (indirectly) via the second electrical impedance 138.

[0073] The second protection transistor 140 can be a self-blocking transistor, specifically a silicon self-blocking transistor. In addition, the second protection transistor 140 can be configured as a field effect transistor. In an example, the second protection transistor 140 is configured as and / or referred to as an enhancement transistor or an enhancement FET. The second protection transistor 140 may also be referred to as a "normally disconnected" transistor. In an example, the second protection transistor 140 is configured so that in the absence of a positive gate voltage at the gate terminal 142 of the second protection transistor 140, no conduction electrons (or conduction carriers) are available. In other words, in the absence of a positive gate voltage at the gate terminal 142 of the second protection transistor 140, no conductivity (and / or conductive channel) is established between the drain terminal 144 and the source terminal 146 of the second protection transistor 140. In the absence of a positive gate voltage applied to the gate terminal 142 of the second protection transistor 140, the second protection transistor 140 is disconnected. On the other hand, if a positive gate voltage is applied to the gate terminal 142 of the second protection transistor 140, a conductive channel is established between the drain terminal 144 and the source terminal 146. Therefore, current may flow between the drain terminal 144 and the source terminal 146 via the conductive channel.

[0074] The first protection transistor 106 and / or the second protection transistor 140 may be coupled in a Darlington arrangement. The effect is that the current through the Zener string 108 to control the first protection transistor 106 may be kept small, at least relative to the second protection transistor 140. In addition, the Darlington arrangement of the first protection transistor 106 and the second protection transistor 140 provides the following advantages: a conductive connection can be made particularly quickly across the second protection transistor 140 after at least one Zener diode 110, 166 has changed to a conductive state. In an example, the Zener string 108 includes a plurality of Zener diodes 110, 166. The plurality of Zener diodes 110, 166 may generate a corresponding series resistance through the Zener string 108, which makes it difficult to quickly change the state of the second protection transistor 140. In an example, the size of the first protection transistor 106 is less than 50%, 40%, 30%, or 20% of the size of the second protection transistor 140. The drain terminal 144 of the second protection transistor 140 may be directly electrically connected to the first node 116, and the source terminal 146 may be directly electrically connected to the second terminal 114, so that the second protection transistor 140 may at least substantially function to suppress the oscillation response immediately after the time point T1 and / or immediately after the time point T2. Figure 4The first protection transistor 106 in the example of FIG. 1 can be used at least substantially to control the second protection transistor 140. If the first protection transistor 106 comprises a smaller size, in particular a significantly smaller size, than the second protection transistor 140, the Zener string 108 can result in a fast control response of the first protection transistor 106 and thus of the second protection transistor 140, although the series resistance may be large.

[0075] In an example, the control transistor 104, the first protection transistor 106, and the second protection transistor 140 are monolithically integrated into a single semiconductor chip of the circuit 100. Specifically, the monolithic integration may be achieved by coupling the drain terminal 126 of the first protection transistor 106, the drain terminal 144 of the second protection transistor 140, and the drain terminal 120 of the control transistor 104 to each other and / or to the first node 116. The monolithic integration of the three transistors 104, 106, 140 enables a particularly small size of the circuit 100.

[0076] In an example, the control transistor 104, the first protection transistor 106, the second protection transistor 140, and the at least one Zener diode 110, 166 of the Zener string 108 are monolithically integrated in a single semiconductor chip of the circuit 100. The at least one Zener diode 110, 166 may be isolated from the control transistor 104, the first protection transistor 106, and / or the second protection transistor 140 in the semiconductor chip. By monolithically integrating the three transistors 104, 106, 140 and the at least one Zener diode 110, 166, an even smaller size of the circuit 100 may be achieved.

[0077] However, it is also possible that the at least one Zener diode 110 , 166 of the Zener string 108 is not monolithically integrated into the semiconductor chip, but that the at least one Zener diode 110 , 166 is a discrete component.

[0078] In an example, the control transistor 104, the first protection transistor 106, and / or the second protection transistor 140 may be LFETs. In an example, the LEF configuration may allow and / or support the Zener diodes 110, 166 to be constructed from or with polysilicon.

[0079] Fig. 9 An example of an embodiment of a method 200 is schematically shown. The method 200 refers to a method for the circuit 100, wherein the method comprises the following steps:

[0080] a) driving the gate terminal of the control transistor via the third terminal so that the control transistor becomes conductive and sets the circuit in a state referred to as an on-state,

[0081] b) driving the gate terminal of the control transistor via the third terminal so that the control transistor becomes blocking and places the circuit in a state referred to as the off state, and

[0082] d) If the voltage across the Zener string exceeds a reverse voltage predefined by the at least one Zener diode, driving the gate terminal of the protection transistor via the Zener string such that the protection transistor becomes conductive and sets and / or maintains the circuit in a state referred to as the protection state.

[0083] For the method 200 , reference is made in an analogous manner to the above explanations, preferred features, technical effects and advantages as explained in conjunction with the circuit 100 , the circuit arrangement 180 and / or the device 153 .

[0084] Although the described exemplary embodiments disclosed herein focus on devices, systems, and methods of using the same, the present disclosure is not necessarily limited to the example embodiments shown herein.

[0085] The systems and methods described herein may be embodied, at least in part, by a computer program or multiple computer programs, which may exist in a single computer system or across multiple computer systems in a variety of forms in both active and inactive states. For example, the computer program may exist as a software program consisting of program instructions in source code, object code, executable code, or other formats for performing some steps. Any of the above formats may be implemented in compressed or uncompressed form on a computer-readable medium, which may include storage devices and signals.

[0086] It should be noted that the above embodiments have been described with reference to different subject matters. Specifically, some embodiments may have been described with reference to method claims, while other embodiments may have been described with reference to apparatus claims. However, those skilled in the art will appreciate from the foregoing that, unless otherwise stated, any combination of features relating to different subject matters, in particular a combination of features of a method claim with features of an apparatus claim, in addition to any combination of features belonging to one type of subject matter, is also deemed to be disclosed with this document.

[0087] In addition, it should be noted that the drawings are schematic. In different drawings, similar or identical elements are represented by the same figure mark. In addition, it should be noted that in order to provide a concise description of the illustrative embodiments, the implementation details that belong to the customary practices of technicians may not be described. It should be understood that in the development of any such implementation scheme, as in any engineering or design project, a large number of implementation scheme-specific decisions must be made in order to achieve the specific goals of the developer, such as complying with system-related and business-related constraints, which may be different in different implementation schemes. In addition, it should be understood that such development work may be complex and time-consuming, but it is nothing more than a routine task for those skilled in the art to design, manufacture and produce.

[0088] Finally, it should be noted that a person skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claims. The words "comprise(s)" or "comprising" do not exclude the presence of elements or steps other than those listed in the claims. The words "a" or "an" preceding an element do not exclude the presence of a plurality of such elements. The measures recited in the claims may be implemented by means of hardware comprising several different elements and / or by means of a suitably programmed processor. In a device claim listing several components, several of these components may be embodied by the same item in hardware. The mere fact that certain measures are recited in different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0089] Unless otherwise stated, terms such as "first," "second," etc., are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal priority or other priority of such elements.

Claims

1. A circuit, characterized in that: include: A self-conducting transistor called a power transistor, Another transistor called the control transistor, a further transistor referred to as a first protection transistor, and a string called a Zener string, said string comprising at least one Zener diode, wherein the power transistor is coupled between a first terminal of the circuit and a first node of the circuit, wherein the control transistor is coupled between the first node and a second terminal of the circuit, wherein the gate terminal of the control transistor is coupled to a third terminal of the circuit, wherein the first protection transistor is coupled between the first node and the second terminal, and The Zener string is coupled between the first terminal and a gate terminal of the first protection transistor.

2. Circuit according to the preceding claim, characterized in that The power transistor is a gallium nitride transistor, a silicon carbide transistor, or another compound semiconductor transistor.

3. A circuit according to any preceding claim, characterised in that The control transistor and the first protection transistor are monolithic.

4. The circuit according to any one of the preceding claims 1 to 2, characterized in that The control transistor, the first protection transistor and the at least one Zener diode are monolithic.

5. A circuit according to any preceding claim, characterised in that A drain terminal of the power transistor is coupled to the first terminal, and wherein a source terminal of the power transistor is coupled to the first node.

6. A circuit according to any preceding claim, characterised in that The gate terminal of the power transistor is coupled to the second terminal.

7. A circuit according to any preceding claim, characterised in that A drain terminal of the control transistor is coupled to the first node, and wherein a source terminal of the control transistor is coupled to the second terminal.

8. A circuit according to any preceding claim, characterised in that At least one of the control transistor and the first protection transistor is a self-blocking transistor, specifically a silicon Si self-blocking transistor.

9. A circuit according to any preceding claim, characterised in that A drain terminal of the first protection transistor is coupled to the first node, and wherein a source terminal of the first protection transistor is coupled to the second terminal.

10. A method for a circuit, characterized in that, The circuit comprises a self-conducting power transistor, a further transistor referred to as a control transistor, a further transistor referred to as a first protection transistor and a string referred to as a Zener string comprising at least one Zener diode, wherein the power transistor is a gallium nitride transistor or a silicon carbide transistor, wherein the power transistor is coupled between a first end of the circuit and a first node of the circuit, wherein the control transistor is coupled between the first node and a second end of the circuit, wherein a gate terminal of the control transistor is coupled to a third end of the circuit, wherein the first protection transistor is coupled between the first node and the second end, and wherein the Zener string is coupled between the first end and the gate terminal of the first protection transistor, and wherein the method comprises the following steps: a) driving the gate terminal of the control transistor via the third terminal so that the control transistor becomes conductive and sets the circuit in a state referred to as an on-state, b) driving the gate terminal of the control transistor via the third terminal so that the control transistor becomes blocking and places the circuit in a state referred to as an off state, and c) if the voltage across the Zener string exceeds a reverse voltage predefined by the at least one Zener diode, driving the gate terminal of the protection transistor via the Zener string such that the protection transistor becomes conductive and sets and / or maintains the circuit in a state referred to as a protection state.

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