Ultra-low power consumption and high-speed level shift circuit and method based on subthreshold conduction

Abstract

An ultra-low power consumption and high speed level shift circuit and method based on subthreshold conduction comprises an input shift circuit and a low power consumption output buffer, the input shift circuit comprises a pull-up network, a pull-down network and a feedback transistor, the pull-up network is of a current mirror structure, the pull-down network is composed of a first pull-down tube and a second pull-down tube, and the feedback transistor is connected with the first pull-down tube and the second pull-down tube. A feedback transistor is added, and when input signal high level conduction succeeds, the current mirror structure is switched off; and the second pull-down tube uses a common-gate transistor, and pulls down the output end of the input shift circuit to a low level by using the sub-threshold conduction principle of the common-gate transistor when the input signal is at a low level. According to the invention, the conversion speed of the falling edge signal in the circuit is effectively improved, the time delay is reduced, the static power consumption is ultralow, the wide voltage conversion range is provided, and meanwhile, the area is very small.

Description

Technical Field

[0001] The present invention belongs to the technical field of level conversion, and more specifically, relates to an ultra-low power consumption, high-speed level shifting circuit and method based on subthreshold conduction. Background Art

[0002] As the complexity of System on Chip (SoC) increases, power consumption also increases. The most effective and direct way to reduce the power consumption of integrated circuits and systems is to reduce their power supply signals. Therefore, circuit modules often work between different core signal domains, and the level conversion between domains depends on the level shifter (LS). Subthreshold LS can convert the signal VDDL below the MOSFET threshold signal into the signal VDDH above the threshold signal, and has attracted much attention in some low-power applications, such as wireless sensor networks, environmental monitoring systems, and micro medical devices. LS needs to provide a wide signal conversion range to enable different signal domains to communicate with each other within the SoC. Power consumption and propagation delay are two important characteristics of LS. As the number of signal domains in the SoC increases, the number of LS required also increases, and the power consumption and delay associated with these LS also increase, which has an important impact on the overall performance of the system.

[0003] At present, there are two typical LS: Figure 1 The Cross-Coupled Level Shift (CCLS) circuit shown in FIG. Figure 2 The Current Mirror Level Shift (CMLS) circuit based on current mirror is shown.

[0004] There is a serious competition problem between the PMOS in the pull-up network of CCLS and the NMOS in the pull-down network, which causes the signals at points A and B to fail to drop below the thresholds of M3 and M4 quickly, affecting the transmission delay of the entire circuit. CMLS uses a current mirror to replace the cross-coupling part, getting rid of the transistor competition problem, but it also greatly increases the static power consumption of the circuit, which does not meet the application requirements of low-power SOC design. At the same time, the traditional structure uses an inverter as a high-low signal conversion unit at the input end, and the propagation delay in the subthreshold region is longer, resulting in the traditional LS having a longer falling edge delay than the rising edge delay when transmitting signals, which does not meet the application requirements of increasingly higher signal frequencies, and in severe cases may even change the duty cycle of the signal.

[0005] Currently, high-speed, low-power level shift circuits are relatively complex and large in area. In view of the actual application requirements and the drawbacks of the above structures, researchers are exploring new design methods to simplify the circuits, reduce the area, and maintain or improve the performance of the circuits. Summary of the invention

[0006] In view of the problems of long transmission delay and high power consumption in traditional level shifting circuits, the present invention provides an ultra-low power consumption, high-speed level shifting circuit and method based on subthreshold conduction, which uses feedback transistors to eliminate static current, uses common-gate transistors to remove the inverter in the traditional solution, adds a low-power output buffer, and uses self-biased transistors to reduce power consumption.

[0007] The first aspect of the present invention proposes an ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction, including an input shift circuit and a low power consumption output buffer, specifically:

[0008] An input shift circuit, whose input terminal is connected to an input signal and whose output terminal is connected to a low-power output buffer for level shifting;

[0009] The input end of the low power output buffer is connected to the output end of the input shift circuit, and its output end serves as the output end of the subthreshold conduction level shift circuit. The level of the buffer output end is consistent with the input end for signal transmission.

[0010] Preferably, the input shift circuit comprises a pull-up network, a pull-down network and a feedback transistor.

[0011] The pull-up network is a current mirror structure, and the pull-down network consists of a first pull-down tube and a second pull-down tube.

[0012] The source end of the current mirror is connected to the high level VDDH of the desired output, the input end of the current mirror is connected to the output end of the first pull-down tube through the feedback transistor, and the output end of the current mirror is connected to the output end of the second pull-down tube as the output end of the input shift circuit.

[0013] The input signal VIN is connected to the input end of the first pull-down tube and the input end of the second pull-down tube respectively, the fixed potential end of the first pull-down tube is connected to the ground, and the fixed potential end of the second pull-down tube is connected to the low level VDDL;

[0014] When the input voltage VIN is at a high level, the first pull-down tube is turned on, the second pull-down tube is turned off, the input end of the current mirror is pulled down to a low level, and the output end of the input shift circuit is pulled up to a high level VDDH;

[0015] When the input voltage VIN is at a low level, the first pull-down tube is turned off, the second pull-down tube is turned on, and the output end of the input shift circuit is pulled down to a low level. Preferably, the feedback transistor is used to control the on or off of the current mirror input branch; the control end of the feedback transistor is connected to the feedback signal, and the effective state of the feedback signal is: when VIN is at a high level, the signal representing the successful conduction of the input signal high level in the low-power output buffer. Preferably, the second pull-down tube uses a common-gate transistor, with the source as the input end and the drain as the output end, and the gate is connected to a fixed level VDDL. When the source input is at a low level, the transistor is subthreshold turned on.

[0016] Preferably, the current mirror comprises a PMOS tube M16 and a PMOS tube M17, the sources of the two PMOS tubes are connected to the high level VDDH, the gate and drain of the PMOS tube M16 and the gate of the PMOS tube M17 are connected as the input end of the current mirror, and the drain of the PMOS tube M17 serves as the output end of the current mirror;

[0017] The feedback transistor is an NMOS tube M15, the drain of the feedback transistor is connected to the drain of the PMOS tube M16, the source of the feedback transistor is connected to the output end of the first pull-down tube, and the gate of the feedback transistor serves as a control end;

[0018] The first pull-down tube is an NMOS tube M13, the gate of the NMOS tube M13 is connected to the input signal VIN of the input shift circuit as an input terminal, the source is connected to the ground as a fixed potential terminal, and the drain is connected to the source of the feedback transistor as an output terminal;

[0019] The second pull-down tube is an NMOS tube M14, whose gate is connected to the low level VDDL, whose source is connected to the input signal VIN of the input shift circuit as an input terminal, and whose drain is connected to the drain terminal of the PMOS tube M17 as an output terminal of the input shift circuit.

[0020] Preferably, the low-power output buffer is composed of a first inverter and a second inverter connected in series, and the output signal of the output end of the input shift circuit is reversed twice. The first inverter is composed of a PMOS tube M18, a self-biased transistor M19 and an NMOS tube M20 connected in series in sequence. The source of the PMOS tube M18 is connected to VDDH, the drain is connected to the drain of the NMOS tube M20 through the self-biased transistor M19, the gate is connected to the gate of the NMOS tube M20, and the source of the NMOS tube M20 is connected to the ground;

[0021] The second inverter is composed of a PMOS tube M21 and an NMOS tube M22 connected in series. The source of the PMOS tube M21 is connected to VDDH, the drain is connected to the drain of the NMOS tube M22, and the gate is connected to the drain of the PMOS tube M18. The source of the NMOS tube M22 is connected to the ground, and the gate is connected to the drain of the NMOS tube M20.

[0022] Preferably, the self-biasing transistor divides the output terminal of the first inverter into two;

[0023] The self-biased transistor is a PMOS tube M19, whose source is connected to the drain of the PMOS tube M18 as the first output end of the first inverter; whose drain and gate are connected to the drain of the NMOS tube M20 as the second output end of the first inverter.

[0024] Preferably, the signal F outputted from the second output terminal of the first inverter is a feedback signal representing successful high-level conduction of the input signal, and is inputted to the control terminal of the feedback transistor of the input shift circuit.

[0025] The second aspect of the present invention provides an ultra-low power consumption, high-speed level shifting method based on subthreshold conduction using the circuit described in the first aspect, specifically:

[0026] When level shifting is required, an input signal is sent to the input shift circuit. If it is required to shift to the high level VDDH, the input signal changes from a low level to a high level, controlling the first pull-down tube to be turned on and the second pull-down tube to be turned off. Otherwise, the input signal changes from a high level to a low level, controlling the first pull-down tube to be turned off and the second pull-down tube to be turned on at a sub-threshold value.

[0027] When the first pull-down tube is turned on, the control end of the current mirror is pulled down to a low level, and the output of the input shift circuit is a high level VDDH; when the second pull-down tube is turned on, the output of the input shift circuit is a low level;

[0028] The signal output from the output end of the input shift circuit is transmitted to the low-power output buffer, is inverted by the first inverter, and the dead time of the second inverter is increased by the self-biased transistor in the first inverter, and is then inverted by the second inverter and output;

[0029] At the same time, the feedback signal of the second output terminal of the first inverter is transmitted to the feedback transistor of the input shift circuit. When the input signal changes from a low level to a high level, the feedback signal changes from a high level to a low level, controls the feedback transistor to turn off, and interrupts the current mirror current.

[0030] The beneficial effects of the present invention are that, compared with the prior art, (1) a subthreshold conduction common-gate transistor is used to replace the traditional inverter as the input end, and the signal is transmitted by utilizing the principle of subthreshold conduction of the common-gate transistor, which effectively improves the conversion speed of the falling edge signal in the circuit, reduces the delay, and the subthreshold conduction current is low, which is conducive to reducing the overall power consumption. (2) A novel low-power output buffer is designed, and a self-biased transistor is added between the NMOS tube and the PMOS tube of the first inverter, so that the input end of the second inverter is separated. On the one hand, a dead time is generated between the NMOS tube and the PMOS tube of the second inverter, and on the other hand, the drain-source voltage of the NMOS tube and the PMOS tube of the first inverter is reduced, so that its conduction current is reduced. (3) A feedback transistor is added, and the input signal of the second inverter NMOS tube of the low-power output buffer is used as the feedback signal to control the conduction and shutdown of the current mirror branch, so that the branch only generates current at the edge of VIN, thereby having ultra-low static power consumption; (4) In addition, the circuit of the present invention uses only ten transistors to realize the subthreshold level shifting function, providing a wide voltage conversion range while having a very small area. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of a level shift circuit based on a cross-coupling pair in the prior art;

[0032] Figure 2 It is a schematic diagram of a level shift circuit based on a current mirror in the prior art;

[0033] Figure 3 It is a schematic diagram of the level shift circuit disclosed in the present invention;

[0034] Figure 4 This is a circuit working state diagram when the input signal is converted from low to high in an embodiment of the present invention;

[0035] Figure 5 This is a circuit working state diagram when the input signal is converted from high to low in an embodiment of the present invention;

[0036] Figure 6 is a signal timing diagram of input and output signals in an embodiment of the present invention;

[0037] Figure 7 This is a diagram of the static current simulation result of the level shift circuit of the present invention;

[0038] Figure 8 It is the simulation result of CMSL static current in the prior art; DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The embodiments described in this application are only embodiments of a part of the present invention, rather than all embodiments. Based on the spirit of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the protection scope of the present invention.

[0040] like Figure 3 As shown, Embodiment 1 of the present invention discloses an ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction, including an input shift circuit and a low power consumption output buffer, specifically:

[0041] An input shift circuit, whose input terminal is connected to an input signal and whose output terminal is connected to a low-power output buffer for level shifting;

[0042] The input end of the low power output buffer is connected to the output end of the input shift circuit, and its output end serves as the output end of the subthreshold conduction level shift circuit. The level of the buffer output end is consistent with the input end for signal transmission.

[0043] Preferably, the input shift circuit comprises a pull-up network, a pull-down network and a feedback transistor.

[0044] The pull-up network is a current mirror structure, and the pull-down network consists of a first pull-down tube and a second pull-down tube.

[0045] The source end of the current mirror is connected to the high level VDDH of the desired output, the input end of the current mirror is connected to the output end of the first pull-down tube through the feedback transistor, and the output end of the current mirror is connected to the output end of the second pull-down tube as the output end of the input shift circuit.

[0046] The input signal VIN is connected to the input end of the first pull-down tube and the input end of the second pull-down tube respectively, the fixed potential end of the first pull-down tube is connected to the ground, and the fixed potential end of the second pull-down tube is connected to the low level VDDL;

[0047] When the input voltage VIN is at a high level, the first pull-down tube is turned on, the second pull-down tube is turned off, the input end of the current mirror is pulled down to a low level, and the output end of the input shift circuit is pulled up to a high level VDDH;

[0048] When the input voltage VIN is at a low level, the first pull-down tube is turned off, the second pull-down tube is turned on, and the output end of the input shift circuit is pulled down to a low level. Preferably, the feedback transistor is used to control the conduction or shutdown of the current mirror input branch; the control end of the feedback transistor is connected to the feedback signal, and the effective state of the feedback signal is: when VIN is at a high level, the signal in the low-power output buffer represents the successful conduction of the input signal at a high level.

[0049] Preferably, the second pull-down tube uses a common-gate transistor, with the source as the input terminal, the drain as the output terminal, and the gate connected to a fixed level VDDL. When the source input is at a low level, the transistor is subthreshold turned on.

[0050] Preferably, the current mirror comprises a PMOS tube M16 and a PMOS tube M17, the sources of the two PMOS tubes are connected to the high level VDDH, the gate and drain of the PMOS tube M16 and the gate of the PMOS tube M17 are connected as the input end of the current mirror, and the drain of the PMOS tube M17 serves as the output end of the current mirror;

[0051] The feedback transistor is an NMOS tube M15, the drain of the feedback transistor is connected to the drain of the PMOS tube M16, the source of the feedback transistor is connected to the output end of the first pull-down tube, and the gate of the feedback transistor serves as a control end;

[0052] The first pull-down tube is an NMOS tube M13, the gate of the NMOS tube M13 is connected to the input signal VIN of the input shift circuit as an input terminal, the source is connected to the ground as a fixed potential terminal, and the drain is connected to the source of the feedback transistor as an output terminal;

[0053] The second pull-down tube is an NMOS tube M14, whose gate is connected to the low level VDDL, whose source is connected to the input signal VIN of the input shift circuit as an input terminal, and whose drain is connected to the drain terminal of the PMOS tube M17 as an output terminal of the input shift circuit.

[0054] Preferably, the low-power output buffer is composed of a first inverter and a second inverter connected in series, and the output signal of the output end of the input shift circuit is reversed twice. The first inverter is composed of a PMOS tube M18, a self-biased transistor M19 and an NMOS tube M20 connected in series in sequence. The source of the PMOS tube M18 is connected to VDDH, the drain is connected to the drain of the NMOS tube M20 through the self-biased transistor M19, the gate is connected to the gate of the NMOS tube M20, and the source of the NMOS tube M20 is connected to the ground;

[0055] The second inverter is composed of a PMOS tube M21 and an NMOS tube M22 connected in series. The source of the PMOS tube M21 is connected to VDDH, the drain is connected to the drain of the NMOS tube M22, and the gate is connected to the drain of the PMOS tube M18. The source of the NMOS tube M22 is connected to the ground, and the gate is connected to the drain of the NMOS tube M20.

[0056] Preferably, the self-biasing transistor divides the output terminal of the first inverter into two;

[0057] The self-biased transistor is a PMOS tube M19, whose source is connected to the drain of the PMOS tube M18 as the first output end of the first inverter; whose drain and gate are connected to the drain of the NMOS tube M20 as the second output end of the first inverter.

[0058] Preferably, the signal F outputted from the second output terminal of the first inverter is a feedback signal representing successful high-level conduction of the input signal, and is inputted to the control terminal of the feedback transistor of the input shift circuit.

[0059] The specific working process of this embodiment is as follows:

[0060] (a) If Figure 4 When the input signal VIN is at a rising edge (VIN changes from low level to high level)

[0061] NMOS tube M13 is turned on, NMOS tube M14 is turned off, and the current mirror branch generates current, causing the voltage at point D to jump from a low level to a high level. NMOS tube M20 begins to turn on, and the presence of PMOS tube M19 reduces the drain voltage of NMOS tube M20, thereby reducing the power consumption of the branch. Then PMOS tube M18 is turned off, and the voltages at points E and F are both changed from a high level to a low level, and VOUT outputs a high level. The voltage at point E is always higher than the voltage at point F, which adds a short dead time to PMOS tube M21 and NMOS tube M22, eliminating the short-circuit current in the signal conversion process of the traditional inverter. At the same time, signal F turns off the feedback transistor M15, the current in the current mirror branch is terminated, and the entire rising edge signal transmission is completed.

[0062] (b) If Figure 5 As shown in the figure, when the input signal VIN is at a falling edge (VIN changes from high level to low level)

[0063] The NMOS tube M13 is turned off and the NMOS tube M14 is turned on. There is no current transmission on the current mirror. The voltage at point D jumps from a high level to a low level. The PMOS tube M18 starts to turn on. M19 can reduce the power consumption of this branch. Then the NMOS tube M20 is turned off. Then the voltages at points E and F both change from a low level to a high level. VOUT outputs a low level. There is still a dead time between the PMOS tube M21 and the NMOS tube M22. The entire falling edge signal transmission is completed.

[0064] like Figure 6 The timing logic waveform diagram of the input signal VIN, the traditional LS output signal VOUT1, and the new LS output signal VOUT2 is shown; where t1 represents the rising edge signal conversion delay; t2 represents the falling edge conversion delay of the traditional structure. It can be seen that replacing the inverter with the input common-gate transistor can effectively improve the falling edge signal conversion delay. t3 represents the falling edge conversion delay of this embodiment, which is significantly lower than the falling edge delay of the traditional CMLS.

[0065] like Figure 7 The figure shows the static current simulation result of the level shift circuit of this embodiment under the conditions of VDDL=400mV, VDDH=1.8V. It can be seen that the static current of the structure is only about 74.3pA, and the static power consumption is only about 0.13nW. Figure 8 The simulation results of the static current of traditional CMLS under the same simulation conditions show that the static current of traditional CMLS is as high as 256.7nA and the static power consumption is 426.1nW.

[0066] Embodiment 2 of the present invention discloses a subthreshold conduction level shifting method of a low power consumption sensor of the shift circuit described in the first aspect of the present invention, specifically:

[0067] When level shifting is required, an input signal is sent to the input shift circuit. If it is required to shift to the high level VDDH, the input signal changes from a low level to a high level, controlling the first pull-down tube to be turned on and the second pull-down tube to be turned off. Otherwise, the input signal changes from a high level to a low level, controlling the first pull-down tube to be turned off and the second pull-down tube to be turned on at a sub-threshold value.

[0068] When the first pull-down tube is turned on, the control end of the current mirror is pulled down to a low level, and the output of the input shift circuit is a high level VDDH; when the second pull-down tube is turned on, the output of the input shift circuit is a low level;

[0069] The signal output from the output end of the input shift circuit is transmitted to the low-power output buffer, is inverted by the first inverter, and the dead time of the second inverter is increased by the self-biased transistor in the first inverter, and is then inverted by the second inverter and output;

[0070] At the same time, the feedback signal of the second output terminal of the first inverter is transmitted to the feedback transistor of the input shift circuit. When the input signal changes from a low level to a high level, the feedback signal changes from a high level to a low level, controls the feedback transistor to turn off, and interrupts the current mirror current.

[0071] The beneficial effects of the present invention are that, compared with the prior art, (1) a subthreshold conduction common-gate transistor is used to replace the traditional inverter as the input end, and the signal is transmitted by utilizing the principle of subthreshold conduction of the common-gate transistor, which effectively improves the conversion speed of the falling edge signal in the circuit, reduces the delay, and the subthreshold conduction current is low, which is conducive to reducing the overall power consumption. (2) A novel low-power output buffer is designed, and a self-biased transistor is added between the NMOS tube and the PMOS tube of the first inverter, so that the input end of the second inverter is separated. On the one hand, a dead time is generated between the NMOS tube and the PMOS tube of the second inverter, and on the other hand, the drain-source voltage of the NMOS tube and the PMOS tube of the first inverter is reduced, so that its conduction current is reduced. (3) A feedback transistor is added, and the input signal of the second inverter NMOS tube of the low-power output buffer is used as the feedback signal to control the conduction and shutdown of the current mirror branch, so that the branch only generates current at the edge of VIN, thereby having ultra-low static power consumption; (4) In addition, the circuit of the present invention uses only ten transistors to realize the subthreshold level shifting function, providing a wide voltage conversion range while having a very small area.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction, comprising an input shift circuit and a low power consumption output buffer, characterized in that: An input shift circuit, whose input terminal is connected to an input signal and whose output terminal is connected to a low-power output buffer for level shifting; The input end of the low power output buffer is connected to the output end of the input shift circuit, and its output end serves as the output end of the subthreshold conduction level shift circuit. The level of the buffer output end is consistent with the input end for signal transmission.

2. The ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction according to claim 1, characterized in that: The input shift circuit includes a pull-up network, a pull-down network and a feedback transistor. The pull-up network is a current mirror structure, and the pull-down network consists of a first pull-down tube and a second pull-down tube. The source end of the current mirror is connected to the high level VDDH of the desired output, the input end of the current mirror is connected to the output end of the first pull-down tube through the feedback transistor, and the output end of the current mirror is connected to the output end of the second pull-down tube as the output end of the input shift circuit. The input signal VIN is connected to the input end of the first pull-down tube and the input end of the second pull-down tube respectively, the fixed potential end of the first pull-down tube is connected to the ground, and the fixed potential end of the second pull-down tube is connected to the low level VDDL; When the input voltage VIN is at a high level, the first pull-down tube is turned on, the second pull-down tube is turned off, the input end of the current mirror is pulled down to a low level, and the output end of the input shift circuit is pulled up to a high level VDDH; When the input voltage VIN is at a low level, the first pull-down tube is turned off, the second pull-down tube is turned on, and the output end of the input shift circuit is pulled down to a low level.

3. The ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction according to claim 2, characterized in that: The feedback transistor is used to control the on or off of the current mirror input branch; the control terminal of the feedback transistor is connected to the feedback signal, and the effective state of the feedback signal is: when VIN is at a high level, the signal in the low-power output buffer represents the successful conduction of the high level input signal.

4. The ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction according to claim 2, characterized in that: The second pull-down tube uses a common-gate transistor, with a source as an input terminal and a drain as an output terminal, and a gate connected to a fixed level VDDL. When the source input is at a low level, the transistor is subthreshold turned on.

5. An ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction according to any one of claims 3 and 4, characterized in that: The current mirror includes a PMOS tube M16 and a PMOS tube M17, the sources of the two PMOS tubes are connected to a high level VDDH, the gate and drain of the PMOS tube M16 and the gate of the PMOS tube M17 are connected as the input end of the current mirror, and the drain of the PMOS tube M17 is used as the output end of the current mirror; The feedback transistor is an NMOS tube M15, the drain of the feedback transistor is connected to the drain of the PMOS tube M16, the source of the feedback transistor is connected to the output end of the first pull-down tube, and the gate of the feedback transistor serves as a control end; The first pull-down tube is an NMOS tube M13, the gate of the NMOS tube M13 is connected to the input signal VIN of the input shift circuit as an input terminal, the source is connected to the ground as a fixed potential terminal, and the drain is connected to the source of the feedback transistor as an output terminal; The second pull-down tube is an NMOS tube M14, whose gate is connected to the low level VDDL, whose source is connected to the input signal VIN of the input shift circuit as an input terminal, and whose drain is connected to the drain terminal of the PMOS tube M17 as an output terminal of the input shift circuit.

6. The ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction according to claim 5, characterized in that: The low-power output buffer is composed of a first inverter and a second inverter connected in series, and the output signal of the output end of the input shift circuit is reversed twice. The first inverter is composed of a PMOS tube M18, a self-biased transistor M19 and an NMOS tube M20 connected in series in sequence. The source of the PMOS tube M18 is connected to VDDH, the drain is connected to the drain of the NMOS tube M20 through the self-biased transistor M19, the gate is connected to the gate of the NMOS tube M20, and the source of the NMOS tube M20 is connected to the ground; The second inverter is composed of a PMOS tube M21 and an NMOS tube M22 connected in series. The source of the PMOS tube M21 is connected to VDDH, the drain is connected to the drain of the NMOS tube M22, and the gate is connected to the drain of the PMOS tube M18. The source of the NMOS tube M22 is connected to the ground, and the gate is connected to the drain of the NMOS tube M20.

7. The ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction according to claim 6, characterized in that: The self-biasing transistor divides the output terminal of the first inverter into two; The self-biased transistor is a PMOS tube M19, whose source is connected to the drain of the PMOS tube M18 as the first output end of the first inverter; whose drain and gate are connected to the drain of the NMOS tube M20 as the second output end of the first inverter.

8. The ultra-low power consumption, high-speed level shift circuit based on subthreshold conduction according to claim 7, characterized in that: The signal F outputted from the second output terminal of the first inverter is a feedback signal representing successful high-level conduction of the input signal, and is inputted to the control terminal of the feedback transistor of the input shift circuit.

9. An ultra-low power consumption, high-speed level shifting method based on subthreshold conduction based on the shifting circuit according to any one of claims 1 to 8, characterized in that: When level shifting is required, an input signal is sent to the input shift circuit. If it is required to shift to the high level VDDH, the input signal changes from a low level to a high level, controlling the first pull-down tube to be turned on and the second pull-down tube to be turned off. Otherwise, the input signal changes from a high level to a low level, controlling the first pull-down tube to be turned off and the second pull-down tube to be turned on at a sub-threshold value. When the first pull-down tube is turned on, the input end of the current mirror is pulled down to a low level, and the output of the input shift circuit is a high level VDDH; when the second pull-down tube is turned on, the output of the input shift circuit is a low level; The signal output from the output end of the input shift circuit is transmitted to the low-power output buffer, is inverted by the first inverter, and the dead time of the second inverter is increased by the self-biased transistor in the first inverter, and is then inverted by the second inverter and output; At the same time, the feedback signal of the second output terminal of the first inverter is transmitted to the feedback transistor of the input shift circuit. When the input signal changes from a low level to a high level, the feedback signal changes from a high level to a low level, controlling the feedback transistor to turn off and interrupting the current mirror current.

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