Frequency division synchronization circuit applied to multichannel analog-to-digital converter

Abstract

The invention discloses a frequency division synchronous circuit applied to a multi-channel analog-to-digital converter. The frequency division synchronous circuit is composed of three main modules including a frequency division reconstruction circuit, a synchronous signal generation circuit and a clock distribution circuit. A multi-channel analog-to-digital converter needs a reasonably designed clock system to provide a time sequence basis for cooperative work of all modules, however, an existing clock system has the problems of large jitter, fuzzy state, low efficiency and the like, and the multi-channel analog-to-digital converter based on the problems is difficult to meet the requirements of rapidly developed communication and detection array systems. According to the improved clock system, the sampling clock jitter is reduced through the edge reconstruction technology, so that the sampling noise is improved, and the conversion precision is improved; the phase ambiguity of frequency division is eliminated through a synchronization strategy, data processing and correction are facilitated, the device can be controlled to be reset to a specific initial state, and array application is facilitated; through a bus type clock distribution strategy, the number of clock transmission lines is reduced, and the circuit operation efficiency is improved.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, and in particular to a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter. Background Art

[0002] The analog-to-digital converter is a tool that converts the received analog signal into a digital signal that is easy to process. The conversion accuracy, power consumption, and synchronizability usually affect the implementation form and performance of the entire communication and detection system. Therefore, continuously improving the structure of the analog-to-digital converter to make it have higher conversion accuracy and lower power consumption, and have synchronizability that is more suitable for array applications, has important practical significance for the rapidly developing communication and detection array systems.

[0003] In high-speed, medium-to-high precision analog-to-digital converters, multiple sample-and-hold channels and multiple conversion channels are usually used for time interleaving design to achieve the target rate and accuracy. However, as the number of channels increases, the structure of the analog-to-digital converter becomes complex, and a reasonably designed clock system is required to provide a timing basis for the coordinated work of each module, while ensuring power efficiency and physical feasibility.

[0004] However, the clock system of traditional multi-channel analog-to-digital converters usually has the following problems:

[0005] 1. The multi-phase clock generated by the frequency divider has large jitter, which causes jitter at the sampling time, thus introducing noise and reducing the signal-to-noise ratio;

[0006] 2. The initial state of the frequency divider is uncertain and cannot be reset, which leads to a certain degree of ambiguity in the operating sequence and working state of the channels, which is not conducive to the subsequent data correction and the application of multi-converter arrays;

[0007] 3. As the number of channels and the number of clocks required for each channel increase, a large number of clock lines are used to transmit clock signals, resulting in low clock distribution efficiency and higher requirements for layout. Summary of the invention

[0008] Multi-channel analog-to-digital converters require a well-designed clock system to achieve high-quality sampling and holding and time interleaving of conversion channels to achieve the target accuracy. However, traditional clock systems have the disadvantages of large jitter, fuzzy state, and low distribution efficiency, which makes them difficult to be applied well.

[0009] The present invention aims to address the above-mentioned deficiencies and proposes a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter, so that the clock system satisfies the state determination and resettability while having the advantages of low jitter, low power consumption and low complexity.

[0010] The technical solution of the present invention is:

[0011] The present invention includes a frequency division reconstruction circuit, a synchronization signal generation circuit, and a clock distribution circuit;

[0012] The frequency division and reconstruction circuit is used to divide the external input clock signal into multiple clock signals required by multiple sampling and holding channels and multiple conversion channels, and apply signal reconstruction technology to reduce clock jitter generated during the frequency division process;

[0013] The synchronization signal generating circuit is used to generate a synchronization signal to provide a resettable, determined starting time and initial state for the frequency division of the clock signal, so that each clock signal after the frequency division runs in a set state;

[0014] The clock distribution circuit is used to distribute the divided multi-channel clock signals to the corresponding sampling and holding channels and conversion channels.

[0015] In a preferred embodiment, the frequency division and reconstruction circuit includes a two-stage frequency divider, the first stage frequency divider divides the external input clock signal into multiple clocks corresponding to the sampling and holding channel, and each clock is input to a second stage frequency divider and further divided into multiple clock signals required by the conversion channel.

[0016] In a preferred embodiment, in the first-stage frequency divider, the divided signal is reconstructed into a clock with low clock jitter after a logical operation with the input clock signal, and is output to the corresponding sampling and holding channel for low-jitter sampling to improve the sampling signal-to-noise ratio.

[0017] In a preferred embodiment, both stages of the frequency divider are composed of a D-type flip-flop ring, which is driven by the pre-division clock to generate the required post-division clock.

[0018] In a preferred embodiment, the synchronization signal generating circuit is driven by an external input synchronization source signal, generates a synchronization signal pulse for resetting the frequency division and reconstruction circuit, and has a deburring function.

[0019] In a preferred embodiment, the signal pulses generated by the synchronization signal generating circuit are divided into two types, one having a length consistent with the period of the external input clock signal and used to reset the state of the first-stage frequency dividing circuit, and the other having a length consistent with the period of the output clock of the first-stage frequency divider and used to reset the state of the second-stage frequency dividing circuit.

[0020] In a preferred embodiment, the clock distribution circuit is divided into two levels. The first-level clock distribution circuit distributes the multiple clocks output by the first-level frequency divider to the corresponding sampling and holding channels through a tree structure for signal sampling and second-level frequency division.

[0021] In a preferred embodiment, the clock distribution circuit is divided into two levels. The second-level clock distribution circuit distributes the multiple clock signals required by the conversion channel output by the second-level divider to the conversion channel. The distribution strategy is bus distribution and on-demand selection, that is, the clocks of all phases of the second-level frequency division output in the sampling and holding channel are uniformly transmitted to the vicinity of the conversion channel in a bus manner, and each conversion channel obtains the clock of the required phase to realize clock distribution.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] (1) The design of two-level frequency division of the sample-and-hold channel and the conversion channel makes the layout of the clock link more reasonable and more suitable for multi-channel time-interleaved high-speed analog-to-digital converters with sample-and-hold devices.

[0024] (2) Signal reconstruction technology is used to reconstruct the sampling and holding channel clock after frequency division, eliminating the clock jitter of the sampling edge caused by the frequency division process, improving the signal-to-noise ratio of the sampling process, and thus improving the overall performance of the analog-to-digital converter.

[0025] (3) A synchronization strategy is designed to eliminate the phase ambiguity of the frequency division process, so that the clocks of each channel have a definite correspondence and a definite order, which is beneficial to data processing and correction; and the clock system can be reset to a specific initial state for the correction and synchronization of operating state offsets, which is beneficial to the application of analog-to-digital converters in large-scale arrays.

[0026] (4) For the case where there are many conversion channels and each channel requires multiple clocks, a bus-based clock distribution strategy is proposed, that is, the clock module outputs all phase clocks to the clock bus, and each channel takes them out as needed, which greatly reduces the number of clock transmission lines, is more conducive to layout, and improves circuit operation speed and power efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 The invention is a structural schematic diagram of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter.

[0029] Figure 2 The invention discloses a first-level timing flow chart of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter.

[0030] Figure 3 The invention discloses a second-level timing flow chart of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter.

[0031] Figure 4 The present invention is a circuit schematic diagram of a first-stage frequency divider in a frequency division reconstruction circuit.

[0032] Figure 5 The present invention is a circuit schematic diagram of a second-stage frequency divider in a frequency division reconstruction circuit.

[0033] Figure 6 The invention is a circuit schematic diagram of a synchronous signal generating circuit.

[0034] Figure 7 It is a timing flow chart of a synchronization strategy when synchronization occurs.

[0035] Figure 8 The schematic diagram of a second-stage clock distribution circuit. DETAILED DESCRIPTION

[0036] The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become more apparent. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0037] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0038] In the description of the present invention, if the terms "upper", "lower", "left", "right", etc. indicate an orientation or positional relationship, they are based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "highest", "first", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0039] It should be noted that the number of channels, the number of D flip-flops, and the frequency, phase, etc. associated therewith in the description are only the scheme of this preferred embodiment. In order to simplify the description, the circuit details are described based on this number. The present invention is also applicable to the case of other numbers of channels. The circuit behaviors such as "rising edge" and "falling edge" in the description are only the implementation methods and corresponding relationships selected by this preferred embodiment. The purpose is to simplify the description and is not used to limit the present invention.

[0040] The present application proposes a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter, which is composed of a frequency division reconstruction circuit, a synchronization signal generation circuit, and a clock distribution circuit.

[0041] The main function of the frequency division and reconstruction circuit is to divide the external input clock signal into the driving clock required by each part of the analog-to-digital converter, and to reconstruct the clock edge related to sampling to make it have lower clock jitter to obtain lower noise sampling.

[0042] The main function of the synchronization signal generation circuit is to generate synchronization pulses according to the external input synchronization source signal, and transmit them to the two-stage frequency divider respectively, reset the frequency divider state and serve as the frequency division starting point of the frequency divider.

[0043] The clock distribution circuit distributes the various clocks generated by the frequency divider to the corresponding sampling and holding channels and analog-to-digital conversion channels.

[0044] In this preferred embodiment, the sampling conversion part of the analog-to-digital converter is composed of four time-interleaved sampling and holding channels 107, and each sampling and holding channel includes four time-interleaved analog-to-digital conversion channels 105. Corresponding to the sampling conversion part, the frequency division and reconstruction circuit is divided into two stages. The first-stage frequency divider 101 divides the external input clock signal CLK_input (frequency is recorded as f) into four clocks with a frequency of f / 4, a phase difference of 90°, and a duty cycle of 1 / 4 through a trigger ring composed of four D flip-flops, and reconstructs the falling edges of these four clocks through a logic circuit to make them have lower clock jitter. The reconstructed four clocks (102-A, 102-B, 102-C, 102-D) are distributed to each sampling and holding channel 107 by the first-stage clock distribution circuit in a tree structure 109. Each sampling and holding channel 107 receives one of the clocks. Inside the sampling and holding channel 107, this clock enters the sampling and holding 106 to drive the sampling and holding action, and also enters the second-stage frequency divider 103. There are 4 second-stage frequency dividers 103 in the frequency division reconstruction circuit, which are located inside each sampling and holding channel 107, and operate independently of each other. From the perspective of timing, they are time-interleaved. Taking one of the second-stage frequency dividers 103 as an example, the clock input to the sampling and holding channel 107 is divided into 4 clocks with a frequency of f / 16, a phase difference of 90°, and a duty cycle of 1 / 4 (104-Xa, 104-Xb, 104-Xc, 104-Xd, where X represents one of A, B, C, and D) through a trigger ring composed of 4 D flip-flops. Since each conversion channel 105 requires clocks of 3 phases, the 4 conversion channels 105 in this sampling and holding channel 107 require 12 clocks. If all of them are distributed using clock lines, this is complicated in terms of layout. The second-stage clock distribution circuit transmits these 4 clocks to all conversion channels 105 in this sampling and holding channel 107 through the clock bus 110, and the conversion channel 105 only needs to take out the required 3 phase clocks.

[0045] In the preferred embodiment, the synchronization signal generating circuit 108 is driven by the external input clock signal CLK_input according to the rising edge of the external input synchronization source signal to generate a first-stage synchronization clock SYNC1 with a length of 1 / f, which is used to reset the state of the first-stage frequency divider 101. Then, driven by one of the four clocks (102-A, 102-B, 102-C, 102-D) output by the first-stage frequency divider 101, a second-stage synchronization clock SYNC2 with a length of 4 / f is generated to reset the state of the second-stage frequency divider 103.

[0046] The present application is further described below in conjunction with the accompanying drawings and preferred embodiments.

[0047] Figure 11 is a structural diagram of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter in this embodiment. The clock signal CLK_input is input from the outside, and the first-stage frequency divider 101 in the frequency division reconstruction circuit divides and reconstructs it into 4 clock signals 102-A, 102-B, 102-C, and 102-D, which are respectively input into the second-stage frequency divider 103 and the sample holder 106 in the 4-way sampling and holding channel 107. The second-stage frequency divider 103 divides the 102 signals of each channel into 4 clock signals 104-Xa, 104-Xb, 104-Xc, and 104-Xd, where X represents one of the four channels A, B, C, and D, and generates a total of 16 divided signals 104. Each conversion channel 105 requires three-phase clocks, which are obtained from the clock bus 110 of the respective sampling and holding channel 107.

[0048] The synchronization signal generating circuit 108 receives the external input synchronization source signal SYNC_input and generates synchronization signals SYNC1 and SYNC2 for the first and second frequency dividers respectively. The first frequency divider 101 is reset to the initial working state by SYNC1, and the second frequency divider 103 is reset to the initial working state by SYNC2.

[0049] The first-level clock distribution circuit uses a tree structure 109 to distribute the clock to the sampling and holding channel 107. The layout orientation of the clock line of the tree structure is consistent with the schematic diagram. 102-A, 102-B, 102-C, and 102-D are symmetrically arranged. Starting from the global center point, they are divided into two groups extending in opposite directions. After each group extends to the center point on both sides, it is divided into two groups again inside and extends in opposite directions. For more channels, the same is true, so as to ensure that the path length to each channel is the same. The second-level clock distribution circuit uses a clock bus 110 to distribute the clock to the conversion channel 105.

[0050] Figure 2 This is a first-level timing flow chart of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter in this embodiment. Assuming that the frequency of the external input clock signal CLK_input is f, triggered by the rising edge of CLK_input, the state of the clock signal 102 changes, and it cycles in the order of 102-A, 102-B, 102-C, and 102-D, with a frequency of f / 4, a phase difference of 90°, and a duty cycle of 1 / 4.

[0051] Figure 3This is a second-level timing flow chart of a frequency division synchronization circuit applied to a multi-channel analog-to-digital converter in this embodiment. Taking the sampling and holding channel A as an example, the clock signal 102-A is divided by the second-level frequency divider and triggered by the rising edge of 102-A. The state of the clock 104 changes and is cycled in the order of 104-Aa, 104-Ab, 104-Ac, and 104-Ad. The frequency is f / 16, the phases differ by 90°, and the duty cycle is 1 / 4. The other three sampling and holding channels have similar behaviors.

[0052] Figure 4 4 is a circuit schematic diagram of a first-stage frequency divider in a frequency division and reconstruction circuit in this embodiment. The first-stage frequency divider in the frequency division and reconstruction circuit includes two parts, one is a frequency division part 401, which is composed of a trigger ring composed of four D flip-flops connected end to end, and the other is a reconstruction part 402, which is composed of a logic circuit and reconstructs the sampling edge (the falling edge of 102 in this embodiment).

[0053] Further, in this embodiment, the D flip-flop ring is composed of three D flip-flops 403 with synchronous reset ports (Reset) and one D flip-flop 404 with synchronous set port (Set). When the synchronization signal SYNC1 is at a high level, the rising edge of the clock input CLK_input triggers the synchronous reset and synchronous set. At this time, the outputs QA, QB, QC, and QD of the four D flip-flops are set to low level, low level, high level, and low level respectively, and the frequency divider is reset to the starting working state. When the synchronization signal SYNC1 is at a low level, the frequency divider is in a normal working state, and the four flip-flops are triggered by the rising edge of the clock input CLK_input, and the output level of the previous flip-flop is read and output, thereby generating cyclic signals QA, QB, QC, and QD with a frequency of f / 4 and a duty cycle of 1 / 4, and their corresponding inverted signals QNA, QNB, QNC, and QND.

[0054] Since the clock jitter generated by the frequency divider is relatively large, QA, QB, QC, and QD are respectively input into the reconstruction part 402, and QD is used as an example for explanation here. QD and CLK_input are subjected to the output clock of the inverter 405 to perform the NAND logic 406. Since the falling edge of QD is slightly slower than the falling edge of the output clock of the inverter 405, the rising edge clock jitter of the NAND logic 406 output clock is determined by the output clock of the inverter 405, thereby eliminating the large clock jitter caused by the D flip-flop during the frequency division process. The output clock of the NAND logic 406 is subjected to the NAND logic 408 with QND after passing through the delay module 407 to restore its phase and duty cycle, thereby generating a signal 102-D with a smaller falling edge clock jitter. This signal is used for sampling by the sample holder in the sample-hold channel D and for frequency division by the second-stage frequency divider, and other channels have similar behaviors.

[0055] Figure 5 : is a circuit schematic diagram of a second-stage frequency divider in a frequency division reconstruction circuit in this embodiment. The second-stage frequency divider is composed of a trigger ring composed of four D flip-flops connected end to end, including a D flip-flop 501 with a synchronous set port (Set) and three D flip-flops 502 with a synchronous reset port (Reset). Taking the second-stage frequency divider 103-A as an example, when the synchronization signal SYNC2 is at a high level, the rising edge of the clock input 102-A triggers the synchronous reset and synchronous set. At this time, the outputs 104-Aa, 104-Ab, 104-Ac, and 104-Ad of the four D flip-flops are set to high level, low level, low level, and low level respectively, and the frequency divider is reset to the starting working state. When the synchronization signal SYNC2 is at a low level, the frequency divider is in a normal working state, and the four flip-flops are triggered by the rising edge of the clock input 102-A, and the output level of the previous flip-flop is read and output, thereby generating cyclic signals 104-Aa, 104-Ab, 104-Ac, and 104-Ad with a frequency of f / 16 and a duty cycle of 1 / 4. The phase difference of these signals is 90° in sequence, and they are used to drive the four conversion channels corresponding to the sampling and holding channel A.

[0056] Figure 6 The synchronous signal generating circuit generates synchronous pulses SYNC1 and SYNC2 according to the rising edge of the input external synchronous signal SYNC_input, and transmits them to the two-stage frequency divider respectively, resets the frequency divider state and serves as the frequency division starting point of the frequency divider. The input external clock CLK_input drives the two D flip-flops 601 to work. It can be seen that the output signal 611 is delayed by two beats (2 / f) than the external synchronization signal SYNC_input. The D flip-flop output signal 611 and the signal of SYNC_input after passing through the inverter 602 perform an OR logic 603. Only when the D flip-flop output signal 611 is low and SYNC_input is high, the level of the OR logic output signal 612 is low. In other words, only when the current SYNC_input is high and the SYNC_input two beats ago is low, the level of the OR logic output signal 612 is low. The D flip-flop 604 with reset function is in a non-reset state. Driven by the clock, the output SYNC1 becomes a high level after one beat, and the D flip-flop QN output signal 613 becomes a low level. In the next clock beat, SYNC1 returns to a low level, and then the D flip-flop 604 returns to the reset state. Since the external synchronization signal SYNC_input is used to periodically reset the analog-to-digital converter and is a low-frequency signal in the application scenario, this structure can be regarded as a rising edge trigger with a de-glitching function. The rising edge of SYNC_input can trigger SYNC1 to generate a high-level pulse with a length of 1 / f.

[0057] After SYNC1 is generated, it is input to the first-stage frequency divider, and after being delayed by one beat by the D flip-flop 605, it is input to the reset port of the D flip-flop 608 driven by the clock signal 102-D through the absolute delay 606 and the inverter 607. Only when the SYNC1_D output by the absolute delay 606 is high, the D flip-flop 608 is not in the reset state. At this time, it is triggered by the rising edge of the clock signal 102-D, the output SYNC2 becomes high level, and the output signal 614 of the D flip-flop QN becomes low level, and the reset state is restored at the next rising edge of the clock signal 102-D. As a result, SYNC2 generates a high level pulse with a duration of 4 / f.

[0058] Figure 7 It is a timing flow chart of a synchronization strategy in this embodiment when synchronization occurs. The shaded part in the figure is a phase ambiguity state. After SYNC1 becomes a high level, the first-stage frequency divider is reset, and 102-A, 102-B, 102-C, and 102-D are respectively set to low level, low level, high level, and low level, and enter the normal cycle state. It can be seen that when SYNC1_D is a high level, it is triggered by the rising edge of 102-D, and a high-level pulse with a length of 4 / f is generated in SYNC2. After SYNC2 is input to the four second-stage frequency dividers, with the arrival of the rising edges of 102-A, 102-B, 102-C, and 102-D, 104-Ax, 104-Bx, 104-Cx, and 104-Dx (x represents a, b, c, and d) are reset in turn, thereby realizing that all conversion channels run in sequence, and each sampling and holding channel and the conversion channel have a definite corresponding relationship.

[0059] Figure 8 : is a circuit schematic diagram of a clock distribution circuit in this embodiment. Since each conversion channel 105 requires a three-phase clock (801), in the second-level clock distribution of each sampling and holding channel, if these clocks are input separately, 12 clock lines are required, which is 48 clock lines for the entire analog-to-digital converter in this embodiment, which is relatively complex and inefficient in terms of layout. Taking sampling and holding channel A as an example, the bus-type clock distribution strategy proposed in the present invention, the four-phase clocks (104-Aa, 104-Ab, 104-Ac, 104-Ad) form a clock bus (110) and are transmitted to the vicinity of the four conversion channels (105), and the conversion channels obtain the clocks of the required phases to achieve clock distribution. In this way, the entire clock distribution system is greatly simplified, and higher speed and higher power efficiency can be achieved.

[0060] The frequency division synchronization circuit applied to a multi-channel analog-to-digital converter proposed in the embodiment of the present application, compared with the traditional clock system, matches the high-speed analog-to-digital converter architecture with a sampling and holding channel through a hierarchical structure; reduces the sampling edge clock jitter through edge reconstruction technology, thereby improving sampling noise and conversion accuracy; eliminates the phase ambiguity of the frequency division through a synchronization strategy, so that each channel clock has a definite corresponding relationship, which is beneficial to data processing and correction, and can be reset to a specific initial state by an external signal, which is beneficial to array applications; through a bus-type clock distribution strategy, the number of clock transmission lines is greatly reduced, which is more conducive to layout layout, and improves circuit operation speed and power efficiency. It can be used for the design of low-power, high-precision, synchronizable multi-channel high-speed analog-to-digital converters, providing more possibilities for the array design and low-cost and high-efficiency implementation of various communication and detection systems.

[0061] Those skilled in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.

Claims

1. A frequency division synchronization circuit applied to a multi-channel analog-to-digital converter, comprising a frequency division reconstruction circuit, a synchronization signal generation circuit and a clock distribution circuit, characterized in that: The frequency division and reconstruction circuit is used to divide the external input clock signal into multiple clock signals required by multiple sampling and holding channels and multiple conversion channels, and apply signal reconstruction technology to reduce clock jitter generated during the frequency division process; The synchronization signal generating circuit is used to generate a synchronization signal to provide a resettable, determined starting time and initial state for the frequency division of the clock signal, so that each clock signal after the frequency division runs in a set state; The clock distribution circuit is used to distribute the divided multi-channel clock signals to the corresponding sampling and holding channels and conversion channels.

2. A frequency division synchronization circuit for a multi-channel analog-to-digital converter according to claim 1, characterized in that: The frequency division and reconstruction circuit includes two stages of frequency dividers. The first stage frequency divider divides the external input clock signal into multiple clocks corresponding to the sampling and holding channels, and each clock is input to a second stage frequency divider to be further divided into multiple clock signals required by the conversion channel.

3. The frequency division synchronization circuit applied to a multi-channel analog-to-digital converter according to claim 2, characterized in that: In the first-stage frequency divider, the divided signal is reconstructed into a clock with low clock jitter after logical operation with the input clock signal, and is output to the corresponding sample-and-hold channel for low-jitter sampling, thereby improving the sampling signal-to-noise ratio.

4. The frequency division synchronization circuit applied to a multi-channel analog-to-digital converter according to claim 2, characterized in that: Both stages of the frequency divider are composed of a D-type flip-flop ring, which is driven by the pre-division clock to generate the required post-division clock.

5. The frequency division synchronization circuit applied to a multi-channel analog-to-digital converter according to claim 1, characterized in that: The synchronization signal generating circuit is driven by an external input synchronization source signal, generates a synchronization signal pulse for resetting the frequency division and reconstruction circuit, and has a deburring function.

6. The frequency division synchronization circuit applied to a multi-channel analog-to-digital converter according to claim 2, characterized in that: The signal pulses generated by the synchronization signal generating circuit are divided into two types, one of which has a length consistent with the period of the external input clock signal and is used to reset the state of the first-stage frequency dividing circuit, and the other has a length consistent with the period of the output clock of the first-stage frequency divider and is used to reset the state of the second-stage frequency dividing circuit.

7. The frequency division synchronization circuit applied to a multi-channel analog-to-digital converter according to claim 2, characterized in that: The clock distribution circuit is divided into two levels. The first-level clock distribution circuit distributes the multiple clocks output by the first-level frequency divider to the corresponding sampling and holding channels through a tree structure for signal sampling and second-level frequency division.

8. The frequency division synchronization circuit applied to a multi-channel analog-to-digital converter according to claim 2, characterized in that: The clock distribution circuit is divided into two levels. The second-level clock distribution circuit distributes the multi-channel clock signals required by the conversion channel output by the second-level divider to the conversion channel. The distribution strategy is bus distribution and on-demand selection, that is, the clocks of all phases of the second-level frequency division output in the sampling and holding channel are uniformly transmitted to the vicinity of the conversion channel in a bus manner, and each conversion channel obtains the clock of the required phase to realize clock distribution.

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