A fast-start crystal oscillator based on phase interpolation synchronous injection

Abstract

The present invention discloses a fast-start crystal oscillator based on phase interpolation synchronous injection, which includes a digital module, a time-to-digital converter, a ring oscillator, a phase interpolation module, a first and a second level shifter, an amplifier, a crystal, a first and a second load capacitor, a first to a fourth switch, and a comparator; the present invention accelerates the start of the crystal by means of intermittent energy injection into the crystal. During the injection interval, the time-to-digital converter is used to detect the time difference between the injection phase and the crystal oscillation signal, and the phase interpolation module is used to generate the correct injection phase to achieve fast start. The present invention realizes high-efficiency energy injection, ensures the stable growth of the crystal oscillation amplitude; and the synchronous injection technology based on the phase interpolation module reduces the accuracy requirement of the energy injection signal, reduces the design difficulty of the on-chip injection source while ensuring the start efficiency, and significantly optimizes the chip yield.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a fast-start crystal oscillator based on phase interpolation synchronous injection. Background Art

[0002] As a key component in integrated circuits, crystal oscillators are widely used in the frequency multiplication operation of phase-locked loop systems. Their startup efficiency has a decisive influence on the timeliness of system data transmission and reception and the power consumption of systems using duty cycle working modes. With the rapid advancement of integrated circuit technology and the growing demand for low power consumption, the development of high-frequency crystal oscillators with fast startup capabilities has become particularly important.

[0003] At present, the mainstream method for fast startup of high-frequency crystal oscillators is energy injection technology. Energy injection technology helps the crystal quickly establish a stable energy state and complete the frequency selection process by injecting energy into the crystal in a short period of time. Once the crystal amplitude reaches the expected value, the energy injection is disconnected and the amplifier maintains the steady-state oscillation of the crystal. This technology significantly shortens the time of crystal frequency selection amplification and reduces the startup time. However, the energy injection method requires a precise injection source for injection to achieve fast startup; once the deviation between the injection source and the crystal oscillation frequency is large, high-efficiency injection cannot be achieved. Therefore, most energy injections use frequency adjustment technology, which takes dozens to hundreds of cycles to adjust the injection frequency to be close to the crystal oscillation frequency, and then there is no accelerated startup effect during this period, which weakens the effectiveness of the fast startup technology. In addition, the energy injection efficiency is also affected by the phase error between the injection signal and the oscillation signal. The frequency adjustment technology cannot make the injection signal frequency completely match the oscillation frequency. The frequency difference between them will cause the phase error to accumulate over time, thereby limiting the extension of the energy injection time. In addition, for large frequency errors, the crystal obtains very little energy from the energy injection process, because the rapid accumulation of phase errors means that very little energy can be effectively injected. Summary of the invention

[0004] Purpose of the invention: In order to solve the problems existing in the above-mentioned prior art, the present invention provides a fast-start crystal oscillator based on phase interpolation synchronous injection.

[0005] Technical solution: The present invention provides a fast-start crystal oscillator based on phase interpolation synchronous injection, comprising a digital module, a time-to-digital converter, a ring oscillator, a phase interpolation module, a first and a second level shifter, an amplifier, a crystal, a first and a second load capacitor, a first to a fourth switch and a comparator;

[0006] One end of the crystal is recorded as XO+, and the other end is recorded as XO-. The digital module is internally provided with a counter, an even-numbered inverter, and an odd-numbered inverter. The counter generates an enable signal EN. INJ ,EN CL and EN LS The ring oscillator generates n injection signals to the phase interpolation module, and the phase interpolation module adjusts the phases of the n injection signals to generate a signal INJ gen , and the signal INJ gen Output to the digital module, n is a positive integer greater than 2; signal INJ gen The signal INJ+ is generated through an even-numbered inverter; the signal INJ gen The signal INJ- is generated through the odd-numbered inverters; the amplifier is connected across the two ends of the crystal, one end of the first load capacitor is grounded, and the other end is connected to one end of the third switch, the other end of the third switch is connected to the XO+ end of the crystal and one end of the first switch, and the other end of the first switch is connected to the signal INJ+; one end of the second load capacitor is grounded, the other end of the second load capacitor is connected to one end of the fourth switch, the other end of the fourth switch is connected to the XO- end of the crystal and one end of the second switch, and the other end of the second switch is connected to the signal INJ-; enable signal EN CL Control the third switch and the fourth switch, enable signal EN INJ Control the first switch and the second switch; the first signal input end of the first level shifter is connected to the XO+ end of the crystal, and the second signal input end of the first level shifter receives the enable signal EN sent by the digital module LS The output end of the first level shifter is connected to the first input end of the comparator; the first signal input end of the second level shifter is connected to the XO- end of the crystal, and the second signal input end of the second level shifter receives the enable signal EN sent by the digital module LS The output end of the second level shifter is connected to the second input end of the comparator, and the signal INJ+ and the pulse signal CMP outputted from the output end of the comparator are connected. OUT Connected to a time-to-digital converter; the time-to-digital converter quantizes the signal INJ+ and the pulse signal CMP OUT The phase difference between them is the quantized result D τ , and D τ Transmitted to the digital module, the digital module receives the D τ Update the multi-bit control word required by the phase interpolation module and transmit the updated multi-bit control word to the phase interpolation module, thereby changing the signal INJ gen phase.

[0007] Furthermore, the digital module is connected to an external signal EN SU , the counter generates an enable signal EN INJ ,ENCL and EN LS Specifically, the counter counts the signal INJ gen such that the count value of the counter is T. Thresholds T1, T2, T3, T4, and T5 are set inside the digital module, and T1 < T2 < T3 < T4 < T5; when T ≤ T1, EN INJ = 1, EN LS = 0, EN CL = 0; when T1 < T ≤ T2, EN INJ = 0, EN LS = 1, EN CL = 0; when T2 < T ≤ T3, EN INJ = 1, EN LS = 0, EN CL = 0; when T3 < T ≤ T4, EN INJ = 0, EN LS = 1, EN CL = 0; when T4 < T ≤ T5, EN INJ = 1, EN LS = 0, EssN CL = 0; when T > T5, EN INJ = 0, EN LS = 0, EN CL = 1.

[0008] Furthermore, the digital module updates the multi-bit control word CTRL required by the phase interpolation module according to the received D τ specifically as: CTRLnew = CTRold + N / X, where N is the phase difference of D τ and X is the resolution of the phase interpolator; CTRLnew represents the updated multi-bit control word, and CTROld represents the multi-bit control word before update.

[0009] Furthermore, the phase interpolation module includes a first multiplexer and first to third phase interpolators. The input terminal of the first multiplexer is connected to the output terminal of the ring oscillator, and the control terminal of the first multiplexer is connected to the multi-bit control word output by the digital module. The first multiplexer selects two adjacent injection signals Ø i and Ø i+1 from n injection signals according to the multi-bit control word, where Ø i represents the i-th injection signal and Ø i+1 represents the (i + 1)-th injection signal, 0 < i < n; Ø i , Ø i+1 and the multi-bit control word are input to the first phase interpolator to generate the signal Ø A ; Ø i , Ø i+1and a multi-bit control word are input to the second phase interpolator to generate a signal Ø B ; The signal Ø A , signal Ø B and a multi-bit control word are input to the third phase interpolator to generate a signal INJ gen .

[0010] Further, the first to third phase interpolators all include a phase interpolator unit, which includes first to sixth MOS tubes, first and second resistors and a first capacitor; the source of the first MOS tube is connected to the power supply voltage VDD, the drain is connected to the source of the second MOS tube, the gate is connected to the gate of the sixth MOS tube as the input end of the phase interpolator unit, the drain of the second MOS tube is connected to one end of the first resistor, the gate of the second MOS tube is connected to the drain of the third MOS tube and the drain of the fourth MOS tube, the other end of the first resistor is used as the output end of the phase interpolator unit, and is connected to one end of the first capacitor and one end of the second resistor, and the other end of the first capacitor is grounded; the other end of the second resistor is connected to the drain of the fifth MOS tube, the source of the fifth MOS tube is connected to the drain of the sixth MOS tube, the gate of the fifth MOS tube is used as the multi-bit control word input end, and is connected to the gate of the third MOS tube and the gate of the fourth MOS tube, the source of the third MOS tube is connected to the external power supply voltage, and the sources of the fourth MOS tube and the sixth MOS tube are both grounded;

[0011] The first phase interpolator and the second phase interpolator have the same structure and both include 20 phase interpolator units. The input ends of 10 phase interpolator units among the 20 phase interpolator units are connected together and then connected to the injection signal Ø i , the inputs of the other 10 phase interpolator units are connected together and then connected to the injection signal Ø i+1 , the output ends of the 20 phase interpolator units are connected together as the output end of the phase interpolator;

[0012] The third phase interpolator includes 16 phase interpolator units, wherein the input ends of 8 phase interpolator units are connected together and then connected to the signal Ø A , the inputs of the other 8 phase interpolator units are connected together and then connected to the signal Ø B , the output ends of the 16 phase interpolator units are connected together as the output end of the third phase interpolator.

[0013] Further, the time-to-digital converter includes a coarse-level time-to-digital converter, a fine-level time-to-digital converter and an encoder;

[0014] The coarse time-to-digital converter comprises M first delay units, M first D flip-flops, and second and third multiplexers; the input end of the first delay unit is connected to the signal INJ+, the M first delay units are connected in sequence, the output end of the mth first delay unit is connected to the reset end of the mth first D flip-flop and the mth input end of the second multiplexer, m=1,2,…,M; the output end of the second multiplexer is connected to the fine time-to-digital converter; the data input ends of the M first D flip-flops are all connected to the output end of the comparator and the input end of the third multiplexer; the output ends of the M first D flip-flops are all connected to the encoder, and the output end of the third multiplexer is connected to the fine time-to-digital converter;

[0015] The fine-level time-to-digital converter includes R second delay units, R third delay units and R second D flip-flops, the input end of the first second delay unit is connected to the output end of the third multiplexer; the input end of the first third delay unit is connected to the output end of the second multiplexer, the R second delay units are connected in sequence, the R third delay units are connected in sequence, the output end of the rth second delay unit is connected to the data input end of the rth second D flip-flop, the output end of the rth third delay unit is connected to the reset end of the rth second D flip-flop, r=1,2,…,R; the output ends of the R second D flip-flops are all connected to the encoder;

[0016] The output of the encoder is used as the output of the time-to-digital converter.

[0017] Beneficial effects: The present invention adopts a phase interpolation synchronous injection method, and uses the interpolation method of the phase interpolation module to obtain an ideal injection signal, complete the synchronization of the injection signal and the crystal oscillation signal, eliminate the phase error, and achieve efficient injection. A time-to-digital converter is used to detect the phase error, and a single detection process can be completed in only two cycles, which greatly reduces the auxiliary stage that cannot play an acceleration effect during the startup process and improves the startup time efficiency. The synchronization method based on the phase interpolation module of the present invention achieves high precision and high flexibility of phase adjustment, so that the injection phase is no longer limited to the phase that the injection source itself can provide; at the same time, even for large frequency errors, the phase error can be continuously eliminated through the phase interpolation technology, the effective injection time is extended and efficient energy injection is guaranteed, which greatly reduces the frequency accuracy requirements of the signal source that generates the energy injection signal, reduces the difficulty of designing the on-chip injection signal source of the fast-start crystal oscillator and the accuracy requirements of the off-chip calibration, and significantly improves the chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the overall circuit diagram of the present invention;

[0019] Figure 2 is a structural diagram of the phase interpolation module of the present invention;

[0020] Figure 3 is a circuit diagram of a phase interpolator unit of the present invention;

[0021] Figure 4 is a circuit diagram of a time-to-digital converter of the present invention;

[0022] Figure 5 This is the waveform diagram of the control signal working timing simulation of the digital module when the crystal oscillator frequency is 24MHz and the ring oscillator frequency is 24.48MHz;

[0023] Figure 6 This is a simulation waveform diagram of the comparator operation in the phase detection stage when the crystal oscillator frequency is 24MHz and the ring oscillator frequency is 24.48MHz;

[0024] Figure 7 The figure is a simulation waveform diagram of the injection signal generated by the ring oscillator and the phase interpolation module when the crystal oscillator frequency is 24 MHz and the ring oscillator frequency is 24.48 MHz;

[0025] Figure 8 This is a simulated waveform diagram of the two ends of the crystal during the crystal oscillator quick startup process when the crystal oscillator frequency is 24MHz and the ring oscillator frequency is 24.48MHz. DETAILED DESCRIPTION

[0026] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0027] like Figure 1 As shown, this embodiment provides a fast start-up crystal oscillator based on phase interpolation synchronous injection, including a digital module, a time-to-digital converter, a ring oscillator, a phase interpolation module, a comparator, a first level shifter, a second level shifter, an amplifier, a crystal, a first load capacitor C L1 , the second load capacitance C L2 , a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW4; the crystal is a two-terminal element, used to accurately generate an oscillation signal with a frequency of 24MHz, and its two ends are recorded as XO+ and XO-; the first load capacitor C L1 and the second load capacitor C L2 Both are two-terminal components, used to calibrate the oscillation frequency of the crystal, C L1 The lower plate is grounded, C L1 The upper plate is connected to one end of the third switch SW3, and the second load capacitor C L2 The lower plate is grounded, C L2The upper plate is connected to one end of the fourth switch SW4; the amplifier is used to maintain the oscillation of the crystal after the crystal is quickly started, and the amplifier is connected across the two ends of the crystal; the first signal input end of the first level shifter is connected to the XO+ end, the signal output end is connected to the comparator, and the second signal input end of the first level shifter is connected to the output EN of the digital module LS In the detection phase, the digital module controls the first level shifter to shift the level output from the XO+ terminal to a specified potential and outputs the adjusted signal XO OUT+ The first signal input terminal of the second level shifter is connected to the XO-terminal, the signal output terminal of the second level shifter is connected to the comparator, and the second signal input terminal of the second level shifter is connected to the output EN of the digital module LS In the detection phase, the digital module controls the second level shifter to shift the level of the output of the XO-terminal to the specified potential and outputs the adjusted signal XO OUT- The comparator is used to compare the signal XO OUT+ and XO OUT- , thereby generating a pulse signal CMP OUT , CMP OUT connected to a time-to-digital converter; the time-to-digital converter is used to quantize the rising edge of the signal INJ+ and the pulse signal CMP OUT The time difference between the edges of the time-to-digital converter is the time difference quantization result D τ , and quantize the time difference D τ Connected to the digital module; the ring oscillator is used to provide n phase injection signals, the phase interval between two adjacent injection signals is 40°, in this embodiment n=9, the ring oscillator outputs 9 injection signals (the 9 injection signals Ø 1 , Ø 2 , Ø 3 , Ø 4 , Ø 5 , Ø 6 , Ø 7 , Ø 8 and Ø 9 Denoted as Ø 1-9 ) is connected to a phase interpolation module; the phase interpolation module is used to adjust the phase of the injection signal, the control input end of the phase interpolation module is connected to the multi-bit control word CTRL output by the digital module, and the output end of the phase interpolation module outputs a signal INJ gen To the digital module; the first switch SW1 is enabled by the enable signal EN output by the digital module INJ Control, one end of the first switch SW1 is connected to the XO+ end of the crystal, and the other end is connected to the signal INJ+; the first switch SW1 controls whether the crystal XO+ end performs square wave injection; the second switch SW2 is controlled by the enable signal EN output by the digital moduleINJ Control, one end of the second switch SW2 is connected to the XO- end of the crystal, and the other end is connected to the signal INJ-, the second switch SW2 controls whether the crystal XO- end performs square wave injection; one end of the third switch SW3 is connected to the first load capacitor C L1 The other end of the upper plate is connected to the XO+ end of the crystal. The third switch SW3 is driven by the enable signal EN output by the digital module. CL The third switch SW3 controls whether the first load capacitor C is mounted on the crystal XO+ terminal. L1 One end of the fourth switch SW4 is connected to the second load capacitor C L2 The other end of the upper plate is connected to the crystal XO-end, and the fourth switch SW4 is driven by the enable signal EN output by the digital module. CL The fourth switch SW4 controls whether the crystal XO- terminal is mounted with the second load capacitor C L2 The digital module is used to control the operation of each module during the crystal oscillator quick start process, and the enable input terminal EN of the digital module SU Provided externally.

[0028] Digital modules according to D τ The reflected phase difference N, and the formula CTRLnew=CTRLold+N / X, update the multi-bit control word required by the phase interpolation module, where X is the resolution of the phase interpolation module; CTRLnew represents the updated multi-bit control word, and CTRLold represents the multi-bit control word before the update. Refresh the multi-bit control word and change the INJ output by the phase interpolation module. gen Phase, INJ gen The even-numbered inverters in the digital module generate signals INJ+ and INJ gen The odd-numbered inverters in the digital module generate the signal INJ-; therefore, the INJ output by the phase interpolation module is changed. gen By adjusting the phase, the error between the signals INJ-, INJ+ generated by the digital module and the crystal oscillation signal can be eliminated.

[0029] The digital module has a counter inside and an external signal EN is connected to the digital module. SU , the counter is for signal INJ gen Counting; setting thresholds T1, T2, T3, T4, T5, and T1<T2<T3<T4<T5, so that the count value of the counter is T; in this embodiment, the counter generates an enable signal EN INJ ,EN CL and EN LS Specifically:

[0030] When T≤T1, EN INJ =1,EN LS =0,ENCL = 0;

[0031] When T1 < T ≤ T2, EN INJ = 0, EN LS = 1, EN CL = 0;

[0032] When T2 < T ≤ T3, EN INJ = 1, EN LS = 0, EN CL = 0;

[0033] When T3 < T ≤ T4, EN INJ = 0, EN LS = 1, EN CL = 0;

[0034] When T4 < T ≤ T5, EN INJ = 1, EN LS = 0, EssN CL = 0;

[0035] When T > T5, EN INJ = 0, EN LS = 0, EN CL = 1.

[0036] As Figure 2 shown, the phase interpolation module includes a first multiplexer and first to third phase interpolators. The input end of the first multiplexer is connected to the output end of the ring oscillator, and the control end of the first multiplexer is connected to the multi-bit control word output by the digital module. The first multiplexer selects two adjacent injection signals Ø i and Ø i+1 from the n injection signals output by the ring oscillator according to the multi-bit control word. Ø i represents the i-th injection signal, and Ø i+1 represents the (i + 1)-th injection signal; Ø i , Ø i+1 and the multi-bit control word are input to the first phase interpolator to generate a signal Ø A , Ø i , Ø i+1 and the multi-bit control word are input to the second phase interpolator to generate a signal Ø B , and the signal Ø A , the signal Ø B and the multi-bit control word are input to the third phase interpolator to generate a signal INJ gen . The first phase interpolator and the second phase interpolator can generate signals Ø i and Ø i+1 whose phases are between the signals Ø A and have an interval of 4°.B , the third phase interpolator generates a phase between Ø A and Ø B The signal INJ is spaced 0.5° apart. gen .

[0037] like Figure 3 As shown, the first to third phase interpolators all include a phase interpolator unit, and the phase interpolator unit includes first to sixth MOS tubes, first and second resistors, and a first capacitor C O ; The first MOS tube M 1 The source is connected to the power supply voltage VDD, and the drain is connected to the second MOS tube M 2 The source and gate of the phase interpolator unit are connected to the sixth MOS tube M 6 The gate of the second MOS tube M 2 The drain of the first resistor R 1 One end of the second MOS tube M 2 The gate of the third MOS tube M 3 The drain and the fourth MOS tube M 4 The drain, the first resistor R 1 The other end of the phase interpolator unit is used as the output end and connected to the first capacitor C O One end and the second resistor R 2 One end of the first capacitor C O The other end of the second resistor R 2 The other end is connected to the fifth MOS tube M 5 The drain of the fifth MOS tube M 5 The source of the sixth MOS tube M is connected 6 The drain of the fifth MOS tube M 5 The gate of the third MOS tube M is used as the multi-bit control word input terminal and connected to the third MOS tube M 3 The gate of the fourth MOS tube M 4 The gate of the third MOS tube M 3 The source of the fourth MOS tube M is connected to the external power supply voltage. 4 And the sixth MOS tube M 6 In this embodiment, the first to third MOS tubes are PMOS tubes, and the fourth to sixth MOS tubes are NMOS tubes.

[0038] In this embodiment, the first phase interpolator and the second phase interpolator have the same structure and both include 20 phase interpolator units. The input ends of 10 phase interpolator units among the 20 phase interpolator units are connected together and then connected to the injection signal Ø i , the inputs of the other 10 phase interpolator units are connected together and then connected to the injection signal Ø i+1, the output ends of the 20 phase interpolator units are connected together as the output end of the phase interpolator.

[0039] The third phase interpolator of this embodiment includes 16 phase interpolator units, wherein the input ends of 8 phase interpolator units are connected together and then connected to the signal Ø A , the inputs of the other 8 phase interpolator units are connected together and then connected to the signal Ø B , the output ends of the 16 phase interpolator units are connected together as the output end of the third phase interpolator.

[0040] like Figure 4 As shown, the time-to-digital converter includes a coarse-level time-to-digital converter, a fine-level time-to-digital converter and an encoder.

[0041] The coarse time-to-digital converter comprises M first delay units τ 1 , M first D flip-flops and second and third multiplexers; the first first delay unit τ 1,1 The input end of is connected to the injection signal INJ+, the M first delay units are connected in sequence, and the mth first delay unit τ 1,m The output end of the mth D flip-flop is connected to the reset end of the mth first D flip-flop and the mth input end of the second multiplexer, m=1,2,…,M; the output end of the second multiplexer is denoted as IN FA , connected to a fine-scale time-to-digital converter; the data input terminals of the M first D flip-flops are all connected to the output terminal of the comparator and the input terminal of the third multiplexer; the output terminals of the M first D flip-flops are all connected to the encoder, and the output terminal of the third multiplexer is recorded as IN FB , connected to a fine-scale time-to-digital converter. In this embodiment, M=30.

[0042] The fine-scale time-to-digital converter includes R second delay units τ 2 , R third delay units τ 3 and R second D flip-flops, the first second delay unit τ 2,1 The input end is connected to the output end of the third multiplexer; the first third delay unit τ 3,1 The input end of is connected to the output end of the second multiplexer, R second delay units are connected in sequence, R third delay units are connected in sequence, and the rth second delay unit τ 2,r The output end of is connected to the data input end of the rth second D flip-flop, and the rth third delay unit τ 3,r The output end of is connected to the reset end of the rth second D flip-flop, r=1, 2, ..., R; the output ends of the R second D flip-flops are all connected to the encoder. In this embodiment, R=108.

[0043] The encoder obtains the injection signal INJ+ and the pulse signal CMP according to the output results of the M first D flip-flops in the coarse time-to-digital converter and the output results of the R second D flip-flops in the fine time-to-digital converter. OUT The phase error information is output as D τ As the output of the overall time-to-digital converter.

[0044] In this embodiment, the high-frequency crystal frequency is set to 24 MHz and the ring oscillator frequency is set to 24.48 MHz, with a 2% injection frequency deviation.

[0045] like Figure 5 As shown, the quick start process of the crystal oscillator of this embodiment includes six stages, namely the first injection stage 1, the first detection stage 2, the second injection stage 3, the second detection stage 4, the third injection stage 5 and the steady-state oscillation stage 6; the first injection duration is preset and fixed, set by the application end, and the second injection duration is determined by the calculation result of the first detection stage; the injection stage is used to help the crystal achieve rapid energy growth, and the detection stage is used to detect the phase difference between the signal (INJ+ and INJ-) output by the digital module and the crystal oscillation signal, and adjust the control of the phase interpolation module to eliminate the phase difference and achieve efficient energy growth.

[0046] like Figure 6 As shown, during the detection period, the signals input to the XO+ and XO- terminals are a pair of anti-phase sinusoidal signals. The level shifter adjusts the potential of the output signals of the XO+ and XO- terminals to the same level. The comparator compares the signals output by the two level shifters and outputs the comparison result CMP. OUT , CMP OUT The midpoint of the pulse is the second level shifter output signal XO OUT- The peak value of the time-to-digital converter quantifies the INJ+ rising edge and CMP OUT The time difference between the rising edges of 1 , quantify the rising edge of INJ+ and CMP OUT The time difference between the falling edges of 2 , thus obtaining the INJ+ injection edge and XO OUT- The time difference between the peak points (i.e. the best injection position) is (t 1 + t 2 ) / 2, this method only needs two cycles to detect the phase difference.

[0047] like Figure 7 As shown, the nine outputs of the ring oscillator are connected to the input of the phase interpolation module, which refines the phase interval into 0.5° and generates a signal INJ gen. The interpolation of the phase interpolation module is divided into two steps. In the first step, two adjacent signals Ø i and Ø i+1 (0 < i < 9) of the ring oscillator are selected according to the multi-bit control word and connected to the first phase interpolator and the second phase interpolator. The first phase interpolator outputs signal Ø A , and the second phase interpolator outputs signal Ø B . The phase interval between Ø A and Ø B is 4°; Ø A and Ø B are connected to the input end of the third phase interpolator. Finally, the third phase interpolator outputs INJ gen , and the phase of INJ gen can be adjusted at a phase interval of 0.5° according to the multi-bit control word, so as to eliminate the phase difference.

[0048] As Figure 8 shown, when the digital module starts the high-frequency crystal oscillator at EN SU , it counts the signal INJ gen . When the count value reaches the preset number of times, the digital module sets EN INJ to 0 and sets EN CL to 1 to start the steady-state oscillation stage. Figure 8 It can be seen that the crystal oscillator completes the fast start in only 7 μs and achieves stable oscillation.

[0049] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention does not further describe various possible combination methods.

Claims

1. A fast-start crystal oscillator based on phase interpolation synchronous injection, characterized in that: It includes a digital module, a time-to-digital converter, a ring oscillator, a phase interpolation module, a first level shifter and a second level shifter, an amplifier, a crystal, a first load capacitor and a second load capacitor, a first to a fourth switch and a comparator; One end of the crystal is recorded as XO+, and the other end is recorded as XO-. The digital module is internally provided with a counter, an even-numbered inverter, and an odd-numbered inverter. The counter generates an enable signal EN. INJ ,EN CL and EN LS The ring oscillator generates n injection signals to the phase interpolation module, and the phase interpolation module adjusts the phases of the n injection signals to generate a signal INJ gen , and the signal INJ gen Output to the digital module, n is a positive integer greater than 2; signal INJ gen The signal INJ+ is generated through an even-numbered inverter; the signal INJ gen The signal INJ- is generated through the odd-numbered inverters; the amplifier is connected across the two ends of the crystal, one end of the first load capacitor is grounded, and the other end is connected to one end of the third switch, the other end of the third switch is connected to the XO+ end of the crystal and one end of the first switch, and the other end of the first switch is connected to the signal INJ+; one end of the second load capacitor is grounded, the other end of the second load capacitor is connected to one end of the fourth switch, the other end of the fourth switch is connected to the XO- end of the crystal and one end of the second switch, and the other end of the second switch is connected to the signal INJ-; enable signal EN CL Control the third switch and the fourth switch, enable signal EN INJ Control the first switch and the second switch; the first signal input end of the first level shifter is connected to the XO+ end of the crystal, and the second signal input end of the first level shifter receives the enable signal EN sent by the digital module LS The output end of the first level shifter is connected to the first input end of the comparator; the first signal input end of the second level shifter is connected to the XO- end of the crystal, and the second signal input end of the second level shifter receives the enable signal EN sent by the digital module LS The output end of the second level shifter is connected to the second input end of the comparator, and the signal INJ+ and the pulse signal CMP outputted from the output end of the comparator are connected. OUT Connected to a time-to-digital converter; the time-to-digital converter quantizes the signal INJ+ and the pulse signal CMP OUT The phase difference between them is the quantized result D τ , and D τ Transmitted to the digital module, the digital module receives the D τ Update the multi-bit control word required by the phase interpolation module and transmit the updated multi-bit control word to the phase interpolation module, thereby changing the signal INJ gen phase.

2. A fast-start crystal oscillator based on phase interpolation synchronous injection according to claim 1, characterized in that: The digital module externally connects to the external signal EN SU , and the counter generates the enable signal EN INJ 、EN CL and EN LS Specifically: The counter counts the signal INJ gen , makes the count value of the counter be T, and internally sets thresholds T1, T2, T3, T4, T5 in the digital module, and T1 < T2 < T3 < T4 < T5; when T ≤ T1, EN INJ = 1, EN LS = 0, EN CL = 0; when T1 < T ≤ T2, EN INJ = 0, EN LS = 1, EN CL = 0; when T2 < T ≤ T3, EN INJ = 1, EN LS = 0, EN CL = 0; when T3 < T ≤ T4, EN INJ = 0, EN LS = 1, EN CL = 0; when T4 < T ≤ T5, EN INJ = 1, EN LS = 0, EssN CL = 0; when T > T5, EN INJ = 0, EN LS = 0, EN CL = 1.

3. A fast-start crystal oscillator based on phase interpolation synchronous injection according to claim 1, characterized in that: The digital module receives the D τ The multi-bit control word CTRL required to update the phase interpolation module is specifically: CTRLnew=CTRLold+N / X, where N is D τ where X is the resolution of the phase interpolation module, CTRLnew represents the updated multi-bit control word, and CTRLold represents the updated multi-bit control word.

4. A fast-start crystal oscillator based on phase interpolation synchronous injection according to claim 1, characterized in that: The phase interpolation module includes a first multiplexer and first to third phase interpolators, wherein the input end of the first multiplexer is connected to the output end of the ring oscillator, the control end of the first multiplexer is connected to the multi-bit control word output by the digital module, and the first multiplexer selects two adjacent injection signals from n injection signals according to the multi-bit control word. i and Ø i+1 , Ø i represents the i-th injected signal, Ø i+1 represents the i+1th injection signal, 0<i<n; i , Ø i+1 and a multi-bit control word are input to the first phase interpolator to generate a signal Ø A ; Ø i , Ø i+1 and a multi-bit control word are input to the second phase interpolator to generate a signal Ø B ; The signal Ø A , signal Ø B and a multi-bit control word are input to the third phase interpolator to generate a signal INJ gen .

5. A fast-start crystal oscillator based on phase interpolation synchronous injection according to claim 4, characterized in that: The first to third phase interpolators all include a phase interpolator unit, which includes first to sixth MOS tubes, first and second resistors and a first capacitor; the source of the first MOS tube is connected to the power supply voltage VDD, the drain is connected to the source of the second MOS tube, the gate is connected to the gate of the sixth MOS tube as the input end of the phase interpolator unit, the drain of the second MOS tube is connected to one end of the first resistor, the gate of the second MOS tube is connected to the drain of the third MOS tube and the drain of the fourth MOS tube, the other end of the first resistor is used as the output end of the phase interpolator unit, and is connected to one end of the first capacitor and one end of the second resistor, and the other end of the first capacitor is grounded; the other end of the second resistor is connected to the drain of the fifth MOS tube, the source of the fifth MOS tube is connected to the drain of the sixth MOS tube, the gate of the fifth MOS tube is used as the multi-bit control word input end, and is connected to the gate of the third MOS tube and the gate of the fourth MOS tube, the source of the third MOS tube is connected to the external power supply voltage, and the sources of the fourth MOS tube and the sixth MOS tube are both grounded; The first phase interpolator and the second phase interpolator have the same structure and both include 20 phase interpolator units. The input ends of 10 phase interpolator units among the 20 phase interpolator units are connected together and then connected to the injection signal Ø i , the inputs of the other 10 phase interpolator units are connected together and then connected to the injection signal Ø i+1 , the output ends of the 20 phase interpolator units are connected together as the output end of the phase interpolator; The third phase interpolator includes 16 phase interpolator units, wherein the input ends of 8 phase interpolator units are connected together and then connected to the signal Ø A , the inputs of the other 8 phase interpolator units are connected together and then connected to the signal Ø B , the output ends of the 16 phase interpolator units are connected together as the output end of the third phase interpolator.

6. A fast-start crystal oscillator based on phase interpolation synchronous injection according to claim 1, characterized in that: The time-to-digital converter comprises a coarse-level time-to-digital converter, a fine-level time-to-digital converter and an encoder; The coarse time-to-digital converter comprises M first delay units, M first D flip-flops, and second and third multiplexers; the input end of the first delay unit is connected to the signal INJ+, the M first delay units are connected in sequence, the output end of the mth first delay unit is connected to the reset end of the mth first D flip-flop and the mth input end of the second multiplexer, m=1,2,…,M; the output end of the second multiplexer is connected to the fine time-to-digital converter; the data input ends of the M first D flip-flops are all connected to the output end of the comparator and the input end of the third multiplexer; the output ends of the M first D flip-flops are all connected to the encoder, and the output end of the third multiplexer is connected to the fine time-to-digital converter; The fine-level time-to-digital converter includes R second delay units, R third delay units and R second D flip-flops, the input end of the first second delay unit is connected to the output end of the third multiplexer; the input end of the first third delay unit is connected to the output end of the second multiplexer, the R second delay units are connected in sequence, the R third delay units are connected in sequence, the output end of the rth second delay unit is connected to the data input end of the rth second D flip-flop, the output end of the rth third delay unit is connected to the reset end of the rth second D flip-flop, r=1,2,…,R; the output ends of the R second D flip-flops are all connected to the encoder; The output of the encoder is used as the output of the time-to-digital converter.

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