Electronic circuit

Abstract

The present invention addresses the problem of holding an input voltage with high precision. An electronic circuit includes: a sample / hold circuit (1) including a switching circuit, a capacitance element, and an output buffer circuit having a zero point calibration function for adjusting an input offset voltage thereof to zero, the output buffer circuit having a terminal of the capacitance element as an input; and a clock generation circuit (4) that outputs a clock signal (CLK) for zero calibration only at a specific timing and causes the output buffer circuit (2a) to perform a zero calibration operation so as to hold the voltage at the input terminal (Vin) in synchronization with the clock signal ([phi] S). According to the present invention, the charge error of the capacitance of the sample / hold circuit due to zero calibration can be suppressed to the minimum, and the input voltage can be held with high precision by the sample / hold circuit.

Description

Technical Field

[0001] The invention relates to an electronic circuit comprising a sample / hold circuit. Background Art

[0002] Generally speaking, when performing signal processing, a buffer circuit including an operational amplifier circuit is used to perform impedance conversion before performing analog / digital (A / D) conversion on the output voltage of a circuit with high output impedance. It is ideal that the buffer circuit outputs a voltage equal to the input voltage. However, an offset voltage exists at the input of the operational amplifier circuit, and an error occurs in the output voltage due to the offset voltage.

[0003] There are circuit methods for reducing offset voltage by self-calibration in operational amplifier circuits. Generally, there are structures called auto-zero amplifiers or chopper-stabilized amplifiers. These structures are useful circuits when high-precision A / D conversion is desired (see Non-Patent Document 1 and Patent Document 1).

[0004] As an example of a circuit that performs impedance conversion, consider a sample / hold circuit. Figure 7 As shown, the sampling / holding circuit 1 includes a switch SW1 and a capacitor C1 for voltage holding. Figure 7 In the illustrated configuration, while the switch SW1 is turned on, the output voltage of the output buffer circuit 2 follows the voltage of the input terminal Vin. Since the capacitor C1 holds charge, when the switch SW1 is turned off, the voltage immediately after the switch SW1 is turned off continues to be output.

[0005] When a self-calibration operational amplifier circuit is used as an output buffer circuit when performing impedance conversion on a voltage of a terminal having high output impedance, such as a capacitor terminal in a sample-and-hold circuit, the following problems occur.

[0006] In the calibration operation of the operational amplifier circuit, in the case of either the auto-zero amplifier or the chopper-stabilized amplifier, an operation of switching the connection of the input terminal is included in the internal circuit. When the operation of switching the connection of the input terminal is generated, clock feedthrough from the switch element inside the operational amplifier circuit or charge charging and discharging to the gate terminal of the metal oxide semiconductor (MOS) transistor for input is generated, and current input and output are instantaneously generated inside the amplifier. Therefore, a voltage error is generated at the input terminal (output terminal of the sample / hold circuit) of the operational amplifier circuit.

[0007] As an example of the problem, consider using a self-calibrating operational amplifier circuit as Figure 7The capacitor terminal of the sample / hold circuit 1 is connected to the output buffer circuit 2. If instantaneous current input and output occur during calibration of the operational amplifier circuit, the charge of the voltage holding capacitor C1 will leak, causing an error in the held voltage.

[0008] [Prior art literature]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Publication No. 2009-517895

[0011] [Non-patent literature]

[0012] [Non-Patent Document 1] Reza Moghimi, “To Chop or Auto Zero That Is the Question,” Analog Devices, Inc., 2011, <https: / / www.analog.com / jp / technical-articles / to-chop-or-auto-zero-that-is-the-question.html> Summary of the invention

[0013] [Problems to be solved by the invention]

[0014] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an electronic circuit capable of maintaining an input voltage with high accuracy.

[0015] [Technical means to solve the problem]

[0016] The electronic circuit of the present invention includes: a sampling / holding circuit and a clock generating circuit, wherein the sampling / holding circuit includes a switching circuit, a capacitor element, and an output buffer circuit which uses the terminal of the capacitor element as an input and has a zero-point calibration function for adjusting its own input offset voltage to zero, so that the voltage of the input terminal is maintained synchronously with the first clock signal, and the clock generating circuit is configured to output a second clock signal for zero-point calibration only at a specific time, so that the output buffer circuit performs a zero-point calibration operation.

[0017] In addition, a structural example of the electronic circuit of the present invention also includes an A / D converter, which is configured to perform A / D conversion on the output signal of the sampling / holding circuit, and the clock generation circuit outputs the second clock signal to the output buffer circuit only when the A / D converter performs A / D conversion.

[0018] In addition, a configuration example of the electronic circuit of the present invention is characterized in that the sample / hold circuit and the A / D converter are integrated into the same integrated circuit (IC).

[0019] Furthermore, in one configuration example of the electronic circuit of the present invention, the output buffer circuit is an auto-zero amplifier or a chopper-stabilized amplifier.

[0020] [Effects of the Invention]

[0021] According to the present invention, by providing a clock generation circuit that outputs a second clock signal for zero-point calibration only at a specific timing so that the output buffer circuit performs a zero-point calibration operation, the charge error of the capacitor of the sampling / holding circuit caused by the zero-point calibration can be suppressed to a minimum, thereby enabling the input voltage to be held with high precision by the sampling / holding circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a block diagram showing the structure of an electronic circuit according to an embodiment of the present invention.

[0023] Figure 2 This is a timing chart for explaining the operation of the electronic circuit according to the embodiment of the present invention.

[0024] Figure 3 This is a block diagram showing a configuration example of an auto-zero amplifier.

[0025] Figure 4 This is a timing diagram that explains the operation of the auto-zero amplifier.

[0026] Figure 5 This is a block diagram showing a configuration example of a chopper-stabilized amplifier.

[0027] Figure 6 This is a circuit diagram showing the structure of a differential input and differential output type sample / hold circuit.

[0028] Figure 7 This is a block diagram showing the structure of a conventional sample / hold circuit.

[0029] [Explanation of Symbols]

[0030] 1.1-1, 1-2: Sample / hold circuit

[0031] 2a: Output buffer circuit

[0032] 3: A / D Converter

[0033] 4: Clock generation circuit

[0034] A1~A3:Amplifier

[0035] C1, C1-1, C1-2, C2~C3: capacitors

[0036] SW1, SW1-1, SW1-2, SW2~SW13: switches

[0037] MOD1: Modulation circuit

[0038] DEM1: Demodulation circuit DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 1 is a block diagram showing the structure of an electronic circuit according to an embodiment of the present invention. The electronic circuit according to this embodiment includes a sample / hold circuit 1 , an output buffer circuit 2 a , an A / D converter 3 , and a clock generation circuit 4 .

[0040] The sample / hold circuit 1 holds the voltage of the input terminal Vin in synchronization with the clock signal φS. As in the conventional circuit, the sample / hold circuit 1 includes a switch SW1 provided between the input terminal Vin and the output terminal Vout, and a capacitor C1 having one end connected to the output terminal Vout and the other end connected to the ground.

[0041] The output buffer circuit 2a includes an operational amplifier circuit with a zero-point calibration function. Figure 1 , the output buffer circuit 2a is depicted outside the sample / hold circuit 1, but the output buffer circuit 2a is included in the sample / hold circuit 1. A configuration example of the output buffer circuit 2a will be described later. The A / D converter 3 performs A / D conversion on the output signal of the output buffer circuit 2a.

[0042] The clock generation circuit 4 supplies the clock signal φS and the clock signal CLK to the sample / hold circuit 1 and the output buffer circuit 2 a , respectively, and supplies the enable signal φC to the A / D converter 3 .

[0043] Figure 2 This is a timing diagram for explaining the operation of the electronic circuit of this embodiment. First, the switch SW1 of the sample / hold circuit 1 is turned on when the clock signal φS is at a high level (sampling mode). As a result, the voltage of the output terminal Vout of the sample / hold circuit 1 follows the voltage of the input terminal Vin.

[0044] Next, the switch SW1 is turned off when the clock signal φS is at a low level (hold mode). The sample / hold circuit 1 continues to output the voltage of the input terminal Vin before the switch SW1 is switched from on to off until the switch SW1 is turned on next time.

[0045] The clock generation circuit 4 sets the enable signal φC to a high level when the sample / hold circuit 1 is in the hold mode. As a result, the operation of the A / D converter 3 is enabled, and the A / D converter 3 samples the output voltage of the output buffer circuit 2a in synchronization with the clock signal (not shown) supplied from the clock generation circuit 4 and converts it into a digital signal. The clock generation circuit 4 returns the enable signal φC to a low level at a predetermined timing to stop the operation of the A / D converter 3.

[0046] In addition, the clock generation circuit 4 outputs the clock signal CLK for zero point calibration to the output buffer circuit 2a only when the enable signal φC is at a high level (at a specific timing, in this embodiment, during A / D conversion). In this way, in this embodiment, by outputting the clock signal CLK for zero point calibration that adjusts the offset voltage generated at the input of the output buffer circuit 2a to zero only during A / D conversion, and stopping the zero point calibration operation of the output buffer circuit 2a at timings other than A / D conversion, the charge error of the capacitor C1 of the sample / hold circuit 1 caused by the zero point calibration can be suppressed to a minimum. Since the voltage error when the sample / hold circuit 1 is combined with the zero point calibration operation is proportional to the integrated value of the current input and output during the zero point calibration, the error can be reduced by minimizing the number of zero point calibration operations.

[0047] Next, a specific example of the output buffer circuit 2a will be described. Figure 3 1 is a block diagram showing a configuration example of an auto-zero amplifier as an example of an output buffer circuit 2a. The auto-zero amplifier includes a differential input single-phase output type main (wide bandwidth) amplifier A1, a non-inverting input terminal and an input terminal Vi on the positive phase side of the auto-zero amplifier. + Connect the inverting input terminal to the inverting input terminal Vi of the auto-zero amplifier - The output terminal is connected to the output terminal Vo of the automatic zeroing amplifier; the inverting input terminal of the differential input single-phase output type zero adjustment amplifier A2 is connected to the inverting input terminal Vi of the automatic zeroing amplifier - connection; a capacitor C2, one end of which is connected to the offset adjustment input terminal VNB of the main amplifier A1, and the other end is connected to the ground; a capacitor C3, one end of which is connected to the offset adjustment input terminal VNA of the zero point adjustment amplifier A2, and the other end is connected to the ground; a switch SW2, which is arranged between the non-inverting input terminal and the inverting input terminal of the zero point adjustment amplifier A2; a switch SW3, which is arranged between the non-inverting input terminal of the main amplifier A1 and the non-inverting input terminal of the zero point adjustment amplifier A2; a switch SW4, which is arranged between the output terminal of the zero point adjustment amplifier A2 and the offset adjustment input terminal VNA; and a switch SW5, which is arranged between the output terminal of the zero point adjustment amplifier A2 and the offset adjustment input terminal VNB of the main amplifier A1.

[0048] The auto-zero amplifier switches between two phases ( Figure 4 At the clock phase φA of the clock signal CLK supplied from the clock generating circuit 4, switches SW2 and SW4 are turned on, and switches SW3 and SW5 are turned off. + , Input terminal Vi - The input signal is supplied only to the main amplifier A1. The main amplifier A1 operates in the same manner as a normal operational amplifier. The voltage stored in the capacitor C2 is applied to the offset adjustment input terminal VNB of the main amplifier A1.

[0049] When the switch SW2 is turned on, the non-inverting input terminal and the inverting input terminal of the zero-point adjustment amplifier A2 are short-circuited, so that an output voltage corresponding to the offset voltage of the zero-point adjustment amplifier A2 itself is generated at the output terminal of the zero-point adjustment amplifier A2, and the voltage is fed back to the zero-point adjustment amplifier A2 itself, thereby canceling the offset voltage of the zero-point adjustment amplifier A2. The offset voltage is held in the capacitor C3 and is held even when the phase is switched.

[0050] Next, at the clock phase φB of the clock signal CLK, the switches SW3 and SW5 are turned on, and the switches SW2 and SW4 are turned off. At the clock phase φB, the zero adjustment amplifier A2 amplifies the signal including the offset voltage of the main amplifier A1. The output voltage of the zero adjustment amplifier A2 is supplied to the offset adjustment input terminal VNB of the main amplifier A1, thereby canceling the offset of the main amplifier A1. The output voltage of the zero adjustment amplifier A2 is held in the capacitor C3 and is held even when the phase is switched.

[0051] The main amplifier A1 and the zero adjustment amplifier A2 are both operational amplifiers capable of adjusting offset. The relationship between the input and output of the main amplifier A1 is shown in equation (1).

[0052] Vo=α(Vi + -Vi - )+βVNB···(1)

[0053] α is the differential gain, and β is the trimming gain. The input and output relationship of the zero adjustment amplifier A2 is also the same as that of the main amplifier A1.

[0054] In this way, by repeating the two phases, low offset and low temperature drift of the main amplifier A1 are achieved.

[0055] Figure 52 is a block diagram showing a configuration example of a chopper-stabilized amplifier as another example of the output buffer circuit 2a. The chopper-stabilized amplifier includes a modulation circuit MOD1 that modulates a signal from an input terminal Vi. + , Input terminal Vi - The input signal is converted into an alternating current (AC) signal; an amplifier A3 of differential input and differential output type takes the output of the modulation circuit MOD1 as input; a demodulation circuit DEM1 restores the output signal of the amplifier A1 to a direct current (DC) signal; and a low-pass filter F1 of differential input and single-phase output type takes the output of the demodulation circuit DEM1 as input.

[0056] The modulation circuit MOD1 includes a switch SW6 provided at an input terminal Vi on the positive phase side of the chopper-stabilized amplifier. + Between the non-inverting input terminal of the amplifier A3; switch SW7, provided at the input terminal Vi of the inverting side of the chopper-stabilized amplifier - Between the inverting input terminal of the amplifier A3; switch SW8 is set at the input terminal Vi + and a switch SW9, which is provided between the input terminal Vi - and the non-inverting input terminal of amplifier A3.

[0057] The demodulation circuit DEM1 includes: a switch SW10, which is arranged between the non-inverting output terminal of the amplifier A3 and the non-inverting input terminal of the low-pass filter F1; a switch SW11, which is arranged between the inverting output terminal of the amplifier A3 and the inverting input terminal of the low-pass filter F1; a switch SW12, which is arranged between the non-inverting output terminal of the amplifier A3 and the inverting input terminal of the low-pass filter F1; and a switch SW13, which is arranged between the inverting output terminal of the amplifier A3 and the non-inverting input terminal of the low-pass filter F1.

[0058] When the clock signal CLK supplied from the clock generating circuit 4 is at a low level, the switches SW6, SW7, SW10, and SW11 are turned on, and the switches SW8, SW9, SW12, and SW13 are turned off. On the other hand, when the clock signal CLK is at a high level, the switches SW8, SW9, SW12, and SW13 are turned on, and the switches SW6, SW7, SW10, and SW11 are turned off. As a result, the modulation circuit MOD1 receives the input signal Vi. + , Input terminal Vi - The demodulation circuit DEM1 converts the input signal of the amplifier A1 into an AC signal. The demodulation circuit DEM1 restores the output signal of the amplifier A1 to a DC signal.

[0059] Since the input offset voltage of the amplifier A3 does not pass through the modulation circuit MOD1, it is converted into an AC signal by the demodulation circuit DEM1. Therefore, among the amplification results of the amplifier A3, only the information of the input offset voltage converted into an AC signal is removed by the low-pass filter F1.

[0060] Figure 3 , Figure 5 The structure of the output buffer circuit 2a shown is an example, and the present invention is not limited to Figure 3 , Figure 5 The structure shown.

[0061] In addition, the sampling / holding circuit 1, the sampling / holding circuit 1-1, the sampling / holding circuit 1-2, the output buffer circuit 2a, and the A / D converter 3 described in this embodiment may be integrated into the same IC. The clock generating circuit 4 may be provided inside or outside the IC.

[0062] [Industrial Applicability]

[0063] The present invention can be applied to electronic circuits.

Claims

1. An electronic circuit, characterized in that include: A sample / hold circuit including a switch circuit, a capacitor element, and an output buffer circuit having a terminal of the capacitor element as an input and having a zero-point calibration function for adjusting its own input offset voltage to zero, so that the voltage of the input terminal is held synchronously with the first clock signal; as well as The clock generation circuit is configured to output the second clock signal for zero point calibration only at a specific timing, so that the output buffer circuit performs a zero point calibration operation.

2. The electronic circuit according to claim 1, characterized in that Also includes: an analog / digital converter configured to perform analog / digital conversion on an output signal of the sample / hold circuit, The clock generation circuit outputs the second clock signal to the output buffer circuit only when the analog / digital converter performs analog / digital conversion.

3. The electronic circuit according to claim 2, characterized in that The sample / hold circuit and the analog / digital converter are integrated into the same integrated circuit.

4. The electronic circuit according to claim 1, characterized in that The output buffer circuit is an auto-zero amplifier or a chopper-stabilized amplifier.

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