Sigma-delta modulator and switched capacitor integrator

Abstract

The invention provides a sigma-delta modulator and a switched capacitor integrator, which are applied to the technical field of integrated circuits and sigma-delta modulators, a sampling capacitor and an integrating capacitor respectively form a new parallel structure capacitor by two new capacitors, and in the parallel structure, the sampling capacitor and the integrating capacitor are connected in parallel. The sum of the capacitance values of the two new capacitors corresponds to the capacitance value of the original sampling capacitor (or the integrating capacitor), and the top plates and the bottom plates of the two new capacitors are connected in a staggered manner. By improving the capacitor into a new parallel structure, the charge transfer error can be reduced by utilizing the transfer characteristic of charges in the capacitor in the parallel structure, so that the linearity of the capacitor is remarkably improved, and finally, the linearity of the integrator and the modulator can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits and sigma-delta (Sigma-delta) modulators, and in particular to a sigma-delta modulator and a switched capacitor integrator. Background Art

[0002] In discrete Σ-Δ (Sigma-Delta) modulators, the following are usually used: Figure 1 The switched capacitor integrator shown in FIG. 1 includes switches (such as S1 to S4), capacitors (such as sampling capacitor C S , Integral capacitor C I ), op amp (operational amplifier).

[0003] Generally speaking, switches and op amps are nonlinear devices. The nonlinearity of switches is mainly manifested in the change of on-resistance with input signal, and the nonlinearity of operational amplifiers is mainly manifested in the nonlinearity of op amp gain, limited gain bandwidth (GBW) and slew rate (SR).

[0004] At present, there are many existing technologies that have done a lot of innovative work and public elaboration on how to improve the linearity of switches and operational amplifiers. These existing technologies have fully improved the ideal characteristics of switches and operational amplifiers, and to a certain extent improved the linearity of Sigma-Delta modulators. However, in applications with higher linearity requirements, Sigma-Delta modulators are limited by total harmonic distortion (THD) and cannot meet application requirements. Summary of the invention

[0005] In view of this, the present application provides a Sigma-Delta modulator and a switched capacitor integrator, which can significantly reduce capacitor nonlinearity. When the capacitor is used in a Sigmadelta modulator, the total harmonic distortion can be significantly reduced.

[0006] The embodiments of this specification provide the following technical solutions:

[0007] The embodiment of the present specification provides a switched capacitor integrator, including a sampling switch, a holding switch, an integrating capacitor, a sampling capacitor and an operational amplifier, wherein the sampling capacitor and the integrating capacitor are each composed of two capacitor units connected in parallel, the sum of which is the original capacitance value and the top plate and the bottom plate are connected in an alternating manner;

[0008] The integrating capacitor is composed of a first integrating capacitor unit and a second integrating capacitor unit connected in parallel, and the sum of the capacitance of the first integrating capacitor unit and the capacitance of the second integrating capacitor unit is the capacitance of the original integrating capacitor, and the top plate of the first integrating capacitor unit is connected to the bottom plate of the second integrating capacitor unit, and the bottom plate of the first integrating capacitor unit is connected to the top plate of the second integrating capacitor unit;

[0009] The sampling capacitor is composed of a first sampling capacitor unit and a second sampling capacitor unit connected in parallel, and the sum of the capacitance of the first sampling capacitor unit and the capacitance of the second sampling capacitor unit is the capacitance of the original sampling capacitor, and the top plate of the first sampling capacitor unit is connected to the bottom plate of the second sampling capacitor unit, and the bottom plate of the first sampling capacitor unit is connected to the top plate of the second sampling capacitor unit.

[0010] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of this specification include at least:

[0011] By optimizing and improving the linearity of the sampling capacitor and the integrating capacitor in the switched capacitor integrator, for example, in the improvement of the linearity of the sampling capacitor, a new sampling capacitor is obtained by using a parallel structure in which the sum of two capacitances is the original capacitance and the top plate and the bottom plate are staggered and connected. Similarly, the integrating capacitor is also composed of a parallel structure in which two top plates and the bottom plates are staggered and connected. Thus, the linearity of the capacitor is improved by using the parallel structure in which the top and the bottom plates are staggered and connected. Ultimately, the linearity of the integrator can be improved, which is beneficial to reducing the total harmonic distortion of the discrete Sigmadelta modulator. For example, after using the capacitor structure of the present application, the total harmonic distortion of the first-order modulator can be improved by more than 30 dB. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 It is a structural schematic diagram of the switched capacitor integrator before improvement;

[0014] Figure 2 is a structural diagram of the improved switched capacitor integrator in this application;

[0015] Figure 3a , 3b They are schematic diagrams of simulation results for harmonic suppression before and after the switch capacitor integrator is improved in the present application;

[0016] Figure 4a It is a schematic diagram of the overall circuit principle of a fourth-order modulator in this application;

[0017] Figure 4b It is a schematic diagram of the model structure of a fourth-order modulator in this application;

[0018] Figure 4c is a schematic diagram of a single modulator circuit in the present application;

[0019] Figure 5a , 5b They are schematic diagrams of simulation results for harmonic suppression before and after the improvement of the fourth-order modulator in this application. DETAILED DESCRIPTION

[0020] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0021] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0022] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0025] In circuit implementation, discrete Sigma-Delta modulators usually use switched capacitor integrators to complete sampling and integration and holding. Figure 1Schematic diagram, where S1 and S3 are sampling switches, S2 and S4 are integral holding switches (also called holding switches), C S is the sampling capacitor, C I In addition, switches S2 and S3 can be grounded or connected to a reference Vref, which is not limited below.

[0026] Although the linearity of the modulator can be improved to a certain extent by improving the nonlinearity of the integrator switch and the operational amplifier, the overall performance is still limited by the total harmonic distortion of the modulator in high-performance applications. That is, the total harmonic distortion of the modulator is still large and cannot meet the design index requirements in high-performance applications.

[0027] In view of this, through in-depth research and improvement exploration of the Sigma-Delta modulator and the integrator circuit used in it, it is found that:

[0028] On the one hand, in capacitor applications, capacitors are usually used as linear devices. Therefore, in the prior art, in the nonlinear improvement of the integrator circuit (or the Sigma-Delta modulator), usually only the nonlinearity of the switches, operational amplifiers and other devices in the integrator are considered, and there is no improvement plan to improve the linearity of capacitors such as sampling capacitors and holding capacitors.

[0029] On the other hand, when the nonlinearity of switches and op amps is very obvious, the linearity of sampling capacitors, holding capacitors and other capacitors may not have much limit on the nonlinear impact on the overall performance, resulting in no one considering improvements in the linearity of sampling capacitors, holding capacitors and other capacitors.

[0030] Thirdly, after fully improving the ideal characteristics of the switch and the op amp, the linearity of the sampling capacitor and / or the holding capacitor itself becomes particularly important for the linearity of the overall circuit.

[0031] In summary, in improving the linearity of an integrator or a modulator, the linearity of a sampling capacitor and / or a holding capacitor is a key indicator that cannot be ignored.

[0032] Therefore, in addition to switches and op amps, reducing the nonlinearity of capacitors is a key factor in improving the overall linearity of the modulator.

[0033] It is further found that in the circuit implementation of the switched capacitor, the sampling capacitor and / or the holding capacitor are generally made of polysilicon and polysilicon, or metal in the semiconductor process to realize the capacitor structure, and the capacitance value depends on the voltage stored in the capacitor, which will cause errors in the process of charge transfer, thus manifesting as the nonlinearity of the capacitor. Moreover, after in-depth analysis, it is found that this error is a cause of the distortion of the output signal of the integrator (or modulator).

[0034] Based on this, the present application proposes a capacitor structure improvement scheme for the sampling capacitor and / or holding capacitor in the switched capacitor integrator: Figure 2 The circuit principle diagram is as follows: for the sampling capacitor C in the integrator S and the integrating capacitor C I The structures of the two capacitors are each improved to a parallel structure consisting of two corresponding new capacitors, wherein the parallel equivalent capacitance of the two new capacitors is maintained as the original capacitance value, that is, the sum of the capacitance of the two new capacitors is the capacitance of the original sampling capacitor (or integrating capacitor), thereby maintaining the capacitance value of the capacitor used in the integrator unchanged, avoiding the obvious impact of other performance index designs due to the new structure of the capacitor, and reducing the design difficulty; and, when realizing the parallel structure of plate-structured capacitors, unlike the traditional parallel structure (that is, the top plate and the top plate are connected, and the bottom plate and the bottom plate are connected to form a parallel structure), the present application is to stagger the top plates and the bottom plates of the two new capacitors so as to offset the transfer error when the charge is transferred between the top plate and the bottom plate, so that in the realized new parallel structure, the staggered parallel structure can be used to eliminate the nonlinearity of the capacitor and improve the linearity of the capacitor.

[0035] The staggered connection of the top plates and bottom plates of the two new capacitors means that the top plate of the first capacitor is connected to the bottom plate of the second capacitor, and the top plate of the second capacitor is connected to the bottom plate of the first capacitor. Figure 2 Illustration: For the sampling capacitor C S , by two new capacitors ( Figure 2 C S1 , C S2 ) in parallel, and C S1 and C S2 The top plate terminal and the bottom plate terminal are connected interchangeably (also called staggered connection), that is, in the plate capacitor structure, C S1 The top plate terminals are connected to the C S2 The bottom plate terminal connection, C S1 The bottom plate terminals and C S2 The top plate terminal of the capacitor is connected, so that the parallel structure of the two new capacitors connected in an interlaced manner reconstructs the sampling capacitor. In addition, the integrating capacitor C I Also similar to the sampling capacitor C S Improved structure, i.e. integral capacitor C I Also by two new capacitors ( Figure 2 C I1 , C I2 ) are connected in parallel, and the top and bottom terminals of the two capacitors are staggered, such as C I1 The top plate terminals are connected to the C I2 The bottom plate terminal connection, C I1 The bottom plate terminals and CI2 The top plate terminal connections.

[0036] By using two plate structure capacitors that are staggered between the top plate and the bottom plate to form a new capacitor with a parallel structure, a capacitor structure with higher linearity can be formed, which can greatly reduce the nonlinearity of the capacitor, improve the linearity of the integrating capacitor and the sampling capacitor, and significantly reduce the total harmonic distortion of the integrator (or Sigmadelta modulator).

[0037] For example, refer to Figure 3a and Figure 3b As shown in the figure, without the capacitor improvement structure of the present application, the amplitude of the second harmonic is about -78.dB, while after adopting the capacitor improvement structure of the present application, the amplitude of the second harmonic is about -121.2dB, which is significantly increased by about 40dB, and the amplitudes of other harmonics are also significantly reduced. Therefore, by improving the linearity of the capacitor, the second and third harmonic components of the signal are significantly suppressed, which is conducive to significantly reducing the total harmonic distortion (THD).

[0038] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0039] like Figure 2 As shown, the present application provides a switched capacitor integrator, including a sampling switch (such as Figure 2 S1, S3 shown), hold switch (such as Figure 2 S2, S4 shown), integral capacitor (such as Figure 2 C I ), sampling capacitor (such as Figure 2 C S ) and op amps (such as Figure 2 Amp shown).

[0040] Different from the traditional switched capacitor integrator, the present application improves the sampling capacitor and the integrating capacitor into the following structure: Figure 2 As shown, the sampling capacitor and the integrating capacitor are each formed by connecting two capacitors in parallel whose sum of capacitance is equal to the original capacitance, and the top plates and bottom plates of the two parallel capacitors are connected in an alternating manner to form a parallel capacitor structure unit.

[0041] For example, the integrating capacitor C I The first integrating capacitor unit C I1 and the second integral capacitor unit C I2 The first integral capacitor unit C I1 The capacitance of the second integral capacitor unit C I2 The sum of the capacitances of the original integrating capacitor and the first integrating capacitor unit C I1 The top plate and the second integrating capacitor unit C I2The bottom plate connection of the first integrating capacitor unit C I1 The bottom plate and the second integrating capacitor unit C I2 Top plate connection.

[0042] For example, the sampling capacitor C S The first sampling capacitor unit C S1 and the second sampling capacitor unit C S2 connected in parallel, and the first sampling capacitor unit C S1 The capacitance of the second sampling capacitor unit C S2 The sum of the capacitances of the original sampling capacitor and the first sampling capacitor unit C S1 The top plate and the second sampling capacitor unit C S2 The bottom plate connection of the first sampling capacitor unit C S1 The bottom plate and the second sampling capacitor unit C S2 Top plate connection.

[0043] In an implementation example, the first sampling capacitor unit C S1 The bottom plate or the first sampling capacitor unit C S1 The top plate of the sampling capacitor is used as the input end of the sampling capacitor. Similarly, the first integrating capacitor unit C I1 The bottom plate or the first integral capacitor unit C I1 The top plate serves as the input terminal of the integrating capacitor.

[0044] In some embodiments, the first integral capacitor unit C I1 The capacitance of the second integrating capacitor unit C I2 The ratio of the capacitance values ​​is a preset first ratio, for example, the first ratio is a simple ratio relationship such as 1:1, 1:2, 2:1, etc.

[0045] In some implementations, the first sampling capacitor unit C S1 The capacitance of the second sampling capacitor unit C S2 The ratio of the capacitance values ​​is a preset second ratio, and the second ratio can also be a simple ratio relationship such as 1:1, 1:2, 2:1, etc.

[0046] In some examples, the first ratio and the second ratio may be set to the same value or to different values.

[0047] As a preferred example, the first integral capacitor unit C I1 The capacitance of the second integral capacitor unit C I2 The capacitance of is preferably set to be equal, and the capacitance is easily half of the original integrating capacitor.

[0048] As a preferred example, the first sampling capacitor unit C S1 The capacitance of the second sampling capacitor unit C S2The capacitance is equal to that of the original sampling capacitor and is half of that of the original sampling capacitor.

[0049] As a preferred example, the first integral capacitor unit C I1 and the second integral capacitor unit C I1 They are capacitor units with the same structure and capacitance.

[0050] As a preferred example, the first sampling capacitor unit C S1 and the second sampling capacitor unit C S2 They are capacitor units with the same structure and capacitance.

[0051] In some embodiments, the top plate and the bottom plate of the plate structure capacitor may be polysilicon or metal.

[0052] For example, the first integrating capacitor unit C I1 The top plate is made of polysilicon layer or metal layer, and the first integral capacitor unit C I1 The bottom plate is made of polysilicon layer or metal layer, that is, the first integral capacitor unit C I1 The top plate and the bottom plate can be made of polysilicon or metal, or can be layers of different materials.

[0053] For example, the second integral capacitor unit C I2 The top plate includes a polysilicon layer or a metal layer, and the second integral capacitor unit C I2 The base plate includes a polysilicon layer or a metal layer.

[0054] For example, the first sampling capacitor unit C S1 The top plate includes a polysilicon layer or a metal layer, and the first sampling capacitor unit C S1 The base plate includes a polysilicon layer or a metal layer.

[0055] For example, the second sampling capacitor unit C S2 The top plate includes a polysilicon layer or a metal layer, and the second sampling capacitor unit C S2 The base plate includes a polysilicon layer or a metal layer.

[0056] In summary, by improving the capacitor into a new parallel structure, that is, in the new parallel structure, the top plate and the bottom plate of the capacitor are staggeredly connected, the staggered connection relationship can be used to reduce the charge transfer error in the charge transfer in the capacitor, thereby improving the linearity of the equivalent capacitor obtained in the parallel structure, which is beneficial to significantly improve the linearity of the overall circuit when the new parallel structure capacitor is used in an integrator (or modulator).

[0057] In some embodiments, the foregoing description is based on Figure 2The schematic single-ended circuit form is used for explanation, but those skilled in the art should understand that the parallel structure capacitor obtained by the above improvement can be used in capacitors in single-ended circuit form, and can also be used in capacitors in differential circuit form, and when used in capacitors in differential circuit form, it can significantly further reduce the amplitude of the second harmonic of the signal.

[0058] Based on the same inventive concept, the present application further provides a Σ-Δ modulator based on a new parallel structure capacitor (or a switched capacitor integrator based on a new parallel structure capacitor).

[0059] Compared with the traditional discrete Σ-Δ modulator based on switched capacitor integrator, the sampling capacitor and / or integration capacitor in at least one stage integrator in the Σ-Δ modulator of the present application is replaced by the new parallel structure capacitor in the aforementioned example, that is, the sampling capacitor and / or integration capacitor of the switched capacitor integrator in the modulator is improved into the following new parallel structure equivalent capacitor: two capacitors are used to form a new capacitor in parallel structure, wherein the sum of the capacitance of the two capacitors is the original capacitance value, and the top plates and bottom plates of the two capacitors are exchanged and connected.

[0060] In practice, if multiple integrators are used in the modulator, the original connection relationship between these integrators is still retained, that is, the multiple integrators are connected to each other for feedback to form a circuit with one or more high-order Sigmadelta modulators. It is only necessary to connect the sampling capacitors in at least one integrator in parallel with the capacitors connected in an interlaced manner on the top plate and the bottom plate to form a sampling capacitor with higher linearity. Of course, the integration capacitor can also be improved and designed similarly to the new parallel structure of the sampling capacitor.

[0061] In summary, the total harmonic distortion (THD) of the switched capacitor discrete Sigmadelta modulator can be greatly reduced by simply replacing the sampling integration capacitor of each stage integrator of the switched capacitor discrete Sigmadelta modulator with the capacitor structure of the present invention.

[0062] It should be noted that although the present application is illustrated by the improvement of capacitor linearity applied to a Σ-Δ modulator (or a switched capacitor integrator), the present application can significantly improve the parallel structure capacitor of the capacitor linearity, and is also suitable for other applications with high requirements on capacitor linearity, and is suitable for use in other types of Sigmadelta modulator circuits.

[0063] In some embodiments, the Sigmadelta modulator can be in single-ended or differential form, and in the differential form can significantly reduce the 2nd harmonic signal.

[0064] In some implementations, the present application provides a fourth-order discrete sigma-delta modulator.

[0065] refer to Figure 4a-4c The circuit principle shown is schematically shown. The four switched capacitor integrators in the fourth-order discrete Σ-Δ modulator all adopt the switched capacitor integrator described in any of the aforementioned examples of the present application, thereby utilizing the new integrator to improve the linearity of the modulator.

[0066] The overall circuit is Figure 4a As shown, the core consists of a dual-channel modulator (Modulator1 / Modulator2) and a digital control module (Digital). Other circuits may also include bias (BIAS), buffer (BUFFER), LS (level shifter) and input and output interface IO (INPUT, OUTPUT and other interface modules). The main feature of the feedforward (FF) structure modulator is that the input of the quantization comparator is the sum of the output of each stage integrator multiplied by a certain coefficient. A local negative feedback loop is added to the FF structure to form a resonator. The zero point of the FF type NTF (Noise Transfer Function) is moved from DC to the unit circle through the resonator to achieve better noise suppression, which is a feedforward (CRFF) structure modulator with a local resonator.

[0067] The example circuit is a dual-channel, high dynamic range, fourth-order Δ∑ modulator. Each channel uses a 1-bit 4th-order CRFF type Δ∑ modulator structure. The model is as follows Figure 4b The main circuit includes 4 integrators (INT), a quantizer (Quantizer), a DAC feedback module, a feed forward sum circuit (Feed forward Sum), a chopper circuit (Chopper is applied to the first stage integrator), and a clock module and a bias module.

[0068] The circuit diagram of a single modulator is as follows: Figure 4c As shown, Figure 4a The structure corresponds to that of , including 4 integrators, wherein the input and output ends of the first-stage integrator have Choppers to reduce noise, as well as DAC feedback control ports, feedforward summing circuits, quantizers, and OFST control modules.

[0069] refer to Figure 5a and Figure 5b It is shown that the spectrum of the Sigmadelta output code stream obtained by simulation with Cadence software is compared and analyzed. After adopting the improved capacitor structure of the present application, the total harmonic distortion (THD) is optimized by nearly 60dB, indicating that by improving the linearity of the sampling capacitor and the integrating capacitor, the total harmonic distortion (THD) of the Sigmadelta modulator system can be significantly improved.

[0070] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0071] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A switched capacitor integrator, comprising a sampling switch, a holding switch, an integrating capacitor, a sampling capacitor and an operational amplifier, characterized in that: The sampling capacitor and the integrating capacitor are each composed of two capacitor units connected in parallel, the sum of which is the original capacitance value and the top plate and the bottom plate are connected in an alternating manner; The integrating capacitor is composed of a first integrating capacitor unit and a second integrating capacitor unit connected in parallel, and the sum of the capacitance of the first integrating capacitor unit and the capacitance of the second integrating capacitor unit is the capacitance of the original integrating capacitor, and the top plate of the first integrating capacitor unit is connected to the bottom plate of the second integrating capacitor unit, and the bottom plate of the first integrating capacitor unit is connected to the top plate of the second integrating capacitor unit; The sampling capacitor is composed of a first sampling capacitor unit and a second sampling capacitor unit connected in parallel, and the sum of the capacitance of the first sampling capacitor unit and the capacitance of the second sampling capacitor unit is the capacitance of the original sampling capacitor, and the top plate of the first sampling capacitor unit is connected to the bottom plate of the second sampling capacitor unit, and the bottom plate of the first sampling capacitor unit is connected to the top plate of the second sampling capacitor unit.

2. The switched capacitor integrator according to claim 1, characterized in that: The ratio of the capacitance of the first integrating capacitor unit to the capacitance of the second integrating capacitor unit is a preset first ratio; and / or the ratio of the capacitance of the first sampling capacitor unit to the capacitance of the second sampling capacitor unit is a preset second ratio.

3. The switched capacitor integrator according to claim 1, characterized in that: The capacitance of the first integrating capacitor unit is equal to that of the second integrating capacitor unit, and the capacitance is half of the original integrating capacitor; and / or the capacitance of the first sampling capacitor unit is equal to that of the second sampling capacitor unit, and the capacitance is half of the original sampling capacitor.

4. The switched capacitor integrator according to claim 3, characterized in that: The first integrating capacitor unit and the second integrating capacitor unit are capacitor units with the same structure and the same capacitance; and / or the first sampling capacitor unit and the second sampling capacitor unit are capacitor units with the same structure and the same capacitance.

5. The switched capacitor integrator according to any one of claims 1 to 4, characterized in that: The top plate of the first integrating capacitor unit includes a polysilicon layer or a metal layer, and the bottom plate of the first integrating capacitor unit includes a polysilicon layer or a metal layer; and / or, the top plate of the second integrating capacitor unit includes a polysilicon layer or a metal layer, and the bottom plate of the second integrating capacitor unit includes a polysilicon layer or a metal layer; and / or, the top plate of the first sampling capacitor unit includes a polysilicon layer or a metal layer, and the bottom plate of the first sampling capacitor unit includes a polysilicon layer or a metal layer; and / or, the top plate of the second sampling capacitor unit includes a polysilicon layer or a metal layer, and the bottom plate of the second sampling capacitor unit includes a polysilicon layer or a metal layer.

6. A sigma-delta modulator, characterized in that In the Σ-Δ modulator, at least one switched capacitor integrator adopts the switched capacitor integrator as claimed in any one of claims 1-5.

7. The sigma-delta modulator according to claim 6, characterized in that The Σ-Δ modulator is a fourth-order discrete Σ-Δ modulator, and the four switched capacitor integrators are all switched capacitor integrators as described in any one of claims 1-5.

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