A transmitter applied to USB-PD communication

Abstract

The present invention provides a transmitter applied to USB-PD communication, which relates to the technical field of serial communication. It includes: the non-inverting input terminal of the first operational amplifier circuit receives a reference voltage, the output terminal of the first operational amplifier circuit is connected to the first end of the slew rate control circuit, and the inverting input terminal of the first operational amplifier circuit is connected to the second end of the slew rate control circuit; the non-inverting input terminal of the second operational amplifier circuit is connected to the third end of the slew rate control circuit, the inverting input terminal and the output terminal of the second operational amplifier circuit are connected to the source terminal of the port protection circuit, and the output terminal of the port protection circuit is connected to the configuration channel port. The second operational amplifier circuit is used to output a communication signal with good stability and strong anti-interference ability, and the port protection circuit is used to shield the high voltage of the configuration channel port. The beneficial effects are that a trapezoidal wave meeting the requirements of the USB-PD communication protocol is generated, and the rising edge and the falling edge of the trapezoidal wave are trimmed and controlled, which can cope with the deviations generated by different processes and has a wider applicability, and can meet the different withstand voltage requirements of the ports.

Description

Technical Field

[0001] The present invention relates to the technical field of serial communication, and particularly to a transmitter applied to USB-PD communication. Background Art

[0002] In recent years, as human society has gradually entered the intelligent era, the popularity of intelligent devices has been increasing day by day. People have put forward higher requirements for the portability and low-power consumption characteristics of electronic devices, and at the same time, the demand for high-performance chips has also been growing. However, the stronger the performance of the chip, the higher the power consumption, which poses a more severe challenge to the battery and its control technology. Common improvement measures include increasing the battery capacity to improve the endurance, or increasing the device charging speed to shorten the charging time. However, up to now, the lithium battery technology has encountered a research and development bottleneck. Simply relying on increasing the battery volume to increase the capacity will make the device heavier, which is contrary to the pursuit of portability. Therefore, in the context that no breakthrough has been made in battery storage technology, increasing the charging speed of intelligent devices has become a more effective solution. The fast charging technology has emerged and developed rapidly. The main principle of the fast charging technology is to increase the charging power by increasing the charging current and voltage.

[0003] The PD fast charging technology adopts a fast charging method with high voltage and large current, and has various charging levels and strong interface adaptability. This technology not only supports the charger to charge the device, but also allows devices to charge each other. Now, PD fast charging has been widely used. At the same time, the protocol stipulates that the USB Type-C interface is uniformly adopted. This interface is small and convenient, supports plugging in either way, and supports high transmission rate and high charging power, and has been widely popularized in the fields of consumer electronics and the like.

[0004] According to the USB-PD protocol, there are clear requirements for the signal quality of the transmission: the output high-level voltage range needs to be between (1.04~1.2)V, the output low-level voltage range needs to be between (0~0.075)V, the rising edge and falling edge time are at least 300ns, and the maximum time of the rising edge and falling edge cannot violate the eye diagram rule. While the USB-PD transmitter circuit sends communication signals that meet the requirements of the communication protocol, it also needs to consider the situation that the communication signals do not meet the protocol requirements due to electromagnetic interference that may exist in the actual USB PD communication process, as well as the voltage withstand requirements of the short-circuit fault for the CC port (Configuration Channel port). Therefore, strict requirements are put forward for the USB-PD transmitter circuit. Summary of the Invention

[0005] In view of the problems existing in the prior art, the present invention provides a transmitter applied to USB-PD communication, including: a first operational amplifier circuit, the non-inverting input terminal of the first operational amplifier circuit receives a reference voltage, the output terminal of the first operational amplifier circuit is connected to the first end of a slew rate control circuit, the inverting input terminal of the first operational amplifier circuit is connected to the second end of the slew rate control circuit, and the first operational amplifier circuit and the slew rate control circuit are used to generate a trapezoidal wave meeting the requirements of the USB-PD communication protocol; a second operational amplifier circuit, the non-inverting input terminal of the second operational amplifier circuit is connected to the third end of the slew rate control circuit, the inverting input terminal and the output terminal of the second operational amplifier circuit are connected to the input terminal of a port protection circuit, the output terminal of the port protection circuit is connected to a configuration channel port, the second operational amplifier circuit is used to output a communication signal, and the port protection circuit is used to shield high voltage on the configuration channel port.

[0006] Preferably, the first operational amplifier circuit includes a first-stage common-source amplifier and a second-stage common-source amplifier; the first-stage common-source amplifier includes: a first P-type MOS device, the source electrode of the first P-type MOS device is connected to the source electrode of a second P-type MOS device, the source electrode of the first P-type MOS device is also connected to the negative electrode of a second current source, the gate of the first P-type MOS device receives the reference voltage, and the gate of the second P-type MOS device is connected to the second end of the slew rate control circuit; a third N-type MOS device, the drain of the third N-type MOS device is connected to the drain of the first P-type MOS device and its own gate, the source electrode of the third N-type MOS device is connected to the source electrode of a fourth N-type MOS device and grounded, and the drain of the fourth N-type MOS device is connected to the drain of the second P-type MOS device and its own gate; the second-stage common-source amplifier includes: a second N-type MOS device, the gate of the second N-type MOS device is connected to the gate of the third N-type MOS device, the drain of the second N-type MOS device is connected to the drain of a third P-type MOS device, the gate of the third P-type MOS device, and the gate of a fourth P-type MOS device, the source electrode of the third P-type MOS device and the source electrode of the fourth P-type MOS device are connected to the positive electrode of the second current source; the gate of a fifth N-type MOS device is connected to the gate of the fourth N-type MOS device, the source electrode of the fifth N-type MOS device is connected to the source electrode of the second N-type MOS device and grounded, and the drain of the fifth N-type MOS device is connected to the drain of the fourth P-type MOS device and connected to the first end of the slew rate control circuit.

[0007] Preferably, the slew rate control circuit includes: a first switch, one end of the first switch is connected to one end of a second switch and the output end of the first operational amplifier circuit, the other end of the first switch is respectively connected to the inverting input end of the first operational amplifier circuit, one end of a first resistor, and one end of a third switch, and the other end of the second switch is grounded; a first current source, the positive pole of the first current source is connected to the other end of the third switch, and the negative pole of the first current source is grounded; a first capacitor, one end of the first capacitor is connected to the other end of the first resistor, one end of a fourth switch, one end of a fifth switch, and the non-inverting input end of the second operational amplifier circuit, the other end of the fourth switch is connected to one end of a second capacitor, the other end of the fifth switch is connected to one end of a third capacitor, and the other ends of the first capacitor, the second capacitor, and the third capacitor are grounded.

[0008] Preferably, the second operational amplifier circuit includes a cascode amplifier and a push-pull amplifier; a first input end of the cascode amplifier is connected to a third end of the slew rate control circuit, and a second input end of the cascode amplifier is connected to an input end of the port protection circuit; a first input end of the push-pull amplifier is connected to a first output end of the cascode amplifier, a second input end of the push-pull amplifier is connected to a second output end of the cascode amplifier, and an output end of the push-pull amplifier is connected to the input end of the port protection circuit.

[0009] Preferably, the cascode amplifier includes: a third current source, the negative electrode of the third current source is connected to the source electrodes of a fifth P-type MOS device and a sixth P-type MOS device, the gate of the fifth P-type MOS device is connected to the third terminal of the slew rate control circuit, and the gate of the sixth P-type MOS device is connected to the input terminal of the port protection circuit; a seventh P-type MOS device, the source of the seventh P-type MOS device is connected to the positive electrode of the third current source and the source of an eighth P-type MOS device, the drain of the seventh P-type MOS device is connected to the source of a ninth P-type MOS device, and the gate of the seventh P-type MOS device is connected to the gate of the eighth P-type MOS device and the drain of the ninth P-type MOS device; a tenth P-type MOS device, the source of the tenth P-type MOS device is connected to the drain of the eighth P-type MOS device, and the gate of the tenth P-type MOS device is connected to the gate of the ninth P-type MOS device; an eleventh P-type MOS device, the source of the eleventh P-type MOS device is connected to the drain of the tenth P-type MOS device and the drain of a tenth N-type MOS device, and the drain of the eleventh P-type MOS device is connected to the source of the tenth N-type MOS device and the drain of a ninth N-type MOS device; a sixth N-type MOS device, the drain of the sixth N-type MOS device is connected to the drain of the fifth P-type MOS device and the source of an eighth N-type MOS device, the drain of the eighth N-type MOS device is connected to the drain of the ninth P-type MOS device, and the gate of the eighth N-type MOS device is connected to the gate of the ninth N-type MOS device; a seventh N-type MOS device, the gate of the seventh N-type MOS device is connected to the gate of the sixth N-type MOS device, the source of the seventh N-type MOS device is connected to the source of the sixth N-type MOS device and grounded, and the drain of the seventh N-type MOS device is connected to the source of the ninth N-type MOS device.

[0010] Preferably, the push-pull amplifier includes: a twelfth P-type MOS device, the gate of the twelfth P-type MOS device is connected to the first output terminal of the cascode amplifier, the drain of the twelfth P-type MOS device is connected to one end of a fifth resistor, the other end of the fifth resistor is connected to the drain of an eleventh N-type MOS device, and the gate of the eleventh N-type MOS device is connected to the second output terminal of the cascode amplifier.

[0011] Preferably, the second operational amplifier circuit further includes a first Miller compensation circuit between the cascode amplifier and the push-pull amplifier. The first Miller compensation circuit includes: a third resistor, one end of the third resistor is connected to the first input terminal of the push-pull amplifier, the other end of the third resistor is connected to one end of a fourth capacitor, the other end of the fourth capacitor is connected to one end of a fifth capacitor and the output terminal of the push-pull amplifier, the other end of the fifth capacitor is connected to one end of a fourth resistor, and the other end of the fourth resistor is connected to the second input terminal of the push-pull amplifier.

[0012] Preferably, the second operational amplifier circuit further includes a negative feedback loop. The negative feedback loop includes: a fourth current source, the positive electrode of the fourth current source is connected to the source of a fourteenth P-type MOS device, and the gate of the fourteenth P-type MOS device is connected to the negative electrode of the fourth current source; a thirteenth P-type MOS device, the gate of the thirteenth P-type MOS device is connected to the drain of the fourteenth P-type MOS device and the first input terminal of the push-pull amplifier, the drain of the thirteenth P-type MOS device is connected to the drain and gate of a twelfth N-type MOS device and the gate of a thirteenth N-type MOS device, the sources of the thirteenth N-type MOS device and the twelfth N-type MOS device are grounded, and the drain of the thirteenth N-type MOS device is connected to the negative electrode of the fourth current source.

[0013] Preferably, the negative feedback loop further includes a second Miller compensation circuit. The second Miller compensation circuit includes: a sixth capacitor, one end of the sixth capacitor is connected to the drain of the fourteenth P-type MOS device, the other end of the sixth capacitor is connected to one end of a sixth resistor, and the other end of the sixth resistor is connected to the negative electrode of the fourth current source.

[0014] Preferably, the port protection circuit includes: a first N-type MOS device, the source of the first N-type MOS device is connected to the inverting input terminal and the output terminal of the second operational amplifier circuit, the drain of the first N-type MOS device is connected to one end of a second resistor, and the other end of the second resistor is connected to the configuration channel port.

[0015] The above technical solution has the following advantages or beneficial effects: A transmitter circuit applied to USB-PD communication is provided. A trapezoidal wave that meets the requirements of the USB-PD communication protocol is generated by using the first operational amplifier circuit and the slew rate control circuit, and the rising edge and the falling edge of the trapezoidal wave can be adjusted to cope with the deviations generated by different processes, and the applicability is wider. In addition, the second operational amplifier circuit is used as the output stage, and the CLASS AB operational amplifier structure has stronger driving ability and can cope with different cable loads. Finally, a port protection circuit is introduced to meet the different withstand voltage requirements of the configuration channel. Description of the Drawings

[0016] Figure 1 In a preferred embodiment of the present invention, it is a schematic structural diagram of a transmitter applied to USB-PD communication;

[0017] Figure 2 In a preferred embodiment of the present invention, it is a schematic structural diagram of a first operational amplifier circuit;

[0018] Figure 3 In a preferred embodiment of the present invention, it is a schematic structural diagram of a second operational amplifier circuit. Detailed implementation manners

[0019] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and as long as it conforms to the gist of the present invention, other embodiments may also fall within the scope of the present invention.

[0020] In a preferred embodiment of the present invention, in view of the above problems existing in the prior art, a transmitter applied to USB-PD communication is now provided, as Figure 1 shown, including: a first operational amplifier circuit 001, the non-inverting input terminal of the first operational amplifier circuit 001 receives a reference voltage VREF, the output terminal of the first operational amplifier circuit 001 is connected to the first end of a slew rate control circuit 002, the inverting input terminal of the first operational amplifier circuit 001 is connected to the second end of the slew rate control circuit 002, and the first operational amplifier circuit and the slew rate control circuit 002 are used to generate a trapezoidal wave meeting the requirements of the USB-PD communication protocol, wherein the slew rate control circuit 002 is used to adjust the rising and falling edges of the trapezoidal wave; a second operational amplifier circuit 003, the non-inverting input terminal of the second operational amplifier circuit 003 is connected to the third end of the slew rate control circuit 002, the inverting input terminal and the output terminal of the second operational amplifier circuit 003 are connected to the source terminal of a port protection circuit 004, and the output terminal of the port protection circuit 004 is connected to a configuration channel port CC. The second operational amplifier circuit 003 is used to output a communication signal with good stability, strong driving ability and strong anti-interference ability, and the port protection circuit 004 is used to shield the high voltage on the configuration channel port.

[0021] Specifically, in this embodiment, as Figure 1 shown, a transmitter circuit applied to USB-PD communication is provided. The first operational amplifier circuit and the slew rate control circuit are used to generate a trapezoidal wave meeting the requirements of the USB-PD communication protocol, and the rising and falling edges of the trapezoidal wave can be adjusted by trimming to cope with the deviations generated by different processes, with wider applicability. In addition, the second operational amplifier circuit is used as the output stage, and the CLASS AB operational amplifier structure has stronger driving ability and can cope with different cable loads. Finally, a port protection circuit is introduced to meet the different withstand voltage requirements of the CC port.

[0022] In a preferred embodiment of the present invention, the first operational amplifier circuit 001 includes a first-stage common-source amplifier 011 and a second-stage common-source amplifier 012; the first-stage common-source amplifier 011 includes: a first P-type MOS device, the source of the first P-type MOS device is connected to the source of the second P-type MOS device, the source of the first P-type MOS device is also connected to the negative electrode of the second current source, the gate of the first P-type MOS device receives a reference voltage, and the gate of the second P-type MOS device is connected to the second end of the slew rate control circuit; a third N-type MOS device, the drain of the third N-type MOS device is connected to the drain of the first P-type MOS device and its own gate, the source of the third N-type MOS device is connected to the source of the fourth N-type MOS device and grounded, and the drain of the fourth N-type MOS device is connected to the drain of the second P-type MOS device and its own gate; the second-stage common-source amplifier includes: a second N-type MOS device, the gate of the second N-type MOS device is connected to the gate of the third N-type MOS device, the drain of the second N-type MOS device is connected to the drain of the third P-type MOS device, the gate of the third P-type MOS device, and the gate of the fourth P-type MOS device, and the sources of the third P-type MOS device and the fourth P-type MOS device are connected to the positive electrode of the second current source; the gate of the fifth N-type MOS device is connected to the gate of the fourth N-type MOS device, the source of the fifth N-type MOS device is connected to the source of the second N-type MOS device and grounded, and the drain of the fifth N-type MOS device is connected to the drain of the fourth P-type MOS device and the first end of the slew rate control circuit.

[0023] Specifically, as Figure 2 shown, the first operational amplifier circuit 001 in this embodiment uses a two-stage common-source amplifier. The first-stage common-source amplifier 011 includes a first P-type MOS device MP1, a second P-type MOS device MP2, a third N-type MOS device MN3, a fourth N-type MOS device MN4, and a second current source I2; the gate VNN of the first P-type MOS device MP1 serves as the non-inverting input terminal of the first operational amplifier circuit 001 to receive the reference voltage VREF, and the gate of the second P-type MOS device MP2 serves as the inverting input terminal of the first operational amplifier circuit 001 and is connected to the second end of the slew rate control circuit 002; the second-stage common-source amplifier 012 includes a second N-type MOS device MN2, a fifth N-type MOS device MN5, a third P-type MOS device MP3, and a fourth P-type MOS device MP4.

[0024] In a preferred embodiment of the present invention, the slew rate control circuit 002 includes: a first switch, one end of the first switch is connected to one end of the second switch and the output end of the first operational amplifier circuit, and the other end of the first switch is respectively connected to the inverting input end of the first operational amplifier circuit, one end of the first resistor, and one end of the third switch, and the other end of the second switch is grounded; a first current source, the positive pole of the first current source is connected to the other end of the third switch, and the negative pole of the first current source is grounded; a first capacitor, one end of the first capacitor is connected to the other end of the first resistor, one end of the fourth switch, one end of the fifth switch, and the non-inverting input end of the second operational amplifier circuit, the other end of the fourth switch is connected to one end of the second capacitor, the other end of the fifth switch is connected to one end of the third capacitor, and the other ends of the first capacitor, the second capacitor, and the third capacitor are grounded.

[0025] Specifically, in this embodiment, as Figure 1 shown, the slew rate control circuit 002 includes a first switch S1, a second switch S2, a third switch S3, a first current source I1, a first resistor R1, a first capacitor C1, a fourth switch S4, a fifth switch S5, a second capacitor C2, and a third capacitor C3. Through logical control, the opening and closing of the switches S1, S2, and S3 in the slew rate control circuit 002 are controlled to input a trapezoidal wave signal that meets the high and low levels and the rising and falling edge time requirements in the USB-PD communication protocol to the positive input end of the second operational amplifier circuit 003.

[0026] When the switch S1 is closed, the first operational amplifier circuit 001 forms a unity gain amplifier, and the first switch S1, the second switch S2, and the third switch S3 are controlled by the BMC signal (Biphase Mark Code). When the BMC signal is at a high level, the first switch S1 is closed, and the second switch S2 and the third switch S3 are opened. At this time, the first operational amplifier circuit 001 is a unity gain amplifier, clamping the non-inverting input end and the inverting input end of the first operational amplifier circuit 001.

[0027] The current of the fourth P-type MOS device MP4 in the first operational amplifier circuit 001 charges the first capacitor C1 through the first resistor R1, and the inverting input terminal of the first operational amplifier circuit 001 slowly rises to the VREF voltage. When the BMC signal is at a low level, the first switch S1 is disconnected, and the second switch S2 and the third switch S3 are closed. At this time, the output terminal of the first operational amplifier circuit 001 is directly shorted to GND to prevent affecting the rising edge and falling edge of the BMC code of the next bit. The first current source I1 discharges the first capacitor C1 through the first resistor R1, and the inverting input terminal of the first operational amplifier circuit 001 slowly drops to 0V. A trapezoidal wave that meets the requirements of the USB-PD communication protocol is generated. In addition, the fourth switch S4 and the fifth switch S5 are controlled by a trimming signal, and the load capacitance at the output terminal of the first operational amplifier circuit 001 is changed by opening and closing the fourth switch S4 and the fifth switch S5, so as to accurately adjust the rising edge and falling edge of the trapezoidal wave.

[0028] In a preferred embodiment of the present invention, the second operational amplifier circuit 003 includes a cascode amplifier 031 and a push-pull amplifier 032; the first input terminal of the cascode amplifier 031 is connected to the third terminal of the slew rate control circuit 002, and the second input terminal of the cascode amplifier 031 is connected to the input terminal of the port protection circuit 004; the first input terminal of the push-pull amplifier 032 is connected to the first output terminal of the cascode amplifier 031, the second input terminal of the push-pull amplifier 032 is connected to the second output terminal of the cascode amplifier 031, and the output terminal of the push-pull amplifier 032 is connected to the input terminal of the port protection circuit 004.

[0029] Specifically, in this embodiment, as Figure 3 shown, the CLASS AB operational amplifier structure is adopted to enhance the driving ability of the circuit to cope with different cable loads. The first stage uses a folded cascode amplifier, and the second stage uses a push-pull amplifier.

[0030] In a preferred embodiment of the present invention, the cascode amplifier 031 includes: a third current source, the negative electrode of the third current source is connected to the source electrodes of a fifth P-type MOS device and a sixth P-type MOS device, the gate electrode of the fifth P-type MOS device is connected to the third terminal of the slew rate control circuit, and the gate electrode of the sixth P-type MOS device is connected to the input terminal of the port protection circuit 004; a seventh P-type MOS device, the source electrode of the seventh P-type MOS device is connected to the positive electrode of the third current source and the source electrode of an eighth P-type MOS device, the drain electrode of the seventh P-type MOS device is connected to the source electrode of a ninth P-type MOS device, and the gate electrode of the seventh P-type MOS device is connected to the gate electrode of the eighth P-type MOS device and the drain electrode of the ninth P-type MOS device; a tenth P-type MOS device, the source electrode of the tenth P-type MOS device is connected to the drain electrode of the eighth P-type MOS device, and the gate electrode of the tenth P-type MOS device is connected to the gate electrode of the ninth P-type MOS device; an eleventh P-type MOS device, the source electrode of the eleventh P-type MOS device is connected to the drain electrode of the tenth P-type MOS device and the drain electrode of a tenth N-type MOS device, and the drain electrode of the eleventh P-type MOS device is connected to the source electrode of the tenth N-type MOS device and the drain electrode of a ninth N-type MOS device; a sixth N-type MOS device, the drain electrode of the sixth N-type MOS device is connected to the drain electrode of the fifth P-type MOS device and the source electrode of an eighth N-type MOS device, the drain electrode of the eighth N-type MOS device is connected to the drain electrode of the ninth P-type MOS device, and the gate electrode of the eighth N-type MOS device is connected to the gate electrode of the ninth N-type MOS device; a seventh N-type MOS device, the gate electrode of the seventh N-type MOS device is connected to the gate electrode of the sixth N-type MOS device, the source electrode of the seventh N-type MOS device is connected to the source electrode of the sixth N-type MOS device and grounded, and the drain electrode of the seventh N-type MOS device is connected to the source electrode of the ninth N-type MOS device.

[0031] In a preferred embodiment of the present invention, the push-pull amplifier includes: a twelfth P-type MOS device, the gate electrode of the twelfth P-type MOS device is connected to the first output terminal of the cascode amplifier, the drain electrode of the twelfth P-type MOS device is connected to one end of a fifth resistor, the other end of the fifth resistor is connected to the drain electrode of an eleventh N-type MOS device, and the gate electrode of the eleventh N-type MOS device is connected to the second output terminal of the cascode amplifier.

[0032] Specifically, the specific circuit structures of the cascode amplifier 031 and the push-pull amplifier 032 are as Figure 3 shown.

[0033] The folded cascode amplifier 031 includes a third current source I3, a fifth P-type MOS device MP5, a sixth P-type MOS device MP6, a seventh P-type MOS device MP7, an eighth P-type MOS device MP8, a ninth P-type MOS device MP9, a tenth P-type MOS device MP10, an eleventh P-type MOS device MP11, a sixth N-type MOS device MN6, a seventh N-type MOS device MN7, an eighth N-type MOS device MN8, a ninth N-type MOS device MN9, and a tenth N-type MOS device MN10.

[0034] The push-pull amplifier 032 includes a twelfth P-type MOS device MP112, an eleventh N-type MOS device MN11, and a fifth resistor R5.

[0035] The output terminal of the second operational amplifier circuit 003 is connected to one end of the fifth resistor R5, one end of the fourth capacitor C4, one end of the fifth capacitor C5, and the drain terminal of the eleventh N-type MOS device MN11. When the waveform at the CC port is affected by electromagnetic interference, the waveform at the output terminal of the second operational amplifier circuit 003 will also be affected. At the same time, the current of the twelfth P-type MOS device MP112 in the second operational amplifier circuit 003 will fluctuate. The thirteenth P-type MOS device MP13 samples the current of the twelfth P-type MOS device MP112. The twelfth N-type MOS device MN12 and the thirteenth N-type MOS device MN13 form a current mirror. Therefore, the current fluctuation of the twelfth P-type MOS device MP12 will be replicated to the current fluctuation of the thirteenth N-type MOS device MN13. By comparing with the fourth current source I4, the gate voltage of the fourteenth P-type MOS device MP14 is changed, thereby changing the gate voltage of the twelfth P-type MOS device MP12, suppressing the current fluctuation of the twelfth P-type MOS device MP12, and thus reducing the influence of electromagnetic interference on the output waveform.

[0036] In a preferred embodiment of the present invention, the second operational amplifier circuit further includes a first Miller compensation circuit 033 between the cascode amplifier and the push-pull amplifier. The first Miller compensation circuit 033 includes: a third resistor, one end of the third resistor is connected to the first input terminal of the push-pull amplifier, the other end of the third resistor is connected to one end of the fourth capacitor, the other end of the fourth capacitor is connected to one end of the fifth capacitor and the output terminal of the push-pull amplifier, the other end of the fifth capacitor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the second input terminal of the push-pull amplifier.

[0037] Specifically, as Figure 3 shown, Miller compensation with a zeroing resistor is adopted between the cascode amplifier and the push-pull amplifier to ensure the stable operation of the circuit, including a third resistor R3, a fourth resistor R4, a fourth capacitor C4, and a fifth capacitor C5.

[0038] In a preferred embodiment of the present invention, the second operational amplifier circuit 003 further includes a negative feedback loop 034, and the negative feedback loop 034 includes: a fourth current source, the positive electrode of the fourth current source is connected to the source of the fourteenth P-type MOS device, and the gate of the fourteenth P-type MOS device is connected to the negative electrode of the fourth current source; a thirteenth P-type MOS device, the gate of the thirteenth P-type MOS device is connected to the drain of the fourteenth P-type MOS device and the first input terminal of the push-pull amplifier, the drain of the thirteenth P-type MOS device is connected to the drain and gate of the twelfth N-type MOS device and the gate of the thirteenth N-type MOS device, the sources of the thirteenth N-type MOS device and the twelfth N-type MOS device are grounded, and the drain of the thirteenth N-type MOS device is connected to the negative electrode of the fourth current source.

[0039] Specifically, in this embodiment, as Figure 3 shown, additionally introducing the negative feedback loop 034 effectively reduces the influence of electromagnetic interference on the communication signal during the USB PD communication process. The negative feedback loop includes a thirteenth P-type MOS device MP13, a fourteenth P-type MOS device MP14, a twelfth N-type MOS device MN12, a thirteenth N-type MOS device MN13, a sixth capacitor C6, a sixth resistor R6, and a fourth current source I4.

[0040] In a preferred embodiment of the present invention, the negative feedback loop 034 further includes a second Miller compensation circuit 035, and the second Miller compensation circuit 035 includes: a sixth capacitor, one end of the sixth capacitor is connected to the drain of the fourteenth P-type MOS device, the other end of the sixth capacitor is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the negative electrode of the fourth current source.

[0041] Specifically, in this embodiment, as Figure 3 shown, the sixth capacitor C6 and the sixth resistor R6 constitute a Miller compensation with a zero cancellation resistor for the negative feedback loop to stabilize the negative feedback loop.

[0042] In a preferred embodiment of the present invention, the port protection circuit 004 includes: a first N-type MOS device, the source of the first N-type MOS device is connected to the inverting input terminal and the output terminal of the second operational amplifier circuit, and the drain of the first N-type MOS device is connected to one end of the second resistor, and the other end of the second resistor is connected to the configuration channel port.

[0043] Specifically, in this embodiment, as Figure 1 shown, the port protection circuit 004 includes a first N-type MOS device MN1 and a second resistor R2.

[0044] Among them, the first N-type MOS device MN1 is a high-voltage device, and its source is connected to the output terminal and the inverting input terminal of the second operational amplifier circuit 003. The second resistor R2 is a small resistor that does not affect the output waveform but can limit the ESD current of the CC port to protect the internal circuit. The first N-type MOS device MN1 can select different voltage-resistant devices according to different voltage withstand requirements and be applied to different usage scenarios.

[0045] The above are only preferred embodiments of the present invention, and do not limit the implementation manners and protection scope of the present invention. For those skilled in the art, it should be able to realize that the solutions obtained by equivalent replacements and obvious changes made by using the content of this specification and the drawings should all be included in the protection scope of the present invention.

Claims

1. A transmitter for USB-PD communication, characterized in that: include: a first operational amplifier circuit, wherein a non-inverting input terminal of the first operational amplifier circuit receives a reference voltage, an output terminal of the first operational amplifier circuit is connected to a first terminal of a slew rate control circuit, an inverting input terminal of the first operational amplifier circuit is connected to a second terminal of the slew rate control circuit, and the first operational amplifier circuit and the slew rate control circuit are used to generate a trapezoidal wave that meets the requirements of the USB-PD communication protocol; a second operational amplifier circuit, wherein a non-inverting input terminal of the second operational amplifier circuit is connected to a third terminal of the slew rate control circuit, an inverting input terminal and an output terminal of the second operational amplifier circuit are connected to an input terminal of a port protection circuit, an output terminal of the port protection circuit is connected to a configuration channel port, the second operational amplifier circuit is used to output a communication signal, and the port protection circuit is used to shield a high voltage on the configuration channel port; The slew rate control circuit comprises: a first switch, wherein one end of the first switch is connected to one end of the second switch and the output end of the first operational amplifier circuit, the other end of the first switch is respectively connected to the inverting input end of the first operational amplifier circuit, one end of the first resistor and one end of the third switch, and the other end of the second switch is grounded; a first current source, wherein a positive electrode of the first current source is connected to the other end of the third switch, and a negative electrode of the first current source is grounded; A first capacitor, one end of the first capacitor is connected to the other end of the first resistor, one end of the fourth switch, one end of the fifth switch and the non-inverting input end of the second operational amplifier circuit, the other end of the fourth switch is connected to one end of the second capacitor, the other end of the fifth switch is connected to one end of the third capacitor, and the other ends of the first capacitor, the second capacitor and the third capacitor are grounded.

2. The transmitter according to claim 1, characterized in that The first operational amplifier circuit includes a first-stage common-source amplifier and a second-stage common-source amplifier; The first-stage common-source amplifier comprises: a first P-type MOS device, wherein a source of the first P-type MOS device is connected to a source of a second P-type MOS device, the source of the first P-type MOS device is also connected to a negative electrode of a second current source, a gate of the first P-type MOS device receives the reference voltage, and a gate of the second P-type MOS device is connected to a second end of the slew rate control circuit; a third N-type MOS device, wherein the drain of the third N-type MOS device is connected to the drain of the first P-type MOS device and its own gate, the source of the third N-type MOS device is connected to the source of the fourth N-type MOS device and is grounded, and the drain of the fourth N-type MOS device is connected to the drain of the second P-type MOS device and its own gate; The second-stage common-source amplifier comprises: a second N-type MOS device, wherein a gate of the second N-type MOS device is connected to a gate of the third N-type MOS device, a drain of the second N-type MOS device is connected to a drain of a third P-type MOS device, a gate of the third P-type MOS device and a gate of a fourth P-type MOS device, and a source of the third P-type MOS device and a source of the fourth P-type MOS device are connected to a positive electrode of the second current source; The gate of the fifth N-type MOS device is connected to the gate of the fourth N-type MOS device, the source of the fifth N-type MOS device is connected to the source of the second N-type MOS device and is grounded, and the drain of the fifth N-type MOS device is connected to the drain of the fourth P-type MOS device and to the first end of the slew rate control circuit.

3. The transmitter according to claim 1, characterized in that The second operational amplifier circuit includes a cascode amplifier and a push-pull amplifier; The first input terminal of the common-source common-gate amplifier is connected to the third terminal of the slew rate control circuit, and the second input terminal of the common-source common-gate amplifier is connected to the input terminal of the port protection circuit; The first input end of the push-pull amplifier is connected to the first output end of the common-source common-gate amplifier, the second input end of the push-pull amplifier is connected to the second output end of the common-source common-gate amplifier, and the output end of the push-pull amplifier is connected to the input end of the port protection circuit.

4. The transmitter according to claim 3, characterized in that The cascode amplifier comprises: a third current source, wherein a negative electrode of the third current source is connected to a source of a fifth P-type MOS device and a source of a sixth P-type MOS device, a gate of the fifth P-type MOS device is connected to a third terminal of the slew rate control circuit, and a gate of the sixth P-type MOS device is connected to an input terminal of the port protection circuit; a seventh P-type MOS device, wherein a source of the seventh P-type MOS device is connected to the positive electrode of the third current source and the source of the eighth P-type MOS device, a drain of the seventh P-type MOS device is connected to the source of the ninth P-type MOS device, and a gate of the seventh P-type MOS device is connected to the gate of the eighth P-type MOS device and the drain of the ninth P-type MOS device; a tenth P-type MOS device, wherein a source of the tenth P-type MOS device is connected to a drain of the eighth P-type MOS device, and a gate of the tenth P-type MOS device is connected to a gate of the ninth P-type MOS device; an eleventh P-type MOS device, wherein the source of the eleventh P-type MOS device is connected to the drain of the tenth P-type MOS device and the drain of the tenth N-type MOS device, and the drain of the eleventh P-type MOS device is connected to the source of the tenth N-type MOS device and the drain of the ninth N-type MOS device; a sixth N-type MOS device, wherein a drain of the sixth N-type MOS device is connected to the drain of the fifth P-type MOS device and the source of an eighth N-type MOS device, a drain of the eighth N-type MOS device is connected to the drain of the ninth P-type MOS device, and a gate of the eighth N-type MOS device is connected to the gate of the ninth N-type MOS device; A seventh N-type MOS device, wherein the gate of the seventh N-type MOS device is connected to the gate of the sixth N-type MOS device, the source of the seventh N-type MOS device is connected to the source of the sixth N-type MOS device and is grounded, and the drain of the seventh N-type MOS device is connected to the source of the ninth N-type MOS device.

5. The transmitter according to claim 3, characterized in that The push-pull amplifier comprises: A twelfth P-type MOS device, wherein the gate of the twelfth P-type MOS device is connected to the first output terminal of the common-source common-gate amplifier, the drain of the twelfth P-type MOS device is connected to one end of a fifth resistor, the other end of the fifth resistor is connected to the drain of an eleventh N-type MOS device, and the gate of the eleventh N-type MOS device is connected to the second output terminal of the common-source common-gate amplifier.

6. The transmitter according to claim 3, characterized in that The second operational amplifier circuit further includes a first Miller compensation circuit between the common-source common-gate amplifier and the push-pull amplifier, and the first Miller compensation circuit includes: a third resistor, one end of the third resistor is connected to the first input end of the push-pull amplifier, the other end of the third resistor is connected to one end of a fourth capacitor, the other end of the fourth capacitor is connected to one end of a fifth capacitor and the output end of the push-pull amplifier, the other end of the fifth capacitor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the second input end of the push-pull amplifier.

7. The transmitter according to claim 3, characterized in that The second operational amplifier circuit also includes a negative feedback loop, and the negative feedback loop includes: a fourth current source, wherein a positive electrode of the fourth current source is connected to a source electrode of a fourteenth P-type MOS device, and a negative electrode of the fourteenth P-type MOS device is connected to a negative electrode of the fourth current source; a thirteenth P-type MOS device, wherein the gate of the thirteenth P-type MOS device is connected to the drain of the fourteenth P-type MOS device and the first input terminal of the push-pull amplifier, the drain of the thirteenth P-type MOS device is connected to the drain and gate of the twelfth N-type MOS device and the gate of the thirteenth N-type MOS device, the source of the thirteenth N-type MOS device and the source of the twelfth N-type MOS device are grounded, and the drain of the thirteenth N-type MOS device is connected to the negative electrode of the fourth current source.

8. The transmitter according to claim 7, characterized in that The negative feedback loop also includes a second Miller compensation circuit, and the second Miller compensation circuit includes: A sixth capacitor, one end of the sixth capacitor is connected to the drain of the fourteenth P-type MOS device, the other end of the sixth capacitor is connected to one end of a sixth resistor, and the other end of the sixth resistor is connected to the negative electrode of the fourth current source.

9. The transmitter according to claim 1, characterized in that The port protection circuit comprises: A first N-type MOS device, wherein a source of the first N-type MOS device is connected to an inverting input terminal and an output terminal of the second operational amplifier circuit, a drain of the first N-type MOS device is connected to one end of a second resistor, and the other end of the second resistor is connected to the configuration channel port.

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