Domestic switching chip high-speed signal quality evaluation method, device, medium and system

Abstract

The invention discloses a domestic switch chip high-speed signal quality evaluation method, device, medium and system, and belongs to the field of embedded systems, and the method comprises the following steps: reporting a PortWrite event for a domestic switch chip, and carrying out random sequence error rate test on lane of the switch chip by using a pseudo-random binary sequence PRBS generator of a 1800 chip. The method has the advantages of low cost, simplicity in operation and accurate result.

Description

Technical Field

[0001] The present invention relates to the field of embedded systems, and more specifically, to a method, device, medium and system for evaluating the quality of high-speed signals of a domestic switching chip. Background Art

[0002] In embedded system applications, all hardware components are connected based on bus mode. Due to the limitations of transmission rate and system topology, traditional interconnection buses can no longer meet the growing needs of processor frequency and performance. Therefore, in embedded environments, RapidIO high-speed serial bus is basically used to meet the interconnection transmission between chips and boards, which can achieve a communication rate of 1Gbps to 60Gbps.

[0003] At present, the integrated electronic information system mainly includes network switching module (RCM), general data processing module (DPM), general signal processing module (SPM), etc. The domestic RapidIO switching chip is used between chips and boards to achieve high-reliability data transmission. Among them, the network switching module, general signal processing module, and data processing module are equipped with one or more domestic SRIO switching chips, forming a RapidIO-based network transmission framework.

[0004] During system integration, domestic switching chips often report PortWrite events. According to the chip manual, the reason for the report may be poor hardware signal quality or software errors, which may cause nodes to exit the network or fail to join the network, and the system cannot work properly. At this time, it is necessary to quickly isolate whether it is caused by hardware or software problems. The traditional way is to use an oscilloscope to draw an eye diagram. This oscilloscope has high requirements for bandwidth and sampling rate and is expensive.

[0005] The disadvantages of this existing method are:

[0006] (1) Oscilloscopes have high bandwidth and sampling rate requirements, are expensive, and may not be available at times.

[0007] (2) When using an oscilloscope for testing, it is necessary to manually confirm the start and end points of the eye-drilling diagram, which is cumbersome.

[0008] (3) The eye diagram obtained by using an oscilloscope signal may not be accurate. The signal capture position and time as well as the experience of using the oscilloscope have a great impact on the eye diagram result. Summary of the invention

[0009] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a method, device, medium and system for evaluating the quality of high-speed signals of a domestic switching chip, which have the advantages of low cost, simple operation and accurate results.

[0010] The object of the present invention is achieved through the following solutions:

[0011] A method for evaluating the quality of high-speed signals of a domestic switching chip uses a pseudo-random binary sequence PRBS generator of an 1800 chip to perform a random sequence bit error rate test on the lanes of the switching chip, specifically comprising the following steps:

[0012] S1, traverses and detects all domestic switching chips in the network;

[0013] S2, traverse and detect all ports 0 to 17 of the switch chip;

[0014] S3, if the RIO Port Error and Status CSR PORT_OK bit field is 2, the port is valid, otherwise the port is invalid and jumps to S2 to detect the next port;

[0015] S4, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip local port Lane{0..47}Control Register register value to 0x28E000A;

[0016] S5, through I2C write operation, according to the mapping relationship between port and LANE, configure the control register value of Lane{0..47} of the opposite port of the switch chip to 0x28E000A;

[0017] S6, read the Lane{0..47}PRBS Error CounterRegister register values ​​of the local and peer switching chips through I2C read operations;

[0018] S7, store and analyze the data to determine the port quality. If the PRBS_ERR bit field is 0, the signal quality is good. If the PRBS_ERR bit field is 1, the signal quality is poor. The larger the PRBS_ERR_CNT bit field value is, the more errors there are and the worse the signal quality is.

[0019] S8, record the data and jump to S2 to detect the next port;

[0020] S9, after detecting the current switch chip, jump to S1 to detect the next switch chip;

[0021] S10, reporting the signal quality results of all switch chip ports.

[0022] Further, in step S1, the detection network is a SRIO network.

[0023] Furthermore, the SRIO network includes: 1 SRIO switching board, 1 data processing board and 2 signal processing boards. The data processing board and the signal processing board are interconnected through the SRIO domestic switching chip to jointly build the SRIO network environment.

[0024] Furthermore, a testing device is also included, and the testing device resides in a master control node of the SRIO switch board.

[0025] A domestic switching chip high-speed signal quality assessment device comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, any of the above methods is executed.

[0026] A computer-readable storage medium stores a computer program, wherein the computer program executes any of the above methods when loaded by a processor.

[0027] A domestic switching chip high-speed signal quality assessment system comprises the domestic switching chip high-speed signal quality assessment device as described above.

[0028] The beneficial effects of the present invention include:

[0029] (1) The solution of the present invention is aimed at the problem of domestic switching chips reporting PortWrite events in the prior art. The pseudo-random binary sequence (PRBS) generator of the 1800 chip is used to perform a random sequence bit error rate test on the lanes of the switching chip, thereby providing a solution for evaluating the node quality of domestic switching chips.

[0030] (2) The solution of the present invention has the advantage of low cost. The method of using an oscilloscope to drill an eye diagram to detect signal quality requires an expensive oscilloscope. The present invention uses the pseudo-random binary sequence (PRBS) generator of the 1800 chip to perform a random sequence bit error rate test on the lanes of the switching chip, and then completes the monitoring, recording and analysis of the port. It is simple and effective, and does not require an expensive, high-bandwidth and high-sampling-rate oscilloscope.

[0031] (3) The scheme of the present invention has the advantages of simple operation and accurate results. The eye diagram result of using an oscilloscope signal may be inaccurate. The capture position and time of the signal and the experience of using the oscilloscope have a great influence on the eye diagram result. The method and device of the present invention can automatically traverse and detect the signal quality of all paths passing through the port in the SRIO network. The operation is simple, no manual eye diagram is required, and the result is accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 A schematic diagram of a domestic switch chip node quality assessment device according to an embodiment of the present invention;

[0034] Figure 2 FIG. 4 is a schematic diagram of an SRIO network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0036] Explanation of terms

[0037] RIO Port Error and Status CSR PORT_OK, PORT_OK field of the RIO port error status register;

[0038] Lane{0..47}Control Register(0xFF8000), channel control register base address;

[0039] Lane{0..47}PRBS Error Counter Register(0xFF8008;), channel PRBS error counter register base address;

[0040] 0xFF8008+0x100*lanenum, the PRBS error count register address of the channel with channel number lanenum;

[0041] BIT23 refers to the BIT32 bit of the RIO Port Error and Status CSR register, namely the PORT_OK bit field;

[0042] lane, passage.

[0043] like Figure 2 As shown in FIG. 1 , a schematic diagram of an SRIO network is shown. The chassis contains one SRIO domestic switch board, one data processing board and two signal processing boards. The modules are interconnected through SRIO domestic switch chips to jointly build an SRIO network environment. The test device resides in the master control node of the switch module. As a further embodiment of the present invention, Figure 1 As shown, a method for evaluating the quality of a domestic switching chip node is provided, comprising the following steps:

[0044] S1, traverses and detects all domestic switching chips in the network;

[0045] S2, traverse and detect all ports 0 to 17 of the switch chip;

[0046] S3, if the PORT_OK field bit of the RIO Port Error and Status CSR (address 0x158+0x20*portnum) is 2, the port is valid, otherwise the port is invalid and jumps to S2 to detect the next port;

[0047] S4, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip local port Lane{0..47}Control Register register (address 0x FF8000+0x100*lanenum) value to 0x28E000A;

[0048] S5, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip opposite port Lane{0..47}Control Register register (address 0x FF8000+0x100*lanenum) value to 0x28E000A;

[0049] S6, read the values ​​of Lane{0..47}PRBS Error CounterRegister registers (address 0xFF8008+0x100*lanenum) of the local and peer switching chips through I2C read operations;

[0050] S7, store and analyze the data to determine the port quality. If the PRBS_ERR bit field result is 0, the signal quality is good. If the PRBS_ERR bit field result is 1, the signal quality is poor. The larger the PRBS_ERR_CNT bit field value is, the more errors there are and the worse the signal quality is.

[0051] S8, record the data and jump to S2 to detect the next port;

[0052] S9, after detecting the current switch chip, jump to S1 to detect the next switch chip;

[0053] S10, reporting the signal quality results of all switch chip ports.

[0054] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0055] Example 1

[0056] A method for evaluating the quality of high-speed signals of a domestic switching chip uses a pseudo-random binary sequence PRBS generator of an 1800 chip to perform a random sequence bit error rate test on the lanes of the switching chip, specifically comprising the following steps:

[0057] S1, traverses and detects all domestic switching chips in the network;

[0058] S2, traverse and detect all ports 0 to 17 of the switch chip;

[0059] S3, if the RIO Port Error and Status CSR PORT_OK bit field is 2, the port is valid, otherwise the port is invalid and jumps to S2 to detect the next port;

[0060] S4, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip local port Lane{0..47}Control Register register value to 0x28E000A;

[0061] S5, through I2C write operation, according to the mapping relationship between port and LANE, configure the control register value of the opposite port Lane{0..47} of the switch chip to 0x28E000A;

[0062] S6, read the Lane{0..47}PRBS Error CounterRegister register values ​​of the local and peer switching chips through I2C read operations;

[0063] S7, store and analyze the data to determine the port quality. If the PRBS_ERR bit field is 0, the signal quality is good. If the PRBS_ERR bit field is 1, the signal quality is poor. The larger the PRBS_ERR_CNT bit field value is, the more errors there are and the worse the signal quality is.

[0064] S8, record the data and jump to S2 to detect the next port;

[0065] S9, after detecting the current switch chip, jump to S1 to detect the next switch chip;

[0066] S10, reporting the signal quality results of all switch chip ports.

[0067] Example 2

[0068] Based on Example 1, in step S1, the detection network is a SRIO network.

[0069] Example 3

[0070] On the basis of Example 2, the SRIO network includes: 1 SRIO switching board, 1 data processing board and 2 signal processing boards. The data processing board and the signal processing board are interconnected through the SRIO domestic switching chip to jointly build an SRIO network environment.

[0071] Example 4

[0072] On the basis of embodiment 3, a test device is also included, and the test device resides in the master control node of the SRIO switch board.

[0073] Example 5

[0074] A domestic switching chip high-speed signal quality assessment device comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is loaded by the processor, the method described in any one of Embodiments 1 to 5 is executed.

[0075] Example 6

[0076] A computer-readable storage medium stores a computer program, and when the computer program is loaded by a processor, the method described in any one of Embodiments 1 to 4 is executed.

[0077] Example 7

[0078] A domestic switching chip high-speed signal quality assessment system includes the domestic switching chip high-speed signal quality assessment device as described in Example 5.

[0079] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0080] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.

[0081] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

Claims

1. A method for evaluating the quality of high-speed signals of a domestic switching chip, characterized in that: Using the pseudo-random binary sequence PRBS generator of the 1800 chip, the random sequence bit error rate test is performed on the lane of the switching chip, which specifically includes the following steps: S1, traverses and detects all domestic switching chips in the network; S2, traverse and detect all ports 0 to 17 of the switch chip; S3, if the RIO Port Error and Status CSR PORT_OK bit field is 2, the port is valid, otherwise the port is invalid and jumps to S2 to detect the next port; S4, through I2C write operation, according to the mapping relationship between port and LANE, configure the switch chip local port Lane{0..47}Control Register register value to 0x28E000A; S5, through I2C write operation, according to the mapping relationship between port and LANE, configure the control register value of Lane{0..47} of the opposite port of the switch chip to 0x28E000A; S6, read the Lane{0..47}PRBS Error CounterRegister register values ​​of the local and peer switching chips through I2C read operations; S7, store and analyze the data to determine the port quality. If the PRBS_ERR bit field is 0, the signal quality is good. If the PRBS_ERR bit field is 1, the signal quality is poor. The larger the PRBS_ERR_CNT bit field value is, the more errors there are and the worse the signal quality is. S8, record the data and jump to S2 to detect the next port; S9, after detecting the current switch chip, jump to S1 to detect the next switch chip; S10, reporting the signal quality results of all switch chip ports.

2. The method for evaluating the quality of high-speed signals of domestic switching chips according to claim 1 is characterized in that: In step S1, the detection network is a SRIO network.

3. The method for evaluating the quality of high-speed signals of domestic switching chips according to claim 2 is characterized in that: The SRIO network includes: 1 SRIO switching board, 1 data processing board and 2 signal processing boards. The data processing board and the signal processing board are interconnected through SRIO domestic switching chips to jointly build an SRIO network environment.

4. The method for evaluating the quality of high-speed signals of domestic switching chips according to claim 3 is characterized in that: The system also includes a testing device, which resides in a master control node of the SRIO switch board.

5. A domestic switching chip high-speed signal quality assessment device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 1 to 5 is executed.

6. A computer-readable storage medium, characterized in that: A computer program is stored in a readable storage medium, and when the computer program is loaded by a processor, the method according to any one of claims 1 to 4 is executed.

7. A domestic switching chip high-speed signal quality evaluation system, characterized in that: It includes the domestic switching chip high-speed signal quality evaluation device as described in claim 5.

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