Semiconductor structure and manufacturing method thereof
By introducing a bit line structure with a double air gap spacer into the semiconductor structure, the problems of increasing parasitic capacitance and leakage in DRAM are solved, and the effect of improving operating speed and process yield is achieved.
Patent Information
- Application Number
- CN202311694713.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-16
- Filing Date
- 2023-12-11
- Publication Date
- 2025-03-18
AI Technical Summary
As the semiconductor structure size decreases, the parasitic capacitance between conductive structures in DRAM increases, resulting in a decrease in the operating speed of DRAM and serious leakage problems, affecting the process yield.
Using a bit line structure with a double air gap spacer, a first air gap and a second air gap are formed by depositing a first oxide layer and a spacer of a multi-layer structure on the bit line structure, thereby reducing parasitic capacitance.
It effectively reduces the parasitic capacitance between the bit line structure and the unit contacts, improves the operating speed of the semiconductor structure, reduces the leakage rate, and improves the process yield.
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Figure CN119653772A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor structure and a method for manufacturing the same. More specifically, the present disclosure relates to a semiconductor structure including a bit line structure with a double air gap spacer and a method for manufacturing the same. Background Art
[0002] As electronic devices become lighter and thinner, semiconductor devices such as dynamic random access memory (DRAM) are becoming more highly integrated. Furthermore, by shortening the spacing between semiconductor structures in DRAM, the performance of DRAM can be improved. As the size of semiconductor structures decreases, in addition to increasing the difficulty of the manufacturing process, the components in the semiconductor structures are also prone to leakage due to being too close.
[0003] Therefore, in the semiconductor manufacturing process, how to reduce leakage to improve the process yield of the semiconductor structure becomes an important issue. Summary of the invention
[0004] The embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps. A substrate is provided, and the substrate includes a plurality of active regions and a plurality of isolation regions located between the active regions. A plurality of bit line structures are formed on the top surface of the substrate. A first oxide layer is deposited on the bit line structure. A spacer structure is deposited on the first oxide layer, and the spacer structure is a multilayer structure and includes a second oxide layer. The first oxide layer and the second oxide layer are removed to form a first air gap and a second air gap. A plurality of contact pads are formed above the bit line structure, the first air gap, and the second air gap.
[0005] In some embodiments, the material of the first oxide layer is the same as the material of the second oxide layer.
[0006] In some embodiments, the first oxide layer and the second oxide layer are removed simultaneously.
[0007] In some embodiments, depositing a spacer structure on the first oxide layer includes the following steps: forming a first nitride layer on the first oxide layer, forming a second oxide layer on the first nitride layer, and forming a second nitride layer on the second oxide layer.
[0008] In some embodiments, the method further includes the following steps: depositing a first barrier layer on the substrate, and the first barrier layer covers the active region and the isolation region. After forming the first barrier layer, forming a plurality of first openings of the first barrier layer, and the first openings extend through the substrate and expose a portion of the active region. Forming a plurality of bit line contacts in the first openings, and the bit line contacts are electrically connected to the active region.
[0009] In some embodiments, removing the first oxide layer and the second oxide layer comprises the following steps: After depositing the spacer structure, removing the first oxide layer and the spacer structure in a horizontal direction.
[0010] In some embodiments, after removing the first oxide layer and the second oxide layer, a spacer is formed, and the spacer includes a first air gap, a first nitride layer, a second air gap, and a second nitride layer arranged in sequence from the bit line structure outward.
[0011] In some embodiments, the first air gap includes a first gap formed along a vertical direction between the bit line structure and a vertical portion of the first nitride layer, and a second gap formed along a horizontal direction between a horizontal portion of the first nitride layer and a top surface of the first barrier layer.
[0012] In some embodiments, the second air gap includes a third gap and a fourth gap. The third gap is formed between the vertical portion of the first nitride layer and the second nitride layer along a vertical direction, and the fourth gap is formed between the top surface of the horizontal portion of the first nitride layer and the bottom surface of the second nitride layer along a horizontal direction.
[0013] In some embodiments, forming the contact pad includes the following steps: depositing a fourth conductive layer on the first barrier layer, and the fourth conductive layer covers the bit line structure; removing a portion of the fourth conductive layer to form a plurality of third openings.
[0014] In some embodiments, the method further comprises the following steps: forming a sealing layer on the contact pad, the first air gap and the second air gap layer, and the sealing layer fills the third opening.
[0015] In some embodiments, after forming the sealing layer, the first air gap has a fourth height in the vertical direction, and the second air gap has a fifth height in the vertical direction. The fourth height is measured from the surface of the sealing layer abutting the first air gap to the top surface of the first barrier layer, and the fifth height is measured from the surface of the sealing layer abutting the second air gap to the top surface of the horizontal portion of the first nitride layer. And, the fourth height is greater than the fifth height.
[0016] The embodiments disclosed herein also provide a semiconductor structure. The semiconductor structure includes a substrate, a first barrier layer, a plurality of bit line structures, a spacer, and a plurality of contact pads. The substrate includes a plurality of active regions and a plurality of isolation regions between the active regions. The first barrier layer is disposed on the substrate. The bit line structure is disposed on the first barrier layer and protrudes from the substrate. The spacer is disposed around the sidewall of the bit line structure, and the spacer includes a first air gap, a first nitride layer, a second air gap, and a second nitride layer arranged in sequence outward from the bit line structure. The contact pad is disposed above the bit line structure including the spacer.
[0017] In some embodiments, the first air gap includes a first gap and a second gap. The first gap is disposed between a vertical portion of the first nitride layer and the bit line structure along a vertical direction, and the second gap is disposed between a horizontal portion of the first nitride layer and the first barrier layer along a horizontal direction.
[0018] In some embodiments, the first gap has a first distance, and the second gap has a second distance, and the first distance is related to the second distance.
[0019] In some embodiments, the second air gap includes a third gap and a fourth gap, wherein the third gap is disposed between the vertical portion of the first nitride layer and the vertical portion of the second nitride layer along a vertical direction, and the fourth gap is disposed between the second nitride layer and the top surface of the horizontal portion of the first nitride layer along a horizontal direction.
[0020] In some embodiments, the third gap has a third distance, and the fourth gap has a fourth distance, and the third distance is related to the fourth distance.
[0021] In some embodiments, the bit line structure includes a bottom cover layer disposed above the substrate, a conductive layer disposed on the bottom cover layer, and a top cover layer disposed on the conductive layer.
[0022] In some embodiments, the bottom cover layer has a first height, the conductive layer has a second height, and the top cover layer has a third height. The third height is greater than the second height, and the second height is greater than the first height.
[0023] In some embodiments, the semiconductor structure further includes a sealing layer disposed on the contact pad and the spacer. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The following embodiments are read in conjunction with the accompanying drawings to clearly understand the concepts of the present disclosure. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion.
[0025] Figures 1 to 7 is a diagram of a method of manufacturing a semiconductor structure during forming a first air gap and a second air gap according to some embodiments of the present disclosure;
[0026] Figures 8 to 12 is a diagram of a method of manufacturing a semiconductor structure during formation of a plurality of cell contacts according to some embodiments of the present disclosure;
[0027] Figures 13 to 16 is a diagram of a method of manufacturing a semiconductor structure during forming a plurality of contact pads according to some embodiments of the present disclosure;
[0028] Fig.17is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure; and
[0029] Fig.18 FIG. 1 is a comparison diagram of parasitic capacitance between a single air-gap semiconductor structure and a double air-gap semiconductor structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0030] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0031] Additionally, for ease of description, spatially relative terms such as "on," "above," "below," and "between" may be used in the present disclosure to describe the relationship of one element or feature to another element as shown in the drawings) or function. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in the present disclosure should be interpreted accordingly.
[0032] The terms "including", "having", "comprising" and the like used in this disclosure are open terms, meaning including but not limited to.
[0033] As DRAM technology nodes continue to expand, the conductive structures in DRAM elements become increasingly dense, thereby increasing the parasitic capacitance between conductive structures (e.g., between a bit line structure and a cell contact), which reduces the operating speed of the DRAM device. In order to solve the problem of parasitic capacitance, the present disclosure provides a semiconductor structure and a method for manufacturing the same, which introduces a bit line structure with a double-air-gap spacer into a DRAM, thereby minimizing the problem of reducing the operating speed of the DRAM due to parasitic capacitance.
[0034] It should be noted that when the following drawings (such as Figures 1 to 16 ) is described and illustrated as a series of operations or steps, the order in which these operations or steps are described should not be limited. For example, some operations or steps may be performed in a different order than in the present disclosure, or some operations or steps may occur simultaneously, or some operations may not be performed, and / or some operations or steps may be repeated. In addition, the actual operations or steps of the process stage may need to be performed before the semiconductor structure (e.g., Fig.14Additional operations or steps are performed before, during, or after the semiconductor structure 100 in the embodiment to complete the semiconductor structure 100. Therefore, the present disclosure may briefly describe some of these additional operations or steps. In addition, unless otherwise specified, for the following figures (e.g. Figures 1 to 16 )The same explanations discussed above can be directly applied to the other figures.
[0035] See also Figures 1 to 7 . Figures 1 to 7 is a diagram of a method of manufacturing a semiconductor structure during the formation of a first air gap 152A and a second air gap 156A according to some embodiments of the present disclosure, wherein Figure 1 is a top view of a semiconductor structure having a plurality of active regions 110 (or active regions AA) and a plurality of isolation regions 120 according to some embodiments of the present disclosure, wherein Figure 1 In the semiconductor structure 100, a plurality of word line structures WL are also included; Figures 2 to 6 According to some embodiments of the present disclosure, Figure 1 A cross-sectional view taken along the NN′ cross-sectional line at one stage of forming the first air gap 152A and the second air gap 156A.
[0036] like Figure 2 As shown, a substrate 102 is provided. The substrate 102 includes an active region 110 and an isolation region 120, and each isolation region 120 is disposed between the active regions 110. In some embodiments, the substrate 102 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 102 may include an elemental semiconductor, such as germanium. In some embodiments, the substrate 102 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium indium phosphide, or other suitable materials. In some embodiments, the substrate 102 may include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, in some embodiments, optionally, the substrate 102 may have a semiconductor-on-insulator (SOI) structure.
[0037] Next, after the active region 110 and the isolation region 120 are formed, a first barrier layer 130 is formed on the top surface of the substrate 102 to cover the active region 110 and the isolation region 120. Further, a patterning process is performed on the first barrier layer 130 to form a plurality of first openings OP1 in the first barrier layer 130. In addition, each first opening OP1 exposes a portion of each active region 110. It is worth mentioning that Figure 2 The number of the first opening OP1 shown is one, but the present disclosure is not limited thereto.
[0038] Then, if Figure 3As shown, a plurality of bit line structures 140 (or bit line structures BL) are formed above the substrate 102. After forming a first opening OP1 in the first barrier layer 130, a first conductive material is filled in each first opening OP1 to form a bit line contact BC. The bit line contact BC contacts the portion of each active region 110, and the bit line contact BC is electrically connected to each active region 110, especially the source region (not shown). In particular, Figure 3 The number of the bit line contact BC shown is 1, but the present disclosure is not limited thereto.
[0039] Subsequently, a bit line structure 140 is formed on the first barrier layer 130, and the bit line structure 140 protrudes from the substrate 102, for example, along the Z direction, as shown in FIG. Figure 3 In some embodiments, the bit line structure 140 is spaced apart from another bit line structure 140 at substantially equal intervals above the substrate 102. Each bit line structure 140 can be divided into three parts along a direction substantially perpendicular to the substrate 102 (e.g., the Z direction), one part is a bottom cover layer 142 disposed close to the substrate 102, another part is a conductive layer 144 disposed on the bottom cover layer 142, and another part is a top cover layer 146 disposed on the conductive layer 144. Figure 3 The number of the bit line structures 140 shown is three, but the present disclosure is not limited thereto.
[0040] The following is a method for forming the bottom capping layer 142, the conductive layer 144, and the top capping layer 146. A first insulating material is deposited on the first barrier layer 130, a second conductive material is deposited on the first insulating material, and then the second insulating material is deposited on the second conductive material. Then, in some embodiments, the first insulating material, the second conductive material, and the second insulating material can be etched substantially simultaneously to form the bottom capping layer 142, the conductive layer 144, and the top capping layer 146 simultaneously. Therefore, each bit line structure 140 (including the bottom capping layer 142, the conductive layer 144, and the top capping layer 146) can be etched in a first direction (e.g., Figure 4 In the X direction of the diagram, the Figure 4 In some embodiments, the bottom cover layer 142, the conductive layer 144, and the top cover layer 146 may be etched non-simultaneously. In such embodiments, the second insulating material is first etched into a desired pattern, and then the second conductive material and the first insulating material are etched using the patterned second insulating material as an etching mask for the conductive material and the first insulating material to form the conductive layer 144 and the bottom cover layer 142, respectively.
[0041] In some embodiments, the first insulating material and the second insulating material are the same material or different materials. In some embodiments, the first insulating material includes a dielectric material, such as silicon nitride, but the disclosure is not limited thereto. In some embodiments, the second insulating material includes a dielectric material, such as silicon nitride, but the disclosure is not limited thereto.
[0042] In some embodiments, the second conductive material of the conductive layer 144 may be at least one of a doped semiconductor, a metal, a conductive metal nitride, and a metal silicide. In some embodiments, the conductive layer 144 may have a stacked structure. For example, the second conductive material may be a stacked structure consisting of doped polysilicon and a metal nitride or a metal (e.g., tungsten, tungsten nitride, and / or titanium nitride). In addition, the conductive layer 144 may be electrically connected to the bit line contact BC.
[0043] It is worth noting that the bottom cover layer 142, the conductive layer 144, and the top cover layer 146 are collectively referred to as the bit line structure 140. In some embodiments, the bottom cover layer 142 has a first height H1, which is the vertical height of the bottom cover layer 142 along the Z direction. The conductive layer 144 has a second height H2, which is the vertical height of the conductive layer 144 along the Z direction. Similarly, the top cover layer 146 has a third height H3, which is the vertical height of the top cover layer 146 along the Z direction. In some embodiments, the third height H3 is greater than the second height H2, and the second height H2 is greater than the first height H1.
[0044] Next, see Figure 4 , a first oxide layer 152 is deposited on each bit line structure 140 and the first barrier layer 130. Specifically, the first oxide layer 152 is deposited along the sidewall of each bit line structure 140. In some embodiments, the material of the first oxide layer 152 includes an oxide, such as silicon oxide or other suitable oxides, and the present disclosure is not limited thereto. In addition, the first oxide layer 152 deposited on the sidewall of each bit line structure 140 has a first thickness TH1, that is, the first oxide layer 152 in the Z direction has the first thickness TH1. The first oxide layer 152 on the top surface of the bit line structure 140 and the top surface of the first barrier layer 130 has a second thickness TH2, that is, the first oxide layer 152 in the horizontal direction (such as the X direction and the Y direction) has a second thickness TH2. It can be understood that in some embodiments, the first thickness TH1 is associated with the second thickness TH2, for example, the first thickness TH1 is equal to the second thickness TH2.
[0045] The first oxide layer 152 may serve as a sacrificial layer and be transformed into an air gap in a subsequent process.
[0046] For further information, see Figure 5. A spacer structure 150 is formed on the first oxide layer 152 and above each bit line structure 140. Specifically, the spacer structure 150 surrounds the sidewalls and top surface of each bit line structure 140. The spacer structure 150 is a multi-layer structure, and the spacer structure 150 includes a first nitride layer 154, a second oxide layer 156, and a second nitride layer 158 formed on the first oxide layer 152 and arranged in sequence from each bit line structure 140 (particularly from the first oxide layer 152) outward. In some embodiments, the materials of the first nitride layer 154 and the second nitride layer 158 are the same or different. In some embodiments, the material of the first nitride layer 154 includes silicon nitride. In some embodiments, the material of the second nitride layer 158 includes silicon nitride. In some embodiments, the material of the second oxide layer 156 includes oxide, such as silicon oxide or other suitable oxides, and the present disclosure is not limited thereto.
[0047] In addition, the second oxide layer 156 on the sidewall of each bit line structure 140 has a third thickness TH3, that is, the second oxide layer 156 in the Z direction has a third thickness TH3. The second oxide layer 156 on the top surface of the bit line structure 140 and the first barrier layer 130 has a fourth thickness TH4, that is, the second oxide layer 156 has a fourth thickness TH4 in the horizontal direction (e.g., the X direction and the Y direction). It can be understood that in some embodiments, the third thickness TH3 is associated with the fourth thickness TH4, for example, the third thickness TH3 is equal to the fourth thickness TH4. It is worth mentioning that the first thickness TH1 is the same as or different from the third thickness TH3, and the second thickness TH2 is the same as or different from the fourth thickness TH4. In addition, the second oxide layer 156 located between the first nitride layer 154 and the second nitride layer 158 is a sacrificial layer, which is transformed into another air gap in the subsequent process, and will be described later.
[0048] In some embodiments, the spacer structure 150 having the first nitride layer 154, the second oxide layer 156, and the second nitride layer 158 may be formed by a suitable deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable deposition processes, or any combination thereof.
[0049] Next, see Figure 6, the first oxide layer 152 and the spacer structure 150 in the horizontal direction (e.g., the X direction and the Y direction) are removed. More specifically, the first oxide layer 152 and the spacer structure 150 on the top surface of each bit line structure 140 and the top surface of the first barrier layer 130 are removed in the same removal process. In some embodiments, the removal process is performed by any suitable etching process (e.g., a reactive ion etching (RIE) process). Alternatively, in some embodiments, the removal process is performed by a planarization process (e.g., a chemical mechanical planarization (CMP) process).
[0050] Then, see Figure 7 , a first air gap 152A and a second air gap 156A are formed by an etching process. The first oxide layer 152 and the second oxide layer 156 are removed in the same etching process. Therefore, the first oxide layer 152 and the second oxide layer 156 have etching selectivity relative to the first nitride layer 154 and the second nitride layer 158. In other words, in the same etching process, the etching rate of the first oxide layer 152 and the second oxide layer 156 is faster than the etching rate of the first nitride layer 154 and the second nitride layer 158. Therefore, a first air gap 152A is formed between each bit line structure 140 and the first nitride layer 154, and a second air gap 156A is formed between the first nitride layer 154 and the second nitride layer 158. It is worth mentioning that the first air gap 152A, the first nitride layer 154, the second air gap 156A and the second nitride layer 158 are collectively referred to as a "double air gap spacer 150A". In some embodiments, the etching process for forming the first air gap 152A and the second air gap 156A is a dry etching process, such as a vapor phase etching process.
[0051] like Figure 7 As shown, for convenience of explanation, the first nitride layer 154 includes a vertical portion 154A of the first nitride layer 154 and a horizontal portion 154B of the first nitride layer 154. After forming the first air gap 152A and the second air gap 156A, the first air gap 152A includes a first gap SP1 and a second gap SP2. Further, the first gap SP1 is disposed between each bit line structure 140 and the vertical portion 154A of the first nitride layer 154, and each bit line structure 140 has a first distance d1 from the vertical portion 154A of the first nitride layer 154. The second gap SP2 is disposed between the bottom surface of the horizontal portion 154B of the first nitride layer 154 and the top surface of the first barrier layer 130, and has a second distance d2 from the bottom surface of the horizontal portion 154B of the first nitride layer 154 to the bottom surface of the first barrier layer 130.
[0052] The second air gap 156A includes a third gap SP3 and a fourth gap SP4. Further, the third gap SP3 is disposed between the vertical portion 154A of the first nitride layer 154 and the second nitride layer 158, and a third distance d3 is provided between the vertical portion 154A of the first nitride layer 154 and the second nitride layer 158. The second gap SP2 is disposed between the second nitride layer 158 and the top surface of the horizontal portion 154B of the first nitride layer 154, and a fourth distance d4 is provided between the second nitride layer 158 and the top surface of the horizontal portion 154B of the first nitride layer 154.
[0053] In some embodiments, the first distance d1 is associated with the second distance d2, for example, the first distance d1 is equal to the second distance d2. In some embodiments, the third distance d3 is associated with the fourth distance d4, for example, the third distance d3 is equal to the fourth distance d4. It is understood that in some embodiments, the first distance d1 is associated with the first thickness TH1, and the third distance d3 is associated with the third thickness TH3. In addition, the second distance d2 is associated with the second thickness TH2, and the fourth distance d4 is associated with the fourth thickness TH4.
[0054] For further information, see Figures 8 to 11 . Figures 8 to 11 is a diagram of a method of manufacturing a semiconductor structure during formation of a plurality of cell contacts CC according to some embodiments of the present disclosure, wherein Figure 8 is a top view of a semiconductor structure 100 having a cell contact CC according to some embodiments; Figures 9 to 11 According to some embodiments of the present disclosure, Figure 8 The NN' section line is a cross-sectional view at one of the stages during the formation of the cell contact CC.
[0055] See also Fig. 9 After forming the first air gap 152A and the second air gap 156A, a plurality of second openings OP2 are formed between adjacent bit line structures 140. It is worth noting that the depth of the second openings OP2 is sufficient to expose a portion of each active region 110. The second openings OP2 are formed by an etching process, such as a dry etching process, but the present disclosure is not limited thereto. It is worth noting that Fig. 9 The number of the second openings OP2 shown is 2, but the present disclosure is not limited thereto.
[0056] Next, see Fig.10After forming the second opening OP2, a conductive material layer 160 is deposited in the second opening OP2, and the conductive material layer 160 covers each bit line structure 140. In some embodiments, the conductive material layer 160 includes silicon, for example, the material of the conductive material layer 160 includes doped polysilicon. In some embodiments, the material of the conductive material layer 160 may include a semiconductor material, a doped semiconductor material, a metal, a metal nitride, a metal silicide, other appropriate conductive materials, or any combination thereof.
[0057] Then, see Figure 8 and Fig.11 . A plurality of cell contacts CC are formed in the second opening OP2. In more detail, a portion of the conductive material layer 160 is removed to expose an upper portion of the dual air gap spacer 150A and an upper portion of each bit line structure 140. In some embodiments, the portion of the conductive material layer 160 is removed by an etch-back process (e.g., a dry etch-back process) to form cell contacts CC between adjacent bit line structures 140. Specifically, each cell contact CC is formed at an opposite position of the conductive layer 144 of the bit line structure 140. In some embodiments, an etching process (e.g., an RIE process) is performed during the removal of a portion of the conductive material layer 160 to form the cell contacts CC. In addition, although Fig.11 The number of the unit contacts CC shown is 2, but the present disclosure is not limited thereto.
[0058] Next, see Fig.12 . A second barrier layer 162 is formed on each bit line structure 140. In more detail, the second barrier layer 162 is formed on the top surface of each cell contact CC, and the second barrier layer 162 surrounds the upper portion of the double air gap spacer 150A. In some embodiments, the material of the second barrier layer 162 may include a metal (e.g., titanium or tantalum, etc.), a metal nitride (e.g., titanium nitride or tantalum nitride, etc.), or a combination thereof. In some embodiments, the second barrier layer 162 may include titanium nitride.
[0059] For further information, see Figures 13 to 16 is a diagram of a method for manufacturing a semiconductor structure 100 during the formation of a plurality of contact pads LP according to some embodiments of the present disclosure, wherein Fig.13 is a top view of a semiconductor structure 100 having a contact pad LP according to some embodiments; Figures 14 to 16 According to some embodiments of the present disclosure Fig.13 The cross-sectional view taken along the NN' section line is a cross-sectional view of a stage during the formation of the contact pad LP.
[0060] See also Fig.14The fourth conductive material layer 170 is formed on the second barrier layer 162, and the fourth conductive material layer 170 covers each bit line structure 140 and the cell contact CC. In some embodiments, the fourth conductive material layer 170 may include a conductive material, such as tungsten, copper, aluminum, alloy, or other suitable conductive materials. In some embodiments, the fourth conductive material layer 170 may be formed by blanket deposition.
[0061] Next, see Fig.15 , a plurality of contact pads LP and a plurality of third openings OP3 are formed on each bit line structure 140 and on the sides, respectively. More specifically, a portion of the fourth conductive material layer 170 is removed to form a plurality of contact pads LP and a plurality of third openings OP3. In some embodiments, the portion of the fourth conductive material layer 170 is removed by an etching process. Contact pads LP are formed between adjacent bit line structures 140 and on adjacent bit line structures 140. In addition, a third opening OP3 is formed adjacent to each contact pad LP. Furthermore, a portion of the second barrier layer 162 and a portion of the dual air gap spacer 150A are removed during the etching process. In some embodiments, after the third opening OP3 is formed, the first nitride layer 154 of the dual air gap spacer 150A has a fourth height H4, and the second nitride layer 158 of the dual air gap spacer 150A has a fifth height H5. In some embodiments, the fourth height H4 is greater than the fifth height H5. In addition, due to the presence of the second barrier layer 162, the material diffusion of the contact pad LP can be reduced. In addition, in Fig.15 The number of the third openings OP3 shown in the figure is 3, and the number of the contact pads LP shown in the figure is 3, but the present disclosure is not limited thereto.
[0062] For further information, see Fig.16 . The sealing layer 180 will fill the third opening OP3 and be formed on each contact pad LP. Specifically, the sealing layer 180 will contact the contact pad LP, a portion of the second barrier layer 162, and a portion of the double air gap spacer 150A. The sealing layer 180 can be formed by CVD, ALD, PVD, other appropriate deposition techniques, or a combination thereof. In some embodiments, the sealing layer 180 is formed by ALD to avoid forming voids. The sealing layer 180 may include any suitable dielectric material, such as silicon oxide or silicon nitride.
[0063] like Fig.16As shown, after forming the sealing layer 180, the first air gap 152A has a fourth height H4 in the vertical direction (e.g., Z direction), and the second air gap 156A has a fifth height H5 in the vertical direction (e.g., Z direction). Further, the fourth height H4 is measured from the surface of the sealing layer 180 abutting against the first air gap 152A to the top surface of the first barrier layer 130, and the fifth height H5 is measured from the surface of the sealing layer 180 abutting against the second air gap 156A to the top surface of the horizontal portion 154B of the first nitride layer 154. And, the fourth height H4 is greater than the fifth height H5.
[0064] By using the method for manufacturing the semiconductor structure 100 provided in the embodiment of the present disclosure, a semiconductor structure 100 including a bit line structure 140 having a double air gap spacer 150A can be obtained. The dielectric constant of air is approximately 1, therefore, the method for manufacturing the semiconductor structure 100 provided in the present disclosure that introduces the double air gap spacer 150A can reduce the parasitic capacitance between the conductive layer 144 and the cell contact CC, thereby improving the performance of the semiconductor structure 100. In addition, since the first oxide layer 152 and the second oxide layer 156 are removed in the same step, the method for manufacturing the semiconductor structure 100 disclosed in the present disclosure is quite efficient.
[0065] In addition, the semiconductor structure 100 with the spacer 150A having a double air gap has some technical features. Fig.17 , Fig.17 is a schematic diagram of a semiconductor structure 100 according to some embodiments of the present disclosure.
[0066] like Fig.17 As shown, the present disclosure provides a semiconductor structure 100. The semiconductor structure 100 includes a substrate 102, a bit line structure 140, and a spacer 150A. The bit line structure 140 is disposed on the substrate 102 and protrudes from the substrate 102. The spacer 150A is disposed around the sidewall of each bit line structure 140. In addition, the spacer 150A is a double air gap spacer 150A, and the spacer 150A includes a first air gap 152A, a first nitride layer 154, a second air gap 156A, and a second nitride layer 158 sequentially disposed outward from each bit line structure 140. The first nitride layer 154 includes a vertical portion 154A and a horizontal portion 154B. It is worth mentioning that the dielectric constant of air is approximately 1. Therefore, the semiconductor structure 100 using the bit line structure 140 with the first air gap 152A and the second air gap 156A can minimize the parasitic capacitance between the bit line structure 140 and the cell contact CC.
[0067] In addition, the substrate 102 includes a plurality of active regions 110 and isolation regions 120 disposed between the active regions 110. The semiconductor structure 100 includes a first barrier layer 130 on the substrate 102, and the first barrier layer 130 covers a portion of the active regions 110 and the isolation regions 120. In addition, the semiconductor structure 100 includes a bit line contact BC disposed in the first barrier layer 130. The bit line contact BC is disposed under each bit line structure 140 and passes through the first barrier layer 130 to contact the active region 110, so that the bit line contact BC is electrically connected to the active region 110.
[0068] In addition, each bit line structure 140 includes a bottom cover layer 142, a conductive layer 144, and a top cover layer 146. The bottom cover layer 142 is disposed on the first barrier layer 130 and contacts the bit line contact BC. The conductive layer 144 is disposed on the bottom cover layer 142. The top cover layer 146 is disposed on the conductive layer 144. In addition, the materials of the bottom cover layer 142 and the top cover layer 146 are insulating materials, and the insulating materials of the bottom cover layer 142 and the top cover layer 146 may be the same or different. In some embodiments, the insulating material includes a dielectric material, such as silicon nitride, but the present disclosure is not limited thereto. In some embodiments, the material of the conductive layer 144 may be at least one of a doped semiconductor, a metal, a conductive metal nitride, and a metal silicide. In some embodiments, the conductive layer 144 may have a stacked structure, for example, the material of the conductive layer 144 may be a stacked structure composed of doped polysilicon and a metal nitride or a metal (such as tungsten, tungsten nitride, and / or titanium nitride). The conductive layer 144 may be electrically connected to the bit line contact BC.
[0069] Further, the first air gap 152A of the dual air gap spacer 150A includes a first gap SP1 and a second gap SP2. Specifically, the first gap SP1 is disposed between the vertical portion 154A of the first nitride layer 154 and the bit line structure 140, and a first distance d1 is provided between the vertical portion 154A of the first nitride layer 154 and the bit line structure 140. The second gap SP2 is disposed between the horizontal portion 154B of the first nitride layer 154 and the first barrier layer 130, and a second distance d2 is provided between the horizontal portion 154B of the first nitride layer 154 and the first barrier layer 130. In addition, the first distance d1 is a horizontal distance (e.g., in the X direction and the Y direction), and the second distance d2 is a vertical distance (e.g., in the Z direction). The first distance d1 is associated with the second distance d2, and for example, the first distance d1 is equal to the second distance d2. The second air gap 156A of the dual air gap spacer 150A includes a third gap SP3 and a fourth gap SP4. The third gap SP3 is disposed between the vertical portion 154A of the first nitride layer 154 and the second nitride layer 158, and a third distance d3 is formed between the vertical portion 154A of the first nitride layer 154 and the second nitride layer 158. The fourth gap SP4 is disposed between the second nitride layer 158 and the horizontal portion 154B of the first nitride layer 154, and a fourth distance d4 is formed between the second nitride layer 158 and the horizontal portion 154B of the first nitride layer 154. The third distance d3 is associated with the fourth distance d4, for example, the third distance d3 is equal to the fourth distance d4. In addition, the third distance d3 is a horizontal distance (for example, in the X direction and the Y direction), and the fourth distance d4 is a vertical distance (for example, in the Z direction).
[0070] Next, the semiconductor structure 100 includes a cell contact CC disposed between adjacent bit line structures 140. The cell contact CC is disposed on opposite sides of the conductive layer 144 of each bit line structure 140, and the cell contact CC passes through the first barrier layer 130 and the substrate 102 to be electrically connected to the active region 110. In addition, the upper sidewall of the cell contact CC contacts the side surface SF of the second nitride layer 158. More specifically, the upper sidewall of the cell contact CC contacts the lower portion of the side surface SF of the second nitride layer 158.
[0071] In addition, the semiconductor structure 100 includes a second barrier layer 162 covering an upper portion of the bit line structure 140. Also, the second barrier layer 162 is disposed on a top surface of the cell contact CC. More specifically, the second barrier layer 162 is disposed around the double air gap spacer 150A.
[0072] In addition, the semiconductor structure 100 includes a plurality of contact pads LP, and the contact pads LP are located between and above each bit line structure 140. Furthermore, the contact pads LP are disposed on the second barrier layer 162. Due to the presence of the second barrier layer 162, material diffusion of the contact pads LP can be reduced. In some embodiments, each contact pad LP surrounds a portion of the upper portion of each bit line structure 140 using a double air gap spacer 150A.
[0073] In addition, the semiconductor structure 100 includes a sealing layer 180 disposed on the contact pad LP. More specifically, the sealing layer 180 is disposed on the contact pad LP, the second barrier layer 162, and the dual air gap spacer 150A. In addition, the material of the sealing layer 180 may include any appropriate dielectric material, such as silicon oxide or silicon nitride. After the sealing layer 180 is formed, the first air gap 152A has a fourth height H4 in the vertical direction (e.g., the Z direction), and the second air gap 156A has a fifth height H5 in the vertical direction (e.g., the Z direction). Further, the fourth height H4 is measured from the surface of the sealing layer 180 abutting against the first air gap 152A to the top surface of the first barrier layer 130, and the fifth height H5 is measured from the surface of the sealing layer 180 abutting against the second air gap 156A to the top surface of the horizontal portion 154B of the first nitride layer 154. In addition, the fourth height H4 is greater than the fifth height H5.
[0074] For further information, see Fig.18 , Fig.18 The parasitic capacitance comparison diagram of the semiconductor structure with a single air gap and the semiconductor structure with a double air gap in some embodiments of the present disclosure is shown. Fig.18 As shown, compared with the semiconductor structure with a single air gap, the parasitic capacitance between the bit line structure 140 and the cell contact CC of the semiconductor structure 100 with the double air gap spacer 150A is reduced by about 13.6%. Therefore, the semiconductor structure 100 with the double air gap spacer 150A can minimize the parasitic capacitance between the bit line structure 140 and the cell contact CC. In this way, the operating speed of the semiconductor structure 100 can be improved.
[0075] Although some embodiments of the present disclosure have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0076] The above briefly describes the features of multiple embodiments of the present disclosure, so that those skilled in the art can more easily understand the present disclosure. Any person skilled in the art should understand that the present disclosure can easily serve as a basis for the change or design of other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments of the present disclosure. Any person skilled in the art can also understand that the structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.
[0077]
Explanation of symbols
[0078] 100:Semiconductor structure
[0079] 102:Substrate
[0080] 110,AA: Active Zone
[0081] 120: Isolation Area
[0082] 130: first barrier layer
[0083] 140,BL: Bit Line Structure
[0084] 142: Bottom covering layer
[0085] 144: Conductive layer
[0086] 146: Top cover
[0087] 150: Spacer structure
[0088] 150A: Spacer
[0089] 152: First oxide layer
[0090] 152A: First air gap
[0091] 154: first nitride layer
[0092] 154A: Vertical section
[0093] 154B: Horizontal part
[0094] 156: Second oxide layer
[0095] 156A: Second air gap
[0096] 158: Second nitride layer
[0097] 160: Conductive material layer
[0098] 162: Second barrier layer
[0099] 170: fourth conductive material layer
[0100] 180: Sealing layer
[0101] BC: Bit Line Contact
[0102] CC: Unit contact
[0103] LP: Contact Pad
[0104] WL: word line structure
[0105] d1: first distance
[0106] d2: second distance
[0107] d3: third distance
[0108] d4: fourth distance
[0109] H1: First Height
[0110] H2: Second Height
[0111] H3: The third height
[0112] H4: The fourth height
[0113] H5: The fifth height
[0114] SP1: First gap
[0115] SP2: Second gap
[0116] SP3: The third gap
[0117] SP4: The fourth gap
[0118] OP1: First opening
[0119] OP2: Second opening
[0120] OP3: The third opening
[0121] TH1: First thickness
[0122] TH2: Second thickness
[0123] TH3:Third thickness
[0124] TH4: Fourth thickness
[0125] NN': Section line
[0126] X,Y,Z: direction.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate comprises a plurality of active regions and a plurality of isolation regions between the active regions; forming a plurality of bit line structures on a top surface of the substrate; depositing a first oxide layer on each of the bit line structures; depositing a spacer structure on the first oxide layer, wherein the spacer structure is a multi-layer structure and includes a second oxide layer; removing the first oxide layer and the second oxide layer to form a first air gap and a second air gap; as well as A plurality of contact pads are formed over the bit line structures, the first air gap, and the second air gap.
2. The method according to claim 1, characterized in that The material of the first oxide layer is the same as that of the second oxide layer.
3. The method according to claim 1, characterized in that The first oxide layer and the second oxide layer are removed simultaneously.
4. The method according to claim 1, characterized in that: Wherein depositing the spacer structure on the first oxide layer comprises: forming a first nitride layer on the first oxide layer; forming the second oxide layer on the first nitride layer; and A second nitride layer is formed on the second oxide layer.
5. The method according to claim 4, characterized in that Further including: Depositing a first barrier layer on the substrate, wherein the first barrier layer covers the active regions and the isolation regions; After forming the first barrier layer, forming a plurality of first openings of the first barrier layer, wherein the first openings extend through the substrate and expose a portion of each of the active regions; as well as A plurality of bit line contacts are formed in the first openings, wherein each of the bit line contacts is electrically connected to each of the active regions.
6. The method according to claim 5, characterized in that The removing of the first oxide layer and the second oxide layer comprises: After depositing the spacer structure, the first oxide layer and the spacer structure in the horizontal direction are removed.
7. The method according to claim 5, characterized in that wherein after removing the first oxide layer and the second oxide layer, forming a spacer; and The spacer includes the first air gap, the first nitride layer, the second air gap and the second nitride layer which are sequentially arranged outward from each of the bit line structures.
8. The method according to claim 7, characterized in that The first air gap includes a first gap and a second gap, wherein the first gap is formed along a vertical direction between each of the bit line structures and a vertical portion of the first nitride layer; and The second gap is formed along a horizontal direction between a horizontal portion of the first nitride layer and a top surface of the first barrier layer.
9. The method according to claim 7, characterized in that: The second air gap includes a third gap and a fourth gap, wherein the third gap is formed along a vertical direction between a vertical portion of the first nitride layer and the second nitride layer; and The fourth gap is formed between a top surface of the horizontal portion of the first nitride layer and a bottom surface of the second nitride layer along a horizontal direction.
10. The method according to claim 5, characterized in that The forming of the contact pads comprises: Depositing a fourth conductive layer on the first barrier layer, wherein the fourth conductive layer covers each of the bit line structures; and A portion of the fourth conductive layer is removed to form a plurality of third openings.
11. The method according to claim 10, characterized in that Further including: A sealing layer is formed on each of the contact pads, the first air gap and the second air gap layer, and the sealing layer fills the third openings.
12. The method according to claim 11, characterized in that After the sealing layer is formed, the first air gap has a fourth height in the vertical direction, and the second air gap has a fifth height in the vertical direction, the fourth height is measured from a surface of the sealing layer against the first air gap to a top surface of the first barrier layer, and the fifth height is measured from a surface of the sealing layer against the second air gap to a top surface of a horizontal portion of the first nitride layer; as well as The fourth height is greater than the fifth height.
13. A semiconductor structure, characterized in that: include: A substrate including a plurality of active regions and a plurality of isolation regions between the active regions; A first barrier layer is disposed on the substrate; A plurality of bit line structures are disposed on the first barrier layer and protrude from the substrate; A spacer is disposed around the sidewall of each bit line structure, wherein the spacer includes a first air gap, a first nitride layer, a second air gap and a second nitride layer arranged in sequence outward from each bit line structure; as well as A plurality of contact pads are disposed above the bit line structures including the spacer.
14. The semiconductor structure according to claim 13, characterized in that: The first air gap includes a first gap and a second gap; and The first gap is disposed between the vertical portion of the first nitride layer and each of the bit line structures along a vertical direction, and the second gap is disposed between the horizontal portion of the first nitride layer and the first barrier layer along a horizontal direction.
15. The semiconductor structure according to claim 14, characterized in that: wherein the first gap has a first distance, and the second gap has a second distance; and The first distance is related to the second distance.
16. The semiconductor structure according to claim 13, characterized in that wherein the second air gap includes a third gap and a fourth gap; and The third gap is disposed between the vertical portion of the first nitride layer and the vertical portion of the second nitride layer along a vertical direction, and the fourth gap is disposed between the second nitride layer and a top surface of the horizontal portion of the first nitride layer along a horizontal direction.
17. The semiconductor structure according to claim 16, characterized in that: wherein the third gap has a third distance, and the fourth gap has a fourth distance; and The third distance is related to the fourth distance.
18. The semiconductor structure according to claim 13, characterized in that Each of the bit line structures includes: A bottom covering layer is disposed above the substrate; a conductive layer disposed on the bottom covering layer; and A top covering layer is disposed on the conductive layer.
19. The semiconductor structure according to claim 18, characterized in that wherein the bottom cover layer has a first height, the conductive layer has a second height, and the top cover layer has a third height; and The third height is greater than the second height, and the second height is greater than the first height.
20. The semiconductor structure according to claim 13, characterized in that Further including: The sealing layer is disposed on each of the contact pads and the spacer.