Manufacturing method of vertical PIN diode structure and vertical PIN diode structure

Abstract

The invention discloses a manufacturing method of a vertical PIN diode structure and the vertical PIN diode structure, and the manufacturing method comprises the steps: providing a substrate which is provided with a first surface and a second surface which are opposite to each other; forming an epitaxial structure on the first surface, wherein the epitaxial structure comprises an N-type buffer layer, an intrinsic layer, a P-type doped layer and a P-type heavily doped layer which are sequentially arranged in the direction away from the substrate; forming a first electrode on the surface of the P-type heavily doped layer, wherein the first electrode exposes part of the P-type heavily doped layer; performing N ion implantation in the exposed region of the P-type heavily doped layer to form a plurality of field ring structures arranged at intervals; forming a second electrode on the second surface; and forming a passivation layer exposing part of the first electrode on the P-type heavily doped layer. According to the manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure, N ion implantation is adopted to form a field ring structure, and device performance and device isolation are achieved at the same time.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor preparation, and in particular relates to a method for preparing a vertical PIN diode structure and a vertical PIN diode structure. Background Art

[0002] Gallium nitride (GaN) is recognized as one of the leaders of the third-generation semiconductors, with a series of excellent physical properties, such as a wide bandgap of 3.4eV, a critical breakdown field strength of 3.7MV / cm, and a 7 The high saturation electron drift velocity of cm / s and the direct band gap structure make it have broad application prospects in the field of power electronics.

[0003] PIN diode is a semiconductor device composed of P-type semiconductor, I-type intrinsic layer and N-type semiconductor. Due to the existence of I-type layer, the depletion region is wider than PN junction and can withstand greater reverse voltage. When forward biased, electrons and holes are injected into the intrinsic layer to act as a conductive channel. At this time, the resistance is very small, which is similar to a path; when reverse biased, the potential barrier increases and the depletion region widens. At this time, there is only weak reverse leakage, which appears as an open circuit. PIN diodes are widely used in RF switches, photodetectors, antenna matching and signal modulation, especially in situations where high-power or high-frequency signals need to be processed.

[0004] At present, mainstream research focuses on planar devices or quasi-vertical devices, and these device structures mainly rely on heteroepitaxial growth. However, heteroepitaxial growth has problems such as lattice mismatch and thermal mismatch, which will affect the reverse performance of the device and limit the application of GaN devices in the high-voltage field.

[0005] At present, there are relatively few studies on vertical structure gallium nitride devices, and the potential of GaN as a wide bandgap material has not been fully explored. An important factor restricting development is the selection of terminal structure. When the device is not terminated, the edge of the anode electrode will break down prematurely due to the "electric field concentration" effect, causing the device to fail prematurely. After the device is terminated, it will expand the depletion region, thereby alleviating the edge electric field concentration, reducing reverse leakage, and increasing the breakdown voltage.

[0006] Mainstream terminal structure designs include deep etching, field plates, beveled terraces, junction terminal extensions, etc. Etching and beveled terraces both involve etching processes. Under the action of a plasma source, the reactive gas bombards the sample surface under the action of an electric field. This physical process will cause a lot of etching damage. If the etching depth is not deep enough, the relief of the electric field is also limited. The field plate terminal involves spin-on-glass (SOG), which complicates the process and may introduce new leakage channels. In order to achieve the best performance of junction terminal extension, precise control of the injection depth at the nanometer level is required, which is not easy to achieve on the process side.

[0007] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0008] The purpose of the present invention is to provide a method for manufacturing a vertical PIN diode structure and a vertical PIN diode structure, which adopts N ion implantation to form a field ring structure, achieves optimal performance by adjusting the spacing of the field ring structure, and simultaneously achieves the effect of device isolation.

[0009] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0010] A method for manufacturing a vertical PIN diode structure, comprising:

[0011] Providing a substrate having a first surface and a second surface disposed opposite to each other;

[0012] forming an epitaxial structure on the first surface, the epitaxial structure comprising an N-type buffer layer, an intrinsic layer, a P-type doped layer, and a P-type heavily doped layer sequentially arranged in a direction away from the substrate;

[0013] forming a first electrode on the surface of the P-type heavily doped layer, wherein the first electrode exposes a portion of the P-type heavily doped layer;

[0014] Performing N ion implantation in the exposed region of the P-type heavily doped layer to form a plurality of field ring structures arranged at intervals, wherein the field ring structures at least penetrate into the P-type doped layer, and the first electrode is located within the range of the field ring structures;

[0015] forming a second electrode on the second surface;

[0016] A passivation layer covering the first electrode is formed on the P-type heavily doped layer, and the passivation layer is etched to expose a portion of the first electrode.

[0017] In one or more embodiments of the present invention, the energy range of the N ion implantation is 20keV-350keV; and / or,

[0018] The dose range of the N ion implantation is 5×10 12 cm -3 -8×10 12 cm -3 .

[0019] In one or more embodiments of the present invention, N ion implantation is performed multiple times in the exposed region of the P-type heavily doped layer using a photoresist as a mask to form the field ring structure.

[0020] In one or more embodiments of the present invention, the energy of multiple N ion implantations is gradually reduced.

[0021] In one or more embodiments of the present invention, the number of N ion implantations is 5, and the energy range and metering range of each implantation are respectively:

[0022] The first time, the energy was 345keV-355keV and the dose was 7×10 12 cm -3 -9×10 12 cm -3 ;

[0023] The second time, the energy was 245keV-255keV and the dose was 4×10 12 cm -3 -6×10 12 cm -3 ;

[0024] The third time, the energy was 175keV-185keV, and the dose was 5×10 12 cm -3 -7×10 12 cm -3 ;

[0025] The fourth time, energy 75keV-85keV, dose 4×10 12 cm -3 -6×10 12 cm -3 ;

[0026] The fifth time, the energy was 15keV-25keV, the dose was 7×10 12 cm -3 -9×10 12 cm -3 .

[0027] In one or more embodiments of the present invention, the spacing between adjacent field ring structures is 4 μm-6 μm, and the width of the field ring structure is 2 μm-5 μm.

[0028] In one or more embodiments of the present invention, forming a passivation layer covering the first electrode on the P-type heavily doped layer includes:

[0029] forming a first passivation layer on the P-type heavily doped layer by plasma enhanced atomic layer deposition technology;

[0030] forming a second passivation layer on the first passivation layer by plasma enhanced chemical vapor deposition technology;

[0031] Wherein, the thickness of the first passivation layer is 10nm-20nm, and the thickness of the second passivation layer is 200nm-500nm.

[0032] A vertical PIN diode structure, comprising:

[0033] A substrate having a first surface and a second surface disposed opposite to each other;

[0034] an epitaxial structure formed on the first surface, the epitaxial structure comprising an N-type buffer layer, an intrinsic layer, a P-type doped layer and a P-type heavily doped layer sequentially arranged in a direction away from the substrate, the epitaxial structure having a middle region and an edge region surrounding the middle region, a plurality of spaced field ring structures being formed in the P-type heavily doped layer in the edge region;

[0035] A first electrode formed on the surface of the P-type heavily doped layer in the middle region;

[0036] a passivation layer formed on a surface of the P-type heavily doped layer, wherein the passivation layer exposes a portion of the first electrode; and

[0037] The second electrode is formed on the second surface.

[0038] In one or more embodiments of the present invention, the spacing between adjacent field ring structures is 4 μm-6 μm, and the width of the field ring structure is 2 μm-5 μm.

[0039] In one or more embodiments of the present invention, the materials of the substrate, the N-type buffer layer, the intrinsic layer, the P-type doped layer and the P-type heavily doped layer are all gallium nitride; and / or,

[0040] The doping source of the substrate, the N-type buffer layer and the intrinsic layer is Si, and the doping source of the P-type doping layer and the P-type heavily doped layer is Mg; and / or,

[0041] The doping concentration of Si in the substrate is 0.5×10 18 cm-3 -1.5×10 18 cm -3 and / or,

[0042] The thickness of the substrate is 350 μm-450 μm; and / or,

[0043] The doping concentration of Si in the N-type buffer layer is 4×10 18 cm -3 -6×10 18 cm -3 , and / or,

[0044] The thickness of the N-type buffer layer is 0.5 μm-1 μm; and / or,

[0045] The doping concentration of Si in the intrinsic layer is less than 1×10 16 cm -3 and / or,

[0046] The thickness of the intrinsic layer is 4 μm-8 μm; and / or,

[0047] The doping concentration of the Mg doping source in the P-type doping layer is 0.5×10 19 cm -3 -1.5×10 19 cm -3 and / or,

[0048] The thickness of the P-type doped layer is 0.3 μm-0.5 μm; and / or,

[0049] The doping concentration of the Mg doping source in the P-type heavily doped layer is 0.5×10 20 cm -3 -1.5×10 20 cm -3 and / or,

[0050] The thickness of the P-type heavily doped layer is 0.01 μm-0.03 μm.

[0051] In one or more embodiments of the present invention, the first electrode is configured as a circular structure.

[0052] Compared with the prior art, the manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention are based on a homogeneous substrate, and a suitable terminal structure is designed. Through N ion implantation, a field ring structure is formed and isolation between devices is achieved at the same time, thereby maximizing the voltage resistance performance of the gallium nitride material.

[0053] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention use N ion implantation to form a field ring structure, achieve optimal performance by adjusting the spacing of the field ring structure, and simultaneously achieve the effect of device isolation.

[0054] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention explore the parameters of the appropriate field ring structure so that the field ring structure can maximize the alleviation of the electric field concentration at the edge of the anode, expand the area of ​​the depletion region, and greatly increase the reverse withstand voltage performance of the device.

[0055] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention select a non-physical damage process such as a field ring structure as a device terminal, thereby avoiding performance degradation of the device due to unnecessary process defects, reducing damage to the device caused by complex processes, and improving the stability of the device.

[0056] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention are based on a gallium nitride self-supporting substrate for device manufacturing, and the dislocation density is lower, which means lower reverse leakage; the vertical device has a higher voltage resistance and can withstand a higher current in a smaller device area.

[0057] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention, the design elements such as the P-type heavily doped layer, the circular electrode and the passivation layer not only reduce the on-resistance of the device, but also effectively reduce the reverse leakage and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 FIG. 1 is a process flow chart of a method for manufacturing a vertical PIN diode structure in one embodiment of the present invention;

[0060] Figure 2 A cross-sectional view of a vertical PIN diode structure in one embodiment of the present invention;

[0061] Figure 3 A top view of a vertical PIN diode structure in one embodiment of the present invention (without a passivation layer);

[0062] Figure 4 for Figure 3 Detailed view of part A;

[0063] Figure 5 A top view of a vertical PIN diode structure according to an embodiment of the present invention;

[0064] Figure 6 This is a diagram showing the reverse withstand voltage simulation results of a vertical PIN diode structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0066] As mentioned in the background technology, there is relatively little research on vertical structure gallium nitride devices, and the potential of GaN as a wide bandgap material has not been fully explored. An important factor restricting development is the selection of terminal structure. When the device is not terminated, the edge of the anode electrode will break down prematurely due to the "electric field concentration" effect, causing the device to fail prematurely. After the device is terminated, it will expand the depletion region, thereby alleviating the edge electric field concentration, reducing reverse leakage, and increasing the breakdown voltage.

[0067] Mainstream terminal structure designs include deep etching, field plates, beveled terraces, junction terminal extensions, etc. Etching and beveled terraces both involve etching processes. Under the action of a plasma source, the reactive gas bombards the sample surface under the action of an electric field. This physical process will cause a lot of etching damage. If the etching depth is not deep enough, the relief of the electric field is also limited. The field plate terminal involves spin-on-glass (SOG), which complicates the process and may introduce new leakage channels. In order to achieve the best performance of junction terminal extension, precise control of the injection depth at the nanometer level is required, which is not easy to achieve on the process side.

[0068] Based on this, the present invention provides a method for manufacturing a vertical PIN diode structure and a vertical PIN diode structure, adopts a method for forming a field ring structure by N ion implantation, achieves optimal performance by adjusting the spacing of the field ring structure, and simultaneously achieves the effect of device isolation. The method is simple and easy to implement, does not require complex processes, and does not affect the forward performance of the device while optimizing the reverse withstand voltage.

[0069] like Figure 1 As shown, a method for manufacturing a vertical PIN diode structure in an embodiment of the present invention specifically includes the following steps:

[0070] S1, providing a substrate, wherein the substrate has a first surface and a second surface arranged opposite to each other; and forming an epitaxial structure on the first surface.

[0071] The substrate is preferably a gallium nitride single crystal substrate. The doping concentration of Si in the gallium nitride substrate is 0.5×10 18 cm -3 -1.5×10 18 cm -3 , preferably 1×10 18 cm -3 The thickness of the gallium nitride single crystal substrate is 350 μm-450 μm, preferably 400 μm.

[0072] An epitaxial structure is grown by MOCVD epitaxy, and the epitaxial structure includes an N-type buffer layer, an intrinsic layer, a P-type doped layer, and a P-type heavily doped layer arranged in sequence in a direction away from the substrate. The materials of the N-type buffer layer, the intrinsic layer, the P-type doped layer, and the P-type heavily doped layer are all gallium nitride. The doping source of the N-type buffer layer and the intrinsic layer is Si. The doping source of the P-type doped layer and the P-type heavily doped layer is Mg.

[0073] The doping concentration of Si in the N-type buffer layer is 4×10 18 cm -3 -6×10 18 cm -3 , preferably 5×10 18 cm -3 The thickness of the N-type buffer layer is 0.5 μm-1 μm.

[0074] The doping concentration of Si in the intrinsic layer is less than 1×10 16 cm -3 ; The thickness of the intrinsic layer is 4μm-8μm.

[0075] The doping concentration of Mg doping source in the P-type doping layer is 0.5×10 19 cm -3 -1.5×10 19 cm -3 , preferably 1×10 19 cm -3 The thickness of the P-type doped layer is 0.3 μm-0.5 μm.

[0076] The doping concentration of the Mg doping source in the P-type heavily doped layer is 0.5×10 20 cm -3 -1.5×10 20 cm -3 , preferably 1×10 20 cm -3The thickness of the P-type heavily doped layer is 0.01 μm-0.03 μm, preferably 0.02 μm.

[0077] S2, forming a first electrode on the surface of the P-type heavily doped layer. The first electrode exposes a portion of the P-type heavily doped layer.

[0078] Before step S2, the step of cleaning the sample is also included. Specifically, the sample is cleaned normally using organic cleaning and inorganic cleaning. Among them, the organic cleaning is to use acetone, isopropanol, and deionized water to clean twice, each time for 5 minutes. The inorganic cleaning is to first clean with BOE for 5 minutes, and then clean with a mixed solution of hydrochloric acid, hydrogen peroxide, and water in a ratio of 1:1:6 for 5 minutes.

[0079] After cleaning and drying the sample, Ni / Au (20nm / 60nm) metal is deposited in the middle area of ​​the surface of the P-type heavily doped layer as the first electrode, and an ohmic contact is formed after annealing. The first electrode is the anode of the vertical PIN diode structure. The first electrode is preferably a circular electrode, and the circular electrode can largely alleviate the electric field concentration caused by the irregularity of the electrode edge.

[0080] S3, N ion implantation is performed in the exposed area of ​​the P-type heavily doped layer to form a plurality of field ring structures arranged at intervals. The field ring structure at least penetrates into the P-type doped layer, and the first electrode is located within the field ring structure.

[0081] Specifically, using photoresist as a mask, N ion implantation is performed multiple times in the exposed edge region of the P-type heavily doped layer to form a field ring structure. The spacing between adjacent field ring structures is 4 μm-6 μm, and the width of the field ring structure is 2 μm-5 μm.

[0082] It can be understood that the width of the field ring structure is the width of the actual N ion implantation region.

[0083] The energy range of N ion implantation is 20keV-350keV; the dose range of N ion implantation is 5×10 12 cm -3 -8×10 12 cm -3 The energy of multiple N ion implantations gradually decreases.

[0084] For example, the number of N ion implantations is 5, and the energy range and dosage range of each implantation are as follows: the first time, the energy is 345keV-355keV, and the dosage is 7×10 12 cm -3 -9×10 12 cm -3 Preferably, the energy is 350keV and the dose is 8×10 12 cm-3 The second time, the energy was 245keV-255keV and the dose was 4×10 12 cm -3 -6×10 12 cm -3 Preferably, the energy is 250keV and the dose is 5×10 12 cm -3 The third time, the energy was 175keV-185keV and the dose was 5×10 12 cm -3 -7×10 12 cm -3 Preferably, the energy is 180keV and the dose is 6×10 12 cm -3 The fourth time, energy 75keV-85keV, dose 4×10 12 cm -3 -6×10 12 cm -3 Preferably, the energy is 80 keV and the dose is 5×10 12 cm -3 The fifth time, the energy was 15keV-25keV, the dose was 7×10 12 cm -3 -9×10 12 cm -3 Preferably, the energy is 20 keV and the dose is 8×10 12 cm -3 .

[0085] N-ion implantation can also achieve the effect of isolating devices from each other. For example, when multiple PIN diode structures are formed on a substrate, the field ring structure formed by N-ion implantation can be used to isolate adjacent PIN diode structures.

[0086] S4, forming a second electrode on the second surface.

[0087] Exemplarily, Ti / Al / Ti / Au (20nm / 130nm / 50nm / 150nm) metal is deposited on the second surface of the substrate as the second electrode. The second electrode is the cathode of the vertical PIN diode structure.

[0088] S5, forming a passivation layer covering the first electrode on the P-type heavily doped layer, and etching the passivation layer to expose a portion of the first electrode.

[0089] Specifically, a first passivation layer can be formed on the P-type heavily doped layer by plasma enhanced atomic layer deposition (PEALD) technology, and the thickness of the first passivation layer is 10nm-20nm. Then, a second passivation layer is formed on the first passivation layer by plasma enhanced chemical vapor deposition (PECVD) technology; the thickness of the second passivation layer is 200nm-500nm. The passivation layer material is preferably silicon oxide.

[0090] In the preparation process of the above passivation layer, the first passivation layer deposited by PEALD is more tightly bonded to the sample surface, which can effectively reduce the leakage of the device interface. The second passivation layer is deposited by PECVD, which increases the thickness of the passivation layer and enhances the passivation effect, effectively improving the compactness of the passivation layer and reducing the leakage of the passivation layer.

[0091] After the passivation layer is formed, a pattern is left on the surface of the device by photolithography, and the passivation layer is etched by reactive ion etching to expose a portion of the first electrode.

[0092] An embodiment of the present invention further provides a vertical PIN diode structure, which can also be manufactured using the above-mentioned manufacturing method.

[0093] refer to Figure 2 As shown, a vertical PIN diode structure according to an embodiment of the present invention includes: a substrate 10 , an epitaxial structure, a first electrode 40 , a passivation layer 50 and a second electrode 60 .

[0094] The substrate 10 has a first surface 10a and a second surface 10b disposed opposite to each other. The substrate 10 is preferably a gallium nitride single crystal substrate. The doping concentration of Si in the gallium nitride substrate is 0.5×10 18 cm -3 -1.5×10 18 cm -3 , preferably 1×10 18 cm -3 The thickness of the gallium nitride single crystal substrate is 350 μm-450 μm, preferably 400 μm.

[0095] The epitaxial structure is formed on the first surface 10 a and includes an N-type buffer layer 21 , an intrinsic layer 22 , a P-type doped layer 23 and a P-type heavily doped layer 24 which are sequentially arranged in a direction away from the substrate 10 .

[0096] The materials of the N-type buffer layer 21, the intrinsic layer 22, the P-type doped layer 23 and the P-type heavily doped layer 24 are all gallium nitride. The doping source of the N-type buffer layer 21 and the intrinsic layer 22 is Si. The doping source of the P-type doped layer 23 and the P-type heavily doped layer 24 is Mg.

[0097] The doping concentration of Si in the N-type buffer layer 21 is 4×10 18 cm-3 -6×10 18 cm -3 , preferably 5×10 18 cm -3 The thickness of the N-type buffer layer 21 is 0.5 μm-1 μm.

[0098] The doping concentration of Si in the intrinsic layer 22 is less than 1×10 16 cm -3 ; The thickness of the intrinsic layer 22 is 4μm-8μm.

[0099] The doping concentration of the Mg doping source in the P-type doping layer 23 is 0.5×10 19 cm -3 -1.5×10 19 cm -3 , preferably 1×10 19 cm -3 The thickness of the P-type doping layer 23 is 0.3 μm-0.5 μm.

[0100] The doping concentration of the Mg doping source in the P-type heavily doped layer 24 is 0.5×10 20 cm -3 -1.5×10 20 cm -3 , preferably 1×10 20 cm -3 The thickness of the P-type heavily doped layer 24 is 0.01 μm-0.03 μm, preferably 0.02 μm.

[0101] refer to Figures 2 to 4 As shown, the epitaxial structure has a middle region B and an edge region C surrounding the middle region. A plurality of spaced field ring structures 30 are formed in at least the P-type heavily doped layer 24 in the edge region C. The plurality of spaced field ring structures 30 are nested in concentric rings.

[0102] Preferably, the field ring structure 30 at least penetrates into the P-type doping layer 23 .

[0103] The distance d between adjacent field ring structures 30 is 4 μm-6 μm, preferably 5 μm. The width of the field ring structure is 2 μm-5 μm, preferably 2 μm.

[0104] refer to Figure 2 and Figure 3 As shown, the first electrode 40 is formed on the surface of the P-type heavily doped layer 24 in the middle region B. The first electrode 40 is preferably a circular electrode. The circular electrode can largely alleviate the electric field concentration caused by the irregularity of the electrode edge.

[0105] refer to Figure 2 and Figure 5As shown, the passivation layer 50 is formed on the surface of the P-type heavily doped layer 24. The passivation layer 50 exposes a portion of the first electrode 40. The passivation layer 50 includes a first passivation layer and a second passivation layer stacked, the first passivation layer having a thickness of 10nm-20nm; the second passivation layer having a thickness of 200nm-500nm.

[0106] The second electrode 60 is formed on the second surface 10 b of the substrate 10 .

[0107] refer to Figure 6 As shown, Figure 6 4 is a simulation diagram of the reverse withstand voltage performance of the vertical PIN diode structure of the present embodiment, which shows the breakdown performance of the vertical PIN diode structure obtained by changing the field ring spacing under the same field ring width (5 μm).

[0108] The present invention manufactures a vertical PIN diode structure on a gallium nitride self-supporting substrate, designs a reasonable doping layer, electrode and passivation layer, and adopts a field ring structure as a terminal, which not only effectively improves the breakdown voltage of the device, but also simplifies the device preparation process.

[0109] Compared with the prior art, the manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention are based on a homogeneous substrate, and a suitable terminal structure is designed. Through N ion implantation, a field ring structure is formed and isolation between devices is achieved at the same time, thereby maximizing the voltage resistance performance of the gallium nitride material.

[0110] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention use N ion implantation to form a field ring structure, achieve optimal performance by adjusting the spacing of the field ring structure, and simultaneously achieve the effect of device isolation.

[0111] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention explore the parameters of the appropriate field ring structure so that the field ring structure can maximize the alleviation of the electric field concentration at the edge of the anode, expand the area of ​​the depletion region, and greatly increase the reverse withstand voltage performance of the device.

[0112] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention select a non-physical damage process such as a field ring structure as a device terminal, thereby avoiding performance degradation of the device due to unnecessary process defects, reducing damage to the device caused by complex processes, and improving the stability of the device.

[0113] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention are based on a gallium nitride self-supporting substrate for device manufacturing, and the dislocation density is lower, which means lower reverse leakage; the vertical device has a higher voltage resistance and can withstand a higher current in a smaller device area.

[0114] The manufacturing method of the vertical PIN diode structure and the vertical PIN diode structure of the present invention, the design elements such as the P-type heavily doped layer, the circular electrode and the passivation layer not only reduce the on-resistance of the device, but also effectively reduce the reverse leakage and improve the reliability of the device.

[0115] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0116] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for manufacturing a vertical PIN diode structure, characterized in that: include: Providing a substrate having a first surface and a second surface disposed opposite to each other; forming an epitaxial structure on the first surface, the epitaxial structure comprising an N-type buffer layer, an intrinsic layer, a P-type doped layer, and a P-type heavily doped layer sequentially arranged in a direction away from the substrate; forming a first electrode on the surface of the P-type heavily doped layer, wherein the first electrode exposes a portion of the P-type heavily doped layer; Performing N ion implantation in the exposed region of the P-type heavily doped layer to form a plurality of field ring structures arranged at intervals, wherein the field ring structures at least penetrate into the P-type doped layer, and the first electrode is located within the range of the field ring structures; forming a second electrode on the second surface; A passivation layer covering the first electrode is formed on the P-type heavily doped layer, and the passivation layer is etched to expose a portion of the first electrode.

2. The method for manufacturing a vertical PIN diode structure according to claim 1, characterized in that: The energy range of the N ion implantation is 20keV-350keV; and / or, The dose range of the N ion implantation is 5×10 12 cm -3 -8×10 12 cm -3 .

3. The method for manufacturing a vertical PIN diode structure according to claim 1, characterized in that: Using photoresist as a mask, N ion implantation is performed multiple times in the exposed region of the P-type heavily doped layer to form the field ring structure.

4. The method for manufacturing a vertical PIN diode structure according to claim 3, characterized in that: The energy of multiple N ion implantations gradually decreases.

5. The method for manufacturing a vertical PIN diode structure according to claim 3, characterized in that: The number of N ion implantations is 5, and the energy range and metering range of each implantation are: The first time, the energy was 345keV-355keV and the dose was 7×10 12 cm -3 -9×10 12 cm -3 ; The second time, the energy was 245keV-255keV and the dose was 4×10 12 cm -3 -6×10 12 cm -3 ; The third time, the energy was 175keV-185keV, and the dose was 5×10 12 cm -3 -7×10 12 cm -3 ; The fourth time, energy 75keV-85keV, dose 4×10 12 cm -3 -6×10 12 cm -3 ; The fifth time, the energy was 15keV-25keV, the dose was 7×10 12 cm -3 -9×10 12 cm -3 .

6. The method for manufacturing a vertical PIN diode structure according to claim 1, characterized in that: The spacing between adjacent field ring structures is 4 μm-6 μm, and the width of the field ring structure is 2 μm-5 μm.

7. The method for manufacturing a vertical PIN diode structure according to claim 1, characterized in that: Forming a passivation layer covering the first electrode on the P-type heavily doped layer, comprising: forming a first passivation layer on the P-type heavily doped layer by plasma enhanced atomic layer deposition technology; forming a second passivation layer on the first passivation layer by plasma enhanced chemical vapor deposition technology; Wherein, the thickness of the first passivation layer is 10nm-20nm, and the thickness of the second passivation layer is 200nm-500nm.

8. A vertical PIN diode structure, characterized in that: include: A substrate having a first surface and a second surface disposed opposite to each other; an epitaxial structure formed on the first surface, the epitaxial structure comprising an N-type buffer layer, an intrinsic layer, a P-type doped layer and a P-type heavily doped layer sequentially arranged in a direction away from the substrate, the epitaxial structure having a middle region and an edge region surrounding the middle region, a plurality of spaced field ring structures being formed in the P-type heavily doped layer in the edge region; A first electrode formed on the surface of the P-type heavily doped layer in the middle region; A passivation layer formed on a surface of the P-type heavily doped layer, wherein the passivation layer exposes a portion of the first electrode; as well as The second electrode is formed on the second surface.

9. The vertical PIN diode structure according to claim 8, characterized in that: The spacing between adjacent field ring structures is 4 μm-6 μm, and the width of the field ring structure is 2 μm-5 μm.

10. The vertical PIN diode structure according to claim 8, characterized in that: The materials of the substrate, the N-type buffer layer, the intrinsic layer, the P-type doped layer and the P-type heavily doped layer are all gallium nitride; and / or, The doping source of the substrate, the N-type buffer layer and the intrinsic layer is Si, and the doping source of the P-type doping layer and the P-type heavily doped layer is Mg; and / or, The doping concentration of Si in the substrate is 0.5×10 18 cm -3 -1.5×10 18 cm -3 and / or, The thickness of the substrate is 350 μm-450 μm; and / or, The doping concentration of Si in the N-type buffer layer is 4×10 18 cm -3 -6×10 18 cm -3 , and / or, The thickness of the N-type buffer layer is 0.5 μm-1 μm; and / or, The doping concentration of Si in the intrinsic layer is less than 1×10 16 cm -3 and / or, The thickness of the intrinsic layer is 4 μm-8 μm; and / or, The doping concentration of the Mg doping source in the P-type doping layer is 0.5×10 19 cm -3 -1.5×10 19 cm -3 and / or, The thickness of the P-type doped layer is 0.3 μm-0.5 μm; and / or, The doping concentration of the Mg doping source in the P-type heavily doped layer is 0.5×10 20 cm -3 -1.5×10 20 cm -3 and / or, The thickness of the P-type heavily doped layer is 0.01 μm-0.03 μm.

Images