Semiconductor device

Abstract

Embodiments relate to a semiconductor device. An embodiment includes a first electrode, a second electrode, a semiconductor portion, a gate electrode, and a structure. The semiconductor part is arranged between the first electrode and the second electrode. The gate electrode is provided between the semiconductor portion and the second electrode. The structure extends into the semiconductor portion under the gate electrode. The semiconductor portion includes first to fifth layers. The first to fifth layers are laminated in this order. The first through third and fifth layers are of the first conductivity type. The fourth layer is of the second conductivity type. The gate electrode faces the fourth layer. The structure includes an insulating film, a conductor, an insulating layer, and a silicide layer. The silicide layer is provided at the lower end of the structure. The lower end of the structure is in contact with the second layer. The second layer comprises a heavy metal. The third layer has a lower heavy metal concentration than the second layer.

Description

[0001] Related Application

[0002] This application claims the priority of Japanese Patent Application No. 2023-149494 (filing date: September 14, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] A metal oxide semiconductor field effect transistor (MOSFET) has a diode connected in anti-parallel therein. When the diode operates, it is preferable to improve the reverse recovery characteristics.

[0005] As a method of improving the reverse recovery characteristics during diode operation, it is known to introduce a heavy metal or the like into a drift layer to control the lifetime of minority carriers in the drift layer. Summary of the invention

[0006] A semiconductor device according to an embodiment includes: a first electrode; a second electrode; a semiconductor portion provided between the first electrode and the second electrode; a gate electrode provided in the semiconductor portion and extending from the second electrode to the first electrode; and a structure provided between the gate electrode and the first electrode and extending from the gate electrode side to the first electrode side in the semiconductor portion. The semiconductor portion includes: a first layer of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second layer of the first conductivity type provided on the first layer and including a heavy metal; a third layer of the first conductivity type provided on the second layer and including the heavy metal at a lower concentration than that of the second layer; a fourth layer of the second conductivity type provided on the third layer, facing the gate electrode via a gate insulating film and electrically connected to the second electrode; and a fifth layer of the first conductivity type provided on the fourth layer and electrically connected to the second electrode. The structure includes: a silicide layer in contact with the second layer; an insulating layer provided on the silicide layer; a conductor provided on the insulating layer, extending from below the gate electrode to the insulating layer and electrically isolated from the gate electrode; and an insulating film provided between the conductor and the second layer and between the conductor and the third layer. The bottom surface and at least a part of the side surface of the silicide layer are in contact with the second layer.

[0007] According to the embodiment, it is possible to provide a semiconductor device having improved reverse recovery characteristics during diode operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic plan view illustrating the semiconductor device according to the first embodiment.

[0009] Figure 2 yes Figure 1 Schematic cross-sectional view taken along line AA.

[0010] Figure 3 yes Figure 2 An enlarged schematic diagram of part B.

[0011] Figure 4 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0012] Figure 5 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 6 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 7 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 8 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Fig. 9 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Fig.10 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Fig.11 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0019] Fig.12 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0020] Fig.13 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0021] Fig.14 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0022] Fig.15 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Fig.16 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0024] Fig.17 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0025] Fig.18 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0026] Fig.19 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0027] Fig. 20 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0028] Fig.21 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0029] Fig. 22 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0030] Fig.23 It is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment.

[0031] Fig.24 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment.

[0032] Fig.25 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment.

[0033] Fig.26 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment.

[0034] Fig. 27 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments do not limit the present invention.

[0036] The same parts in the drawings are marked with the same reference numerals and detailed descriptions are appropriately omitted, and different parts are described. In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. may not be the same as in reality. In addition, even when the same parts are shown, there are cases where the sizes and ratios of each other are shown differently depending on the drawings.

[0037] (First Embodiment)

[0038] Figure 1 It is a schematic plan view illustrating the semiconductor device according to the first embodiment.

[0039] Figure 2 yes Figure 1 Schematic cross-sectional view taken along line AA.

[0040] Figure 3 yes Figure 2 An enlarged schematic diagram of part B.

[0041] like Figure 1 and Figure 2 As shown, the semiconductor device 100 of the present embodiment includes a first electrode 1, a second electrode 2, a semiconductor portion 10, a gate electrode 21, and a structure 40. The semiconductor portion 10 is provided between the first electrode 1 and the second electrode 2. The first electrode 1 is provided on the back side of the semiconductor portion 10 and functions as a drain electrode. The second electrode 2 is provided on the surface side of the semiconductor portion 10 and functions as a source electrode E2. The gate electrode 21 faces the semiconductor portion 10 via a gate insulating film 31. The gate electrode 21 is electrically connected to the gate electrode pad G1. The source electrode E2 and the gate electrode pad G1 are separately arranged and electrically separated when viewed from above. In some cases, an insulating layer K1 is provided between the source electrode E2 and the gate electrode pad G1 as in this example, but the insulating layer K1 may not be provided between the source electrode E2 and the gate electrode pad G1.

[0042] The semiconductor device 100 is a MOSFET having a first electrode 1 as a drain electrode, a second electrode 2 as a source electrode E2, and a gate electrode 21. In the diode operation of the semiconductor device 100, when the semiconductor device 100 is an n-channel MOSFET, the first electrode 1 functions as a cathode electrode, and the second electrode 2 functions as an anode electrode. When the semiconductor device 100 is a p-channel MOSFET, the first electrode 1 functions as an anode electrode, and the second electrode 2 functions as a cathode electrode.

[0043] like Figure 2 As shown, the semiconductor portion 10 includes a first layer 11, a second layer 12, a third layer 13, a fourth layer 14, and a fifth layer 15. The first layer 11, the second layer 12, the third layer 13, and the fifth layer 15 are semiconductor layers of the first conductivity type. The fourth layer is a semiconductor layer of the second conductivity type. The semiconductor portion 10 further includes a sixth layer 16. The sixth layer 16 is a semiconductor layer of the second conductivity type. The semiconductor portion 10 includes, for example, Si.

[0044] The first layer 11 is provided on the first electrode 1. The first layer 11 is a semiconductor substrate.

[0045] The second layer 12 is provided on the first layer 11. The first conductivity type impurity concentration of the second layer 12 is lower than the first conductivity type impurity concentration of the first layer 11. The second layer 12 contains a heavy metal 12a in addition to the first conductivity type impurity. The heavy metal 12a is, for example, platinum (Pt) or gold (Au). In the second layer 12, the concentration of Pt or Au is 1×10 13 cm -3 ~1×10 20 cm -3 The second layer 12 is an n-type drift layer into which a heavy metal 12 a is introduced.

[0046] exist Figure 2 In the specific example shown, the second layer 12 is arranged on the first layer 11 and is connected to the first layer 11, but the following region can also be set between the second layer 12 and the first layer 11: the region is a semiconductor layer having an impurity concentration of the first conductivity type that is approximately equal to the impurity concentration of the first conductivity type of the second layer, and the concentration of the heavy metal 12a is lower than the concentration of the heavy metal 12a of the second layer 12.

[0047] The third layer 13 is provided on the second layer 12. The first conductivity type impurity concentration of the third layer 13 is substantially the same as that of the second layer 12 and lower than that of the first conductivity type impurity concentration of the first layer 11. The third layer 13 is, for example, an n-type drift layer.

[0048] The third layer 13 may also contain a heavy metal 12a. The concentration of the heavy metal 12a in the third layer 13 is lower than the concentration of the heavy metal 12a in the second layer 12. Preferably, the concentration of the heavy metal 12a in the third layer 13 is substantially zero. For example, the concentration of the heavy metal 12a in the third layer 13 decreases as it moves away from the second layer 12. By making the concentration of the heavy metal 12a in the third layer 13 sufficiently low, it is possible to reduce leakage current when a reverse bias is applied between the first electrode 1 and the second electrode 2 when the semiconductor device 100 is cut off.

[0049] The fourth layer 14 is provided on the third layer 13. The fourth layer 14 is, for example, a p-type base layer.

[0050] The fifth layer 15 is provided on the fourth layer 14. The first conductivity type impurity concentration of the fifth layer 15 is higher than that of the second layer 12 and higher than that of the third layer 13. The fifth layer 15 is, for example, an n-type contact layer.

[0051] The sixth layer 16 is selectively provided on the third layer 13. The fourth layer 14 is provided on the sixth layer 16. The fourth layer 14 is provided on the side of the sixth layer 16. The second conductivity type impurity concentration of the sixth layer 16 is higher than the second conductivity type impurity concentration of the fourth layer 14. The sixth layer 16 is, for example, a p-type contact layer.

[0052] An interlayer insulating film 60 is provided on the fifth layer 15. On the interlayer insulating film 60, the second electrode 2 is provided.

[0053] The second electrode 2 includes a connection portion 2a that penetrates the interlayer insulating film 60. The connection portion 2a penetrates the fifth layer 15 and the fourth layer 14 to reach the sixth layer 16. The connection portion 2a is electrically connected to the fifth layer 15, the fourth layer 14, and the sixth layer 16. The fifth layer 15, the fourth layer 14, and the sixth layer 16 are electrically connected to the second electrode 2 via the connection portion 2a.

[0054] In the following, the XYZ coordinate system is sometimes used for explanation. The first layer 11 has a first surface 11a. The first surface 11a is a plane. The second layer 12 is provided on the first surface 11a. The XY plane is provided to be parallel to the first surface 11a. Sometimes the direction from the first electrode 1 toward the second electrode 2 is provided as the direction of the Z axis, referred to as the Z direction. The situation of observing the semiconductor device 100 from the Z direction is referred to as a top view.

[0055] The gate electrode 21 is provided between the second electrode 2 and the first electrode 1. The gate electrode 21 extends in the Z direction in the semiconductor portion 10. A plurality of gate electrodes 21 are provided. Figure 2 In the example of , the plurality of gate electrodes 21 are arranged at equal intervals in the direction of the X axis. The plurality of gate electrodes 21 are also arranged at equal intervals in the direction of the Y axis, for example. In a plan view, the gate electrodes 21 are arranged in a matrix, for example.

[0056] The gate electrode 21 faces the fourth layer 14 via the gate insulating film 31. Figure 2 In the specific example, the gate electrode 21 faces the fifth layer 15 via the gate insulating film 31. Alternatively, the gate electrode 21 may face a portion of the third layer 13 via the gate insulating film 31.

[0057] The gate electrode 21 is made of, for example, polycrystalline Si containing impurities of the first conductivity type.

[0058] The structure 40 is provided between the gate electrode 21 and the first electrode 1. The structure 40 extends in the Z direction in the semiconductor portion 10. The structure 40 is in contact with the third layer 13 at the side surface of the structure 40. The structure 40 is in contact with the second layer 12 at the bottom surface of the structure 40. The structure 40 is in contact with the second layer 12 at a portion of the side surface continuous from the bottom surface of the structure 40.

[0059] The structure 40 includes an insulating film 41, a conductor 42, an insulating layer 43, and a silicide layer 45. The conductor 42 extends in the Z direction below the gate electrode 21. The insulating film 41 is provided between the gate electrode 21 and the conductor 42. The conductor 42 is provided on the insulating layer 43. The insulating layer 43 is provided on the silicide layer 45. The silicide layer 45 is provided on the second layer 12.

[0060] The insulating film 41 extends in the Z direction below the gate electrode 21. Figure 2 In the specific example, the insulating film 41 is provided continuously from the gate insulating film 31 .

[0061] The insulating film 41 surrounds the conductor 42, the insulating layer 43, and the silicide layer 45. The silicide layer 45 is in contact with the second layer 12 on the second layer 12, and the second layer 12 is in contact with the bottom surface of the silicide layer 45 and a part of the side surface continuous from the bottom surface.

[0062] like Figure 3 As shown, the lower end of the insulating film 41 is separated from the first surface 11a by a distance Z1 in the Z direction. The lower end of the silicide layer 45 is separated from the first surface 11a by a distance Z2 in the Z direction. The relationship between the distances Z1 and Z2 is Z1>Z2, and Z1-Z2=ΔZ>0. That is, the silicide layer 45 protrudes from the insulating film 41 of the structure 40 toward the second layer 12.

[0063] In the structure 40, the conductor 42 extends in the Z direction and faces the third layer 13 via the insulating film 41. The conductor 42 functions as a field plate to mitigate the electric field in the third layer 13 generated by the reverse bias voltage applied between the first electrode 1 and the second electrode 2. The conductor 42 preferably faces the third layer 13 via the insulating film 41 over the entire range from the upper end 42T to the lower end 42B of the conductor 42.

[0064] The insulating film 41 and the insulating layer 43 include, for example, silicon oxide. The crystal structure of the insulating film 41 may be different from that of the insulating layer 43. The conductor 42 includes, for example, polycrystalline Si containing first conductivity type impurities. The silicide layer 45 includes, for example, Pt and Pt silicide.

[0065] The operation and effects of the semiconductor device 100 according to the present embodiment will be described.

[0066] Hereinafter, the operation of the semiconductor device 100 will be described assuming that the first conductivity type is an n-type and the second conductivity type is a p-type.

[0067] First, the operation of the semiconductor device 100 when it is turned off is described. In the semiconductor device 100, by applying a voltage sufficiently lower than the gate threshold voltage relative to the gate electrode 21 to the second electrode 2, an inversion layer is not formed on the surface of the third layer 13 facing the gate electrode 21. Therefore, a channel is not formed in the third layer 13, and the semiconductor device 100 is turned off. If a voltage higher than the second electrode 2 is applied to the first electrode 1, the third layer 13 and the fourth layer 14 are reversely biased.

[0068] The conductor 42 functions as a field plate. Therefore, an electric field generated by the voltage applied between the first electrode 1 and the second electrode 2 is formed from the third layer 13 to the conductor 42 .

[0069] The electric field formed between the conductor 42 and the third layer 13 forms a depletion layer in the third layer 13. The depletion layer extends in the third layer 13 along the direction of the electric field. Since the structures 40 are arranged in parallel in the X direction and the Y direction, the depletion layers of the adjacent structures 40 are connected to each other and continuous. That is, in the reverse bias state, the depletion layer is formed throughout the third layer 13, and the third layer 13 is depleted as a whole.

[0070] If there are crystal defects or the like in the depleted third layer 13, leakage current will occur. In particular, if the heavy metal 12a is introduced into the third layer 13, the heavy metal will aggregate on the crystal defects, increasing the leakage current. In the semiconductor device 100 of this embodiment, the concentration of the heavy metal 12a in the third layer 13 is sufficiently lower than the concentration of the heavy metal 12a in the second layer 12, so the leakage current is suppressed.

[0071] When a voltage higher than that of the first electrode 1 is applied to the second electrode 2 in the cut-off state of the semiconductor device 100, holes as minority carriers are injected from the fourth layer 14 to the third layer 13. The holes are supplied to the second layer 12 via the third layer 13. On the other hand, electrons are supplied from the first layer 11 to the second layer 12. Thus, a current flows from the second electrode 2 to the first electrode 1. This current is equivalent to the action of flowing through a diode in which the second electrode 2 is set as an anode electrode and the first electrode 1 is set as a cathode electrode. Such an action is sometimes called a diode action.

[0072] When holes are injected by diode action, carriers are accumulated in the second layer 12. In this state, if a voltage higher than that of the second electrode 2 is applied to the first electrode 1, a reverse recovery current flows due to the accumulated carriers. Since the mobility of holes is low, current continues to flow even after the electrons are ejected.

[0073] In the semiconductor device 100 of the present embodiment, the second layer 12 includes the heavy metal 12a having a higher concentration than that of the third layer 13. Since the heavy metal 12a functions as a recombination center, the excess holes recombine at the heavy metal 12a and disappear. By appropriately setting the concentration of the heavy metal 12a of the second layer 12, the excess holes can be almost completely eliminated, and the reverse recovery time after the current based on the diode operation flows can be shortened.

[0074] The electric field relaxation effect of the field plate of the conductor 42 can increase the impurity concentration of the third layer 13, thereby reducing the on-resistance of the semiconductor device 100. Since the impurity concentration of the third layer 13 is high, the accumulated carriers increase, and on the other hand, the reverse recovery time is further shortened due to the heavy metal 12a. In this way, in the present embodiment, in the MOSFET using the field plate, low on-resistance and shortened reverse recovery time can be achieved.

[0075] Next, the operation of the semiconductor device 100 when turned on is described. In the semiconductor device 100, by applying a voltage sufficiently higher than the gate threshold voltage with respect to the gate electrode 21 to the second electrode 2, an inversion layer is formed on the surface of the third layer 13 facing the gate electrode 21. The inversion layer of the third layer 13 functions as a channel.

[0076] By applying a high voltage to the first electrode 1 relative to the second electrode 2, the electrons supplied from the fifth layer 15 pass through the third layer 13, the second layer 12, and the first layer 11 via the inversion layer to reach the first electrode 1. In other words, the on-resistance of the semiconductor device 100 is the sum of the resistances of the first layer 11 to the fifth layer 15, and the lower their resistance values, the lower the on-resistance can be.

[0077] As described above, the semiconductor device 100 of the present embodiment includes the structure 40 extending in the Z direction in the third layer 13. The electric field when a reverse bias is applied is converted to a direction orthogonal to the Z direction by the structure 40. By making the length of the conductor 42 facing the third layer 13 sufficient, the electric field between the conductor 42 and the third layer 13 can be reduced, and a sufficient withstand voltage can be achieved without reducing the impurity concentration of the second layer 12 and the third layer 13. Therefore, the on-resistance of the semiconductor device 100 is reduced.

[0078] As described above, in the semiconductor device 100 of the present embodiment, a low leakage current and improved reverse recovery characteristics can be achieved by setting a structure in which the depletion layer formed in the off state is mostly formed in the third layer 13 and not in the second layer 12 .

[0079] Furthermore, the structure 40 includes the conductor 42 extending in the Z direction in order to form a depletion layer in the third layer 13. Therefore, the resistance value of the third layer 13 can be reduced, and in the semiconductor device 100, the on-resistance is reduced.

[0080] A method for manufacturing the semiconductor device 100 according to the present embodiment will be described.

[0081] Figure 4 to Figure 22 It is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment.

[0082] like Figure 4 As shown, a mask 1001 is formed on the intermediate layer 13a formed on the first layer 11, and a trench T1 is formed at a position corresponding to the mask 1001. Reactive ion etching (RIE) can be used to form the trench T1. The intermediate layer 13a is a semiconductor layer of the first conductivity type. The mask 1001 is, for example, a photoresist.

[0083] like Figure 5 As shown, an insulating film 1002 is formed to cover the sidewall 13aS, bottom surface 13aB and mask 1001 of the formed trench T1. The insulating film 1002 includes, for example, Si oxide. The insulating film 1002 can be deposited using, for example, chemical vapor deposition (CVD).

[0084] like Figure 6 As shown in FIG. 1 , the insulating film 1002 is anisotropically processed along the Z direction. In the anisotropic processing in the Z direction, the insulating film 1002a is processed along the Z direction, and is hardly processed in the direction orthogonal to the Z direction. In the processing of the insulating film 1002, the insulating film 1002 is removed until the bottom surface 13aB1 of the intermediate layer 13a is exposed. The depth of the bottom surface 13aB1 may be the same as the depth of the bottom surface 13aB of the insulating film 1002a, or may be different from the bottom surface 13aB1 of the intermediate layer 13a. Figure 6 The side wall 1002aS of the insulating film 1002a is almost the same as before the processing. In the anisotropic processing, for example, RIE can be used.

[0085] like Figure 7 As shown, a heavy metal layer 1003 is formed. The heavy metal layer 1003 is formed at least on the bottom surface 13aB1 of the intermediate layer 13a. Figure 7 As in the specific example of FIG. 1 , the heavy metal layer 1003 may be formed on the sidewall 1002aS of the insulating film 1002a, on the insulating film 1002a, and on the mask 1001. The heavy metal layer 1003 includes Pt or Au as a heavy metal. The heavy metal layer 1003 may be formed by, for example, sputtering.

[0086] In the step of forming the heavy metal layer 1003, the heavy metal reacts with Si of the intermediate layer 13a at the bottom surface 13aB1. Therefore, the portion of the heavy metal layer 1003 in contact with the bottom surface 13aB1 includes the heavy metal of the heavy metal layer 1003 and silicide containing the heavy metal.

[0087] like Figure 8 As shown, the heavy metal layer 1003 is removed, leaving the silicide layer 1004 containing heavy metal and silicide. In removing the heavy metal layer 1003, wet etching may be used, for example.

[0088] like Fig. 9 As shown, the heavy metal 12a in the silicide layer 1004 diffuses into the intermediate layer 13a by heat treatment. The second layer 12 is formed in the region where the heavy metal 12a diffuses. The heavy metal 12a in the silicide layer 1004 diffuses into the second layer 12, and the concentration of the heavy metal decreases, forming a silicide layer 45.

[0089] Since the silicide layer 45 is provided at the lower end of the insulating film 1002a, the second layer 12 is formed below the insulating film 1002a. In addition, since the heavy metal 12a is randomly diffused in the intermediate layer 13a by heat treatment, Fig. 9 As shown in the specific example of , the second layer 12 is also formed above the lower end of the insulating film 1002a.

[0090] In the heat treatment of the silicide layer 1004, for example, a high temperature short time annealing method (Rapid Thermal Anneal: RTA) can be used. In RTA, by appropriately setting and controlling the temperature and time, it is possible to suppress the diffusion of the heavy metal 12a upward and make it diffuse to a sufficient range to form the second layer 12. For example, if the temperature of RTA is set to about 600°C to 900°C, the second layer 12 can be suppressed from spreading upward.

[0091] Before the silicide layer 1004 is heated, H may be irradiated from the first layer 11 side. + By irradiating H only to the area where heavy metals are desired to form + , can be H + The irradiated part aggregates the heavy metal at a desired concentration, and can suppress excessive diffusion of the heavy metal in the subsequent heat treatment.

[0092] like Fig.10 As shown in FIG. 1 , an insulating layer 1005 is formed. The insulating layer 1005 is formed on the mask 1001, the insulating film 1002a, and the silicide layer 45. By the step of forming the insulating layer 1005, the insulating layer 43 is formed on the silicide layer 45.

[0093] The insulating layer 1005 can be formed by, for example, a high density plasma CVD method (HDP-CVD). In the HDP-CVD method, by applying a bias voltage to the first layer 11 side, it can be made to have a self-planarization function. Fig.10 As shown in the specific example of , the film can be formed while removing the deposits deposited on the side wall 1002aS of the insulating film 1002a. Figure 5 The insulating film 1002 shown in the figure has different crystal structures when the insulating layer 43 is formed by the HDP-CVD method.

[0094] like Fig.11 As shown, a conductive layer 1006 is formed on the insulating layer 43 and the insulating layer 1005. The conductive layer 1006 is also formed on the sidewalls 1002aS of the insulating film 1002a. When viewed from above, the radial dimension of the sidewalls 1002aS is very small, and the conductive layer 1006 is buried between the sidewalls 1002aS. The conductive layer 1006 can be formed by, for example, CVD.

[0095] like Fig.12 As shown, the conductive layer 1006 is removed until the side wall 1002aS of the upper portion of the insulating film 1002a is exposed, thereby forming the conductor 42. The conductive layer 1006 can be removed by, for example, chemical dry etching (CDE).

[0096] In the formation Fig.11 In the case of the conductive layer 1006 shown, after the upper surface of the conductive layer 1006 is flattened, the conductive body 42 having an appropriate length in the Z direction can be formed by removing the conductive layer 1006. The upper surface of the conductive layer 1006 can be flattened using chemical mechanical polishing (CMP), for example.

[0097] like Fig.13 As shown in FIG. 1 , an insulating film 1007 is formed on the insulating layer 43, the insulating layer 1005, and the sidewall 1002aS exposed by removing the conductive layer 1006. The insulating film 1007 can be formed by, for example, CVD.

[0098] like Fig.14 As shown, the insulating layer 1005 and the insulating film 1007 are removed to expose the side wall 13aS of the upper portion of the third layer 13. The insulating films 1002a and 1007a form the insulating film 41. The insulating layer 1005 and the insulating film 1007 can be removed by, for example, wet etching.

[0099] like Fig.15 As shown, a gate insulating film 1008 is formed on the sidewall 13aS. The gate insulating film 1008 can be formed by, for example, thermal oxidation. In the film forming method based on thermal oxidation, the gate insulating film 1008 is also formed on the third layer 13 and the insulating film 41.

[0100] like Fig.16 As shown in FIG. 1 , a gate electrode layer 1009 is formed on the gate insulating film 1008. The gate electrode layer 1009 can be formed by, for example, low pressure CVD (LPCVD).

[0101] like Fig.17As shown, the upper portion of the gate electrode layer 1009 is removed to form the gate electrode 21. The gate electrode layer 1009 can be removed by, for example, chemical dry etching (CDE).

[0102] like Fig.18 As shown, the fourth layer 14 is formed on the third layer 13. Then, the fifth layer 15 is formed on the fourth layer 14. The fourth layer 14 and the fifth layer 15 can be formed by, for example, ion implantation.

[0103] like Fig.19 As shown in FIG. 1 , an interlayer insulating film 60 is formed on the gate electrode 21 and the fifth layer 15. The interlayer insulating film 60 can be formed by using CVD, for example.

[0104] like Fig. 20 As shown, a contact region (contact) C1 is formed in the interlayer insulating film 60. The contact region C1 is formed so as to penetrate the interlayer insulating film 60 and expose the fifth layer 15.

[0105] like Fig.21 As shown, the sixth layer 16 is formed in the fourth layer 14 by irradiating ions forming a p-type impurity through the contact region C2 by, for example, an ion implantation method.

[0106] like Fig. 22 As shown, a conductive layer is formed on the interlayer insulating film 60 and a conductive layer is also formed in the contact region C2, thereby forming the second electrode 2. Thereafter, a first electrode is formed on the back surface of the first layer 11, thereby forming the semiconductor device 100.

[0107] In the semiconductor device 100 of the present embodiment, the second layer 12 including the heavy metal 12a can be formed between the first layer 11 and the third layer 13 by the above-mentioned manufacturing method. The heavy metal 12a diffuses the heavy metal contained in the silicide layer 1004 formed at the lower end of the insulating film 41 forming the structure 40 by heat treatment. By appropriately setting the temperature and time during the heat treatment, the diffusion of the heavy metal 12a to the upper part of the structure 40 can be suppressed. Therefore, the second layer 12 including the heavy metal 12a is formed at the lower part of the structure 40, and the side surface of the structure 40 is almost in contact with the third layer 13. Thus, the semiconductor device 100 can be manufactured in which the reverse recovery time during the diode operation is shortened without increasing the leakage current when the reverse bias is applied.

[0108] For the layer containing heavy metal 12a, for example, it is conceivable to contact Fig.21The method of introducing the heavy metal 12a from the lower end of the structure 40 is replaced by the method of introducing the heavy metal 12a from the contact area C1 described above. In this case, the third layer 13 is provided on the first layer 11, and the layer containing the heavy metal 12a is provided between the third layer 13 and the fourth layer 14. In this case, a layer containing the heavy metal 12a at a high concentration is formed in the region depleted when a reverse bias is applied. Therefore, the reverse recovery time is shortened, but the leakage current is increased.

[0109] As for the method of introducing the heavy metal 12a through the contact region C1, specifically, a method of forming a layer of the heavy metal 12a on the wall surface of the contact region C1 and then performing a heat treatment to diffuse the heavy metal 12a can be considered. In this case, since a layer of heavy metal silicide remains on the wall surface of the contact region C1, when the second electrode 2 is formed thereafter, the contact resistance between the contact region C1 and the second electrode 2 becomes large, and the on-resistance may increase.

[0110] In contrast, in the method for manufacturing the semiconductor device 100 described above, since the silicide layer 1004 is formed at the lower end of the structure 40 and then subjected to heat treatment, a layer that increases the on-resistance is not formed at the contact position of either the first electrode 1 or the second electrode 2. Therefore, the semiconductor device 100 having a low on-resistance can be stably manufactured.

[0111] (Second Embodiment)

[0112] Fig.23 It is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment.

[0113] Fig.23 is with Figure 1 The cross-sectional view at the position corresponding to the AA line.

[0114] like Fig.23 As shown, in the semiconductor device 200 of this embodiment, the structure 240 has the same Figure 2 The components of the semiconductor device 200 are different from those of the semiconductor device 100. Figure 2 The components of the semiconductor device 100 are the same, and the same reference numerals are used for the same components, and detailed description thereof is appropriately omitted.

[0115] Similar to the semiconductor device 100 of the first embodiment, a plurality of structures 240 are provided, and each of the structures 240 is provided under the plurality of gate electrodes 21 and extends in the Z direction. Also, similar to the semiconductor device 100, the structure 240 is in contact with a portion of the second layer 12 at the bottom of the structure 240, and is in contact with the second layer 12 at least at the bottom surface of the structure 240.

[0116] The structure 240 includes an insulating film 41, a conductor 42, and an insulating layer 243. The conductor 42 extends in the Z-axis direction below the gate electrode 21. The insulating film 41 is provided between the gate electrode 21 and the conductor 42. The conductor 42 is provided on the insulating layer 243. The insulating layer 243 is provided on the second layer 12.

[0117] The insulating film 41 extends in the Z direction below the gate electrode 21. Figure 2 Similarly to the example of , the insulating film 41 is provided continuously from the gate insulating film 31 .

[0118] The insulating film 41 surrounds the conductor 42 and the insulating layer 243. The insulating layer 243 is in contact with the second layer 12 on the second layer 12. The second layer 12 is in contact with the bottom surface of the insulating layer 243 and a part of the side surface that is continuous from the bottom surface. Figure 2 Similarly to the silicide layer 45 of the semiconductor device 100 shown, the insulating layer 243 protrudes from the lower end of the insulating film 41 toward the second layer 12 .

[0119] If you contact later Fig. 27 As described above, the insulating layer 243 includes, for example, silicon oxide formed by the HDP-CVD method, and has a crystal structure different from that of the insulating film 41 including silicon oxide formed by the CVD method.

[0120] The semiconductor device 200 of this embodiment has the same effect as the semiconductor device 100 of the first embodiment. That is, in the cut-off state of the semiconductor device 200, the depletion layer of the third layer 13 extends to the entire third layer 13 between the structures 240, and since the concentration of the heavy metal 12a in the third layer 13 is low, the leakage current between the first electrode 1 and the second electrode 2 is small. The second layer 12 containing the heavy metal 12a having a higher concentration than the third layer 13 is provided at the lower part of the structure 240, and since the heavy metal 12a functions as a recombination center for minority carriers, the reverse recovery time of the semiconductor device 200 during diode operation is shortened.

[0121] In addition, in the semiconductor device 200, since the conductor 42 of the structure 240 functions as a field plate, the depletion layer of the third layer 13 extends to the entire third layer 13 between the structures 240. Therefore, the first conductivity type impurity concentration of the third layer 13 can be increased, and the on-resistance of the semiconductor device 200 can be reduced.

[0122] A method for manufacturing the semiconductor device 200 according to the present embodiment will be described.

[0123] Figure 24 to Figure 27 It is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment.

[0124] The method for manufacturing the semiconductor device 200 is different from the method for manufacturing the semiconductor device 100 of the first embodiment in the step of forming the second layer 12, but is the same in other steps. Figures 4 to 6 After the process, Figure 24 to Figure 27 The process shown, then apply Figure 11 to Figure 21 process.

[0125] In contact Figure 6 After the anisotropic processing step of the insulating film 1002 in the Z direction, as shown in FIG. Fig.24 As shown, a heavy metal region 1201 is formed. The heavy metal region 1201 is formed, for example, by ion implantation via the bottom surface 13aB1 of the intermediate layer 13a. In the ion implantation, by appropriately setting the dose and acceleration energy of the heavy metal 12a, the heavy metal region 1201 is formed from the bottom surface 13aB1 into the intermediate layer 13a. The upper end 1201T of the heavy metal region 1201 is in contact with the bottom surface 13aB1. The upper end 1201T is exposed from the bottom of the area surrounded by the side wall 1002aS of the insulating film 1002a.

[0126] Fig.25 FIG. 2 is a cross-section diagram showing a modified example of the method for manufacturing the semiconductor device 200, showing a case where the heavy metal region 1201a is formed at a position deeper than the heavy metal region 1201 and closer to the intermediate layer 13a. Fig.25 As shown, the heavy metal region 1201a is formed below the heavy metal region 1201 and continuously with the heavy metal region 1201. For example, during the ion implantation of the heavy metal 12a, the acceleration energy is increased compared to when the heavy metal region 1201 is formed, so that the heavy metal region 1201a is formed at an appropriate position.

[0127] like Fig.26 As shown, the heavy metal 12a in the heavy metal region 1201 is diffused into the intermediate layer 13a by heat treatment. The second layer 12 is formed in the region where the heavy metal 12a is diffused. The end 12T of the second layer 12 is exposed from the bottom of the region surrounded by the side wall 1002aS of the insulating film 1002a. The heat treatment can be performed by RTA method, for example.

[0128] like Fig. 27 As shown, an insulating layer 1005 is formed. The insulating layer 1005 is formed on the mask 1001, the insulating film 1002a, and the second layer 12. Fig.10 In the same process as described above, the insulating layer 1005 is formed by the HDP-CVD method. Thus, the insulating layer 243 is formed at the bottom of the region surrounded by the sidewall 1002aS. The insulating layer 243 has a crystal structure different from that of the insulating film 1002.

[0129] Later, contact through the app Figure 11 to Figure 21 The semiconductor device is formed by the described steps.

[0130] In the manufacturing method of the semiconductor device 200 of the present embodiment, in the formation of the second layer 12, the heavy metal region 1201 including the heavy metal 12a is formed in the lower part of the structure 240 using the ion implantation method. In the ion implantation method, by setting the dose and acceleration energy of the heavy metal 12a, the heavy metal region 1201 can be formed at an appropriate position in the intermediate layer 13a. Therefore, the side surface of the insulating film 41 of the structure 240 can be almost entirely formed into the second layer 12 having a low concentration of the heavy metal 12a, and it is possible to achieve both reduction of the leakage current and shortening of the reverse recovery time during the diode operation.

[0131] In this way, a semiconductor device having improved reverse recovery characteristics during diode operation can be realized.

[0132] The relative height of the impurity concentration between each semiconductor region in each embodiment described above can be confirmed, for example, using SCM (scanning electrostatic capacitance microscope). In addition, the carrier concentration in each semiconductor region can be regarded as equal to the activated impurity concentration in each semiconductor region. Therefore, the relative height of the carrier concentration between each semiconductor region can also be confirmed using SCM. In addition, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (secondary ion mass spectrometry).

[0133] Some embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0134] The embodiments include the following aspects.

[0135] (Note 1)

[0136] A semiconductor device comprising:

[0137] a first electrode;

[0138] a second electrode;

[0139] a semiconductor portion disposed between the first electrode and the second electrode;

[0140] a gate electrode provided in the semiconductor portion and extending from the second electrode to the first electrode; and

[0141] a structure provided between the gate electrode and the first electrode and extending from the gate electrode side to the first electrode side in the semiconductor portion;

[0142] The semiconductor unit includes:

[0143] A first layer of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode;

[0144] The second layer of the first conductivity type is disposed on the first layer and comprises a heavy metal;

[0145] The third layer of the first conductivity type is provided on the second layer and contains the heavy metal at a concentration lower than that of the second layer;

[0146] a fourth layer of the second conductivity type, provided on the third layer, facing the gate electrode via a gate insulating film, and electrically connected to the second electrode; and

[0147] The fifth layer of the first conductivity type is disposed on the fourth layer and is electrically connected to the second electrode;

[0148] The structure comprises:

[0149] a silicide layer, connected to the second layer;

[0150] an insulating layer, disposed on the silicide layer;

[0151] a conductor, disposed on the insulating layer, extending from below the gate electrode toward the insulating layer, and electrically isolated from the gate electrode; and

[0152] an insulating film provided between the conductor and the second layer and between the conductor and the third layer;

[0153] A bottom surface and at least a portion of a side surface of the silicide layer are in contact with the second layer.

[0154] (Note 2)

[0155] The semiconductor device according to Supplementary Note 1, wherein:

[0156] The conductor faces the third layer via the insulating film over the entire range from the upper end to the lower end of the conductor.

[0157] (Note 3)

[0158] The semiconductor device according to Supplement 1 or 2, wherein:

[0159] The insulating film is in contact with the second layer at a lower portion of the insulating film.

[0160] (Note 4)

[0161] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0162] The insulating layer has a different crystal structure from that of the insulating film.

[0163] (Note 5)

[0164] The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein:

[0165] The first layer has a first side provided with the second layer,

[0166] A first distance from a lower end of the insulating film to the first surface is longer than a second distance from a lower end of a bottom surface of the silicide layer to the first surface.

[0167] (Note 6)

[0168] A semiconductor device comprising:

[0169] a first electrode;

[0170] a second electrode;

[0171] a semiconductor portion disposed between the first electrode and the second electrode;

[0172] a gate electrode provided in the semiconductor portion and extending from the second electrode to the first electrode; and

[0173] a structure provided between the gate electrode and the first electrode and extending from the gate electrode side to the first electrode side in the semiconductor portion;

[0174] The semiconductor unit includes:

[0175] A first layer of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode;

[0176] The second layer of the first conductivity type is disposed on the first layer and comprises a heavy metal;

[0177] The third layer of the first conductivity type is provided on the second layer and contains the heavy metal at a concentration lower than that of the second layer;

[0178] a fourth layer of the second conductivity type, provided on the third layer, facing the gate electrode via a gate insulating film, and electrically connected to the second electrode; and

[0179] The fifth layer of the first conductivity type is disposed on the fourth layer and is electrically connected to the second electrode;

[0180] The structure comprises:

[0181] an insulating layer, on the second layer and in contact with the second layer;

[0182] a conductor, disposed on the insulating layer, extending from below the gate electrode toward the insulating layer, and electrically isolated from the gate electrode; and

[0183] an insulating film provided between the conductor and the second layer, and between the conductor and the third layer;

[0184] The insulating layer has a different crystal structure from that of the insulating film.

[0185] (Note 7)

[0186] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein:

[0187] The heavy metal includes either Pt or Au.

[0188] (Note 8)

[0189] The semiconductor device according to Supplementary Note 7, wherein:

[0190] The concentration of heavy metals in the second layer is 1×10 13 cm -3 ~1×10 20 cm -3 .

Claims

1. A semiconductor device, characterized in that: have: a first electrode; a second electrode; a semiconductor portion disposed between the first electrode and the second electrode; a gate electrode disposed in the semiconductor portion and extending from the second electrode to the first electrode; as well as a structure provided between the gate electrode and the first electrode and extending from the gate electrode side to the first electrode side in the semiconductor portion; The semiconductor unit includes: A first layer of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode; The second layer of the first conductivity type is disposed on the first layer and comprises a heavy metal; The third layer of the first conductivity type is provided on the second layer and contains the heavy metal at a concentration lower than that of the second layer; a fourth layer of the second conductivity type, provided on the third layer, facing the gate electrode via a gate insulating film, and electrically connected to the second electrode; and The fifth layer of the first conductivity type is provided on the fourth layer and is electrically connected to the second electrode; The structure comprises: a silicide layer, connected to the second layer; an insulating layer, disposed on the silicide layer; A conductor, disposed on the insulating layer, extending from below the gate electrode to the insulating layer, and electrically separated from the gate electrode; as well as an insulating film provided between the conductor and the second layer and between the conductor and the third layer; A bottom surface and at least a portion of a side surface of the silicide layer are in contact with the second layer.

2. The semiconductor device according to claim 1, wherein: The conductor faces the third layer via the insulating film over the entire range from the upper end to the lower end of the conductor.

3. The semiconductor device according to claim 1, wherein: The insulating film is in contact with the second layer at a lower portion of the insulating film.

4. The semiconductor device according to claim 1, wherein: The insulating layer has a different crystal structure from that of the insulating film.

5. The semiconductor device according to claim 1, wherein: The first layer has a first side provided with the second layer, A first distance from a lower end of the insulating film to the first surface is longer than a second distance from a lower end of a bottom surface of the silicide layer to the first surface.

6. A semiconductor device, characterized in that: have: a first electrode; a second electrode; a semiconductor portion disposed between the first electrode and the second electrode; a gate electrode disposed in the semiconductor portion and extending from the second electrode to the first electrode; as well as a structure provided between the gate electrode and the first electrode and extending from the gate electrode side to the first electrode side in the semiconductor portion; The semiconductor unit includes: A first layer of a first conductivity type, disposed on the first electrode and electrically connected to the first electrode; The second layer of the first conductivity type is disposed on the first layer and comprises a heavy metal; The third layer of the first conductivity type is provided on the second layer and contains the heavy metal at a concentration lower than that of the second layer; a fourth layer of the second conductivity type, provided on the third layer, facing the gate electrode via a gate insulating film, and electrically connected to the second electrode; and The fifth layer of the first conductivity type is provided on the fourth layer and is electrically connected to the second electrode; The structure comprises: an insulating layer, on the second layer and in contact with the second layer; A conductor, disposed on the insulating layer, extending from below the gate electrode to the insulating layer, and electrically separated from the gate electrode; as well as an insulating film provided between the conductor and the second layer, and between the conductor and the third layer; The insulating layer has a different crystal structure from that of the insulating film.

7. The semiconductor device according to claim 1, wherein: The heavy metal includes either Pt or Au.

8. The semiconductor device according to claim 7, wherein: The concentration of heavy metals in the second layer is 1×10 13 cm -3 ~1×10 20 cm -3 .

9. The semiconductor device according to claim 6, wherein: The heavy metal includes either Pt or Au.

10. The semiconductor device according to claim 9, wherein: The concentration of heavy metals in the second layer is 1×10 13 cm -3 ~1×10 20 cm -3 .

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