A Double Buried Gate Power MOSFET Structure Based on Charged Plasma

Abstract

This invention relates to power MOSFETs, and particularly to a double-buried-gate power MOSFET structure based on charged plasma. From top to bottom, it includes a p-type body region and an n-type drift region. Polysilicon layers with oxide coatings are respectively disposed at the upper, lower, and inner surfaces of the n-type drift region. n+ charged plasma regions are formed at the left and right ends of the p-type body region, and a p+ charged plasma region is formed at the top of the p-type body region. The substrate is metallized to form the drain. The outer polysilicon gate layer is metallized to form the gate. The outer side of the n+ charged plasma region is metallized to form the first source, and the p+ charged plasma region is metallized to form the second source. Compared with existing VDMOS structures, this invention has a smaller thermal budget, lower manufacturing complexity, lower on-resistance and charge, higher power density, and better high-frequency performance.

Description

Technical Field

[0001] This invention relates to power MOSFETs, and more particularly to a double buried gate power MOSFET structure based on charge plasma. Background Technology

[0002] To achieve ideal switching states, power MOSFET devices need to have lower resistance in the on-state and higher breakdown voltage in the off-state. For better high-frequency characteristics, the device should have lower parasitic capacitance (Cgs) and lower on-resistance, reducing conduction losses. The trench-gate power MOSFET is currently the most widely used power MOSFET structure. This structure forms a vertical gate structure by trenching in the drift region. This structure eliminates the parasitic JFET present in the DMOS structure; secondly, the deep trench in the drift region reduces the drift region resistance of the device. Compared to lateral structures, trench MOSFET structures use a low effective area design, thus having low on-resistance and high power density. However, trench-gate MOSFETs also have three limitations. One is the high gate-drain coupling caused by the reduced distance between the gate and drain. This increases parasitic gate-drain capacitance, thereby reducing the switching performance of the device; secondly, the n+source-p body and n-drift region form a parasitic BJT, interfering with the normal behavior of the transistor in the OFF state; and thirdly, it requires both low on-resistance and high breakdown voltage. Improving all three parameters of power devices to enhance their advantages remains a challenge for device designers. Summary of the Invention

[0003] To reduce device manufacturing complexity and cost, minimize the risk of random doping and high-abrupt junction formation, and improve parasitic transistor effects, this invention proposes a double-buried-gate power MOSFET structure based on charge plasma, comprising:

[0004] Epitaxial layer growth is performed on an n+ type substrate to form an n- type drift region;

[0005] Oxide layer growth and polysilicon deposition are performed sequentially on the surface of the n-type drift region to form an oxide layer and a polysilicon gate layer;

[0006] The oxide layer and polysilicon gate layer are etched. After etching, the oxide layer and polysilicon gate layer at the left and right ends are retained, and the oxide layer and polysilicon gate layer at the middle position are removed.

[0007] After etching, a gate oxide layer is deposited on the surface and excess oxide layer on the middle position and n-type drift region is etched, so that the upper surface and inner side of the polysilicon gate layer are wrapped with silicon dioxide.

[0008] Continue epitaxial growth in the n-type drift region and on the upper surface of the oxide layer, and perform p-type doping on the epitaxial layer above the oxide layer to form a p-type body region;

[0009] An n+ charged plasma region is formed at both ends of the p-type body region, and a p+ charged plasma region is formed at the top of the p-type body region.

[0010] The substrate is metallized to form the drain; the outer polysilicon gate layer is metallized to form the gate; the outer side of the n+ charged plasma region is metallized to form the first source, and the p+ charged plasma region is metallized to form the second source.

[0011] Compared with existing VDMOS structures, the present invention has a smaller thermal budget, lower manufacturing complexity, lower on-resistance and charge, higher power density, and better high-frequency performance. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of the double buried gate power MOSFET device based on charge plasma of the present invention;

[0013] Figure 2 This is a flowchart illustrating the manufacturing process of the double buried gate power MOSFET device based on charge plasma of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This invention proposes a double buried-gate power MOSFET structure based on charged plasma, comprising:

[0016] Epitaxial layer growth is performed on an n+ type substrate to form an n- type drift region;

[0017] Oxide layer growth and polysilicon deposition are performed sequentially on the surface of the n-type drift region to form an oxide layer and a polysilicon gate layer;

[0018] The oxide layer and polysilicon gate layer are etched. After etching, the oxide layer and polysilicon gate layer at the left and right ends are retained, and the oxide layer and polysilicon gate layer at the middle position are removed.

[0019] After etching, a gate oxide layer is deposited on the surface and excess oxide layer on the middle position and n-type drift region is etched, so that the upper surface and inner side of the polysilicon gate layer are wrapped with silicon dioxide.

[0020] Continue epitaxial growth in the n-type drift region and on the upper surface of the oxide layer, and perform p-type doping on the epitaxial layer above the oxide layer to form a p-type body region;

[0021] An n+ charged plasma region is formed at both ends of the p-type body region, and a p+ charged plasma region is formed at the top of the p-type body region.

[0022] The substrate is metallized to form the drain; the outer polysilicon gate layer is metallized to form the gate; the outer side of the n+ charged plasma region is metallized to form the first source, and the p+ charged plasma region is metallized to form the second source.

[0023] This embodiment proposes a charge plasma dual-buried-gate power MOSFET structure. First, it uses metal electrodes on a silicon thin film to generate induced charge plasma using the work function difference between metal and semiconductor to realize the n+ source region and p+ body region, reducing the risk of high-abrupt junctions and random doping during manufacturing, reducing the high-temperature process required for doping, and resulting in a lower thermal budget. Second, due to the presence of Gaussian hole plasma in the p-type body region, the doping concentration in the body region can be higher, the on-resistance of the device is lower, and the Barley figure of merit (FOM1 = BV / Rsp) of the device is improved by 10%. Third, the reduced coupling between the gate and drain reduces the gate-drain coupling capacitance, resulting in a better Barley figure of merit at high frequencies, FOM2 = Rsp.Qsp. At the same time, since there is no doping in the n+ source region and p+ body region, the transistor effect can be effectively suppressed.

[0024] like Figure 1 This invention proposes a dual-buried-gate power MOSFET structure based on charged plasma. From bottom to top, it consists of an n-type drift region and a p-type body region. Polysilicon layers are formed at the left and right ends of the upper part of the n-type drift region, giving the n-type drift region a convex shape. The surfaces of the polysilicon layers that contact the n-type drift region and the p-type body region are isolated by an oxide layer. N+ charged plasma regions are formed at the left and right ends of the p-type body region, and a p+ charged plasma region is formed at the top of the p-type body region. The substrate is metallized to form the drain. The outer polysilicon gate layer is metallized to form the gate. The outer side of the n+ charged plasma region is metallized to form the first source, and the p+ charged plasma region is metallized to form the second source.

[0025] As an optional implementation, the n-type drift region is phosphorus ion doped with a doping concentration of 6.8 × 10⁻⁶. 15 / cm 3 ~7.1×10 15 / cm 3

[0026] As an optional implementation, the p-type body region is boron ion doped with a doping concentration of 1.0 × 10⁻⁶. 16 / cm3 ~1.3×10 16 / cm 3 .

[0027] This embodiment also provides the specific dimensions of a charge plasma-based double buried gate power MOSFET structure. The overall dimensions of the charge plasma-based double buried gate power MOSFET structure are 3um × 7um. The thickness of the polysilicon layer is about 0.1um, the width is about 0.7 to 0.75um, and the polysilicon layer is about 50nm thick. The thickness of the p-type body region is about 0.5um.

[0028] In this embodiment, the oxide layer material is silicon dioxide, the first source electrode is metallized with TiW material, and the second source electrode is metallized with Pt material.

[0029] This embodiment also provides, for example Figure 2 The fabrication process of a charge plasma-based double buried gate power MOSFET structure shown includes the following steps:

[0030] (1) Perform epitaxial layer growth, that is, perform epitaxial layer growth on n+ type substrate, which will form n- type drift region after subsequent doping;

[0031] (2) An oxide layer is grown on the surface of the epitaxial layer;

[0032] (3) Polycrystalline silicon is deposited on the oxide layer;

[0033] (4) Select to remove polysilicon and oxide layer etching, that is, retain the oxide layer and polysilicon gate layer at the left and right ends, and remove the oxide layer and polysilicon gate layer at the middle position;

[0034] (5) Deposit the gate oxide layer, that is, deposit an oxide layer on the surface of the polysilicon gate layer and epitaxial layer;

[0035] (6) Select the oxide layer etching, that is, etch the excess oxide layer in the middle position and the n-type drift region, so that the upper surface and inner side of the polysilicon gate layer are wrapped with silicon dioxide.

[0036] (7) Continue the growth of the silicon epitaxial layer;

[0037] (8) The epitaxial layer above the polysilicon layer is doped to form a p-type body region, and the region below the upper surface of the polysilicon layer is doped to form an n-type drift region;

[0038] (9) Metallize the substrate to form the drain; metallize the outer polysilicon gate layer to form the gate; metallize the outer side of the n+ charged plasma region to form the first source, and metallize the p+ charged plasma region to form the second source.

[0039] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A charge-plasma-based double buried gate power MOSFET structure, characterized in that, The method comprises the following steps: forming an n-type drift region by epitaxial layer growth on an n+ substrate; forming an oxide layer and a polysilicon gate layer by sequentially growing an oxide layer and depositing a polysilicon layer on the surface of the n-type drift region; etching the oxide layer and the polysilicon gate layer, and retaining the oxide layer and the polysilicon gate layer at the left and right ends and removing the oxide layer and the polysilicon gate layer at the middle; depositing a gate oxide layer on the etched surface and etching the oxide layer at the middle and the n-type drift region, so that the upper surface of the polysilicon gate layer and the inner side are wrapped by silicon dioxide; continuing epitaxial layer growth on the upper surface of the n-type drift region and the oxide layer, and p-type doping the epitaxial layer above the oxide layer to form a p-type body region; forming n+ charge plasma regions at the left and right ends of the p-type body region, and forming a p+ charge plasma region at the top of the p-type body region; metallizing the substrate to form a drain, metallizing the outer polysilicon gate layer to form a gate, metallizing the n+ charge plasma region outside to form a first source, and metallizing the p+ charge plasma region to form a second source.

2. A charge plasma based double trench gate power MOSFET structure as claimed in claim 1, wherein, The n-type drift region is doped with phosphorus ions at a doping concentration of 6.8 x 1014 / cm3~7.1 x 1014 / cm3. 15 / cm 3 ~7.1 x 1014 / cm3. 15 / cm 3 .

3. A charge plasma based double trench gate power MOSFET structure as claimed in claim 1, wherein, The thickness of the polysilicon gate layer is 0.1 um.

4. A charge plasma based double trench gate power MOSFET structure as claimed in claim 1, wherein, The width of the oxide layer wrapping each polysilicon layer is 0.75-0.8 um, and the thickness of the oxide layer between the polysilicon layer and the p-type body region or between the polysilicon layer and the n-type drift region is 50 nm.

5. A charge plasma based double trench gate power MOSFET structure as claimed in claim 1, wherein, The oxide layer material is silicon dioxide.

6. A charge plasma based double trench gate power MOSFET structure as claimed in claim 1, wherein, The p-type body region is boron ion doped with a doping concentration of 1.0 x 10 16 / cm 3 ~ 1.3 x 10 16 / cm 3 .

7. A charge plasma based double trench gate power MOSFET structure as claimed in claim 1, wherein, The thickness of the p-type body region is 0.5 um.

8. A charge plasma based double trench gate power MOSFET structure as claimed in claim 1, wherein, The first source is metallized with TiW material, and the second source is metallized with Pt material.

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