Semiconductor structure and preparation method thereof
By forming an isolation layer and an epitaxial layer on the silicon carbide substrate, and etching to form corresponding trenches to cover the inner side wall of the trench, the problem of insufficient quality of the insulating material layer at the bottom of the trench gate is solved, and the performance and reliability of semiconductor devices are significantly improved.
Patent Information
- Application Number
- CN202411678553.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-03-18
AI Technical Summary
When a trench gate is formed in a silicon carbide substrate, the quality of the insulating material layer at the bottom of the trench often has defects, which affects the performance and reliability of semiconductor devices.
The epitaxial layer is formed by first forming an isolation layer on the substrate, then covering the isolation layer, and etching the epitaxial layer at a specific location to form a trench corresponding to the isolation layer one by one. Then, a gate oxide layer is formed on the inner side wall of the trench, so that it contacts the surface of the isolation layer away from the substrate, thereby improving the insulation quality of the bottom of the trench gate.
By increasing the thickness of the isolation layer at the bottom of the trench gate, the quality of the insulating material layer is significantly improved, thereby improving the performance and reliability of semiconductor devices, especially in device degradation, meeting the strict reliability needs.
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Figure CN119653838A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art
[0002] With the continuous development of semiconductor processing technology, semiconductor devices are increasingly used in the fields of electronics, communications, etc. due to their smaller size, higher performance, and higher conversion efficiency. By forming a trench gate in the substrate, the size of the semiconductor device can be further reduced and the performance of the semiconductor device can be improved.
[0003] However, when forming a trench gate in a substrate, especially in a silicon carbide substrate, the quality of the insulating material layer at the bottom of the trench often has defects. For example, the insulating material layer is too thin, which affects the performance and reliability of the device.
[0004] Therefore, how to improve the quality of the material layer with an insulating function at the bottom of the trench gate, thereby improving the performance and reliability of the semiconductor device is an urgent problem to be solved. Summary of the invention
[0005] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to improve the quality of the material layer with an insulating function at the bottom of the trench gate, thereby improving the performance and reliability of the semiconductor device.
[0006] In order to achieve the above objectives, on the one hand, some embodiments of the present application provide a method for preparing a semiconductor structure, comprising the following steps:
[0007] providing a substrate;
[0008] forming a plurality of isolation layers arranged at intervals on a substrate;
[0009] forming an epitaxial layer covering the isolation layer;
[0010] Etching the epitaxial layer to form a plurality of grooves arranged at intervals; wherein the grooves expose the surface of the isolation layer away from the substrate, and the grooves are arranged in a one-to-one correspondence with the isolation layer;
[0011] forming a gate oxide layer covering the inner sidewall of the trench; wherein the gate oxide layer is in contact with a surface of the isolation layer facing away from the substrate;
[0012] The trench is filled to form a gate.
[0013] Among them, the thickness range of the isolation layer includes:
[0014] In some embodiments of the present application, the epitaxial layer includes: a first doped epitaxial layer and a second doped epitaxial layer.
[0015] The epitaxial layer forming the capping isolation layer includes:
[0016] forming a first doped epitaxial layer covering the isolation layer;
[0017] A second doped epitaxial layer is formed on a side of the first doped epitaxial layer facing away from the substrate; wherein the first doping includes N-type doping; and the second doping includes P-type doping.
[0018] In some other embodiments of the present application, the epitaxial layer includes: a first doped epitaxial layer.
[0019] The epitaxial layer forming the capping isolation layer includes:
[0020] A first doped epitaxial layer is formed covering the isolation layer.
[0021] In some embodiments of the present application, the inclination angle range of the side wall of the isolation layer includes: 45° to 90°.
[0022] In some embodiments of the present application, the gate oxide layer also covers the surface of the epitaxial layer facing away from the substrate.
[0023] While forming the gate oxide layer covering the sidewall of the trench, the method also includes: synchronously forming the gate oxide layer covering the surface of the epitaxial layer away from the substrate.
[0024] In some embodiments of the present application, the method for preparing a semiconductor structure further includes the following steps:
[0025] forming first doped regions arranged at intervals in the second doped epitaxial layer;
[0026] A second heavily doped region is formed at least between the first doped regions.
[0027] In some other embodiments of the present application, the method for preparing the semiconductor structure further includes the following steps:
[0028] forming a second doped region in the first doped epitaxial layer;
[0029] forming first doped regions arranged at intervals in the second doped regions;
[0030] A second heavily doped region is formed at least between the first doped regions.
[0031] In some embodiments of the present application, the method for preparing a semiconductor structure further includes the following steps:
[0032] forming a dielectric material layer covering the gate oxide layer on a surface of the gate away from the isolation layer;
[0033] The dielectric material layer is etched to form a metal contact hole, wherein the metal contact hole exposes a surface of the second heavily doped region facing away from the substrate and a surface of a portion of the first heavily doped region facing away from the substrate.
[0034] On the other hand, some embodiments of the present application further provide a semiconductor structure, including: a substrate, a plurality of isolation layers arranged at intervals, an epitaxial layer, a plurality of grooves arranged at intervals, a gate oxide layer and a gate. The plurality of isolation layers arranged at intervals are located on one side of the substrate. The epitaxial layer is located on one side of the substrate and covers the isolation layer. The plurality of grooves arranged at intervals are located in the epitaxial layer. The grooves expose the surface of the isolation layer away from the substrate, and the grooves and the isolation layer are arranged in a one-to-one correspondence. The gate oxide layer covers the sidewalls of the grooves. The gate oxide layer contacts the surface of the isolation layer away from the substrate. The gate is located in the groove.
[0035] Among them, the thickness range of the isolation layer includes:
[0036] In some embodiments of the present application, the epitaxial layer includes: a first doped epitaxial layer and a second doped epitaxial layer, wherein the first doped epitaxial layer is located on one side of the substrate and covers the isolation layer, and the second doped epitaxial layer is located on the side of the first doped epitaxial layer away from the substrate.
[0037] The embodiments of the present application may or at least have the following advantages:
[0038] In the embodiment of the present application, before forming an epitaxial layer on the substrate, an isolation layer is first formed on the substrate to serve as isolation for the bottom of the subsequent trench. Then, an epitaxial layer covering the isolation layer is formed on the substrate, and then the epitaxial layer is etched at a specific position to form a trench corresponding to the isolation layer. Finally, a gate oxide layer is formed to cover the inner sidewall of the trench, and the gate oxide layer is in contact with the surface of the isolation layer facing away from the substrate. The thickness range of the isolation layer includes: In this way, the bottom of the trench gate has an isolation layer that is much higher than the gate insulation requirement, which improves the quality of the insulating material layer at the bottom of the trench, thereby improving the performance of the semiconductor device, especially the degradation of the semiconductor device can be greatly improved to meet stringent reliability requirements.
[0039] In addition, since the isolation layer only exists at the bottom of the trench, it will not affect the threshold voltage and driving power consumption of the gate drive.
[0040] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0042] Figure 1 Schematic diagram of the external and internal Weibull distribution of transistors with different substrate materials in the related art.
[0043] Figure 2 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0044] Figure 3 A flowchart of another semiconductor structure preparation method provided in an embodiment of the present application;
[0045] Figure 4 A flowchart of another method for preparing a semiconductor structure provided in an embodiment of the present application;
[0046] Figure 5 A flowchart of another method for preparing a semiconductor structure provided in an embodiment of the present application;
[0047] Figure 6 A flow chart of forming a metal contact hole in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0048] Figure 7 A schematic cross-sectional view of a structure obtained in S100 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0049] Figure 8 A schematic cross-sectional view of a structure obtained after forming an isolation material layer in a semiconductor structure preparation method provided in an embodiment of the present application;
[0050] Fig. 9 A schematic cross-sectional view of a structure obtained in S200 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0051] Fig.10 A schematic cross-sectional view of a structure obtained in S320 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0052] Fig.11 A schematic cross-sectional view of a structure obtained in S400 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0053] Fig.12 A schematic cross-sectional view of a structure obtained in S500 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0054] Fig.13 A schematic cross-sectional view of a structure obtained after a gate material layer is formed in a semiconductor structure preparation method provided in an embodiment of the present application;
[0055] Fig.14 A schematic cross-sectional view of a structure obtained in S600 of a semiconductor structure preparation method provided in an embodiment of the present application;
[0056] Fig.15 A schematic cross-sectional view of a structure obtained in S800 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0057] Fig.16 A schematic cross-sectional view of a structure obtained in S1000 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0058] Fig.17 A schematic cross-sectional view of a structure obtained in S300' in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0059] Fig.18 It is a schematic cross-sectional structure diagram of another structure obtained in S400 in a semiconductor structure preparation method provided in one embodiment of the present application;
[0060] Fig.19 It is a schematic cross-sectional structure diagram of another structure obtained in S500 in a semiconductor structure preparation method provided in one embodiment of the present application;
[0061] Fig. 20 It is a schematic cross-sectional structure diagram of another structure obtained in S600 in a semiconductor structure preparation method provided in an embodiment of the present application;
[0062] Fig.21 It is a schematic cross-sectional structure diagram of a structure obtained in S800' in a semiconductor structure preparation method provided in an embodiment of the present application;
[0063] Fig. 22 It is a schematic cross-sectional structural diagram of another structure obtained in S1000 in a semiconductor structure preparation method provided in one embodiment of the present application.
[0064] Description of reference numerals:
[0065] 1-substrate; 2-isolation layer; 20-isolation material layer; 3-epitaxial layer; 31-first doped epitaxial layer; 311-second doped region; 32-second doped epitaxial layer; 321-first doped region; 322 second heavily doped region; 4-gate oxide layer; 5-gate; 50-gate material layer; 6-dielectric layer; K-metal contact hole; G-groove. DETAILED DESCRIPTION
[0066] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0068] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.
[0069] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0070] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0071] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).
[0072] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.
[0073] With the continuous development of semiconductor processing technology, semiconductor devices are increasingly used in the fields of electronics, communications, etc. due to their smaller size, higher performance, and higher conversion efficiency. Various power devices represented by insulated gate bipolar transistors (IGBT) and metal oxide semiconductor field effect transistors (MOSFET) usually form a trench gate structure by digging trenches on silicon (Si) or silicon carbide (SiC) substrates to reduce chip area and improve device performance.
[0074] SiC, a wide bandgap semiconductor material, has become the new favorite of high-power devices, especially 4H-SiC, which is recognized as the most suitable for device manufacturing, because its bandgap width is about 3 times that of Si, the breakdown electric field strength is about 10 times that of Si, the electron saturation drift rate is about 2 times that of Si, and the thermal conductivity is about 3 times that of Si. These electrical properties determine that SiC can withstand higher voltages with lower resistivity and thinner drift regions, thereby obtaining high-voltage power devices with greater current density and lower transmission loss.
[0075] The production and epitaxial technology of high-quality 4H-SiC single crystal substrates has also been rapidly developed, and process technologies including donor and acceptor doping have also been realized. However, one difficulty in the production process of SiC devices is the growth of the gate insulating layer, that is, the oxide film. Due to the presence of the "C" element, it is easy to remain on the oxide film and the oxide film / SiC interface when growing the oxide film, and it is not easy to completely remove it. In addition, a large number of interface state densities and defects on SiC will cause quality defects in the oxide film, thereby affecting the performance and reliability of the device. At present, most of the products on the market are planar gate products. The main reason is that it is more difficult to grow a good quality oxide film at the corners of the trench structure of the trench gate to insulate the gate. The defective oxide layer can be caused by deformation caused by defects in the epitaxial layer or substrate, resulting in thinning of the oxide layer (physical defects), or it can be caused by the presence of metal impurities, particles or pores, resulting in a decrease in dielectric field strength, resulting in thinning of the oxide layer (electrical defects).
[0076] Also, for the trench gate process technology applicable to Si, when making trench gate on SiC substrate, the gate insulation oxide film quality at the bottom of the trench is often poor, which affects the performance and reliability of the device. For example: please refer to Figure 1 , Figure 1 Schematic diagram of the extrinsic and intrinsic Weibull distribution of SiC-based MOSFET and Si-based MOSFET with the same oxide layer thickness and area. F refers to the cumulative failure probability and t refers to time. The chip life refers to the time that the device must work normally in the application under normal use conditions. Due to the higher electrical defect density, the extrinsic defect density of the gate oxide layer of the SiC-based MOSFET is 3-4 orders of magnitude higher. That is, when a trench gate is formed in the substrate, especially in a silicon carbide substrate, the quality of the insulating material layer at the bottom of the trench is often defective, for example, the insulating material layer is too thin, which affects the performance and reliability of the device.
[0077] Therefore, how to improve the quality of the material layer with an insulating function at the bottom of the trench gate, thereby improving the performance and reliability of the semiconductor device is an urgent problem to be solved.
[0078] Based on this, it is necessary for the embodiments of the present application to provide a semiconductor structure and a method for preparing the same to improve the quality of the insulating material layer at the bottom of the trench gate, thereby improving the performance and reliability of the semiconductor device.
[0079] See also Figure 2 Some embodiments of the present application provide a method for preparing a semiconductor structure, including steps S100 to S600.
[0080] S100 , providing a substrate.
[0081] S200, forming a plurality of isolation layers arranged at intervals on a substrate.
[0082] S300, forming an epitaxial layer covering the isolation layer.
[0083] S400, etching the epitaxial layer to form a plurality of trenches arranged at intervals.
[0084] The groove exposes a surface of the isolation layer facing away from the substrate, and the groove and the isolation layer are arranged in a one-to-one correspondence.
[0085] S500, forming a gate oxide layer covering the inner sidewall of the trench.
[0086] The gate oxide layer is in contact with a surface of the isolation layer facing away from the substrate.
[0087] S600 , filling the trench to form a gate.
[0088] Among them, the thickness range of the isolation layer includes:
[0089] In the embodiment of the present application, before forming an epitaxial layer on the substrate, an isolation layer is first formed on the substrate to serve as isolation for the bottom of the subsequent trench. Then, an epitaxial layer covering the isolation layer is formed on the substrate, and then the epitaxial layer is etched at a specific position to form a trench corresponding to the isolation layer. Finally, a gate oxide layer is formed to cover the inner sidewall of the trench, and the gate oxide layer is in contact with the surface of the isolation layer facing away from the substrate. The thickness range of the isolation layer includes: In this way, the bottom of the trench gate has an isolation layer that is much higher than the gate insulation requirement, which improves the quality of the insulating material layer at the bottom of the trench, thereby improving the performance of the semiconductor device, especially the degradation of the semiconductor device can be greatly improved to meet stringent reliability requirements.
[0090] In addition, since the isolation layer only exists at the bottom of the trench, it will not affect the threshold voltage and driving power consumption of the gate drive.
[0091] In some embodiments, the inclination angle of the sidewall of the isolation layer ranges from 45° to 90°.
[0092] In some embodiments, the epitaxial layer includes: a first doped epitaxial layer and a second doped epitaxial layer.
[0093] See also Figure 3 Step S300 of forming an epitaxial layer covering the isolation layer includes steps S310 to S320.
[0094] S310 , forming a first doped epitaxial layer covering the isolation layer.
[0095] S320 , forming a second doped epitaxial layer on a side of the first doped epitaxial layer facing away from the substrate.
[0096] The first doping includes N-type doping; the second doping includes P-type doping.
[0097] Accordingly, in some embodiments, see Figure 4 , the method for preparing the semiconductor structure also includes steps S700 to S800.
[0098] S700 , forming first doped regions arranged at intervals in the second doped epitaxial layer.
[0099] S800, forming a second heavily doped region at least between the first doped regions.
[0100] In some other embodiments, the epitaxial layer includes: a first doped epitaxial layer.
[0101] Step S300 of forming an epitaxial layer covering the isolation layer includes step S300 ′: forming a first doped epitaxial layer covering the isolation layer.
[0102] Accordingly, in some embodiments, see Figure 5 , the method for preparing the semiconductor structure further includes steps S700 ′ to S800 ′.
[0103] S700 ′, forming a second doped region in the first doped epitaxial layer.
[0104] S750', forming first doped regions arranged at intervals in the second doped regions.
[0105] S800 ′, forming a second heavily doped region at least between the first doped regions.
[0106] In some embodiments, the gate oxide layer also covers the surface of the epitaxial layer facing away from the substrate.
[0107] While forming the gate oxide layer covering the sidewalls of the trench in step S500 , the step also includes: simultaneously forming a gate oxide layer covering the surface of the epitaxial layer facing away from the substrate.
[0108] It should be noted that, in the above-mentioned embodiments, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps. The method is limited to being able to achieve the preparation of the corresponding semiconductor structure.
[0109] Based on this, with respect to the methods for preparing semiconductor structures provided in some of the above embodiments, the following embodiments of the present application illustrate some methods as some possible implementation methods of the above preparation methods.
[0110] In some embodiments of this application, please refer to Figure 6 The method for preparing the semiconductor structure also includes S900 to S1000.
[0111] S900, forming a dielectric material layer covering the gate oxide layer on a surface of the gate away from the isolation layer.
[0112] S1000, etching the dielectric material layer to form a metal contact hole. The metal contact hole exposes the surface of the second heavily doped region facing away from the substrate and a portion of the surface of the first heavily doped region facing away from the substrate.
[0113] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiment, Figure 7 to Figure 16 The preparation method is described in detail.
[0114] In step S100, refer to Figure 7 , providing a substrate 1.
[0115] In some examples, the material of the substrate 1 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, referred to as DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and the embodiments of the present application are not limited here.
[0116] In step S200, refer to Figure 8 and Fig. 9 , a plurality of isolation layers 2 arranged at intervals are formed on the substrate 1.
[0117] In some examples, forming a plurality of spaced-apart isolation layers 2 on a substrate 1 includes:
[0118] See also Figure 8 , forming an isolation material layer 20 on the substrate 1;
[0119] See also Fig. 9 , etching the isolation material layer 20 to form a plurality of isolation layers 2 arranged at intervals on the substrate 1 .
[0120] For example, the material of the isolation layer 2 includes oxide. For example, the material of the isolation layer 2 may be silicon oxide.
[0121] For example, the thickness range of the isolation layer 2 includes but is not limited to: For example, the thickness of the isolation layer 2 may be: or etc.
[0122] For example, a deposition process may be used to form the isolation material layer 20 on the substrate 1. For example, a chemical vapor deposition process may be used to form a thick isolation material layer 20 on the substrate 1.
[0123] For example, a photoresist material layer may be coated on the isolation material layer 20 first, and the photoresist material layer is subjected to a series of steps such as exposure and development to form a patterned photoresist layer, wherein the patterned photoresist layer has a pattern defining the isolation layer 2, the photoresist may be a positive photoresist or a negative photoresist, and the development method may be a positive development or a negative development. In this way, an etching process may be used to etch the isolation material layer 20 using the patterned photoresist layer as a mask to form the isolation layer 2.
[0124] In some embodiments, the inclination angle of the side wall of the isolation layer 2 includes, but is not limited to, 45° to 90°. For example, the inclination angle of the side wall of the isolation layer 2 may be 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85° or 90°, etc.
[0125] In step S310, refer to Fig.10 , forming a first doped epitaxial layer 31 covering the isolation layer 2. The first doping includes N-type doping.
[0126] In some examples, the first doped epitaxial layer 31 includes, but is not limited to, an N-type doped silicon carbide layer.
[0127] In step S320, please continue to refer to Fig.10 A second doped epitaxial layer 32 is formed on the side of the first doped epitaxial layer 31 away from the substrate 1 . The second doping includes P-type doping. The epitaxial layer 3 includes: a first doped epitaxial layer 31 and a second doped epitaxial layer 32 .
[0128] In some examples, the second doped epitaxial layer 32 includes, but is not limited to, a P-type doped silicon carbide layer.
[0129] In the embodiment of the present application, an N-type doped epitaxial layer is formed first, and then a P-type doped epitaxial layer is formed. That is, the method of growing epitaxial layers with different doping twice can save the subsequent multi-step implantation and thermal activation process of forming an N-type doped region, thereby reducing the preparation cost.
[0130] In step S400, refer to Fig.11 , the epitaxial layer 3 is etched to form a plurality of spaced trenches G. The trenches G expose the surface of the isolation layer 2 facing away from the substrate 1, and the trenches G and the isolation layer 2 are arranged one by one.
[0131] For example, a photoresist material layer may be coated on the second doped epitaxial layer 32 first, and the photoresist material layer is subjected to a series of steps such as exposure and development to form a patterned photoresist layer, wherein the patterned photoresist layer has a pattern that defines the position and shape of the groove G. The photoresist may be a positive photoresist or a negative photoresist, and the development method may be a positive development or a negative development. In this way, the epitaxial layer may be etched using the patterned photoresist layer as a mask to form the groove G by an etching process.
[0132] In step S500, refer to Fig.12 , forming a gate oxide layer 4 covering the inner side wall of the trench G.
[0133] The gate oxide layer 4 is in contact with the surface of the isolation layer 2 facing away from the substrate 1 .
[0134] In some embodiments, the gate oxide layer 4 also covers the surface of the epitaxial layer 3 facing away from the substrate 1 .
[0135] In some examples, while forming the gate oxide layer 4 covering the sidewalls of the trench G, the process also includes: simultaneously forming the gate oxide layer 4 covering the surface of the epitaxial layer 3 facing away from the substrate 1 .
[0136] In some examples, the gate oxide layer 4 may be formed by a thermal oxidation process. Here, since the gate oxide layer 4 only needs to grow on the sidewalls of the trench, it is easy to obtain a gate insulating layer 4 of good quality by controlling the process.
[0137] For example, the material of the gate oxide layer 4 includes but is not limited to oxide. For example, the material of the gate oxide layer 4 may be silicon oxide.
[0138] In step S600, please refer to Fig.13 and Fig.14 , filling the trench G to form a gate 5.
[0139] In some examples, filling the trench G to form the gate 5 includes:
[0140] See also Fig.13 , filling the trench G with a deposition process to form a gate material layer 50;
[0141] See also Fig.14 , remove part of the gate material layer 50 and retain the gate material layer 50 in the trench G as the gate 5.
[0142] For example, the excess gate material layer 50 may be removed by using a chemical mechanical polishing process or an etching process.
[0143] For example, the material of the gate 5 includes but is not limited to polysilicon. For example, the material of the gate 5 can be self-doped high-concentration N-type polysilicon.
[0144] In step S700, please refer to Fig.15 , first doped regions 321 arranged at intervals are formed in the second doped epitaxial layer 32 .
[0145] For example, the first doping region 321 may be formed by using a multiple ion implantation process and a thermal activation process.
[0146] Illustratively, the first doping region 321 includes an N-type doping region.
[0147] In step S800, please continue to refer to Fig.15 , a second heavily doped region 322 is formed at least between the first doped regions 321 .
[0148] For example, the second heavily doped region 322 may be formed by using multiple ion implantation processes and a thermal activation process.
[0149] Illustratively, the second heavily doped region 322 includes a P-type heavily doped region.
[0150] In step S900, please refer to Fig.16 A dielectric material layer (not shown in the figure) covering the gate oxide layer 4 is formed on the surface of the gate 5 away from the isolation layer 2 .
[0151] In some examples, a dielectric material layer covering the gate oxide layer 4 is formed on a surface of the gate 5 facing away from the isolation layer 2 by a deposition process.
[0152] In step S1000, please continue to refer to Fig.16 , the dielectric material layer is etched to form a metal contact hole K, thereby obtaining a dielectric layer 6. The metal contact hole K exposes the surface of the second heavily doped region 322 facing away from the substrate 1 and the surface of a portion of the first heavily doped region 321 facing away from the substrate 1.
[0153] In some examples, a photoresist material layer may be coated on the dielectric material layer first, and the photoresist material layer undergoes a series of steps such as exposure and development to form a patterned photoresist layer, wherein the patterned photoresist layer has a pattern that defines the position and shape of the metal contact hole K, and the photoresist may be a positive photoresist or a negative photoresist, and the development method may be a positive development or a negative development. In this way, an etching process may be used to etch the dielectric material layer using the patterned photoresist layer as a mask to form the metal contact hole K.
[0154] In other embodiments, see Fig.17 , the epitaxial layer 3 includes: a first doped epitaxial layer 31 .
[0155] In step S300', refer to Fig.17 , forming a first doped epitaxial layer 31 covering the isolation layer 2.
[0156] In step S400, refer to Fig.18 , the epitaxial layer 3 is etched to form a plurality of spaced trenches G. The trenches G expose the surface of the isolation layer 2 facing away from the substrate 1, and the trenches G and the isolation layer 2 are arranged one by one.
[0157] For example, a photoresist material layer may be coated on the first doped epitaxial layer 31 first, and the photoresist material layer is subjected to a series of steps such as exposure and development to form a patterned photoresist layer, wherein the patterned photoresist layer has a pattern that defines the position and shape of the groove G, and the photoresist may be a positive photoresist or a negative photoresist, and the development method may be a positive development or a negative development. In this way, the first doped epitaxial layer 31 may be etched using an etching process with the patterned photoresist layer as a mask to form the groove G.
[0158] In step S500, refer to Fig.19 , forming a gate oxide layer 4 covering the inner side wall of the trench G.
[0159] The gate oxide layer 4 is in contact with the surface of the isolation layer 2 facing away from the substrate 1 .
[0160] In some embodiments, the gate oxide layer 4 also covers the surface of the first doped epitaxial layer 31 facing away from the substrate 1 .
[0161] In some examples, while forming the gate oxide layer 4 covering the sidewalls of the trench G, the process also includes: simultaneously forming the gate oxide layer 4 covering the surface of the first doped epitaxial layer 31 facing away from the substrate 1 .
[0162] In some examples, the gate oxide layer 4 may be formed by a thermal oxidation process. Here, since the gate oxide layer 4 only needs to grow on the sidewalls of the trench, it is easy to obtain a gate insulating layer 4 of good quality by controlling the process.
[0163] For example, the material of the gate oxide layer 4 includes but is not limited to oxide. For example, the material of the gate oxide layer 4 may be silicon oxide.
[0164] In step S600, please refer to Fig. 20 , filling the trench G to form a gate 5.
[0165] For example, the material of the gate 5 includes but is not limited to polysilicon. For example, the material of the gate 5 can be self-doped high-concentration N-type polysilicon.
[0166] In step S700', please refer to Fig.21 , a second doped region 311 is formed in the first doped epitaxial layer 31 .
[0167] For example, the second doping region 311 may be formed by using a multiple ion implantation process and a thermal activation process.
[0168] By way of example, the second doping region 311 includes a P-type doping region.
[0169] In step S750', please continue to refer to Fig.21 , forming the first doping regions 321 arranged at intervals in the second doping regions 311 .
[0170] For example, the first doping region 321 may be formed by using a multiple ion implantation process and a thermal activation process.
[0171] Illustratively, the first doping region 321 includes an N-type doping region.
[0172] In step S800', please continue to refer to Fig.21 , at least a second heavily doped region 322 is formed between the first doped regions.
[0173] For example, the second heavily doped region 322 may be formed by using multiple ion implantation processes and a thermal activation process.
[0174] Illustratively, the second heavily doped region 322 includes a P-type heavily doped region.
[0175] In step S900, please refer to Fig. 22 A dielectric material layer (not shown in the figure) covering the gate oxide layer 4 is formed on the surface of the gate 5 away from the isolation layer 2 .
[0176] In some examples, a dielectric material layer covering the gate oxide layer 4 is formed on a surface of the gate 5 facing away from the isolation layer 2 by a deposition process.
[0177] In step S1000, please continue to refer to Fig. 22 , the dielectric material layer is etched to form a metal contact hole K, thereby obtaining a dielectric layer 6. The metal contact hole K exposes the surface of the second heavily doped region 322 facing away from the substrate 1 and the surface of a portion of the first heavily doped region 321 facing away from the substrate 1.
[0178] According to some embodiments, the present application provides a semiconductor structure on the other hand, which is prepared using the semiconductor structure preparation method described in the aforementioned embodiment. The semiconductor structure also has the technical advantages of the aforementioned preparation method, which will not be repeated here.
[0179] In some embodiments, see Fig.16 and Fig. 22 , the semiconductor structure includes: a substrate 1, a plurality of isolation layers 2 arranged at intervals, an epitaxial layer 3, a plurality of grooves G arranged at intervals, a gate oxide layer 4 and a gate 5. The plurality of isolation layers 2 arranged at intervals are located on one side of the substrate 1. The epitaxial layer 3 is located on one side of the substrate 1 and covers the isolation layer 2. The plurality of grooves G arranged at intervals are located in the epitaxial layer 3. The grooves G expose the surface of the isolation layer 2 facing away from the substrate 1, and the grooves G and the isolation layer 2 are arranged one by one. The gate oxide layer 4 covers the sidewalls of the grooves G. The gate oxide layer 4 is in contact with the surface of the isolation layer 2 facing away from the substrate 1. The gate 5 is located in the grooves G.
[0180] Wherein, the thickness range of the isolation layer 2 includes: For example, the thickness of the isolation layer 2 may be: or etc.
[0181] In some examples, the material of the substrate 1 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, referred to as DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and the embodiments of the present application are not limited here.
[0182] For example, the material of the isolation layer 2 includes oxide. For example, the material of the isolation layer 2 may be silicon oxide.
[0183] In some embodiments, the inclination angle of the side wall of the isolation layer 2 includes, but is not limited to, 45° to 90°. For example, the inclination angle of the side wall of the isolation layer 2 may be 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85° or 90°, etc.
[0184] In some embodiments, see Fig.16 The epitaxial layer 3 includes: a first doped epitaxial layer 31 and a second doped epitaxial layer 32. The first doped epitaxial layer 31 is located on one side of the substrate 1 and covers the isolation layer 2. The second doped epitaxial layer 32 is located on the side of the first doped epitaxial layer 31 away from the substrate 1.
[0185] In some examples, the first doped epitaxial layer 31 includes, but is not limited to, an N-type doped silicon carbide layer.
[0186] In some examples, the second doped epitaxial layer 32 includes, but is not limited to, a P-type doped silicon carbide layer.
[0187] In some embodiments, please refer to Fig.16 The semiconductor structure further includes: a first doped region 321 and a second heavily doped region 322 . The first doped region 321 is located in the second doped epitaxial layer 32 . The second heavily doped region 322 is located in the second doped epitaxial layer 32 and at least between the first doped regions 321 .
[0188] Illustratively, the first doping region 321 includes an N-type doping region.
[0189] Illustratively, the second heavily doped region 322 includes a P-type heavily doped region.
[0190] In some other embodiments, see Fig. 22 , the epitaxial layer 3 includes: a first doped epitaxial layer 31 .
[0191] In some examples, the first doped epitaxial layer 31 includes, but is not limited to, an N-type doped silicon carbide layer.
[0192] Accordingly, please continue to refer to Fig. 22 In some examples, the semiconductor structure further includes: a second doping region 311, a first doping region 321, and a second heavily doped region 322. The second doping region 311 is located in the first doped epitaxial layer 31. The first doping region 321 is located in the second doping region 311. The second heavily doped region 322 is located in the second doping region 311 and at least between the first doping regions 321.
[0193] By way of example, the second doping region 311 includes a P-type doping region, the first doping region 321 includes an N-type doping region, and the second heavily doped region 322 includes a P-type heavily doped region.
[0194] For example, please continue to see Fig.16 and Fig. 22 The material of the gate oxide layer 4 includes but is not limited to oxide. For example, the material of the gate oxide layer 4 can be silicon oxide.
[0195] For example, please continue to see Fig.16 and Fig. 22 The material of the gate 5 includes but is not limited to polysilicon. For example, the material of the gate 5 can be self-doped high-concentration N-type polysilicon.
[0196] In some embodiments, please refer to Fig.16 and Fig. 22 The semiconductor structure further includes: a dielectric layer 6. A metal contact hole K is provided in the dielectric layer 6. The dielectric layer 6 is located on the surface of the gate 5 away from the isolation layer 2 to form a covering gate oxide layer 4. The metal contact hole K exposes the surface of the second heavily doped region 322 away from the substrate 1 and the surface of a portion of the first heavily doped region 321 away from the substrate 1.
[0197] In the description of this specification, the technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0198] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of isolation layers arranged at intervals on the substrate; forming an epitaxial layer covering the isolation layer; Etching the epitaxial layer to form a plurality of grooves arranged at intervals; wherein the grooves expose the surface of the isolation layer away from the substrate, and the grooves are arranged in a one-to-one correspondence with the isolation layer; forming a gate oxide layer covering the inner sidewall of the trench; wherein the gate oxide layer is in contact with a surface of the isolation layer facing away from the substrate; Filling the trench to form a gate; Wherein, the thickness range of the isolation layer includes:
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The epitaxial layer includes: a first doped epitaxial layer and a second doped epitaxial layer; the epitaxial layer formed to cover the isolation layer includes: forming a first doped epitaxial layer covering the isolation layer; A second doped epitaxial layer is formed on a side of the first doped epitaxial layer away from the substrate; wherein the first doping includes N-type doping; and the second doping includes P-type doping.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The epitaxial layer includes: a first doped epitaxial layer; the epitaxial layer formed to cover the isolation layer includes: A first doped epitaxial layer is formed covering the isolation layer.
4. The method for preparing a semiconductor structure according to claim 1, wherein: The inclination angle range of the side wall of the isolation layer includes: 45° to 90°.
5. The method for preparing a semiconductor structure according to claim 1, wherein: The gate oxide layer also covers the surface of the epitaxial layer facing away from the substrate; While forming the gate oxide layer covering the sidewalls of the trench, the method also includes: synchronously forming a gate oxide layer covering the surface of the epitaxial layer facing away from the substrate.
6. The method for preparing a semiconductor structure according to claim 2, wherein: Also includes: forming first doped regions arranged at intervals in the second doped epitaxial layer; A second heavily doped region is formed at least between the first doped regions.
7. The method for preparing a semiconductor structure according to claim 3, characterized in that: Also includes: forming a second doped region in the first doped epitaxial layer; forming first doped regions arranged at intervals in the second doped regions; A second heavily doped region is formed at least between the first doped regions.
8. The method for preparing a semiconductor structure according to claim 6 or 7, characterized in that: Also includes: forming a dielectric material layer covering the gate oxide layer on a surface of the gate away from the isolation layer; Etching the dielectric material layer to form a metal contact hole; The metal contact hole exposes a surface of the second heavily doped region facing away from the substrate and a portion of a surface of the first heavily doped region facing away from the substrate.
9. A semiconductor structure, characterized in that: include: substrate; A plurality of isolation layers arranged at intervals are located on one side of the substrate; an epitaxial layer, located on one side of the substrate and covering the isolation layer; A plurality of grooves arranged at intervals are located in the epitaxial layer; wherein the grooves expose the surface of the isolation layer away from the substrate, and the grooves are arranged in a one-to-one correspondence with the isolation layer; A gate oxide layer, covering the sidewalls of the trench; wherein the gate oxide layer is in contact with a surface of the isolation layer facing away from the substrate; A gate, located in the trench; Wherein, the thickness range of the isolation layer includes:
10. The semiconductor structure according to claim 9, wherein: The epitaxial layer includes: a first doped epitaxial layer and a second doped epitaxial layer; wherein the first doped epitaxial layer is located at one side of the substrate and covers the isolation layer; and the second doped epitaxial layer is located at a side of the first doped epitaxial layer away from the substrate.