Semiconductor device

Abstract

A semiconductor device includes: a substrate; lower channel layers spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and extending in the first direction; upper channel layers on the lower channel layers, respectively, and spaced apart from each other in the vertical direction; an intermediate dielectric isolation structure between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers; a lower gate structure on the lower channel layer; an upper gate structure on the upper channel layer and on the lower gate structure, and extending in a second direction perpendicular to the first direction; and a gate isolation insulating layer between the lower gate structure and the upper gate structure, in contact with a side surface of the intermediate dielectric isolation structure, and extending around the lower gate structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0122144 filed in the Korean Intellectual Property Office on September 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device. Background Art

[0004] As demands for high performance, speed, and / or multifunctionality of semiconductor devices increase, there is a need to increase the integration density of semiconductor devices. Summary of the invention

[0005] Example embodiments of the present disclosure provide a semiconductor device having increased integration density and improved reliability.

[0006] According to an example embodiment of the present disclosure, a semiconductor device includes: a substrate; lower channel layers, which are spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extend in a first direction parallel to the upper surface of the substrate; upper channel layers, which are on the lower channel layers and spaced apart from each other in the vertical direction; an intermediate dielectric isolation structure, which is between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers; a lower gate structure, which is on the lower channel layer; an upper gate structure, which is on the upper channel layer and extends in a second direction perpendicular to the first direction; a gate isolation insulating layer, which is between the lower gate structure and the upper gate structure, which is in contact with a side surface of the intermediate dielectric isolation structure on the lower gate structure, and is on at least a portion of the lower gate structure; a lower source / drain region, which is on at least one side of the lower gate structure and is electrically connected to the lower channel layer; an upper source / drain region, which is on at least one side of the upper gate structure and is electrically connected to each of the upper channel layers and is spaced apart from the lower source / drain region in the vertical direction; and a barrier structure, which is between the lower source / drain region and the upper source / drain region.

[0007] According to an example embodiment of the present disclosure, a semiconductor device includes: a substrate; a first lower channel layer, which is spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extends in a first direction parallel to the upper surface of the substrate; a first upper channel layer, which is on the first lower channel layer and is spaced apart from each other in the vertical direction; a first intermediate dielectric isolation structure, which is between an uppermost lower channel layer among the first lower channel layers and a lowermost upper channel layer among the first upper channel layers; a first lower gate structure, which includes a lower gate electrode on the first lower channel layer; and a first upper gate structure, which is on the first upper channel layer and extends in a second direction perpendicular to the first direction. ; a first lower gate isolation insulating layer, between the first lower gate structure and the first upper gate structure; a lower source / drain region, on at least one side of the first lower gate structure and electrically connected to the first lower channel layer, respectively; an upper source / drain region, electrically connected to each of the first upper channel layer on at least one side of the first upper gate structure and spaced apart from the lower source / drain region in the vertical direction; a barrier structure, between the lower source / drain region and the upper source / drain region; a lower gate contact structure, below the first lower gate structure and electrically connected to the lower gate electrode of the first lower gate structure; and a lower interconnect, below the lower gate contact structure and electrically connected to the lower gate contact structure. The first lower gate isolation insulating layer contacts the side surface of the first intermediate dielectric isolation structure. The first lower gate isolation insulating layer extends along the side surface of the first lower gate structure.

[0008] According to an example embodiment of the present disclosure, a semiconductor device includes: a lower structure; an upper structure; an intermediate dielectric isolation structure extending along a first direction between the lower structure and the upper structure and spaced apart from each other in a second direction perpendicular to the first direction; and a gate isolation insulating layer between at least a portion of the lower structure and at least a portion of the upper structure and extending from a side surface of at least a portion of the intermediate dielectric isolation structure toward a lower end of the lower structure, wherein the lower structure includes: lower source / drain regions spaced apart from each other in the first direction; a lower active layer spaced apart from each other in a vertical direction, between the lower source / drain regions, and electrically connected to the lower source / drain regions; and a lower A gate structure, comprising a first lower gate structure and a second lower gate structure, wherein the first lower gate structure has a first lower gate electrode extending in a second direction perpendicular to the first direction, and the second lower gate structure comprises a second lower gate electrode electrically insulated from the first lower gate electrode by a gate isolation insulating layer, wherein the upper structure comprises: upper source / drain regions spaced apart from each other in the first direction and overlapping with the lower source / drain regions in the vertical direction; an upper active layer spaced apart from each other in the vertical direction, electrically connected to the upper source / drain regions between the upper source / drain regions, and overlapping with the lower active layer in the vertical direction; and an upper gate structure extending in the second direction and overlapping with the lower gate structure in the vertical direction. The gate isolation insulating layer contacts the side surface of the intermediate dielectric isolation structure on the second lower gate structure. The gate isolation insulating layer extends along the side surface of the second lower gate structure. The distance between the lower end of the gate isolation insulating layer and the substrate is substantially the same as the distance between the lower end of the second lower gate structure and the lower end of the upper structure and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure;

[0011] Figure 2 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 3 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0013] Figure 4A , Figure 4B and Figure 4C is an enlarged view showing a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0014] Figure 5 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0015] Fig. 6A and Figure 6B is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0016] Figure 7 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0017] Figure 8 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure;

[0018] Fig. 9 and Fig.10 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0019] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig.11F , Fig.11G , Fig.11H , Fig.11I , Fig.11J , Figure 11K , Fig.11L , Fig.11M and Fig.11N are cross-sectional views sequentially illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure;

[0020] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D and Fig.12E are cross-sectional views sequentially illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure;

[0021] Fig.13A , Fig. 13B , Fig. 13C , Fig.13D and Fig.13E are cross-sectional views sequentially illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure; and

[0022] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D and Fig.14E are cross-sectional views sequentially illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0024] Figure 1 1 is a plan view illustrating semiconductor devices 100 , 100A, 100B, and 100C according to example embodiments.

[0025] Figure 2 is shown along Figure 1 1 is a cross-sectional view of semiconductor devices 100 , 100A, and 100B according to example embodiments, taken along line II′ in FIG.

[0026] Figure 3 is shown along Figure 1 2 is a cross-sectional view of the semiconductor device 100 , 100A taken along lines II-II′ and III-III′.

[0027] Figure 4A , Figure 4B and Figure 4C is an enlarged view showing semiconductor devices 100 and 100A according to example embodiments, showing Figure 3 Area "A" in the.

[0028] For ease of description, Figure 1 Only a portion of the components of the semiconductor device 100 are shown.

[0029] Reference Figures 1 to 3, the semiconductor device 100 in the example embodiment may be configured as a semiconductor structure, which includes a first surface and a second surface opposite to the first surface. The semiconductor device 100 in the example embodiment may include: a channel structure 140, including a plurality of channel layers 140A and 140B spaced apart from each other in a vertical direction perpendicular to the first surface of the semiconductor structure (or "vertical direction toward the second surface") and extending along a first direction (e.g., X direction); an intermediate dielectric isolation structure MDI (300), disposed between the lower channel layer 140A (or "lower channel structure") and the upper channel layer 140B (or "upper channel structure"); a gate structure 160, including a back gate structure 160_1, a lower gate structure 160A, and an upper gate structure 160B or 160_2; a bottom dielectric isolation structure BDI 400, arranged between the lowest channel layer in the lower channel layer 140A and the back gate structure 160_1; the source / drain region 150, including the lower source / drain region 150A in contact with the lower channel layer 140A and the upper source / drain region 150B in contact with the upper channel layer 140B; the barrier structure 155, arranged between the lower source / drain region 150A and the upper source / drain region 150B; the contact structure of the contact plug 180, including the lower contact plug 180A (or "back contact plug") and the upper contact plug 180B respectively connected to the lower source / drain region 150A and the upper source / drain region 150B; and the gate contact structure 190, including the lower gate contact structure 190A (or "back gate contact structure") and the upper gate contact structure 190B respectively connected to the lower gate structure 160A and the upper gate structure 160B.

[0030] In the semiconductor device 100, the gate structure 160 may be disposed between the bottom dielectric isolation structure BDI (400) and the channel structure 140, between the lower channel layer 140A and the upper channel layer 140B of the channel structure 140, and on the channel structure 140. In example embodiments, the lower gate structure 160A may be disposed between the bottom dielectric isolation structure BDI 400 and the lowest lower channel layer among the lower channel layers 140A, between the lower channel layers 140A, and between the highest lower channel layer among the lower channel layers 140A and the intermediate dielectric isolation structure MDI (300). In example embodiments, the upper gate structure 160B may be disposed between the intermediate dielectric isolation structure MDI (300) and the lowest upper channel layer among the upper channel layers 140B, between the upper channel layers 140B, and on the upper channel layer 140B.

[0031] Therefore, the semiconductor device 100 may include a multi-bridge channel FET (MBCFET TM) structure, which is a ring-gate field effect transistor. In example embodiments, the semiconductor device may include a transistor of a complementary FET (CFET) structure. Example embodiments may also be applied to a transistor having a 3D-SFET (three-dimensional stacked FET) structure in which a plurality of transistors are vertically stacked.

[0032] like Figure 2 and Figure 3 As shown, the semiconductor devices 100 and 100A according to example embodiments may have a first transistor structure TR1 and a second transistor structure TR2 stacked in a vertical direction (eg, Z direction).

[0033] Reference Figure 2 and Figure 3 , the semiconductor devices 100 and 100A according to example embodiments may include a third transistor structure TR3 and a fourth transistor structure TR4 stacked in a vertical direction. The third transistor structure TR3 and the fourth transistor structure TR4 may be configured as transistor structures adjacent to the first transistor structure TR1 and the second transistor structure TR2, respectively, in a first direction (eg, X direction).

[0034] Each of the first transistor structure TR1 , the second transistor structure TR2 , the third transistor structure TR3 , and the fourth transistor structure TR4 employed in the example embodiment may be configured as an MBCFET TM (Multi-bridge channel FET), which includes a lower gate structure 160A extending around the lower channel layer 140A or extending around the lower channel layer 140A and an upper gate structure 160B extending around the upper channel layer 140B or extending around the upper channel layer 140B. Respectively, the first transistor structure TR1 can be configured as one of an N-type MOSFET and a P-type MOSFET, and the second transistor structure TR2 can be configured as one of a P-type MOSFET and an N-type MOSFET. In some example embodiments, the first transistor structure TR1 and the second transistor structure TR2 can be configured as a P-type MOSFET and an N-type MOSFET, respectively. The third transistor structure TR3 and the fourth transistor structure TR4 can also have characteristics that are the same or similar to the characteristics of the MOSFET type of the above-mentioned first transistor structure TR1 and the second transistor structure TR2.

[0035] In an example embodiment, the first transistor structure TR1 and the second transistor structure TR2 may be configured not to share a common gate electrode. For example, each of the first transistor structure TR1 and the second transistor structure TR2 may be configured to be connected to different gate structures 160A and 160B. In addition, by disposing a gate isolation insulating layer 170 between the first transistor structure TR1 and the second transistor structure TR2, the first transistor structure TR1 and the second transistor structure TR2 may be electrically insulated from each other. The third transistor structure TR3 and the fourth transistor structure TR4 also have characteristics that are the same as or similar to those of the first transistor structure TR1 and the second transistor structure TR2, and a detailed description thereof will not be provided.

[0036] Specifically, each of the first transistor structure TR1 and the third transistor structure TR3 may have a lower channel layer 140A spaced apart from each other in a vertical direction (e.g., Z direction), a lower gate electrode 160A_1 extending around or surrounding the lower channel layer 140A, a lower source / drain region 150A connected to the lower channel layer 140A on one side of the lower gate electrode 160A_1, and a gate dielectric layer 162 between the lower channel layer 140A and the lower gate electrode 160A_1.

[0037] In example embodiments, at least one lower gate electrode layer may be sequentially stacked on the side surface and the lower surface of the lower gate electrode 160A_1. In example embodiments, a first lower gate electrode layer 160A_2 may be disposed on the side surface and the lower surface of the lower gate electrode 160A_1, and a second lower gate electrode layer 160A_3 may be disposed on the first lower gate electrode layer 160A_2. The number of lower gate electrode layers disposed on the lower gate electrode 160A_1 is not limited thereto.

[0038] Refer to Figure 4A , a single lower gate electrode layer (or “first lower gate electrode layer 160A_2 ”) may be stacked on the side surfaces and the lower surface of the lower gate electrode 160A_1 .

[0039] Reference Figure 4B , a first lower gate electrode layer 160A_2 , a second lower gate electrode 160A_3 , and a third lower gate electrode 160A_4 may be sequentially stacked on side surfaces and a lower surface of the lower gate electrode 160A_1 .

[0040] Return to reference Figure 2 and Figure 3Each of the second transistor structure TR2 and the fourth transistor structure TR4 may include an upper channel layer 140B, an upper gate electrode 165 extending around or surrounding the upper channel layer 140B, upper source / drain regions 150B connected to the upper channel layer 140B on both sides of the upper gate electrode 165, and a gate dielectric layer 162 between the upper channel layer 140B and the upper gate electrode 165.

[0041] The gate isolation insulating layer 170 may be disposed between the first transistor structure TR1 and the second transistor structure TR2 spaced apart from each other in the vertical direction (eg, in the Z direction), and between the third transistor structure TR3 and the fourth transistor structure TR4 spaced apart from each other in the vertical direction. The gate isolation insulating layer 170 may have a uniform thickness d 2 The second thickness d 2 It may be, for example, about 5 nm or more, for example, 5 nm to 15 nm, 5 nm to 13 nm, 5 nm to 10 nm, or 7 nm to 10 nm. The gate isolation insulating layer 170 may be configured to electrically insulate the first transistor structure TR1 and the second transistor structure TR2 spaced apart from each other in the vertical direction, and the third transistor structure TR3 and the fourth transistor structure TR4 spaced apart from each other in the vertical direction may be configured to electrically insulate each other.

[0042] Reference Figure 3 , the gate isolation insulating layer 170 may contact the side surface of the intermediate dielectric isolation structure MDI (300) on the upper surface of the lower gate structure 160A including the lower gate electrode 160A_1 and at least one lower gate electrode layer 160A_2, 160A_3, and 160A_4. The gate isolation insulating layer 170 may extend downward along the side surface of the lower gate structure 160A in the form of a pad on the upper surface of the lower gate structure 160A. In the lower portion of the lower gate structure 160A, the gate isolation insulating layer 170 may contact at least a portion of the lower surface of the lower gate electrode layer disposed on the outermost side of the at least one lower gate electrode layer 160A_2, 160A_3, and 160A_4. In example embodiments, in the lower portion of the lower gate structure 160A, the gate isolation insulating layer 170 may contact at least a portion of the upper surface of the second lower gate electrode layer 160A_3.

[0043] Refer to Figure 4A In the lower portion of the lower gate structure 160A, the gate isolation insulating layer 170 may contact at least a portion of the lower portion or lower surface of the first lower gate electrode layer 160A_2. In some embodiments, the gate dielectric layer 162 is a portion of the middle dielectric isolation structure MDI.

[0044] Refer to Figure 4B, in the lower portion of the lower gate structure 160A, the gate isolation insulating layer 170 may contact at least a portion of the lower portion or lower surface of the third lower gate electrode layer 160A_4.

[0045] Reference Figure 4C , the upper surface 160A_U of the lower gate structure may have a downwardly curved shape, for example, a downwardly curved parabolic cross-sectional shape. Fig.11H , through the wet etching process, the upper surface 160A_U of the lower gate structure may have a groove portion that is bent downward, such as Figure 4C shown.

[0046] The channel structure 140 may include a lower channel structure 140A and an upper channel structure 140B (eg, Fig.11A ), the lower channel structure 140A includes two or more channel layers (such as lower channel layers) spaced apart from each other in a direction (e.g., Z direction) perpendicular to the upper surface of the active region 105, and the upper channel structure 140B includes an upper channel layer on the active region 105. The plurality of channel layers 140A and 140B may be connected to the source / drain region 150 and may be spaced apart from the bottom dielectric isolation structure BDI 400. The upper channel layers 140B may be respectively disposed on the middle dielectric isolation structure MDI (300) and may be spaced apart from each other in the Z direction.

[0047] The plurality of channel layers 140A and 140B may have the same or similar width in the Y direction. In example embodiments, the width of the plurality of channel layers 140A and 140B in the Y direction may decrease in a direction perpendicular to the first surface (i.e., from the first surface to the second surface). The width of the plurality of channel layers 140A and 140B in the X direction may decrease in a direction perpendicular to the first surface (i.e., from the first surface to the second surface).

[0048] The plurality of channel layers 140A and 140B may be formed of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the plurality of channel layers 140A and 140B may be formed of the same material as the substrate 101 (see Fig.11A ). The plurality of channel layers 140A and 140B may be spaced apart from each other perpendicularly to the first surface. The number and shape of the plurality of channel layers 140A and 140B included in the channel structure 140 may vary in example embodiments.

[0049] The intermediate dielectric isolation structure MDI (300) may be disposed between the uppermost lower channel layer among the lower channel layers 140A and the lowermost upper channel layer among the upper channel layers 140B. The intermediate dielectric isolation structure MDI (300) may include an intermediate insulating pattern 300. The intermediate insulating pattern 300 may include an insulating material such as oxide, nitride, and oxynitride. The intermediate dielectric isolation structure MDI (300) may separate the lower channel layer 140A from the upper channel layer 140B. The intermediate insulating pattern 300 may have a first thickness d between the lower channel layer 140A and the upper channel layer 140B. 1 The first thickness d 1 It may be about 10 nm or more, for example, 10 nm to 100 nm, 10 nm to 80 nm, or 10 nm to 50 nm.

[0050] The bottom dielectric isolation structure BDI (400) may be disposed between the lower gate structure 160A and the active region 105, but example embodiments thereof are not limited thereto. In example embodiments, the bottom dielectric isolation structure BDI (400) may not be disposed, and the lower channel layer 140A (see Figure 7 ). The bottom dielectric isolation structure BDI (400) may include a material substantially the same as that of the middle dielectric isolation structure MDI (300), but example embodiments thereof are not limited thereto.

[0051] The gate structure 160 may include a lower gate structure 160A and upper gate structures 160B and 160_2 .

[0052] The lower gate structure 160A may extend around the lower channel layer 140A or extend around the lower channel layer 140A, respectively, and may extend along the second direction (e.g., the Y direction). The upper surface of the lower gate structure 160A may be disposed at an intermediate height between the heights of the upper surface and the lower surface of the intermediate dielectric isolation structure MDI (300), but example embodiments thereof are not limited thereto. For example, the upper surface of the lower gate structure 160A may be disposed between the heights of the upper surface and the lower surface of the intermediate dielectric isolation structure MDI (300).

[0053] The upper gate structure 160B may extend around each upper channel layer 140B in a plan view or extend around each upper channel layer 140B, and may extend along a second direction (e.g., direction Y). In example embodiments, as described above, the first transistor structure TR1 and the second transistor structure TR2 may not share a common gate electrode, and may be configured to be connected to different gate structures 160A and 160B. Similarly, the third transistor structure TR3 and the fourth transistor structure TR4 may not share a common gate electrode.

[0054] The lower gate structure 160A may include a lower gate electrode 160A_1, and at least one lower gate electrode layer 160A_2, 160A_3, and 160A_4 stacked on the lower gate electrode 160A_1. In example embodiments, the lower gate structure 160A may extend around the lower channel layer 140A or extend around the lower channel layer 140A, respectively, and may include a lower gate electrode 160A_1 extending in a second direction (e.g., a Y direction), and a first lower gate electrode layer 160A_2 and a second lower gate electrode layer 160A_3 sequentially stacked on a side surface and a lower surface of the lower gate electrode 160A_1. The number of lower gate electrode layers disposed on the lower gate electrode 160A_1 may vary in example embodiments.

[0055] As mentioned above, return reference Figure 4A , a single lower gate electrode layer 160A_2 may be stacked on the side surface and the lower surface of the lower gate electrode 160A_1. Figure 4B , a first lower gate electrode layer 160A_2 , a second lower gate electrode layer 160A_3 , and a third lower gate electrode layer 160A_4 may be sequentially stacked on side surfaces and a lower surface of the lower gate electrode 160A_1 .

[0056] The gate structure 160 may further include a back gate structure 160_1 disposed on the back side of the semiconductor structure. The back gate structure 160_1 may be disposed on the lower surface of the bottom dielectric isolation structure BDI (400) and may extend along the second direction (eg, the Y direction).

[0057] The gate dielectric layer 162 may be disposed between the lower channel layer 140A and the lower gate electrode 160A_1, and also between the upper channel layer 140B and the upper gate electrode 165. The gate dielectric layer 162 may extend around or extend around the perimeter of the intermediate insulating pattern 300, and may cover or overlap the upper and side surfaces of the lower insulating pattern or the bottom dielectric isolation structure BDI 400.

[0058] The gate structure 160 may further include a gate spacer layer 164. The gate spacer layer 164 may be disposed on both sidewalls of an electrode portion extending along a second direction (e.g., a Y direction) on the uppermost upper channel layer among the upper gate electrodes 165. In addition, the gate spacer layer 164 may be disposed on both sidewalls of a back gate electrode 167 extending along a second direction (e.g., a Y direction). Although not shown, a gate capping layer may be formed on the gate spacer layer 164, the upper gate electrode 165, the gate spacer layer 164, and the back gate electrode 167.

[0059] The upper gate electrode 165 of the upper gate structures 160B and 160_2, the lower gate electrode 160A_1 of the lower gate structure 160A, the at least one lower gate electrode layer 160A_2, 160A_3, and 160A_4, and the back gate electrode 167 of the back gate structure 160_1 in example embodiments may include a conductive material. For example, each of the upper gate electrode 165, the lower gate electrode 160A_1, the at least one lower gate electrode layer 160A_2, 160A_3, and 160A_4, and the back gate electrode 167 may include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and / or TaAlC.

[0060] The gate electrodes 165, 160A_1, 160A_3, 160A_4, and 167 may include different conductive materials. For example, considering the desired threshold voltage, the upper gate electrode 165 of the upper gate structure 160B, the lower gate electrode 160A_1 of the lower gate structure 160A, and at least one lower gate electrode layer 160A_2, 160A_3, and 160A_4 may be formed of a material having an appropriate work function. Similarly, the gate dielectric layer 162 of the upper gate structure 160B and the gate dielectric layer 162 of the lower gate structure 160A may include different dielectric layers or a combination thereof.

[0061] For example, the gate dielectric layer 162 may include oxide, nitride, or high-k material. High-k material may refer to a material having a higher dielectric constant than silicon oxide (SiO 2 ) dielectric material with a higher dielectric constant. The high-k material can be one of the following: for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and / or praseodymium oxide (Pr 2 O3 ).

[0062] For example, the gate spacer layer 164 may include at least one of silicon oxide, silicon nitride and / or silicon oxynitride. In some example embodiments, the gate spacer layer 164 may include a multilayer structure. The gate capping layer may include, for example, silicon nitride, silicon oxynitride, silicon carbonitride or silicon carbon nitride.

[0063] The source / drain region 150 may include a lower source / drain region 150A and an upper source / drain region 150B.

[0064] The lower source / drain region 150A may be disposed on the active region 105 on at least one side of the lower gate structure 160A, and may be connected to the side surface of the lower channel layer 140A. The lower source / drain region 150A may be disposed as a source region or a drain region of the first transistor structure TR1 and the third transistor structure TR3. The lower source / drain region 150A may include an epitaxial growth using two side surfaces of the lower channel layer 140A as a seed layer. Similarly, the upper source / drain region 150B may be connected to the side surface of the upper channel layer 140B on at least one side of the upper gate structure 160B, and may be spaced apart from the lower source / drain region 150A in the vertical direction. The upper source / drain region 150B may be used as a source region or a drain region of the second transistor structure TR2 and the fourth transistor structure TR4. The upper source / drain region 150B may include an epitaxial growth using two side surfaces of the upper channel layer 140B as a seed layer.

[0065] The lower source / drain region 150A and the upper source / drain region 150B may include semiconductor epitaxy (such as silicon (Si)). The lower source / drain region 150A and the upper source / drain region 150B may include impurities of different types and / or concentrations. For example, when the first transistor structure TR1 is configured as a P-type MOSFET, the lower source / drain region 150A may include P-type doped silicon germanium (SiGe), and when the second transistor structure TR2 is configured as an N-type MOSFET, the upper source / drain region 150B may include N-type doped silicon (Si).

[0066] The barrier structure 155 may be disposed between the lower source / drain region 150A and the upper source / drain region 150B. The barrier structure 155 may vertically overlap the lower source / drain region 150A and the upper source / drain region 150B. The barrier structure 155 may include an insulating material, such as an oxide, a nitride, or a nitride oxide. The barrier structure 155 may separate the lower source / drain region 150A and the upper source / drain region 150B from each other in the vertical direction Z.

[0067] The contact structure 180 may include a contact plug and a barrier layer (not shown) disposed on the sidewall of the contact plug. The contact structure 180 may extend to or penetrate at least a portion of the plurality of interlayer insulating layers 191, 192, 194, and 195, may contact the source / drain region 150, and may apply an electrical signal to the source / drain region 150.

[0068] The contact structure 180 may include a lower contact structure 180A (or “back contact structure”) contacting a lower portion of the lower source / drain region 150A, and an upper contact structure 180B contacting an upper portion of the upper source / drain region 150B.

[0069] The upper contact structure 180B may be disposed to extend to or penetrate the first and second upper insulating layers 191 and 192 and to make contact with an upper portion of the upper source / drain region 150B.

[0070] The back contact structure 180A may be provided to extend to or penetrate the first lower insulating layer 194 and the second lower insulating layer 195, and may contact the lower portion of the lower source / drain region 150A. Although not shown, the back contact structure 180A may be provided on the first lower insulating layer 194, and a via connecting the back contact structure 180A and the second interconnection M2 provided on the third lower insulating layer 196 may be provided on the second lower insulating layer 195.

[0071] The contact plug may include a metal material, such as aluminum (Al), tungsten (W), or molybdenum (Mo). The barrier layer may include a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0072] The gate contact structure 190 may include an upper gate contact structure 190B. The upper gate contact structure 190B may contact the upper gate electrode 165. The gate contact structure 190 may have a shape and material similar to those of the contact structure 180, but example embodiments thereof are not limited thereto. In example embodiments, the upper gate contact structure 190B may include an upper gate contact barrier layer 190B_1.

[0073] The gate contact structure 190 may also include a lower gate contact structure 190A (or a "back gate contact structure 190A"). Figure 3 As described above, the back gate contact structure 190A may be implemented by disposing the gate isolation insulating layer 170 between a plurality of transistor structures spaced apart from each other in the vertical direction (Z direction). In an example embodiment, the lower gate contact structure 190A may include a lower gate contact barrier layer 190A_1. By implementing the back gate contact structure 190A, the first transistor may exchange electrical signals with an external entity through the back gate contact structure 190A.

[0074] The first interconnect M1 may include a first upper metal interconnect M1a and a second upper metal interconnect M1b, and the second interconnect M2 may include a first lower metal interconnect M2a and a second lower metal interconnect M2b. The second upper metal interconnect M1b may be electrically connected to the upper source / drain region 150B through an upper contact structure 180B, and the first upper metal interconnect M1a may be electrically connected to the upper gate electrode 165 through an upper gate contact structure 190B. The second lower metal interconnect M2b may be electrically connected to the lower source / drain region 150A through a lower contact structure 180A, and the first lower metal interconnect M2a may be electrically connected to the lower gate electrode 160A_1 through a lower gate contact structure 190A.

[0075] Refer to Figure 1 , Figure 2 and Figure 3 By implementing a back gate contact structure 190A on the back side of the semiconductor device 100, the upper device and the lower device of the devices adjacent to each other in the X direction can be electrically connected to each other. In the example embodiment, the first transistor structure TR1 (see Figure 2 and Figure 3 (a)) of the first lower metal interconnect M2a and connected to the fourth transistor structure TR4 (see Figure 2 and Figure 3 The first upper metal interconnection M1a of (b)) may be electrically connected to each other in a region other than the region shown in the figure. In this case, the first transistor structure TR1 and the fourth transistor structure TR4 may be cross-coupled to each other by the first lower metal interconnection M2a and the first upper metal interconnection M1a electrically connected to each other XC1 (see Figure 1 ).

[0076] Figure 5 is shown along Figure 1 2 and 3. Cross-sectional views of the semiconductor devices 100 and 100B taken along lines II-II' and III-III' in FIG.

[0077] Fig. 6A and Figure 6B 100 and 100B are enlarged views showing a portion of the semiconductor devices 100 and 100B according to example embodiments. Fig. 6A and Figure 6B Shows Figure 5 Area "B" in the

[0078] Reference Figure 5 , except for a configuration in which the first transistor structure TR1 may be electrically isolated from the fifth transistor structure TR5 adjacent in the second direction (eg, the Y direction) (see Figure 5 , left part) and a configuration in which the third transistor structure TR3 can be electrically insulated from the seventh transistor structure TR7 adjacent in the second direction (see Figure 5 , right part), the semiconductor devices 100, 100B in the example embodiments may be configured as Figures 1 to 4C The examples described are the same or similar.

[0079] Reference Figure 5 , the fifth transistor structure TR5 may be configured as a transistor structure adjacent to the first transistor structure TR1 in the second direction, and the sixth transistor structure TR6 may be configured as a transistor structure adjacent to the second transistor structure TR2 in the second direction. Similarly, the seventh transistor structure TR7 may be configured as a transistor structure adjacent to the third transistor structure TR3 in the second direction, and the eighth transistor structure TR8 may be configured as a transistor structure adjacent to the fourth transistor structure TR4 in the second direction. The sixth transistor structure TR6 and the eighth transistor structure TR8 may be configured as reference structures. Figures 1 to 4C The second transistor structure TR2 and the fourth transistor structure TR4 described are the same or similar, and thus a detailed description thereof will not be provided. In addition to the configuration in which the fifth transistor structure TR5 and the seventh transistor structure TR7 may be electrically insulated from the first transistor structure TR1 and the third transistor structure TR3 adjacent in the second direction, respectively, the fifth transistor structure TR5 and the seventh transistor structure TR7 may be configured to be electrically insulated from the first transistor structure TR1 and the third transistor structure TR3 adjacent in the second direction, respectively. Figures 1 to 4C The first transistor structure TR1 and the third transistor structure TR3 are described to be the same or similar.

[0080] Reference Figure 5 , the first transistor structure TR1 and the third transistor structure TR3 may be respectively configured so that the lower gate electrode 160A_1 extending around the lower channel layer 140A or extending around the lower channel layer 140A may not extend in the second direction. In other words, the lower gate electrodes 160A_1 of the first transistor structure TR1 and the third transistor structure TR3 may be configured not to be connected to the lower gate electrodes 160A_1 of the fifth transistor structure TR5 and the seventh transistor structure TR7, respectively. The first transistor structure TR1 and the fifth transistor structure TR5 may be spaced apart from each other by a first distance l1 in the second direction. For example, the first distance l1 may be the distance between the side surface of the lower gate structure of the first transistor structure TR1 and the side surface of the fifth transistor structure TR5 in the second direction. The first distance l1 may be about 10nm or more, for example, 10nm to 20nm, 10nm to 15nm, or 15nm to 20nm.

[0081] Refer to Figure 5 and Fig. 6A, in the lower gate structure 160A, at least a portion of the side surface of the lower gate electrode 160A_1 and at least a portion of the side surface of the first lower gate electrode layer 160A_2 may be exposed in the second direction. The gate isolation insulating layer 170 may contact the side surface of the middle dielectric isolation structure MDI 300 on the upper surface of the lower gate structure 160A, and may extend along the side surface of the lower gate structure 160A in the form of a pad. In this case, the side surface of the gate isolation insulating layer 170 may be configured to be perpendicular to the first surface and the second surface of the semiconductor structure, but example embodiments thereof are not limited thereto. Figure 6B As shown, the side surface of the gate isolation insulating layer 170 may extend in the downward direction of the lower gate structure 160A along the side surface of the lower gate structure 160A, thereby forming an oblique line with the first surface and the second surface of the semiconductor structure of the substrate 101. In the lower portion of the lower gate structure 160A, the gate isolation insulating layer 170 may contact the exposed side surface of the side surface of the lower gate electrode 160A_1 and the exposed side surface of the first lower gate electrode layer 160A_2. Therefore, the lower gate structure 160A in the example embodiment may be electrically insulated from the upper gate structure 160B.

[0082] Figure 7 is shown along Figure 1 1 is a cross-sectional view of semiconductor devices 100 and 100C according to example embodiments, taken along line II′ in FIG.

[0083] Reference Figure 7 , except for the configuration in which the bottom dielectric isolation structure BDI 400 is not disposed between the lowest channel layer in the lower channel layer 140A and the back gate structure 160_1, the semiconductor device 100 may be similar to the configuration of reference Figures 1 to 6B The examples described are similar.

[0084] like Figure 7 As shown, the bottom dielectric isolation structure BDI 400 is not disposed between the lowermost channel layer among the lower channel layers 140A and the back gate structure 160_1 , and an additional lower channel layer 140A may be further disposed.

[0085] Figure 8 2 is a plan view illustrating semiconductor devices 200 , 200A, and 200B according to example embodiments.

[0086] Fig. 9 is shown along Figure 8 2 is a cross-sectional view of the semiconductor devices 200 and 200A taken along line IV-IV′ and cutting line VV′.

[0087] Fig.10 is shown along Figure 82 is a cross-sectional view of the semiconductor devices 200 and 200B taken along line IV-IV′ and cutting line VV′.

[0088] For ease of description, Figure 8 Only a portion of the components of the semiconductor device are shown.

[0089] Reference Figure 8 In addition to the configuration in which the upper device and the lower device of the devices adjacent to each other in the first direction (e.g., X direction) and the second direction (e.g., Y direction) may be electrically connected to each other, the semiconductor devices 200, 200A, and 200B in the example embodiments may be configured as described with reference to FIG. Figures 1 to 6B The examples described are the same or similar.

[0090] Reference Fig. 9 , electrically connected to the first lower metal interconnection M2a ( Fig. 9 (a)) and a first upper metal interconnection M1a ( Fig. 9 (b)) may be electrically connected to each other in areas other than the areas shown. In this case, the first transistor structure TR1 and the eighth transistor structure TR8 may be cross-coupled to each other by the first lower metal interconnection M2a and the first upper metal interconnection M1a electrically connected to each other XC2 (see Figure 8 ).

[0091] Reference Fig.10 , except that the lower gate electrode 160A_1 extending around the lower channel layer 140A or surrounding the lower channel layer 140A may be configured not to extend in the second direction, the first transistor structure TR1 and the eighth transistor structure TR8 may be configured as described with reference to FIG. Fig. 9 The examples described are the same or similar.

[0092] FIG. 11A to FIG. 11N are cross-sectional views sequentially illustrating processes of a method of fabricating a semiconductor device according to example embodiments.

[0093] FIG. 11A to FIG. 11N An example embodiment of a manufacturing method including patterning the lower gate electrode 160A_1 is shown.

[0094] Reference Fig.11A A device isolation layer 110 defining an active area 105 may be formed on a substrate 101, sacrificial barrier layers 120D, sacrificial layers 120, lower channel layers 140A, semiconductor patterns 140S, and upper channel layers 140B may be alternately stacked, an active structure may be formed, and a sacrificial gate structure 200 may be formed along a second direction Y to intersect the active structure.

[0095] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0096] The active region 105 may be defined by the device isolation layer 110 in the substrate 101, and may be arranged to extend in a first direction (e.g., X direction). The active region 105 may have a structure protruding from the substrate 101. The upper end of the active region 105 may be arranged to protrude a predetermined height from the upper surface of the device isolation layer 110. The active region 105 may be formed as a part of the substrate 101, or may include an epitaxial layer grown from the substrate 101. The active region 105 may include impurities, or may include a doped region containing impurities.

[0097] The device isolation layer 110 may define the active region 105 in the substrate 101. The device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. In an example embodiment, the device isolation layer 110 may further include a region extending deeper and having a step difference with a region below the substrate 101. The device isolation layer 110 may partially expose an upper portion of the active region 105. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0098] The sacrificial barrier layer 120D may be formed of a material having an etching selectivity to the sacrificial layer 120, the lower channel layer 140A, the semiconductor pattern 140S, and / or the upper channel layer 140B. The sacrificial barrier layer 120D may include silicon (Si) or silicon germanium (SiGe). When the sacrificial barrier layer 120D includes silicon germanium (SiGe), the sacrificial barrier layer 120D may have an etching selectivity due to a difference in germanium (Ge) concentration with the sacrificial layer 120. Through subsequent processes, the sacrificial barrier layer 120D may be formed as follows: Figure 2 and Figure 3 The bottom dielectric isolation structure BDI (400) is shown as an alternative.

[0099] The sacrificial layer 120 may include a lower sacrificial layer 120A, a middle sacrificial layer 120C, and an upper sacrificial layer 120B. Figure 3 As shown, through subsequent processes, the lower sacrificial layer 120A may be replaced by the gate dielectric layer 162 and the lower gate electrode 160A_1, and the upper sacrificial layer 120B may be replaced by the gate dielectric layer 162 and the upper gate electrode 165. Through subsequent processes, the middle sacrificial layer 120C and the semiconductor pattern 140S may be replaced by the gate dielectric layer 162 and the upper gate electrode 165. Figure 2 and Figure 3The intermediate dielectric isolation structure MDI (300) is shown as an alternative.

[0100] The sacrificial layer 120 may be formed of a material having an etching selectivity to the lower channel layer 140A, the semiconductor pattern 140S, and the upper channel layer 140B. The lower channel layer 140A, the semiconductor pattern 140S, and the upper channel layer 140B may include a material different from that of the sacrificial layer 120. In example embodiments, the lower channel layer 140A, the semiconductor pattern 140S, and the upper channel layer 140B may include silicon (Si), and the sacrificial layer 120 may include silicon germanium (SiGe), but example embodiments thereof are not limited thereto.

[0101] The sacrificial barrier layer 120D, the sacrificial layer 120, the lower channel layer 140A, and the upper channel layer 140B may be formed by performing an epitaxial growth process using the substrate 101 as a seed. Each of the sacrificial barrier layer 120D, the sacrificial layer 120, the lower channel layer 140A, the semiconductor pattern 140S, and the upper channel layer 140B may have a thickness ranging from about 100 to about 1000. The number of the lower channel layers 140A, the semiconductor patterns 140S, and the upper channel layers 140B alternately stacked with the sacrificial layers 120 may vary in example embodiments.

[0102] Thereafter, an active structure may be formed by removing the sacrificial barrier layer 120D, the sacrificial layer 120 , the lower channel layer 140A, the semiconductor pattern 140S, the upper channel layer 140B, and a portion of the substrate 101 , and a sacrificial gate structure 200 may be formed on the active structure.

[0103] The active structure may include sacrificial barrier layers 120D, sacrificial layers 120, lower channel layers 140A, semiconductor patterns 140S, and upper channel layers 140B alternately stacked on one another, and may also include an active region 105 formed by removing a portion of the substrate 101 and protruding onto the upper surface of the substrate 101. The active structure may be formed in the form of lines extending in one direction (e.g., the X direction) and may be spaced apart from one another in the Y direction.

[0104] The device isolation layer 110 may be formed by filling an insulating material in a region where a portion of the substrate 101 is removed and recessing the active region 105 to protrude. An upper surface of the device isolation layer 110 may be formed at a height lower than that of an upper surface of the active region 105.

[0105] Through subsequent processes, the sacrificial gate structure 200 may be configured as a sacrificial structure formed in a region where the gate dielectric layer 162 and the upper gate electrode 165 are disposed in an upper portion of the channel structure 140, such as Figure 2 and Figure 3As shown. The sacrificial gate structure 200 may include a first sacrificial layer 202 and a second sacrificial layer 205 and a mask pattern layer 206 stacked in sequence. The first sacrificial layer 202 and the second sacrificial layer 205 may be patterned using the mask pattern layer 206. The first sacrificial layer 202 and the second sacrificial layer 205 may be configured as an insulating layer and a conductive layer, respectively. For example, the first sacrificial layer 202 may include silicon oxide, and the second sacrificial layer 205 may include polysilicon. The mask pattern layer 206 may include silicon nitride. The sacrificial gate structure 200 may have a line shape that intersects with the active structure and extends in one direction. For example, the sacrificial gate structure 200 may extend in the Y direction and may be spaced apart from each other in the X direction.

[0106] Reference Fig. 11B , a middle dielectric isolation structure MDI and a bottom dielectric isolation structure BDI may be formed, and a gate spacer layer 164 may be formed to cover or overlap the upper and side surfaces of the sacrificial gate structure 200 and the active structure.

[0107] The middle sacrificial layer 120C and the semiconductor pattern 140S may have an etching selectivity to the sacrificial barrier layer 120D, the lower sacrificial layer 120A, the upper sacrificial layer 120B, the lower channel layer 140A, and the upper channel layer 140B, so that the middle sacrificial layer 120C and the semiconductor pattern 140S may be selectively removed. An intermediate dielectric isolation structure MDI may be formed by filling the region where the middle sacrificial layer 120C and the semiconductor pattern 140S are removed with the middle insulating pattern 300. The middle insulating pattern 300 may include, for example, oxide or nitride.

[0108] Since the sacrificial barrier layer 120D may have an etching selectivity to the sacrificial layer 120, the lower channel layer 140A, and the upper channel layer 140B, the sacrificial barrier layer 120D may be selectively removed. A bottom dielectric isolation structure BDI may be formed by filling a lower insulating pattern 310 in a region where the sacrificial barrier layer 120D is removed. The bottom dielectric isolation structure BDI may include, for example, oxide or nitride. Here, without being limited to the above process, the middle dielectric isolation structure MDI and the bottom dielectric isolation structure BDI may be simultaneously formed by simultaneously removing the sacrificial barrier layer 120D, the middle sacrificial layer 120C, and the semiconductor pattern 140S and filling an insulating material therein.

[0109] The gate spacer layer 164 may be formed to cover both the sidewall and the upper surface of the sacrificial gate structure 200 or overlap both the sidewall and the upper surface of the sacrificial gate structure 200. The gate spacer layer 164 may form a film having a substantially uniform thickness along the upper and side surfaces of the sacrificial gate structure 200 and the active structure. The gate spacer layer 164 may be formed of a low dielectric constant material, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN.

[0110] Reference Fig. 11C , a portion of the gate spacer layer 164 may be removed, a recess may be formed, and a lower source / drain region 150A, a barrier structure or barrier layer 155, and an upper source / drain region 150B may be sequentially formed in the recess region.

[0111] A portion of the gate spacer layer 164 may be removed by anisotropic etching. Thus, the upper surface of the sacrificial gate structure 200 and the gate spacer layer 164 present on the upper surface of the active structure may be removed.

[0112] Between the sacrificial gate structures 200 , a recessed region may be formed by removing a portion of the exposed upper sacrificial layer 120B, the upper channel layer 140B, the middle dielectric isolation structure MDI, the lower sacrificial layer 120A, and the lower channel layer 140A.

[0113] By forming an epitaxial layer in the recessed area, a lower source / drain region 150A can be formed. The lower source / drain region 150A can be formed by epitaxial growth and can extend to contact the lower channel layer 140A and the lower sacrificial layer 120A in the recessed area. The barrier structure or barrier layer 155 can be formed to cover the upper surface of the lower source / drain region 150A or overlap with the upper surface of the lower source / drain region 150A. Thereafter, an upper source / drain region 150B can be formed on the barrier structure or barrier layer 155 and the intermediate dielectric isolation structure MDI to fill the remaining recessed area. The upper source / drain region 150B can be formed by epitaxial growth and can extend to contact the upper channel layer 140B and the upper sacrificial layer 120B in the recessed area.

[0114] Reference Fig.11D , a first upper insulating layer 191 may be formed, and the sacrificial gate structure 200 , the upper sacrificial layer 120B, and the lower sacrificial layer 120A may be removed.

[0115] The first upper insulating layer 191 may be formed by forming an insulating film covering or overlapping the sacrificial gate structure 200 and the source / drain region 150 and performing a planarization process.

[0116] The sacrificial gate structure 200, the upper sacrificial layer 120B, and the lower sacrificial layer 120A may be selectively removed with respect to the gate spacer layer 164, the first upper insulating layer 191, the lower channel layer 140A, the upper channel layer 140B, and the intermediate dielectric isolation structure MDI. First, an upper opening region UOR may be formed by removing the sacrificial gate structure 200, an upper gap region UR may be formed by removing the upper sacrificial layer 120B exposed by the upper opening region UOR, and a lower gap region LR may be formed by removing the exposed lower sacrificial layer 120A. For example, when the lower sacrificial layer 120A and the upper sacrificial layer 120B include silicon germanium (SiGe) and the lower channel layer 140A and the upper channel layer 140B include silicon (Si), the lower sacrificial layer 120A and the upper sacrificial layer 120B may be cleaned by using peracetic acid and / or a solution (NH4OH) used in a standard cleaning-1 (SC1) cleaning process. 4 OH:H 2 O 2 :H 2 A wet etching process is performed using MgO (O=1:1:5) as an etchant to selectively remove the lower sacrificial layer 120A and the upper sacrificial layer 120B.

[0117] Reference Fig.11E , a gate dielectric layer 162 may be formed in the upper opening region UOR, the upper gap region UR, and the lower gap region LR.

[0118] The gate dielectric layer 162 may be formed to conformally cover or conformally overlap inner surfaces of the upper open region UOR, the upper gap region UR, and the lower gap region LR.

[0119] Reference Fig.11F , a first sacrificial gate layer 260_1 covering a surface of the gate dielectric layer 162 or a surface overlapping the gate dielectric layer 162 may be formed.

[0120] Refer to Fig.11E and Fig.11F , the first sacrificial gate layer 260_1 may cover or overlap the surface of the gate dielectric layer 162 formed on the channel structure 140 and the intermediate insulating pattern 300 by filling a portion of the upper opening region UOR, the upper gap region UR, and the lower gap region LR. Here, between the first sacrificial gate layers 260_1, lower opening regions LOR spaced apart from each other in the first direction (e.g., X direction) may be formed.

[0121] The first sacrificial gate layer 260_1 may include a metal material (such as W, Ti, Ta, Mo, TiAlC or TaAlC), a metal oxide (such as AlO and LaO), a metal nitride (such as TiN, TaN, WN or TiAlN), a metal oxynitride (such as TiON) and / or an insulating material (such as SiOx).

[0122] Reference Fig.11G A gap filling layer 350 may be formed by filling the lower opening region LOR and the upper opening region UOR with a gap filling material to cover or overlap the surface of the first sacrificial gate layer 260_1. A portion of the gap filling layer 350 may be recessed to form a first recess region R1.

[0123] When forming the first recessed region R1, the upper surface of the recessed gap filling layer 350 may be formed between the heights of the upper and lower surfaces of the intermediate insulating pattern 300. For example, the height of the upper surface of the recessed gap filling layer 350 may be formed at the center of the heights of the upper and lower surfaces of the intermediate insulating pattern 300.

[0124] In the first recess region R1 , a portion of the first sacrificial gate layer 260_1 extending around or surrounding an upper portion of the intermediate insulating pattern 300 and the upper channel layer 140B (or “upper portion 260_1U of the first sacrificial gate layer”) may be exposed.

[0125] The gap-filling layer 350 may include a carbon-based gap-filling material such as an amorphous carbon film.

[0126] Reference Fig.11H , the upper portion 260_1U of the exposed first sacrificial gate layer may be removed by a first wet etching process in the first recessed region R1. By the wet process, at least a portion of the gate dielectric layer 162 may be exposed. In example embodiments, the upper portion of the intermediate insulating pattern 300 of the gate dielectric layer 162 and a portion covering the surface of the upper channel layer 140B or overlapping the surface of the upper channel layer 140B may be exposed. Therefore, the upper gap region UR between the upper channel layers 140B may be re-exposed.

[0127] Through the first wet etching process, a portion of the first sacrificial gate layer 260_1 extending around or surrounding the lower portion of the intermediate insulating pattern 300 and the lower channel layer 140A (or "lower portion 260_1L of the first sacrificial gate layer") may remain. Here, an upper surface of the lower portion 260_1L of the first sacrificial gate layer may be exposed, and the exposed upper surface may have a cross-section bent downward by the wet process (not shown).

[0128] Reference Fig.11I A first blocking layer 265_1 covering or overlapping a surface of the gate dielectric layer 162 exposed by the first wet etching process and blocking the upper gap region UR may be formed.

[0129] Refer to Fig.11I and Fig.11H , the first barrier layer 265_1 may be formed to extend around or surround the upper channel layer 140B and the gate dielectric layer 162 in the upper gap region UR.

[0130] The first barrier layer 265_1 may include a material similar to that of the first sacrificial gate layer 260_1. For example, the first barrier layer 265_1 may include a metal material (such as W, Ti, Ta, Mo, TiAlC, or TaAlC), a metal oxide (such as AlO and LaO), a metal nitride (such as TiN, TaN, WN, or TiAlN), a metal oxynitride (such as TiON), and / or an insulating material (such as SiOx).

[0131] In example embodiments, the first barrier layer 265_1 may include a material different from that of the first sacrificial gate layer 260_1 so as to have an etching selectivity with respect to the first sacrificial gate layer 260_1. For example, when the first sacrificial gate layer 260_1 includes a metal material such as W or Ti, the first barrier layer 265_1 may include a metal oxide such as AlO or LaO, but example embodiments thereof are not limited thereto.

[0132] Reference Fig.11J , a portion of the first barrier layer 265_1 other than a portion formed in the upper gap region UR may be etched through a second wet etching process. Thereafter, the remaining portion of the gap-filling layer 350 may be removed.

[0133] Through the second wet etching process, portions of the first barrier layer 265_1 formed on side surfaces of upper portions of the intermediate insulating pattern 300 , side surfaces of the upper channel layers 140B, and an upper surface of an uppermost upper channel layer among the upper channel layers may be removed.

[0134] When the remaining portion of the gap-filling layer 350 is removed, the lower opening region LOR may be formed again, and the lower portion 260_1L of the first sacrificial gate layer may be exposed by the lower opening region LOR.

[0135] Reference Figure 11K , the lower portion 260_1L of the first sacrificial gate layer may be removed through the lower opening region LOR by a third wet etching process.

[0136] As reference Fig.11I As described above, the first barrier layer 265_1 and the first sacrificial gate layer 260_1 may have etching selectivity to each other, so that the first sacrificial gate layer 260_1 may be selectively removed by the third wet etching process. When the lower portion 260_1L of the first sacrificial gate layer is removed, the lower gap region LR may be formed again, and only the first barrier layer 265_1 in the upper gap region UR may remain.

[0137] Reference Fig.11L , a second sacrificial gate layer 260_2 may be formed to cover the surface of the gate dielectric layer 162 or overlap the surface of the gate dielectric layer 162 .

[0138] The second sacrificial gate layer 260_2 may at least partially or completely fill the lower gap region LR, and may extend around or surround the surface of the lower channel layer 140A, the side surface of the intermediate insulation pattern 300, the side surface of the first barrier layer 265_1 in the upper gap region UR, and the surface of the upper channel layer 140B.

[0139] The second sacrificial gate layer 260_2 may include a metal material. For example, the second sacrificial gate layer 260_2 may include at least one of a metal material such as W, Ti, Ta, Mo, TiAlC, or TaAlC and a metal nitride such as TiN, TaN, WN, or TiAlN.

[0140] Reference Fig.11M ,and Fig.11G Similar to the process in , a gap-filling layer 350 covering the second sacrificial gate layer 260_2 or overlapping the second sacrificial gate layer 260_2 may be formed. A portion of the gap-filling layer 350 may be recessed and may form a second recessed region R2.

[0141] In the second recessed region R2, a portion of the second sacrificial gate layer 260_2 extending around or surrounding an upper portion of the intermediate insulating pattern 300, the first barrier layer 265_1 in the upper gap region UR, and the upper channel layer 140B (or "an upper portion 260_2U of the second sacrificial gate layer") may be exposed.

[0142] Reference Fig.11N , the upper portion 260_2U of the second sacrificial gate layer and the first barrier layer 265_1 in the upper gap region UR may be removed by a fourth wet etching process, and the remaining portion of the gap-filling layer 350 may be removed.

[0143] Reference Fig.11M , the upper portion 260_2U of the second sacrificial gate layer and the first barrier layer 265_1 in the upper gap region UR may be sequentially etched from the partially recessed gap filling layer 350 by the fourth wet etching process. However, in example embodiments, the upper portion 260_2U of the second sacrificial gate layer and the first barrier layer 265_1 in the upper gap region UR may be removed at the same time. In this case, the upper gap region UR between the upper channel layers 140B may be formed again.

[0144] Thereafter, the remaining portion of the gap-filling layer 350 may be removed, and a lower gate electrode 160A_1 extending around or surrounding the lower channel layer 140A and contacting at least a portion of a side surface of the intermediate insulating pattern 300 may be formed.

[0145] FIG. 12A to FIG. 12E 1 and 2 are cross-sectional views sequentially illustrating processes of a method of manufacturing semiconductor devices 100 and 200 according to example embodiments.

[0146] FIG. 12A to FIG. 12E It is shown that by FIG. 11A to FIG. 11N An example of a method of manufacturing a lower gate structure 160A by forming a plurality of lower gate electrode layers 160A_2 and 160A_3 on the manufactured lower gate electrode 160A_1.

[0147] Reference Fig. 12A A second barrier layer 265_2 may be formed to cover or overlap surfaces of the lower gate electrode 160A_1 and the gate dielectric layer 162. Thereafter, a portion of the second barrier layer 265_2 may be removed by a fifth wet etching process.

[0148] The second barrier layer 265_2 may be formed to cover or overlap surfaces of the lower gate electrode 160A_1 and the gate dielectric layer 162 and fill the upper gap region UR.

[0149] Thereafter, through a fifth wet etching process, the second barrier layer 265_2 may have an etching selectivity with respect to the lower gate electrode 160A_1 so that a portion of the surface of the gate dielectric layer 162 covering the lower gate electrode 160A_1 may be selectively removed and only the second barrier layer 265_2 in the upper gap region UR may remain.

[0150] The second barrier layer 265_2 may include a material that is the same as or similar to that of the first barrier layer 265_1. For example, the second barrier layer 265_2 may include a metal material (such as W, Ti, Ta, Mo, TiAlC, or TaAlC), a metal oxide (such as AlO and LaO), a metal nitride (such as TiN, TaN, WN, or TiAlN), a metal oxynitride (such as TiON), and / or an insulating material (such as SiOx).

[0151] In example embodiments, the second barrier layer 265_2 may include Fig.11L The material of the lower gate electrode 160A_1 (or the "second sacrificial gate layer 260_2") is described to have an etching selectivity for the lower gate electrode 160A_1. For example, when the lower gate electrode 160A_1 includes a metal material (such as W or Ti), the second barrier layer 265_2 may include a metal oxide (such as AlO or LaO), but example embodiments thereof are not limited thereto.

[0152] Reference Fig. 12B ,exist Fig. 12A After the process of, at least one or more sacrificial gate layers may be formed in sequence. In an example embodiment, Fig. 12A After the processes in FIG. 1 , a third sacrificial gate layer 260_3 and a fourth sacrificial gate layer 260_4 may be sequentially formed.

[0153] The third sacrificial gate layer 260_3 and the fourth sacrificial gate layer 260_4 may include Fig.11L The material of the lower gate electrode 160A_1 (or "second sacrificial gate layer 260_2") is different from the material described, and the third sacrificial gate layer 260_3 and the fourth sacrificial gate layer 260_4 may include different materials. For example, considering the desired threshold voltage, the third sacrificial gate layer 260_3 and the fourth sacrificial gate layer 260_4 may include a material with an appropriate work function.

[0154] Reference Fig. 12C , a gap-filling layer 350 covering the surface of the fourth sacrificial gate layer 260_4 may be formed. A portion of the gap-filling layer 350 may be recessed to form a third recessed region R3.

[0155] The lower surface of the third recessed region R3 may be formed at a Fig.11G The height of the lower surface of the first recessed region R1 is described with reference to Fig.11M The height of the lower surface of the second recessed region R2 is described as being high.

[0156] Reference Fig.12DThe third sacrificial gate layer 260_3 and the fourth sacrificial gate layer 260_4 disposed in the third recess region R3 may be removed by the sixth wet etching process. A fourth recess region R4 may be formed between the intermediate insulating pattern 300 and the gap-filling layer 350 by the sixth wet etching process.

[0157] Through the sixth wet etching process, the first lower gate electrode layer 160A_2 and the second lower gate electrode layer 160A_3 sequentially disposed on the side surface and the lower surface of the lower gate electrode 160A_1 may be formed.

[0158] An intermediate insulating pattern 300 and a gap-filling layer 350 may be disposed on side surfaces of the fourth recess region R4 , and a lower surface of the fourth recess region R4 may contact the lower gate electrode 160A_1 and the plurality of lower gate electrode layers 160A_2 and 160A_3 .

[0159] Through the sixth wet etching process, the lower surface of the fourth recessed region R4 may have a groove portion recessed downwardly. For example, the lower surface of the fourth recessed region R4 may have a parabolic cross-section curved downwardly.

[0160] Reference Fig.12E ,exist Fig.12D After the processes in , the remaining portion of the gap-fill layer 350 may be removed, and the lower gate structure 160A may be formed.

[0161] FIG. 13A to FIG. 13E are cross-sectional views sequentially illustrating processes of a method of fabricating a semiconductor device according to example embodiments.

[0162] FIG. 13A to FIG. 13E shows the use of FIG. 12A to FIG. 12E The gate isolation insulating layer 170 and the upper gate structure 160B are formed on the manufactured lower gate structure 160A to manufacture the semiconductor devices 100A and 200A.

[0163] Reference Fig.13A , a gate isolation insulating layer 170 covering or overlapping surfaces of the lower gate electrode 160A_1 and the plurality of lower gate electrode layers 160A_2 and 160A_3 may be formed.

[0164] The gate isolation insulating layer 170 may be conformally formed on the surface of the lower gate electrode 160A_1 and the plurality of lower gate electrode layers 160A_2 and 160A_3. The gate isolation insulating layer 170 may extend along the second direction (eg, the Y direction). The gate isolation insulating layer 170 may be formed, for example, by atomic layer deposition (ALD).

[0165] Reference Fig. 13B, the second barrier layer 265_2 in the upper gap region UR may be removed. Thereafter, by forming a mask pattern M on the predetermined channel structure 140, the gate isolation insulating layer 170 may remain only on the predetermined lower transistor.

[0166] The gate isolation insulating layer 170 may include an insulating material. For example, the gate isolation insulating layer 170 may include at least one insulating material such as SiOx, SiN, SiOCN, or SiCN.

[0167] Since the second barrier layer 265_2 in the upper gap region UR has an etching selectivity with respect to the gate isolation insulating layer 170, the second barrier layer 265_2 may be selectively removed. In this case, the upper gap region UR may be formed again.

[0168] A mask pattern M may be formed on the channel structure 140 on the lower transistor on which the gate isolation insulating layer 170 may remain. Portions of the gate isolation insulating layer 170 formed in portions other than portions in which the mask pattern M is not formed may be etched through an etching process.

[0169] Reference Fig. 13C , a gate structure 160 may be formed in the upper gap region UR.

[0170] The upper gate electrode 165 may be formed to fill the upper gap region UR. Thus, a gate structure 160 including a gate dielectric layer 162 , a gate electrode 165 , and a gate spacer layer 164 may be formed.

[0171] Reference Fig.13D , a contact structure 180B, a gate contact structure 190B, and a first interconnection M1 may be formed.

[0172] A second upper insulating layer 192 may be formed to cover the gate structure 160 or overlap the gate structure 160, a contact hole connected to the source / drain region 150 and the upper gate electrode 165 may be formed in the second upper insulating layer 192, and a barrier layer (not shown) and a plug conductive layer may be formed in sequence so that the contact hole may be at least partially or completely filled.

[0173] The third upper insulating layer 193 may be formed to cover or overlap the contact structure 180B and the gate contact structure 190B, and the first interconnection M1 may be formed by patterning the third upper insulating layer 193 and filling a conductive material.

[0174] Although not shown, an interlayer insulating layer may be further formed between the second upper insulating layer 192 and the third upper insulating layer 193 to form a via hole connecting the contact structure 180 to the first interconnection M1 .

[0175] Reference Fig.13E ,according to Fig.13D The entire structure may be attached to a carrier substrate SUB, and a back gate structure 160_1 and a contact structure 180A may be formed. Thereafter, a back contact hole BCH may be formed.

[0176] The carrier substrate SUB may be attached to the third upper insulating layer 193 or the first interconnection M1 to Fig.13D The process is performed on the lower surface of the substrate 101 in FIG. Fig.13E The entire structure can be shown as Fig.13D A mirror image rotation or inversion of the structure shown in .

[0177] In example embodiments, a lower contact structure 180A penetrating the first lower insulating layer 194 , the back gate structure 160_1 , and the first lower insulating layer 194 and connected to the lower source / drain region 150A may be formed after the substrate 101 , the active region 105 , and the device isolation layer 110 .

[0178] Thereafter, a second lower insulating layer 195 covering or overlapping the first lower insulating layer 194 , the back gate structure 160_1 and the lower contact structure 180A may be formed, and a back contact hole BCH penetrating the second lower insulating layer 195 may be formed.

[0179] A back contact structure 180A and a back gate contact structure 190A may be formed to fill the back contact hole BCH.

[0180] Reference Figure 2 A third lower insulating layer 196 covering the back contact structure 180A and the back gate contact structure 190A or overlapping the back contact structure 180A and the back gate contact structure 190A may be formed, and a second interconnect M2 may be formed by patterning the third lower insulating layer 196 and filling it with a conductive material.

[0181] Refer to Figure 2 as well as FIG. 4A to FIG. 4C , connected to the first lower metal interconnection M2a of the first transistor structure TR1 (see Figure 2 and Figure 4A ) and a first upper metal interconnection M1a connected to the fourth transistor structure TR4 (see Figure 2 and Figure 4B ) may be electrically connected to each other in regions other than the regions shown in the figure.

[0182] FIG. 14A to FIG. 14E are cross-sectional views sequentially illustrating processes of a method of fabricating a semiconductor device according to example embodiments.

[0183] FIG. 14A to FIG. 14E It is a reference FIG. 12A to FIG. 12E A continuation of the description of the manufacturing method is provided to describe a method of manufacturing the semiconductor devices 100B and 200B according to example embodiments.

[0184] Reference Fig.14A , a mask pattern M may be disposed on the predetermined channel structure 140 , and etching may be performed through the mask pattern M, thereby cutting the lower gate electrode 160A_1 connected between the lower transistors adjacent in the second direction (eg, the Y direction).

[0185] For electrical insulation between upper / lower transistors spaced apart from each other in the vertical direction (Z direction), and also for electrical insulation between the lower transistor and the adjacent lower transistor in the second direction (e.g., Y direction), the lower gate electrodes 160A_1 connected between the lower transistors adjacent in the second direction may be cut by a method such as photolithography. The first distance l1 between the cut lower gate electrodes 160A_1 may be about 10 nm or more, for example, 10 nm to 20 nm, 10 nm to 15 nm, or 15 nm to 20 nm. Therefore, at least a portion of the insulating layer formed on the device isolation layer 110 may be exposed.

[0186] The outer side surfaces of the lower gate electrode 160A_1 of the predetermined lower transistor and the plurality of lower gate electrode layers 160A_2 and 160A_3 may be perpendicular to the upper surface of the substrate 101, but example embodiments thereof are not limited thereto. Figure 6B , outer side surfaces of the lower gate electrode 160A_1 of the predetermined lower transistor and the plurality of lower gate electrode layers 160A_2 and 160A_3 may form an oblique line with the upper surface of the substrate 101 .

[0187] Reference Fig. 14B ,and Fig.13A Similar to the process in , a gate isolation insulating layer 170 covering the surfaces of the lower gate electrode 160A_1 and the plurality of lower gate electrode layers 160A_2 and 160A_3 and at least a portion of the insulating layer formed on the device isolation layer 110 may be formed.

[0188] The gate isolation insulating layer 170 may be conformally formed on surfaces of the lower gate electrode 160A_1 and the plurality of lower gate electrode layers 160A_2 and 160A_3. The gate isolation insulating layer 170 may be formed, for example, by atomic layer deposition (ALD).

[0189] Reference Fig. 14C ,and Fig. 13BSimilar to the process in , the second barrier layer 265_2 in the upper gap region UR may be removed. Thereafter, by forming a mask pattern M on the predetermined channel structure 140, the gate isolation insulating layer 170 may remain only on the predetermined lower transistor. A repeated description will not be provided.

[0190] Reference Fig.14D ,and Fig. 13C Similarly, a gate structure 160 may be formed in the upper gap region UR. Fig.13D Similarly, the contact structure 180B, the gate contact structure 190B, and the first interconnection M1 may be formed. A repeated description will not be provided.

[0191] Reference Fig.14E ,and Fig.13E Similar, see FIG. 14A to FIG. 14D The entire structure formed may be attached to a carrier substrate SUB, and a backside process may be performed. A repeated description will not be provided.

[0192] According to the aforementioned example embodiments, a semiconductor device with increased integration density and guaranteed reliability can be provided by including a gate isolation insulating layer that electrically insulates upper and lower devices spaced apart from each other in a vertical direction and / or electrically insulates the lower device of each device adjacent in a horizontal direction.

[0193] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: substrate; lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extending in a first direction parallel to the upper surface of the substrate; an upper channel layer on the lower channel layer and spaced apart from each other in the vertical direction; an intermediate dielectric isolation structure, between the uppermost lower channel layer among the lower channel layers and the lowermost upper channel layer among the upper channel layers; a lower gate structure, on the lower channel layer; an upper gate structure, on the upper channel layer and extending along a second direction perpendicular to the first direction; a gate isolation insulating layer, between the lower gate structure and the upper gate structure, in contact with a side surface of the intermediate dielectric isolation structure on the lower gate structure, and on at least a portion of the lower gate structure; a lower source / drain region on at least one side of the lower gate structure and electrically connected to the lower channel layer; an upper source / drain region electrically connected to each of the upper channel layers on at least one side of the upper gate structure and spaced apart from the lower source / drain region in the vertical direction; as well as A barrier structure is provided between the lower source / drain region and the upper source / drain region.

2. The semiconductor device according to claim 1, wherein The lower gate structure comprises: a lower gate electrode extending around the lower channel layer and extending along the second direction; a first lower gate electrode layer on the side surface and the lower surface of the lower gate electrode; and A second lower gate electrode layer is on the side surface and the lower surface of the first lower gate electrode layer.

3. The semiconductor device according to claim 2, wherein: The gate isolation insulating layer extends along a side surface of the lower gate structure, extends on an upper surface of the lower gate structure, and contacts at least a portion of a lower surface of the second lower gate electrode layer.

4. The semiconductor device according to claim 2, wherein: The lower gate electrode, the first lower gate electrode layer, and the second lower gate electrode layer include different materials.

5. The semiconductor device according to claim 1, wherein The lower gate structure comprises: a lower gate electrode extending around the lower channel layer; a first lower gate electrode layer on the side surface and the lower surface of the lower gate electrode; and a second lower gate electrode layer on the side surface and the lower surface of the first lower gate electrode layer, and The lower gate electrode is in contact with the gate isolation insulating layer, and the first lower gate electrode layer is in contact with the gate isolation insulating layer.

6. The semiconductor device according to claim 5, wherein: The lowermost end of the lower gate structure and the lowermost end of the upper gate structure are substantially at the same height.

7. The semiconductor device according to claim 5, in, In the cross-sectional view in the second direction, the gate isolation insulating layer contacts the side surface of the intermediate dielectric isolation structure on the upper surface of the lower gate structure, The gate isolation insulating layer extends along the side surface of the second lower gate electrode layer, and Wherein, in the lower portion of the lower gate structure, the gate isolation insulating layer is on the side surface of the lower gate electrode and on the side surface of the first lower gate electrode layer.

8. The semiconductor device according to claim 7, wherein: The gate isolation insulating layer vertically extends along the side surface of the lower gate structure toward the upper surface of the substrate.

9. The semiconductor device according to claim 7, in, The gate isolation insulating layer extends diagonally with respect to the upper surface of the substrate along the side surface of the second lower gate electrode layer, and Wherein, in the lower portion of the lower gate structure, the gate isolation insulating layer extends perpendicularly to the upper surface of the substrate along the side surface of the lower gate electrode and the side surface of the first lower gate electrode layer.

10. The semiconductor device according to claim 7, wherein: The lower surface of the gate isolation insulating layer and the lowermost end of the lower gate electrode are substantially at the same distance from the substrate.

11. The semiconductor device according to claim 7, wherein: An upper surface of the lower gate structure is between an upper surface of the intermediate dielectric isolation structure and a lower surface of the intermediate dielectric isolation structure.

12. The semiconductor device according to claim 1, wherein An upper surface of the lower gate structure is between an upper surface of the intermediate dielectric isolation structure and a lower surface of the intermediate dielectric isolation structure.

13. The semiconductor device according to claim 1, in, The upper surface of the lower gate structure has a curved portion, and At least a portion of the gate isolation insulating layer extends into the bent portion.

14. The semiconductor device according to claim 1, wherein The gate isolation insulating layer has a thickness of 5 nm to 15 nm.

15. The semiconductor device according to claim 1, wherein The gate isolation insulating layer has a pad shape.

16. A semiconductor device comprising: substrate; first lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and extending in a first direction parallel to the upper surface of the substrate; a first upper channel layer on the first lower channel layer and spaced apart from each other in the vertical direction; A first intermediate dielectric isolation structure is between the uppermost lower channel layer among the first lower channel layers and the lowermost upper channel layer among the first upper channel layers; A first lower gate structure, comprising a lower gate electrode on the first lower channel layer; a first upper gate structure, on the first upper channel layer and extending along a second direction perpendicular to the first direction; a first lower gate isolation insulating layer, between the first lower gate structure and the first upper gate structure; lower source / drain regions, on at least one side of the first lower gate structure and electrically connected to the first lower channel layer, respectively; an upper source / drain region electrically connected to each of the first upper channel layers on at least one side of the first upper gate structure and spaced apart from the lower source / drain region in the vertical direction; a barrier structure between the lower source / drain region and the upper source / drain region; a lower gate contact structure, below the first lower gate structure and electrically connected to the lower gate electrode of the first lower gate structure; as well as a lower interconnection portion below the lower gate contact structure and electrically connected to the lower gate contact structure, wherein the first lower gate isolation insulating layer contacts the side surface of the first intermediate dielectric isolation structure, and The first lower gate isolation insulating layer extends along the side surface of the first lower gate structure.

17. The semiconductor device according to claim 16, further comprising: a second lower channel layer, spaced apart from each other in the vertical direction, electrically connected to the lower source / drain region, and adjacent to the first lower channel layer in the first direction; a second upper channel layer, on the second lower channel layer, spaced apart from each other in the vertical direction, electrically connected to the upper source / drain region, and adjacent to the first upper channel layer in the first direction; a second intermediate dielectric isolation structure, between the uppermost lower channel layer among the second lower channel layers and the lowermost upper channel layer among the second upper channel layers; a second lower gate structure extending around the second lower channel layer; a second upper gate structure, comprising an upper gate electrode, extending around the second upper channel layer on the second lower gate structure and extending in a second direction perpendicular to the first direction; a second gate isolation insulating layer, between the second lower gate structure and the second upper gate structure; an upper gate contact structure on the second upper gate structure and electrically connected to the upper gate electrode of the second upper gate structure; as well as an upper interconnection portion on the upper gate contact structure and electrically connected to the upper gate contact structure, Wherein, the upper interconnection is electrically connected to the lower interconnection.

18. The semiconductor device according to claim 16, wherein: The first lower gate structure is configured to exchange an input / output signal through the lower interconnection.

19. A semiconductor device comprising: Substructure; Superstructure; intermediate dielectric isolation structures extending along a first direction between the lower structure and the upper structure and spaced apart from each other in a second direction perpendicular to the first direction; a gate isolation insulating layer between at least a portion of the lower structure and at least a portion of the upper structure and extending from a side surface of at least a portion of the intermediate dielectric isolation structure toward a lower end of the lower structure, Wherein, the lower structure comprises: lower source / drain regions spaced apart from each other in the first direction; a lower active layer spaced apart from each other in a vertical direction, between the lower source / drain regions, and electrically connected to the lower source / drain regions; and a lower gate structure, comprising a first lower gate structure and a second lower gate structure, wherein the first lower gate structure has a first lower gate electrode extending in a second direction perpendicular to the first direction, and the second lower gate structure comprises a second lower gate electrode electrically insulated from the first lower gate electrode by the gate isolation insulating layer, Wherein, the superstructure comprises: upper source / drain regions, spaced apart from each other in the first direction and overlapping with the lower source / drain regions in the vertical direction; an upper active layer spaced apart from each other in the vertical direction, between the upper source / drain regions, connected to the upper source / drain regions, and overlapping with the lower active layer in the vertical direction; and an upper gate structure extending along the second direction and overlapping with the lower gate structure in the vertical direction, The gate isolation insulating layer is in contact with the side surface of the intermediate dielectric isolation structure on the second lower gate structure. The gate isolation insulating layer extends along the side surface of the second lower gate structure, and The distance between the lower end of the gate isolation insulating layer and the substrate is substantially the same as the distance between the lower end of the second lower gate structure and the lower end of the upper structure and the substrate.

20. The semiconductor device according to claim 19, wherein The upper source / drain region and the lower source / drain region have different conductivity types.

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