Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device includes: a substrate; a first transistor including a first active layer disposed on the substrate and a first gate electrode disposed on the first active layer; and a first gate insulating layer disposed between the first active layer and the first gate electrode. The first active layer includes an oxide semiconductor containing indium (In) in a content range of about 40 at% to about 54 at%, and the first gate insulating layer has an emission range of oxygen (O2) of about 2.48 E + 19 Molec. / cm < 3 > to about 2.76 E + 19 Molec. / cm < 3 > and / or an emission range of nitrogen monoxide (NO) of about 1.04 E + 20 Molec. / cm < 3 > to about 1.15 E + 20 Molec. / cm < 3 > under a heat treatment condition performed at a temperature range of about 50 DEG C to about 550 DEG C.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0121490 filed on September 13, 2023, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display device and a method for manufacturing the display device. Background Art

[0004] With the development of multimedia technology, the importance of display devices has been increasing. Accordingly, various types of display devices, such as liquid crystal display devices or light emitting display devices, have been developed. Summary of the invention

[0005] Aspects of the present invention provide a display device including an oxide semiconductor and a method for manufacturing the display device.

[0006] The aspects of the present invention are not limited to the embodiments set forth herein. The above and other aspects of the present invention will become more apparent to those skilled in the art to which the present invention pertains by referring to the detailed description of the present invention given below.

[0007] According to an embodiment, a display device is provided, the display device including: a substrate; a first transistor including a first active layer disposed on the substrate and a first gate electrode disposed on the first active layer; and a first gate insulating layer disposed between the first active layer and the first gate electrode. The first active layer includes an oxide semiconductor containing indium (In) having a content ranging from about 40 at% to about 54 at%, and under a heat treatment condition performed at a temperature ranging from about 50°C to about 550°C, the first gate insulating layer has a strength of about 2.48E+19 Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 Oxygen (O 2 ) or has an emission of about 1.04E+20Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 The emissions of nitric oxide (NO) are within the range of .

[0008] In an embodiment, the first active layer may further contain at least one of gallium (Ga), zinc (Zn), and tin (Sn).

[0009] In an embodiment, the first active layer may contain indium gallium zinc oxide (IGZO), indium tin gallium oxide (ITGO), or indium tin gallium zinc oxide (ITGZO).

[0010] In an implementation, the first gate insulating layer may contain silicon oxide.

[0011] In an embodiment, the display device may further include a pixel including a pixel circuit including the first transistor and a light emitting element connected to the pixel circuit.

[0012] In an embodiment, the pixel may further include: a second transistor including a second active layer disposed on the substrate and a second gate electrode disposed on the second active layer; and a second gate insulating layer disposed between the second active layer and the second gate electrode.

[0013] In an embodiment, the second active layer may be disposed in the same layer as the first active layer and contain the same oxide semiconductor as that of the first active layer.

[0014] In an implementation, the second gate insulating layer may be disposed in the same layer as the first gate insulating layer and contain the same insulating material as that of the first gate insulating layer.

[0015] In an implementation, the display device may further include a driver disposed on the substrate and electrically connected to the pixels.

[0016] In an embodiment, the driver may include: a third transistor, including a third active layer disposed on the substrate and containing an oxide semiconductor identical to that of the first active layer, and a third gate electrode disposed on the third active layer; and a third gate insulating layer disposed between the third active layer and the third gate electrode and containing an insulating material identical to that of the first gate insulating layer.

[0017] In an embodiment, the first active layer may include a first channel region overlapping the first gate electrode, and a first drain region and a first source region located on both sides of the first channel region, and the first gate insulation layer may be an insulating pattern disposed only on a portion of the first active layer including the first channel region and exposing the first drain region and the first source region.

[0018] In an embodiment, the display device may further include an interlayer insulating layer disposed on the substrate and covering the first active layer and the first gate electrode, wherein the first transistor may further include at least one of a first drain electrode disposed on the interlayer insulating layer and connected to a portion of the first active layer and a first source electrode disposed on the interlayer insulating layer and connected to another portion of the first active layer.

[0019] In an implementation, the display device may further include a first passivation layer disposed on the interlayer insulating layer and covering the first transistor.

[0020] In an implementation, the first passivation layer may include an inorganic insulating layer including silicon nitride.

[0021] In an embodiment, the display device may further include a second passivation layer disposed on the first passivation layer. The first passivation layer may include an inorganic insulating layer including silicon oxide, and the second passivation layer may include an inorganic insulating layer including silicon nitride.

[0022] In an embodiment, the first transistor may have a 2 / Vs~about 50cm 2 / Vs range.

[0023] In an implementation, the first transistor may have a threshold voltage in a range of about -1.0V to about +0.5V.

[0024] According to an embodiment, a method for manufacturing a display device is provided, including: forming an active layer on a substrate; forming a gate insulating layer on the active layer; and forming a gate electrode on the gate insulating layer. In the formation of the active layer, an oxide semiconductor containing indium (In) having a content ranging from about 40 at% to about 54 at% is used to form the active layer, and in the formation of the gate insulating layer, an insulating material containing an oxide is deposited on the substrate on which the active layer is formed at a pressure ranging from about 1400 mTorr to about 1500 mTorr to form the gate insulating layer.

[0025] In an embodiment, the method may further include etching the gate insulating layer to have a shape corresponding to a shape of the gate electrode.

[0026] In an embodiment, the method may further include forming an interlayer insulating layer covering the active layer and the gate electrode, and forming at least one of a drain electrode connected to a portion of the active layer and a source electrode connected to another portion of the active layer on the interlayer insulating layer.

[0027] A display device according to an embodiment includes: a first transistor including a first active layer and a first gate electrode disposed on the first active layer; and a first gate insulating layer disposed between the first active layer and the first gate electrode. The first active layer may include an oxide semiconductor containing indium (In) having a content ranging from about 40 at% to about 54 at%, and the first gate insulating layer may have an emission amount of nitric oxide (NO) ranging from about 1.04E+20 Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 and / or oxygen (O 2 ) has an emission range of about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 characteristics.

[0028] According to an embodiment, the element characteristics of the transistor can be appropriately controlled and / or ensured while forming a transistor of a relatively simple structure by using a high-mobility oxide semiconductor. In an embodiment, by controlling the content of indium (In) contained in the oxide semiconductor forming the active layer and the reaction with nitrogen monoxide (NO) and / or oxygen (O 2 ) can appropriately and / or easily control the electrical characteristics of the transistor by adjusting the characteristics of the gate insulating layer related to the emission amount of the transistor. Accordingly, the use of a high-mobility oxide semiconductor can form a transistor having element characteristics suitable for a display panel without forming an additional layer for supplying oxygen to the active layer. As a result, the structure and manufacturing process of the display device can be simplified and / or streamlined, and the manufacturing efficiency of the display device can be increased. In addition, by forming a transistor using a high-mobility oxide semiconductor, although the transistor is formed in a micro size, appropriate element characteristics can still be ensured. Accordingly, a high-resolution display device can be easily manufactured.

[0029] The effects according to the embodiments of the present invention are not limited to those exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 A plan view for explaining a display device according to an embodiment;

[0032] Figure 2 To explain the embodiment according to Figure 1 A plan view of a display panel;

[0033] Figure 3 A circuit diagram for explaining a pixel according to an embodiment;

[0034] Figure 4 A cross-sectional view for explaining a display panel according to an embodiment;

[0035] Figure 5 A cross-sectional view for explaining a display panel according to an embodiment;

[0036] Figure 6 A cross-sectional view for explaining a display panel according to an embodiment;

[0037] Figure 7 A graph for explaining that characteristics of a transistor according to an embodiment vary according to a content of indium contained in an active layer of the transistor and a deposition pressure of a gate insulating layer;

[0038] Figure 8A graph for explaining that characteristics of a transistor according to an embodiment vary according to a content of indium contained in an active layer of the transistor and a deposition pressure of a gate insulating layer;

[0039] Fig. 9 A bar graph for explaining an emission amount of nitric oxide according to a deposition pressure of a gate insulating layer according to an embodiment;

[0040] Fig.10 A bar graph for explaining an amount of oxygen discharged according to a deposition pressure of a gate insulating layer according to an embodiment;

[0041] Fig.11 A cross-sectional view for explaining a method for manufacturing a display device according to an embodiment;

[0042] Fig.12 A cross-sectional view for explaining a method for manufacturing a display device according to an embodiment;

[0043] Fig.13 A cross-sectional view for explaining a method for manufacturing a display device according to an embodiment;

[0044] Fig.14 A cross-sectional view for explaining a method for manufacturing a display device according to an embodiment;

[0045] Fig.15 A cross-sectional view for explaining a method for manufacturing a display device according to an embodiment;

[0046] Fig.16 A cross-sectional view for explaining a method for manufacturing a display device according to an embodiment;

[0047] Fig.17 A cross-sectional view for explaining a method for manufacturing a display device according to an embodiment; and

[0048] Fig.18 A cross-sectional view for explaining a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0049] The present invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art.

[0050] It will also be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or intervening layers may also be present. Throughout the specification, like reference numerals refer to like components.

[0051] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0052] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part.

[0053] The terms used in this article are only used to describe the purpose of specific embodiments and are not intended to be limited. Unless the context clearly indicates otherwise, "one (a)", "one (an)" and "at least one" as used in this article do not represent the limitation of quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" is not interpreted as being limited to "one (a)" or "an". "Or" means "and / or". The term "and / or" as used in this article includes any and all combinations of one or more related enumerated items. In addition, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the elements included in the narration, but do not exclude any other elements.

[0054] As used herein, the term "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an ideal or overly formal sense unless explicitly defined as such in this article.

[0056] Embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of ideal embodiments. As such, variations in the illustrated shapes caused by, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the zones as illustrated herein, but should include deviations in shape caused, for example, by manufacturing. For example, a zone illustrated or described as flat may typically have rough and / or nonlinear features. Moreover, the illustrated sharp corners may be rounded. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones and are not intended to limit the scope of the invention.

[0057] The features of each of the individual embodiments may be partially or completely combined with one another and may interact with one another technically differently, and the individual embodiments may be implemented independently of one another or may be implemented together in association with one another.

[0058] Figure 1 1 is a plan view for explaining a display device 100 according to an embodiment. Figure 2 To explain the embodiment according to Figure 1 FIG. 1 is a plan view of a display panel 110 .

[0059] In an embodiment, and with reference to Figure 1 and Figure 2 , the display device 100 is a device for displaying moving images or still images. The display device 100 can be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile personal computers (UMPCs). These are presented only as examples, and the display device 100 can be applied to various other types of electronic devices.

[0060] In an embodiment, the display device 100 may be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device using an ultra-small light-emitting diode such as a micro light-emitting diode or a nano light-emitting diode (micro-LED or nano-LED), but is not limited thereto. For example, the display device 100 may be a type other than a light-emitting display device. Hereinafter, an embodiment in which the display device 100 is an organic light-emitting display device will be disclosed.

[0061] In an embodiment, the display device 100 may include a display panel 110 including pixels PX, and a first driver 120 and a second driver 130 configured to supply a driving signal to the pixels PX. The display device 100 may further include additional components. For example, the display device 100 may further include a power supply unit for supplying a power supply voltage to the pixels PX, the first driver 120 and the second driver 130, and a timing controller for controlling the operation of the first driver 120 and the second driver 130.

[0062] In an embodiment, the display panel 110 may include a display area DA and a non-display area NDA (also referred to as a "frame area"). The display area DA may be an area including pixels PX to display an image. The non-display area NDA is an area outside the display area DA, and an image may not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA may be located around the display area DA and may surround the display area DA.

[0063] In an embodiment, and with reference to Figure 1 and Figure 2 , defining a first direction D1, a second direction D2, and a third direction D3. In an embodiment, the first direction D1 and the second direction D2 may be orthogonal to each other, the first direction D1 and the third direction D3 may be orthogonal to each other, and the second direction D2 and the third direction D3 may be orthogonal to each other. For example, the first direction D1 may be a horizontal direction of the display panel 110 (e.g., a row direction or an X direction), and the second direction D2 may be a vertical direction of the display panel 110 (e.g., a column direction or a Y direction). The third direction D3 may be a thickness direction of the display panel 110 (e.g., a height direction or a Z direction).

[0064] In an embodiment, the display panel 110 may have a rectangular shape in a plan view. For example, the display panel 110 may include two first sides extending in a first direction D1 and two second sides extending in a second direction D2 intersecting the first direction D1. Figure 1 and Figure 2The display panel 110 is explained in which the first side in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction, or a shape in which the lengths of the first side and the second side are substantially the same.

[0065] In an embodiment, the display panel 110 may include an angled corner at a portion where the first side and the second side meet, but the present disclosure is not limited thereto. For example, the display panel 110 may include a rounded corner at a portion where the first side and the second side meet.

[0066] In an embodiment, the planar shape of the display panel 110 is not limited to the illustrated rectangular shape, and other shapes may be applied. For example, the display panel 110 may have a square shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes in a plan view.

[0067] In an embodiment, the display panel 110 may be substantially flat on a plane defined by the first direction D1 and the second direction D2, and may have a uniform thickness in the third direction D3. In another embodiment, the display panel 110 may be provided in a three-dimensional shape having a curved surface or the like.

[0068] In an embodiment, the display panel 110 may be provided as a panel having a rigid property so as not to be substantially deformed, or as a panel having a flexible property that may be deformed to be at least partially folded, bent, or rolled. The display panel 110 may be provided to the display device 100 without being bent, or may be provided to the display device 100 while being partially bent.

[0069] In an embodiment, the display panel 110 may include a substrate SUB and pixels PX disposed on the substrate SUB. The pixels PX may be disposed on the substrate SUB in the display area DA.

[0070] In an implementation, the substrate SUB may be a base member for manufacturing or providing the display panel 110, and may constitute a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA around the display area DA.

[0071] According to an embodiment, the display area DA may have various shapes. For example, in an embodiment, the display area DA may have a quadrilateral shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes. In another embodiment, the display area DA may have a shape corresponding to the shape of the display panel 110, but the present disclosure is not limited thereto.

[0072] In an embodiment, the display area DA may include a pixel area in which the pixel PX is provided and / or arranged. For example, each pixel PX may be arranged in each pixel area located in the display area DA. In an embodiment, the display device 100 may be a light-emitting display device, and each pixel PX may include a light-emitting element located in each emission area and a pixel circuit connected to the light-emitting element. When describing an embodiment, the term "connection" may include electrical connection and / or physical connection.

[0073] In an embodiment, each pixel region may include: an emission region, in which a light emitting element of a corresponding pixel is located, and in which the pixel emits light; and a pixel circuit region, in which circuit elements constituting a pixel circuit of the corresponding pixel are located. In an embodiment, the emission region and the pixel circuit region of each pixel PX may overlap each other, but the present invention is not limited thereto.

[0074] In an embodiment, the pixels PX may be arranged in the display area DA. For example, the pixels PX may be arranged in the display area DA in a stripe structure, a delta structure, a pentile structure, or other arrangement structures.

[0075] In an embodiment, the non-display area NDA may include a driving circuit area located at least one side of the display area DA and a pad area PA provided with pads PD. At least one driver, pads PD and / or wirings may be provided in the non-display area NDA.

[0076] In an embodiment, at least one driver or a portion of at least one driver for driving the pixel PX may be disposed in the driving circuit region. For example, circuit elements constituting the first driver 120 may be disposed on the substrate SUB in the driving circuit region. In an embodiment, the circuit elements of the first driver 120 may be formed in the display panel 110 together with the pixel PX.

[0077] In an embodiment, the pad PD may be disposed in the pad area PA. At least one circuit board 140 may be disposed and / or bonded to the pad area PA. In an embodiment, a plurality of circuit boards 140 connected to different pads PD may be disposed on the pad area PA. The pad PD may include a signal pad and a power pad for transmitting a driving signal and a power supply voltage required for driving the pixel PX and / or the first driver 120 to the display panel 110.

[0078] In an embodiment, the first driver 120 and the second driver 130 may generate a driving signal for controlling the operation timing and brightness of the pixel PX, and may supply the generated driving signal to the pixel PX. For example, the first driver 120 may be a gate driver including a scan driver, and may be connected to the pixel PX through a corresponding gate line. The first driver 120 may generate a gate signal (e.g., a driving signal for controlling the operation timing of the pixel PX, such as Figure 3 The second driver 130 may be a data driver including a source driving circuit and may be connected to the pixel PX through a corresponding data line. The second driver 130 may supply a corresponding data signal to the pixel PX.

[0079] In an embodiment, at least one of the first driver 120 and the second driver 130 or a portion of at least one of the drivers may be embedded in the display panel 110. For example, the first driver 120 or a portion of the first driver 120 may be disposed and / or formed in the non-display area NDA and disposed on the substrate SUB of the display panel 110.

[0080] In an embodiment, although Figure 1 It is explained that the first driver 120 is formed on one side of the display area DA (for example, in the non-display area NDA on the right side of the display area DA), but the present invention is not limited thereto. For example, the first driver 120 may be located only on the other side of the display area DA (for example, in the non-display area NDA on the left side of the display area DA), or may be located on both sides of the display area DA (for example, in the non-display area NDA on the left and right sides of the display area DA). In another embodiment, a portion of the first driver 120 (for example, some circuit elements constituting the first driver 120) is located in the non-display area NDA, and another portion of the first driver 120 (for example, the remaining circuit elements constituting the first driver 120) may be located in a non-emission area inside the display area DA (for example, an area between emission areas of the pixels PX).

[0081] In an embodiment, the other driver of the first driver 120 and the second driver 130 or a part of the other driver may be disposed or formed outside the display panel 110 to be electrically connected to the display panel 110. For example, the second driver 130 or a part of the second driver 130 may be implemented by a plurality of integrated circuit chips and may be placed on a circuit board 140 electrically connected to the pixel PX of the display panel 110. In an embodiment, the second driver 130 may be integrated into an integrated circuit chip separate from the timing controller or may be integrated into one integrated circuit chip with the timing controller. The second driver 130 may be implemented by at least one integrated circuit chip and mounted in the non-display area NDA of the display panel 110.

[0082] In an embodiment, the circuit board 140 may be connected to the display panel 110 through the pad PD. In an embodiment, the circuit board 140 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film (such as a chip on film (COF)), but is not limited thereto. In an embodiment, the circuit board 140 may be connected to the timing controller and / or the power supply unit through another circuit board or a connector, etc.

[0083] Figure 3 1 is a circuit diagram for explaining a pixel PX according to an embodiment. Figure 3 The pixel PX is presented as just one example, and the structure or type of the pixel PX may be variously changed according to the embodiment.

[0084] In an embodiment, and except Figure 1 and Figure 2 In addition, reference Figure 3 , the pixel PX may include a light emitting element ED and a pixel circuit PC connected to the light emitting element ED. The light emitting element ED is a light source of the pixel PX, and it may be, for example, an organic light emitting diode, but is not limited thereto. The pixel circuit PC may control the emission of the light emitting element ED by supplying a driving current Id corresponding to a data signal DATA to the light emitting element ED.

[0085] In an embodiment, the pixel circuit PC may include a pixel transistor Tpx and at least one capacitor C1. For example, the pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor C1. The structure of the pixel circuit PC or the type and number of circuit elements constituting the pixel circuit PC may be variously changed according to the embodiment. For example, the pixel circuit PC may further include at least one other pixel transistor and / or at least one other capacitor. Figure 3 An embodiment in which all pixel transistors Tpx are N-type transistors is explained. However, the type of pixel transistors Tpx is not limited thereto. For example, at least one pixel transistor Tpx may be formed as a P-type transistor.

[0086] In an embodiment, the pixel circuit PC may supply the driving current Id to the light emitting element ED in response to the driving signals supplied from the first driver 120 and the second driver 130. For example, the pixel circuit PC may supply the driving current Id to the light emitting element ED in response to at least one gate signal GW (e.g., a scanning signal for selecting the pixel PX of each horizontal line) supplied from the first driver 120 through at least one gate line GWL (e.g., a scanning line connected to the pixel PX of each horizontal line) and the data signal DATA supplied from the second driver 130 through the data line DL.

[0087] In an embodiment, the first transistor T1 may be a switching transistor that is turned on or off according to a gate-source voltage. The second transistor T2 may be a driving transistor of the pixel PX, and the size of its drain-source current (e.g., driving current Id) is determined according to the gate-source voltage. According to the type (e.g., P-channel transistor or N-channel transistor) and / or operating conditions of each of the first transistor T1 and the second transistor T2, the first electrode of each of the first transistor T1 and the second transistor T2 may be a drain electrode (or drain region) or a source electrode (or source region), and the second electrode thereof may be an electrode different from the first electrode. For example, when the first electrode of the first transistor T1 is a drain electrode, the second electrode of the first transistor T1 may be a source electrode.

[0088] In an embodiment, the pixel PX may be connected to a gate line GWL (e.g., a scan line) transmitting a gate signal GW (e.g., a scan signal) and a data line DL transmitting a data signal DATA. In addition, the pixel PX may be connected to a first pixel power line VDL transmitting a first pixel voltage ELVDD (also referred to as a "first pixel power supply voltage") and a second pixel power line VSL transmitting a second pixel voltage ELVSS (also referred to as a "second pixel power supply voltage").

[0089] In an embodiment, the first transistor T1 and the second transistor T2 may be located in corresponding pixel regions (eg, provided in Figure 4 The first transistor T1 and the second transistor T2 may be formed of a semiconductor material (e.g., an oxide semiconductor material) in a pixel area PXA of any pixel PX in the display area DA, and may be an oxide transistor (also referred to as an "oxide semiconductor transistor"). For example, the active layer (also referred to as an "active pattern" or a "semiconductor pattern") of each of the first transistor T1 and the second transistor T2 may be formed of an oxide semiconductor. However, the present invention is not limited thereto. For example, at least one pixel transistor Tpx may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0090] In an embodiment, an oxide semiconductor has high carrier mobility (e.g., high electron mobility in the case of an N-type transistor) and low leakage current, so even if the driving time of the oxide transistor is long, the voltage drop is not large. For example, a pixel PX including an oxide transistor can be driven at a low frequency because even when driven at a low frequency, the change in brightness and / or color of an image due to the voltage drop is not obvious. In the case of a display device 100 in which the pixel transistor Tpx includes an oxide semiconductor, the leakage current of the pixel PX can be reduced or prevented, and power consumption can be reduced.

[0091] In an embodiment, a lower electrode (also referred to as a "back gate electrode", "counter gate electrode" or "bottom electrode") may be disposed below an active layer constituting at least one pixel transistor Tpx. For example, by disposing a lower electrode below an active layer of a pixel transistor Tpx containing an oxide semiconductor, external light may be blocked. The lower electrode may be disposed to face the gate electrode, with the active layer of the corresponding pixel transistor Tpx interposed therebetween.

[0092] In an embodiment, the pixel transistor Tpx may include a corresponding lower electrode. For example, the first transistor T1 may include a first lower electrode BG1, and the second transistor T2 may include a second lower electrode BG2. By providing the pixel transistor Tpx with a lower electrode, fluctuations in the amount of current of the pixel transistor Tpx due to light may be prevented or reduced, and the operating characteristics of the pixel transistor Tpx may be stabilized.

[0093] In an embodiment, the first transistor T1 may include a gate electrode connected to the gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The first transistor T1 may be turned on by a gate signal GW (e.g., a scanning signal of a gate-on voltage) transmitted to the gate line GWL, and may connect the data line DL to the first node N1. Accordingly, a data signal DATA transmitted through the data line DL may be sent to the first node N1.

[0094] In an embodiment, the first transistor T1 may further include a first lower electrode BG1 (or a first back gate electrode). In an embodiment, the first lower electrode BG1 may be connected to one electrode of the first transistor T1, such as a gate electrode. When the first lower electrode BG1 is connected to the gate electrode of the first transistor T1, the operating characteristics of the first transistor T1 may be improved and / or stabilized. For example, by forming the first transistor T1 with a dual-gate structure, the cut-off characteristics and switching speed of the first transistor T1 may be improved, an additional voltage tolerance range may be ensured, leakage current may be reduced, and voltage stability may be improved.

[0095] In an embodiment, the second transistor T2 may include a gate electrode connected to a first node N1 (or a gate node), a first electrode (e.g., a drain electrode or a drain region) connected to a first pixel power line VDL, and a second electrode (e.g., a source electrode or a source region) connected to a second node N2. The second node N2 may be a node connected to the light emitting element ED. The second transistor T2 may control the size (e.g., current amount) of a driving current Id flowing to the light emitting element ED in response to a data signal DATA transmitted according to a switching operation of the first transistor T1.

[0096] In an embodiment, the second transistor T2 may further include a second lower electrode BG2. For example, the second transistor T2 may further include a second lower electrode BG2 (or a second back gate electrode) connected to the second node N2. When the second lower electrode BG2 is connected to the second node N2 like the second electrode of the second transistor T2, the operating characteristics of the second transistor T2 may be improved.

[0097] In an embodiment, the capacitor C1 may be connected between the first node N1 and the second node N2. For example, the capacitor C1 may be connected between the second electrode and the gate electrode of the second transistor T2. The capacitor C1 may be a storage capacitor of the pixel PX and may store a voltage (eg, a data voltage) corresponding to the data signal DATA.

[0098] In an embodiment, the light emitting element ED may be connected between the pixel circuit PC and the second pixel power supply line VSL. The light emitting element ED may include a first electrode (e.g., an anode electrode or a pixel electrode), a second electrode (e.g., a cathode electrode or a counter electrode) facing the first electrode, and a light emitting layer between the first electrode and the second electrode. The first electrode of the light emitting element ED may be connected to the second node N2. The second electrode of the light emitting element ED may be connected to the second pixel power supply line VSL. In an embodiment, the second electrode of the light emitting element ED may be a common electrode shared by a plurality of pixels PX. During a time period in which a driving current Id is supplied from the pixel circuit PC, the light emitting element ED may emit light having a brightness corresponding to the driving current Id.

[0099] Figure 4 FIG. 1 is a cross-sectional view for explaining a display panel 110 according to an embodiment. Figure 5 FIG. 1 is a cross-sectional view for explaining a display panel 110 according to an embodiment. Figure 4 A portion of the display area DA of the display panel 110 including the connection electrode CNE and the second passivation layer PSV2 is illustrated, and Figure 5 A portion of the display area DA of the display panel 110 excluding the connection electrode CNE and the second passivation layer PSV2 is illustrated.

[0100] In an embodiment, Figure 4 and Figure 5 The first transistor T1 and the second transistor T2 disposed in one pixel area PXA are explained as examples of circuit elements that may be provided or disposed in the panel circuit layer PCL of the display panel 110. In addition, Figure 4 and Figure 5A light-emitting display panel including a light-emitting element ED (e.g., an organic light-emitting diode) is shown as an example of a display panel 110 to which the embodiments can be applied. However, the type and / or structure of the display panel 110 is not limited thereto. For example, the display panel 110 may include a light-emitting element of another type and / or structure, or may be a display panel of another type and / or structure other than a light-emitting display panel.

[0101] In an embodiment, and except Figure 1 to Figure 3 In addition, reference Figure 4 and Figure 5 , the display panel 110 may include a substrate SUB (also referred to as a "substrate member" or a "substrate layer"), a panel circuit layer PCL, a light emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be arranged or provided to overlap each other on the substrate SUB. For example, with respect to the display area DA, the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be sequentially arranged or formed on the substrate SUB along a third direction D3. However, the present invention is not limited thereto, and the mutual positions of the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be changed. For example, the panel circuit layer PCL and the light emitting element layer LEL may be integrated with each other, or the light emitting element layer LEL may be provided on top of the panel circuit layer PCL.

[0102] In an embodiment, the display panel 110 may further include additional elements provided above and / or below the encapsulation layer ENL. For example, the display panel 110 may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a passivation layer (e.g., a passivation film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and the passivation layer may be provided above the encapsulation layer ENL or may be provided between the light emitting element layer LEL and the encapsulation layer ENL. In an embodiment, the sensor layer, the optical layer, and / or the passivation layer may be provided on the display panel 110. For example, the sensor layer, the optical layer, and / or the passivation layer may be manufactured integrally with the display panel 110. In another embodiment, the sensor layer, the optical layer, and / or the passivation layer may be manufactured separately from the display panel 110 and attached to the display panel 110 via an adhesive layer or the like.

[0103] In an embodiment, the substrate SUB as a base member for forming the display panel 110 may be a substrate (or film) having a rigid property or a flexible property. In one embodiment, the substrate SUB may be a substrate including an insulating material (such as glass, etc.) and having a rigid property, and may not be bent. In another embodiment, the substrate SUB may be a flexible substrate including polyimide or other insulating materials, and may be deformed to be bent, folded, or rolled up, and may be bent or may not be bent. The type and / or material of the substrate SUB may vary according to the embodiment.

[0104] In an embodiment, the substrate SUB may include at least a display area DA. In an embodiment, the display area DA may include a pixel area PXA corresponding to each pixel PX. For example, in the display area DA, a corresponding pixel area PXA in which each pixel PX is arranged may be defined.

[0105] In an embodiment, the isolation layer BRL may be provided on the substrate SUB. For example, the display panel 110 may further include an isolation layer BRL disposed between the substrate SUB and the panel circuit layer PCL. In another embodiment, the display panel 110 may not include the isolation layer BRL, and in this case, the panel circuit layer PCL may be directly disposed on the substrate SUB.

[0106] In an embodiment, the isolation layer BRL may include at least one inorganic insulating layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). The isolation layer BRL may protect the pixel PX from moisture penetration through the substrate SUB susceptible to moisture penetration. The material of the isolation layer BRL may be variously changed according to the embodiment.

[0107] In an embodiment, the panel circuit layer PCL may be disposed on one surface of the substrate SUB provided with the isolation layer BRL. The panel circuit layer PCL may include circuit elements including a pixel transistor Tpx and a pixel capacitor (e.g., a capacitor C1 for each pixel PX) and wiring (e.g., a signal line and a power line). In an embodiment, the panel circuit layer PCL may further include an additional conductive pattern (e.g., a bridge pattern).

[0108] In an embodiment, the panel circuit layer PCL may further include an insulating layer disposed on the substrate SUB. For example, the panel circuit layer PCL may include a buffer layer BFL (also referred to as a "first insulating layer"), an interlayer insulating layer ILD (also referred to as a "second insulating layer"), and a first passivation layer PSV1 (also referred to as a "third insulating layer") sequentially disposed on the substrate SUB along a third direction D3.

[0109] In an embodiment, the panel circuit layer PCL may further include a connection electrode CNE and a second passivation layer PSV2 (also referred to as a “fourth insulating layer”) disposed on the first passivation layer PSV1. Figure 4 In another embodiment, the panel circuit layer PCL may not include the connection electrode CNE and the second passivation layer PSV2, such as Figure 5 As shown in Figure 5 In the embodiment of the present invention, one electrode of the second transistor T2 may be directly connected to one electrode of the light emitting element ED.

[0110] In an embodiment, at least one of the first passivation layer PSV1 and the second passivation layer PSV2 may have a multilayer structure including an inorganic layer (e.g., an inorganic insulating layer) and an organic layer (e.g., an organic insulating layer). For example, the first passivation layer PSV1 may include a first inorganic layer IOL1 and a first organic layer ORL1 sequentially disposed on the interlayer insulating layer ILD, and the second passivation layer PSV2 may include a second inorganic layer IOL2 and a second organic layer ORL2 sequentially disposed on the first passivation layer PSV1.

[0111] In an embodiment, at least one of the first passivation layer PSV1 and the second passivation layer PSV2 may include at least one layer including silicon nitride (eg, SiN x ) of the inorganic insulating layer. For example, at least one of the first inorganic layer IOL1 and the second inorganic layer IOL2 may include silicon nitride. Accordingly, the circuit elements and wirings provided in the panel circuit layer PCL may be protected from moisture penetration and the like.

[0112] In an embodiment, if Figure 4 As shown in FIG. 1 , when the panel circuit layer PCL includes the first passivation layer PSV1 and the second passivation layer PSV2, the first inorganic layer IOL1 may not include silicon nitride, and the second inorganic layer IOL2 may include silicon nitride. For example, the first inorganic layer IOL1 may include silicon oxide (e.g., SiO x ), and the second inorganic layer IOL2 may include silicon nitride. Accordingly, the amount of hydrogen introduced into the active layer, etc. may be reduced. In an embodiment, as Figure 5 As shown in , when the panel circuit layer PCL includes the first passivation layer PSV1 but not the second passivation layer PSV2, the first inorganic layer IOL1 may include silicon nitride. Accordingly, circuit elements and wirings provided in the panel circuit layer PCL may be protected from moisture penetration and the like.

[0113] In an embodiment, the panel circuit layer PCL may further include a gate insulating layer GI between the active layer and the gate electrode of each of the pixel transistors Tpx. For example, the panel circuit layer PCL may further include a first gate insulating layer GI1 (also referred to as a "first gate insulating pattern") between the first active layer ACT1 and the first gate electrode GE1 of the first transistor T1, and a second gate insulating layer GI2 (also referred to as a "second gate insulating pattern") between the second active layer ACT2 and the second gate electrode GE2 of the second transistor T2.

[0114] In an embodiment, Figure 4 and Figure 5 It is explained that the display panel 110 has a structure in which the first gate insulating layer GI1 and the second gate insulating layer GI2 are respectively etched into an island-shaped insulating pattern only partially located on a portion of the first active layer ACT1 and the second active layer ACT2. For example, the first gate insulating layer GI1 may be provided only on a portion of the first active layer ACT1 including the first channel region CH1, and may be an insulating pattern in the form of exposing the first drain region DR1 and the first source region SR1. As an example, the first gate insulating layer GI1 may have a shape and size corresponding to the shape and size of the first gate electrode GE1. Similarly, the second gate insulating layer GI2 may be provided only on a portion of the second active layer ACT2 including the second channel region CH2, and may be an insulating pattern in the form of exposing the second drain region DR2 and the second source region SR2. As an example, the second gate insulating layer GI2 may have a shape and size corresponding to the shape and size of the second gate electrode GE2.

[0115] In an embodiment, the shapes of the first gate insulating layer GI1 and the second gate insulating layer GI2 are not limited to Figure 4 and Figure 5 For example, at least one of the first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed entirely in the display area DA. In addition, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed as shown in FIG. Figure 4 and Figure 5 The gate insulating layers GI and GI may be separated from each other as shown in FIG.

[0116] In an embodiment, each of the buffer layer BFL, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the first inorganic layer IOL1 and the second inorganic layer IOL2 may include at least one inorganic insulating layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials).

[0117] In an embodiment, each of the first organic layer ORL1 and the second organic layer ORL2 may include at least one organic insulating layer containing an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating material). The surfaces (e.g., top surfaces) of the first organic layer ORL1 and the second organic layer ORL2 may be substantially flat. The type, material, shape, and / or structure of the insulating layer and / or insulating pattern provided in the panel circuit layer PCL may be variously changed according to the embodiment.

[0118] In an embodiment, the pixel transistor Tpx may be included in the pixel circuit PC of each pixel PX and may be located in the display area DA. For example, the first transistor T1 and the second transistor T2 provided to each pixel PX may be provided in each of the pixel areas PXA in which the corresponding pixel PX is located. In addition, at least one capacitor (e.g., Figure 3 The capacitor C1) may be further provided in each of the pixel areas PXA.

[0119] In an embodiment, at least one pixel transistor Tpx may include a lower electrode. For example, the first transistor T1 may include a first lower electrode BG1, and the second transistor T2 may include a second lower electrode BG2. In an embodiment, the first lower electrode BG1 and the second lower electrode BG2 may be provided in the same layer (e.g., the first conductive layer CDL1) within the panel circuit layer PCL.

[0120] In an embodiment, the first transistor T1 may include a first active layer ACT1 (also referred to as a "first active pattern") disposed on a substrate SUB and a first gate electrode GE1 disposed on the first active layer ACT1. The first gate electrode GE1 may be disposed on a portion of the first active layer ACT1, and a first gate insulating layer GI1 may be disposed between the first gate electrode GE1 and the first active layer ACT1. In an embodiment, the first gate electrode GE1 may be directly disposed on the first gate insulating layer GI1. For example, only the first gate insulating layer GI1 may be interposed between the first gate electrode GE1 and the first active layer ACT1.

[0121] In an embodiment, the first transistor T1 may further include a first lower electrode BG1 overlapping the first active layer ACT1. For example, the first transistor T1 may include the first lower electrode BG1 disposed below the first active layer ACT1. In another embodiment, the first transistor T1 may not include the first lower electrode BG1.

[0122] In an embodiment, the first transistor T1 may further include a first drain electrode DE1 and a first source electrode SE1 connected to different portions of the first active layer ACT1. In another embodiment, the first transistor T1 may not include a separate drain electrode and / or a separate source electrode, and the first drain region DR1 and / or the first source region SR1 of the first active layer ACT1 may be connected to another circuit element, wiring, and / or conductive pattern to function as a drain electrode and / or source electrode of the first transistor T1.

[0123] In an embodiment, the first lower electrode BG1 may be provided on the substrate SUB, in the first conductive layer CDL1. In an embodiment, the first conductive layer CDL1 may be disposed between the substrate SUB and the buffer layer BFL. For example, the first conductive layer CDL1 may be disposed on the isolation layer BRL and covered by the buffer layer BFL.

[0124] The first lower electrode BG1 may overlap the first active layer ACT1. For example, the first lower electrode BG1 may be disposed below the first active layer ACT1 to overlap at least the first channel region CH1. The buffer layer BFL may be disposed between the first lower electrode BG1 and the first active layer ACT1. The first lower electrode BG1 and the first active layer ACT1 may be spaced apart from each other by a distance corresponding to the thickness of the buffer layer BFL. The first lower electrode BG1 may face the first gate electrode GE1 with the first active layer ACT1 interposed therebetween.

[0125] In an embodiment, the first lower electrode BG1 may or may not be connected to one electrode of the first transistor T1. In an embodiment, the first lower electrode BG1 may be connected to the first gate electrode GE1 of the first transistor T1 and may function as a back gate electrode to adjust characteristics of the first transistor T1.

[0126] In an embodiment, the first active layer ACT1 may be provided on the substrate SUB, in the semiconductor layer SCL. In an embodiment, the semiconductor layer SCL may be disposed on the buffer layer BFL, and may be covered by the gate insulating layer GI and the interlayer insulating layer ILD.

[0127] In an embodiment, the first active layer ACT1 may include a first channel region CH1 overlapping the first gate electrode GE1, and a first source region SR1 and a first drain region DR1 spaced apart from each other by the first channel region CH1 interposed therebetween. For example, the first source region SR1 and the first drain region DR1 may be located at both sides of the first channel region CH1. The first channel region CH1 may be a region that maintains semiconductor characteristics without becoming conductive, and the first source region SR1 and the first drain region DR1 may be regions that have become conductive.

[0128] In an embodiment, the first active layer ACT1 may overlap the first lower electrode BG1 and the first gate electrode GE1. For example, the first channel region CH1 of the first active layer ACT1 may be disposed between the first lower electrode BG1 and the first gate electrode GE1 and may overlap the first lower electrode BG1 and the first gate electrode GE1.

[0129] In an embodiment, the first gate electrode GE1 (e.g., the top gate electrode of the first transistor T1) may be provided on the substrate SUB in the second conductive layer CDL2. In an embodiment, the second conductive layer CDL2 may be disposed on the semiconductor layer SCL including the first active layer ACT1 and the gate insulating layer GI including the first gate insulating layer GI1. The second conductive layer CDL2 may be covered by the interlayer insulating layer ILD.

[0130] In an embodiment, the first gate electrode GE1 may be disposed on the first active layer ACT1 to overlap the first channel region CH1. The first gate electrode GE1 and the first active layer ACT1 may be spaced apart from each other with the first gate insulating layer GI1 interposed therebetween.

[0131] In an embodiment, the first gate insulating layer GI1 may be disposed between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer GI1 may cover a portion of the first active layer ACT1 overlapping the first gate electrode GE1 (eg, the first channel region CH1).

[0132] In an embodiment, the first drain electrode DE1 and the first source electrode SE1 may be provided on the substrate SUB, in the third conductive layer CDL3. In an embodiment, the third conductive layer CDL3 may be disposed on the interlayer insulating layer ILD covering the second conductive layer CDL2 including the first gate electrode GE1.

[0133] In an embodiment, the first drain electrode DE1 may be connected to a portion of the first active layer ACT1. For example, the first drain electrode DE1 may be connected to the first drain region DR1 through at least one contact hole passing through the interlayer insulating layer ILD.

[0134] In an embodiment, the first source electrode SE1 may be connected to another portion of the first active layer ACT1. For example, the first source electrode SE1 may be connected to the first source region SR1 through at least one contact hole passing through the interlayer insulating layer ILD.

[0135] In an embodiment, the second transistor T2 may include a second active layer ACT2 (also referred to as a "second active pattern") disposed on the substrate SUB and a second gate electrode GE2 disposed on the second active layer ACT2. The second gate electrode GE2 may be disposed on a portion of the second active layer ACT2, and the second gate insulating layer GI2 may be disposed between the second gate electrode GE2 and the second active layer ACT2. In an embodiment, the second gate electrode GE2 may be directly disposed on the second gate insulating layer GI2. For example, only the second gate insulating layer GI2 may be interposed between the second gate electrode GE2 and the second active layer ACT2.

[0136] In an embodiment, the second transistor T2 may further include a second lower electrode BG2 overlapping the second active layer ACT2. For example, the second transistor T2 may include a second lower electrode BG2 disposed below the second active layer ACT2. In another embodiment, the second transistor T2 may not include the second lower electrode BG2.

[0137] In an embodiment, the second transistor T2 may further include a second drain electrode DE2 and a second source electrode SE2 connected to different portions of the second active layer ACT2. In another embodiment, the second transistor T2 may not include a separate drain electrode and / or a separate source electrode, and the second drain region DR2 and / or the second source region SR2 of the second active layer ACT2 may be connected to another circuit element, wiring, and / or conductive pattern to serve as a drain electrode and / or source electrode of the second transistor T2.

[0138] In an implementation, the second lower electrode BG2 may be provided on the substrate SUB in the first conductive layer CDL1. For example, the second lower electrode BG2 may be provided in the first conductive layer CDL1 together with the first lower electrode BG1.

[0139] In an embodiment, the second lower electrode BG2 may overlap the second active layer ACT2. For example, the second lower electrode BG2 may be disposed below the second active layer ACT2 to overlap at least the second channel region CH2. The buffer layer BFL may be interposed between the second lower electrode BG2 and the second active layer ACT2. The second lower electrode BG2 and the second active layer ACT2 may be spaced apart from each other by a distance corresponding to the thickness of the buffer layer BFL. The second lower electrode BG2 may face the second gate electrode GE2 with the second active layer ACT2 interposed therebetween.

[0140] In an embodiment, the second lower electrode BG2 may or may not be connected to one electrode of the second transistor T2. In an embodiment, the second lower electrode BG2 may be connected to the second source electrode SE2 of the second transistor T2 and may function as a back gate electrode to adjust characteristics of the second transistor T2.

[0141] In an embodiment, the second active layer ACT2 may be provided on the substrate SUB in the semiconductor layer SCL. In an embodiment, the first active layer ACT1 and the second active layer ACT2 may be provided and / or disposed in the same layer (eg, the same semiconductor layer SCL) on the substrate SUB and may include the same oxide semiconductor.

[0142] In an embodiment, the second active layer ACT2 may include a second channel region CH2 overlapping the second gate electrode GE2, and a second source region SR2 and a second drain region DR2 spaced apart from each other by the second channel region CH2 interposed therebetween. For example, the second source region SR2 and the second drain region DR2 may be located at both sides of the second channel region CH2. The second channel region CH2 may be a region that maintains semiconductor characteristics without becoming conductive, and the second source region SR2 and the second drain region DR2 may be regions that have become conductive.

[0143] In an embodiment, the second active layer ACT2 may overlap the second lower electrode BG2 and the second gate electrode GE2. For example, the second channel region CH2 of the second active layer ACT2 may overlap the second lower electrode BG2 and the second gate electrode GE2.

[0144] In an embodiment, the second gate electrode GE2 (e.g., the top gate electrode of the second transistor T2) may be provided on the substrate SUB, in the second conductive layer CDL2. In an embodiment, the first gate electrode GE1 and the second gate electrode GE2 may be provided and / or disposed in the same layer (e.g., the same second conductive layer CDL2) on the substrate SUB. For example, the second gate electrode GE2 may be disposed between the gate insulating layer GI including the first gate insulating layer GI1 and the second gate insulating layer GI2 and the interlayer insulating layer ILD.

[0145] In an embodiment, the second gate electrode GE2 may be disposed on the second active layer ACT2 to overlap the second channel region CH2. The second gate electrode GE2 and the second active layer ACT2 may be spaced apart from each other with the second gate insulating layer GI2 interposed therebetween.

[0146] In an embodiment, the second gate insulating layer GI2 may be disposed between the second gate electrode GE2 and the second active layer ACT2. The second gate insulating layer GI2 may cover a portion of the second active layer ACT2 overlapping with the second gate electrode GE2 (e.g., the second channel region CH2). In an embodiment, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be provided and / or disposed in the same layer (e.g., the gate insulating layer GI between the semiconductor layer SCL and the second conductive layer CDL2) on the substrate SUB and may include the same insulating material.

[0147] In an embodiment, the second drain electrode DE2 and the second source electrode SE2 may be provided on the substrate SUB in the third conductive layer CDL3. In an embodiment, the second drain electrode DE2 and the second source electrode SE2 may be disposed on the substrate SUB in the same layer of the first drain electrode DE1 and the first source electrode SE1. For example, the second drain electrode DE2 and the second source electrode SE2 may be disposed on the interlayer insulating layer ILD covering the second conductive layer CDL2 including the first gate electrode GE1 and the second gate electrode GE2, and may be covered by the first passivation layer PSV1.

[0148] In an embodiment, the second drain electrode DE2 may be connected to a portion of the second active layer ACT2. For example, the second drain electrode DE2 may be connected to the second drain region DR2 through at least one contact hole passing through the interlayer insulating layer ILD.

[0149] In an embodiment, the second source electrode SE2 may be connected to another portion of the second active layer ACT2. For example, the second source electrode SE2 may be connected to the second source region SR2 through at least one contact hole passing through the interlayer insulating layer ILD. In an embodiment, the second source electrode SE2 may be further connected to the second lower electrode BG2. For example, the second source electrode SE2 may be connected to the second lower electrode BG2 through at least one contact hole passing through the interlayer insulating layer ILD and the buffer layer BFL.

[0150] In an embodiment, the pixel transistor Tpx including the first transistor T1 and the second transistor T2 may be covered by at least one passivation layer. For example, the pixel transistor Tpx may be covered by the first passivation layer PSV1 and the second passivation layer PSV2 (eg, Figure 4 ) or may be covered by the first passivation layer PSV1 (as shown in Figure 5 ).

[0151] exist Figure 4 In an embodiment, the second transistor T2 of each pixel PX may be connected to the light emitting element ED of the corresponding pixel PX through the connecting electrode CNE. The connecting electrode CNE may be provided on the substrate SUB and in the fourth conductive layer CDL4. In an embodiment, the fourth conductive layer CDL4 may be provided on the first passivation layer PSV1 and may be covered by the second passivation layer PSV2. For example, the fourth conductive layer CDL4 may be provided between the first passivation layer PSV1 and the second passivation layer PSV2. When the display panel 110 further includes the fourth conductive layer CDL4, the number of conductive layers provided in the display panel 110 increases. Accordingly, sufficient design space for forming various conductive patterns (e.g., electrodes and / or bridge patterns) or wirings, etc. in the display panel 110 may be ensured. Accordingly, even when the display panel 110 is formed with a high resolution, the pixel circuit PC and wirings may be easily and / or appropriately formed.

[0152] In an embodiment, the connection electrode CNE may be connected to one electrode of the second transistor T2. As an example, the connection electrode CNE may be disposed on the second source electrode SE2 and may be connected to the second source electrode SE2 through at least one contact hole or via penetrating the first passivation layer PSV1.

[0153] exist Figure 5 In an embodiment, the second transistor T2 of each pixel PX may be connected to the light emitting element ED of the corresponding pixel PX without passing through the connection electrode CNE. For example, the second source electrode SE2 of each pixel PX may be directly connected to the light emitting element ED of the corresponding pixel PX.

[0154] In an embodiment, the corresponding electrodes, conductive patterns and / or wirings provided in the conductive layer of the panel circuit layer PCL may include at least one conductive material, and each may have a single-layer structure or a multi-layer structure. For example, the electrodes, conductive patterns and / or wirings provided in each of the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3 and the fourth conductive layer CDL4 may include copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg) and at least one of other metals, alloys thereof or other conductive materials, and each may have a single-layer structure or a multi-layer structure. In an embodiment, the electrodes, conductive patterns and / or wirings provided in the same conductive layer may be simultaneously formed using the same conductive material.

[0155] In an embodiment, at least one active layer provided in the semiconductor layer SCL may include an oxide semiconductor including indium (In). For example, each of the first active layer ACT1 and the second active layer ACT2 may include an oxide semiconductor including indium (In) in a content range of about 40 at % (atomic percentage) to about 54 at %.

[0156] In an embodiment, by controlling the atomic ratio of indium (In) contained in the active layer within the range exemplified above, the carrier concentration and / or conductivity of the active layer can be appropriately controlled, and the element characteristics (e.g., mobility and threshold voltage) of the transistor can be appropriately controlled and / or ensured. For example, by limiting the atomic ratio of indium (In) contained in each of the first active layer ACT1 and the second active layer ACT2 to a range of about 40 at% to about 54 at%, the characteristics of the first transistor T1 and the second transistor T2 can be controlled so that each of the first transistor T1 and the second transistor T2 has a mobility suitable for driving the pixel PX (e.g., at about 20 cm 2 / Vs~about 50cm 2 / Vs) and a threshold voltage (for example, a threshold voltage in a range of about -1.0 V to about +0.5 V). The mobility and the threshold voltage of the first transistor T1 and the second transistor T2 are not limited to the above-exemplified ranges and may be changed according to the design conditions or driving conditions of the display panel 110.

[0157] In an embodiment, at least one active layer provided in the semiconductor layer SCL may further contain at least one of gallium (Ga), zinc (Zn), and tin (Sn). For example, each of the first active layer ACT1 and the second active layer ACT2 may contain indium (In) having a content ranging from about 40 at% to about 54 at%, and may include an oxide semiconductor further containing at least one of gallium (Ga), zinc (Zn), and tin (Sn). As an example, each of the first active layer ACT1 and the second active layer ACT2 may be made of a high-mobility oxide semiconductor (e.g., having a molecular weight of about 20 cm) including indium gallium zinc oxide (IGZO), indium tin gallium oxide (ITGO), or indium tin gallium zinc oxide (ITGZO). 2 / Vs or greater or about 30cm 2 / Vs or greater mobility) of an oxide semiconductor material. However, the materials of the first active layer ACT1 and the second active layer ACT2 are not limited to the materials exemplified above. For example, each of the first active layer ACT1 and the second active layer ACT2 may be made of indium gallium oxide (IGO), indium zinc oxide (IZO) or other oxide semiconductors.

[0158] In an embodiment, when the first active layer ACT1 and the second active layer ACT2 are formed of a high-mobility oxide semiconductor, the mobility of the first transistor T1 and the second transistor T2 can be appropriately ensured, while forming the first transistor T1 and the second transistor T2 in a microscopic size (for example, a size of an active layer including a width and / or a length in a range of approximately several micrometers to several tens of micrometers). Accordingly, even in a high-resolution display device in which the area of ​​the pixel region PXA is relatively small, the pixel transistor Tpx can be easily disposed and / or formed, and the element characteristics and / or operation characteristics of the pixel transistor Tpx can be appropriately ensured. In addition, by forming the first active layer ACT1 and the second active layer ACT2 with a high-mobility oxide semiconductor, the power consumption of the display device 100 can be reduced.

[0159] In an embodiment, at least one gate insulating layer GI may have a thickness of about 1.04E+20 Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 The emission range of nitric oxide (NO) is about 1.04×10 20Molec. / cm 3 or larger and about 1.15×10 20 Molec. / cm 3 or less) and / or about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 Oxygen (O 2 ) emissions range (e.g., oxygen (O 2 ) ranges from about 2.48×10 19 Molec. / cm 3 or larger and about 2.76×10 19 Molec. / cm 3 or less). For example, in an analysis performed by thermal desorption spectroscopy (TDS) (or high temperature evolved gas spectroscopy using thermal treatment) using thermal treatment (e.g., thermal treatment performed at a temperature range of about 50° C. to about 550° C.), at least one gate insulating layer GI may be a layer in which an emission amount of nitric oxide (NO) in the case of conversion to nitric oxide (NO) is in the range of about 1.04E+20 Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 and or converted to oxygen (O 2 ) in the case of oxygen (O 2 ) has an emission range of about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 insulating layer (or insulating pattern).

[0160] In an embodiment, each of the first gate insulating layer GI1 and the second gate insulating layer GI2 may have a thickness of about 1.04E+20 Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 Nitric oxide (NO) emissions range and / or about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 Oxygen (O 2 ) of the gate insulating layer (or insulating pattern). For example, each of the first gate insulating layer GI1 and the second gate insulating layer GI2 may include silicon oxide (eg, SiO x ), and may be a process for emitting nitrogen monoxide (NO) and / or oxygen (O) at a concentration within the above-exemplified range by a heat treatment process or the like. 2As an example, in a heat treatment process after depositing the gate insulating layer GI including the first gate insulating layer GI1 and the second gate insulating layer GI2 (for example, a heat treatment process of the gate insulating layer GI and / or the interlayer insulating layer ILD performed at a temperature range of about 50° C. to about 550° C.), the first gate insulating layer GI1 and the second gate insulating layer GI2 may emit about 1.04E+20Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 Nitric oxide (NO) and / or nitric oxide (NO) can be emitted within a concentration range of about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 Oxygen concentration range 2 According to the nitric oxide (NO) and / or oxygen (O 2 ) concentration, the element characteristics (for example, carrier concentration) of the first active layer ACT1 and the second active layer ACT2 can be changed. Accordingly, by appropriately controlling the nitric oxide (NO) and / or oxygen (O 2 ) concentration, the electrical characteristics of the first transistor T1 and the second transistor T2 can be stabilized.

[0161] In addition, in an embodiment, in addition to the content of indium (In) contained in each active layer, nitric oxide (NO) and / or oxygen (O) emitted from each gate insulating layer GI may be controlled. 2 ) is controlled. Accordingly, the electrical characteristics of the first transistor T1 and the second transistor T2 can be optimized and / or stabilized. For example, although the first active layer ACT1 and the second active layer ACT2 are formed using a high-mobility oxide semiconductor, oxygen may be supplied to the first active layer ACT1 and the second active layer ACT2 in a subsequent process including a heat treatment. Accordingly, the carrier concentration of the first active layer ACT1 and the second active layer ACT2 can be appropriately and / or easily controlled without forming a separate oxygen supply layer or the like on the first active layer ACT1 and the second active layer ACT2 including the high-mobility oxide semiconductor (for example, on the gate insulating layer GI).

[0162] In an embodiment, in addition to the content of indium (In) contained in each active layer, nitric oxide (NO) and / or oxygen (O) discharged from the gate insulating layer GI may also be contained. 2) is controlled within the exemplified range so that the first active layer ACT1 and the second active layer ACT2 can be formed so that the first transistor T1 and the second transistor T2 have element characteristics (or operation characteristics) suitable for the switching transistor and the driving transistor of the pixel PX. In an embodiment, the content of indium (In) in the active layer exemplified above and the gas emission amount (e.g., nitric oxide (NO) and / or oxygen (O 2 ) may be a value suitable for (or optimized for) forming the pixel transistor Tpx so as to satisfy all element characteristics required for the switching transistor (e.g., the first transistor T1) and the driving transistor (e.g., the second transistor T2) of the pixel PX (e.g., the threshold voltage and mobility in the appropriate range required for the switching transistor in particular). In addition, the indium (In) content of the active layer and the gas emission amount of the gate insulating layer GI exemplified above may also be a value suitable for forming a driver transistor so as to satisfy the driver transistor (e.g., Figure 6 The element characteristics (or operating characteristics) required by the third transistor T3 in FIG.

[0163] According to an embodiment, the element characteristics of each transistor can be appropriately controlled without forming a separate oxygen supply layer in and / or around the transistor, etc. Accordingly, the structure and manufacturing process of the display panel 110 can be simplified and / or streamlined, and the manufacturing efficiency of the display panel 110 can be increased.

[0164] In an embodiment, the light emitting element layer LEL may be disposed on the panel circuit layer PCL and may be located in the display area DA. For example, the light emitting element layer LEL may be disposed on the panel circuit layer PCL and in the display area DA.

[0165] In an embodiment, the light emitting element layer LEL may include a light emitting element ED of the pixel PX. For example, the light emitting element layer LEL may include a pixel defining layer PDL (also referred to as a "bank") that separates emission regions of the pixel PX and a light emitting element ED located in each emission region. In an embodiment, the light emitting element layer LEL may further include a spacer SPC disposed on a portion of the pixel defining layer PDL.

[0166] In an embodiment, each light emitting element ED may include a first electrode ET1 (e.g., an anode electrode) connected to at least one pixel transistor Tpx (e.g., a second pixel transistor T2) included in a corresponding pixel PX, and a light emitting layer EML and a second electrode ET2 (e.g., a cathode electrode) sequentially disposed on the first electrode ET1. In an embodiment, the light emitting element ED may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) between the light emitting layer EML and the second electrode ET2.

[0167] In an embodiment, the first electrode ET1 of the light emitting element ED may be disposed on the panel circuit layer PCL. Figure 4 In an embodiment, the first electrode ET1 may be disposed on the second passivation layer PSV2 to correspond to each emission region, and may be connected to the connection electrode CNE through at least one contact hole or through-hole passing through the second passivation layer PSV2. Figure 5 In an embodiment of the present invention, the first electrode ET1 may be disposed on the first passivation layer PSV1 to correspond to each emission region, and may be directly connected to at least one pixel transistor Tpx.

[0168] In an embodiment, the first electrode ET1 may include a conductive material. In an embodiment, the first electrode ET1 may include a metal material having high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) or a multilayer structure of a compound thereof (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag and ITO / Ag / ITO).

[0169] In an embodiment, the light emitting layer EML of the light emitting element ED may include a polymer material or a low molecular material. The light emitted from the light emitting layer EML may contribute to image display. In an embodiment, a light emitting layer EML may be provided for each pixel PX, and the light emitting layer EML of each pixel PX may emit visible light of a color corresponding to the corresponding pixel PX. In another embodiment, the light emitting layer EML may be a common layer shared by pixels PX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light desired to be emitted from each pixel PX may be arranged in the emission region of at least some pixels PX.

[0170] In an embodiment, the second electrode ET2 of the light emitting element ED may include a conductive material. In an embodiment, the second electrode ET2 may be a common layer formed across the entire display area DA to cover the light emitting layer EML and the pixel defining layer PDL. In an embodiment, the second electrode ET2 may be formed of a transparent conductive material (TCO) capable of transmitting light such as ITO, IZO, ZnO, or ITZO, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0171] In an embodiment, the pixel defining layer PDL may have an opening corresponding to each emission region and may surround the emission region. For example, the pixel defining layer PDL may be formed to cover the edge of the first electrode ET1 of the light emitting element ED and may include an opening exposing the remaining portion of the first electrode ET1. The area where the exposed first electrode ET1 overlaps with the light emitting layer EML (or an area including the overlapping area) may be defined as the emission region of each pixel PX.

[0172] In an embodiment, the pixel defining layer PDL may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer PDL may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) resin, or other organic insulating materials.

[0173] In an embodiment, the spacer SPC may be disposed on a portion of the pixel defining layer PDL. The spacer SPC may include at least one organic insulating layer containing an organic insulating material. The spacer SPC may include the same material as that of the pixel defining layer PDL or may include a material different from that of the pixel defining layer PDL. In an embodiment, the pixel defining layer PDL and the spacer SPC may be formed sequentially by separate mask processes. In another embodiment, the pixel defining layer PDL and the spacer SPC may be formed simultaneously using a halftone mask. In this case, the pixel defining layer PDL and the spacer SPC may be regarded as a single insulating layer that is integral with each other.

[0174] In an embodiment, the encapsulation layer ENL may be disposed on the light emitting element layer LEL. The encapsulation layer ENL may cover the light emitting element layer LEL in the display area DA, and may extend to the non-display area NDA to contact the panel circuit layer PCL. For example, the encapsulation layer ENL may be disposed in the display area DA to cover the light emitting element layer LEL, and an end of the encapsulation layer ENL may be located in a portion of the non-display area NDA adjacent to the display area DA. The encapsulation layer ENL may block oxygen or moisture from penetrating into the light emitting element layer LEL, and may reduce electrical and / or physical impacts on the panel circuit layer PCL and the light emitting element layer LEL.

[0175] In an embodiment, the encapsulation layer ENL may have a multilayer structure including a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially disposed on the light emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer containing an inorganic material. The second encapsulation layer ENL2 may be an organic encapsulation layer containing an organic material. The structure and / or material of the encapsulation layer ENL may vary according to the embodiment.

[0176] Figure 6 1 is a cross-sectional view for explaining a display panel 110 according to an embodiment. For example, Figure 6 A portion of the display area DA and a portion of the non-display area NDA of the display panel 110 are illustrated. Figure 6 Explains the basis Figure 4 The first transistor T1 and the second transistor T2 of the embodiment are used as examples of circuit elements that may be provided or disposed in the display area DA of the panel circuit layer PCL, and a driver transistor Tdr provided or disposed in the drive circuit area DRA is explained as an example of another circuit element that may be provided to the panel circuit layer PCL.

[0177] In an embodiment, and except Figure 1 to Figure 5 In addition, reference Figure 6 , the display panel 110 may further include a driver transistor Tdr provided in the driving circuit area DRA. For example, the display panel 110 may be provided with a driving circuit area DRA corresponding to a portion of the non-display area NDA, and may further include a plurality of driver transistors Tdr provided in a stage circuit constituting the first driver 120. Figure 6 , only one driver transistor Tdr is illustrated to represent the driver transistor Tdr, and this is referred to as a “third transistor T3”.

[0178] In an embodiment, the substrate SUB and the display panel 110 including the substrate SUB may include a display area DA and a non-display area NDA. In an embodiment, the non-display area NDA may include a driving circuit area DRA. For example, the driving circuit area DRA in which the first driver 120 is disposed may be defined in the non-display area NDA.

[0179] In an embodiment, the panel circuit layer PCL may further include a driver transistor Tdr including a third transistor T3 in addition to the pixel transistor Tpx. The driver transistor Tdr may be provided in a stage region located in the driving circuit region DRA (eg, a corresponding stage region in which a stage circuit constituting a shift register of the first driver 120 is provided).

[0180] In an embodiment, at least one driver transistor Tdr may not include a lower electrode. For example, the driver transistor Tdr including the third transistor T3 may not include a lower electrode. However, the present invention is not limited thereto. For example, the lower electrode provided to the first conductive layer CDL1 may be disposed below the active layer (e.g., the third active layer ACT3) of the at least one driver transistor Tdr. In an embodiment, the lower electrode provided to the at least one driver transistor Tdr may be connected to one electrode (e.g., a gate electrode) of the corresponding driver transistor Tdr.

[0181] In an embodiment, the third transistor T3 may include a third active layer ACT3 (also referred to as a "third active pattern") disposed on the substrate SUB and a third gate electrode GE3 disposed on the third active layer ACT3. The third gate electrode GE3 may be disposed on a portion of the third active layer ACT3, and a third gate insulating layer GI3 may be disposed between the third gate electrode GE3 and the third active layer ACT3.

[0182] In an embodiment, the third transistor T3 may further include a third drain electrode DE3 and a third source electrode SE3 connected to different portions of the third active layer ACT3. In another embodiment, the third transistor T3 may not include a separate drain electrode and / or a separate source electrode, and the third drain region DR3 and / or the third source region SR3 of the third active layer ACT3 may be connected to other circuit elements, wirings, and / or conductive patterns to serve as a drain electrode and / or source electrode of the third transistor T3.

[0183] In an embodiment, the third active layer ACT3 may be provided on the substrate SUB, in the semiconductor layer SCL. In an embodiment, the first active layer ACT1, the second active layer ACT2 and the third active layer ACT3 may be provided and / or disposed in the same layer (eg, the same semiconductor layer SCL) on the substrate SUB.

[0184] In an embodiment, the third active layer ACT3 may include an oxide semiconductor that is the same as that of the first active layer ACT1 and / or the second active layer ACT2, and may be formed simultaneously with the first active layer ACT1 and / or the second active layer ACT2. For example, the first active layer ACT1, the second active layer ACT2, and the third active layer ACT3 may include the same oxide semiconductor. For example, the third active layer ACT3 may include an oxide semiconductor containing indium (In) having a content ranging from about 40 at % to about 54 at %.

[0185] In an embodiment, the third active layer ACT3 may include a third channel region CH3 and a third source region SR3 and a third drain region DR3, and the third source region SR3 and the third drain region DR3 are spaced apart from each other by the third channel region CH3 interposed therebetween. For example, the third source region SR3 and the third drain region DR3 may be located at both sides of the third channel region CH3. The third channel region CH3 may be a region that maintains semiconductor characteristics and does not become conductive, and the third source region SR3 and the third drain region DR3 may be regions that have become conductive.

[0186] In an embodiment, the third active layer ACT3 may overlap the third gate electrode GE3. For example, a portion of the third active layer ACT3 including the third channel region CH3 may overlap the third gate electrode GE3.

[0187] In an embodiment, the third gate electrode GE3 (e.g., the top gate electrode of the third transistor T3) may be provided on the substrate SUB, in the second conductive layer CDL2. In an embodiment, the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be provided and / or disposed in the same layer (e.g., the same second conductive layer CDL2) on the substrate SUB, and may be formed simultaneously.

[0188] In an embodiment, the third gate electrode GE3 may be disposed on the third active layer ACT3 to overlap the third channel region CH3. The third gate electrode GE3 and the third active layer ACT3 may be spaced apart from each other with a third gate insulating layer GI3 interposed therebetween.

[0189] In an embodiment, the third gate insulating layer GI3 may be disposed between the third gate electrode GE3 and the third active layer ACT3. The third gate insulating layer GI3 may cover a portion of the third active layer ACT3 overlapping the third gate electrode GE3 (eg, the third channel region CH3).

[0190] In an embodiment, the third gate insulating layer GI3 may include the same material as the first gate insulating layer GI1 and / or the second gate insulating layer GI2, and may be formed simultaneously with the first gate insulating layer GI1 and / or the second gate insulating layer GI2. For example, the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3 may include the same insulating material (e.g., silicon oxide), and may be formed to have substantially the same or similar film quality. For example, the third gate insulating layer GI3 may be formed to have a film quality of approximately 1.04E+20Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 Nitric oxide (NO) emissions range and / or about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 Oxygen (O 2) of the insulation layer (or insulation pattern) within the emission range.

[0191] In an embodiment, the third drain electrode DE3 and the third source electrode SE3 may be provided on the substrate SUB in the third conductive layer CDL3. In an embodiment, the third drain electrode DE3 and the third source electrode SE3 may be disposed on the substrate SUB in the same layer as the first drain electrode DE1 and the second drain electrode DE2 and the first source electrode SE1 and the second source electrode SE2. For example, the third drain electrode DE3 and the third source electrode SE3 may be disposed on the interlayer insulating layer ILD covering the second conductive layer CDL2, and may be covered by the first passivation layer PSV1.

[0192] In an embodiment, the third drain electrode DE3 may be connected to a portion of the third active layer ACT3. For example, the third drain electrode DE3 may be connected to the third drain region DR3 through at least one contact hole passing through the interlayer insulating layer ILD.

[0193] In an embodiment, the third source electrode SE3 may be connected to another portion of the third active layer ACT3. For example, the third source electrode SE3 may be connected to the third source region SR3 through at least one contact hole passing through the interlayer insulating layer ILD.

[0194] In an embodiment, the pixel transistor Tpx including the first transistor T1 and the second transistor T2 and the driver transistor Tdr including the third transistor T3 may be covered by at least the first passivation layer PSV1. For example, the pixel transistor Tpx and the driver transistor Tdr may be covered by the first passivation layer PSV1 and the second passivation layer PSV2 (eg, Figure 4 ) or may be covered by the first passivation layer PSV1 (as shown in Figure 5 ).

[0195] In an embodiment, the content of indium (In) contained in the third active layer ACT3 may be controlled to be in the range of about 40 at % to about 54 at %, and at the same time, nitric oxide (NO) and / or oxygen (O 2 ) can be controlled within an exemplary range (e.g., the emission range of nitric oxide (NO) is about 1.04E+20Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 and / or oxygen (O 2 ) has an emission range of about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 ). Accordingly, the third transistor T3 may have element characteristics (or operation characteristics) suitable for a switching transistor or a pull-up or pull-down transistor of the first driver 120.

[0196] In an embodiment, Figure 7 and Figure 8 It is explained that the characteristics of the transistor vary according to the content of indium (In) contained in the active layer of the transistor and the deposition pressure of the gate insulating layer GI. For example, Figure 7 The electrical characteristics exhibited by the transistor through the drain-source current Ids according to the gate-source voltage Vgs when the gate insulating layer GI is deposited on an active layer having an indium (In) content of approximately 40at%, approximately 54at%, and approximately 60at%, respectively, at a pressure of approximately 1200mTorr (milliTorr) and approximately 1300mTorr, respectively. Figure 8 The electrical characteristics exhibited by the transistor through the drain-source current Ids according to the gate-source voltage Vgs when the gate insulating layer GI is deposited on an active layer having an indium (In) content of approximately 40at%, approximately 54at%, and approximately 60at%, respectively, are explained. Figure 7 and Figure 8 The electrical characteristics exhibited by the transistor when the gate insulating layer GI is deposited at a pressure of each of about 1200mTorr, about 1300mTorr, about 1400mTorr and about 1500mTorr on an active layer made of indium gallium zinc oxide (IGZO) having an indium (In) content of about 40at%, about 54at% and about 60at%, respectively (or indium tin gallium zinc oxide (ITGZO) to which a small amount (e.g., about 1at% to about 2at%) of tin (Sn) is added and the content of indium (In) or the contents of indium (In) and tin (Sn) are about 40at%, about 54at% and about 60at%, respectively).

[0197] In an embodiment, and with reference to Figure 7 and Figure 8 , in gate-sync. Figure 7 and Figure 8 A transistor having a channel width of about 9.5 μm and a channel length of about 6.0 μm in an active layer is formed in a dual-gate structure (for example, a double-gate structure in which a lower electrode is connected to a gate electrode), and the results of measuring the electrical characteristics of the transistor are explained. In addition, the solid line graph and the dotted line graph represent the results of measuring the electrical characteristics of the transistor under different drain-source voltage Vds conditions. For example, the solid line graph and the dotted line graph represent the measurement results when the drain-source voltage Vds is about 5.1 V and about 0.1 V, respectively, and the threshold voltage Vth is a value extracted from the measurement value when the drain-source voltage Vds is about 5.1 V. The thickness of the gate insulating layer GI between the active layer and the gate electrode of the transistor may be about

[0198] In an embodiment, and except Figure 1 to Figure 6 In addition, reference Figure 7 , when the deposition pressure of the gate insulating layer GI is less than about 1400mTorr, for example, when the gate insulating layer GI is deposited at a pressure of about 1200mTorr or about 1300mTorr, the transistor may exhibit electrical characteristics that are not suitable for use as a pixel transistor Tpx and / or a driver transistor Tdr. For example, when the deposition pressure of the gate insulating layer GI is about 1200mTorr, the transistor may exhibit operating characteristics substantially the same as those of a conductor. Although the deposition pressure of the gate insulating layer GI is about 1300mTorr and the content of indium (In) of the active layer is about 60at%, the transistor may exhibit operating characteristics substantially the same as those of a conductor. When the deposition pressure of the gate insulating layer GI is about 1300mTorr and the content of indium (In) of the active layer is about 40at% or about 54at%, the transistor may not exhibit operating characteristics that are the same as those of a conductor, but may exhibit electrical characteristics that are not suitable for use as a pixel transistor Tpx and / or a driver transistor Tdr of the display panel 110 because the negative offset value of the threshold voltage Vth is large.

[0199] In an embodiment, and except Figure 1 to Figure 7 In addition, reference Figure 8 , when the deposition pressure of the gate insulating layer GI ranges from about 1400mTorr to about 1500mTorr, the transistor may exhibit electrical characteristics suitable for use as a pixel transistor Tpx and / or a driver transistor Tdr according to the content of indium (In) in the active layer, or may operate substantially like a conductor. For example, when the deposition pressure of the gate insulating layer GI is about 1400mTorr or about 1500mTorr and the content of indium (In) in the active layer is about 40at% or about 54at%, the transistor may exhibit electrical characteristics suitable for use as a pixel transistor Tpx and / or a driver transistor Tdr (for example, a threshold voltage Vth and a mobility μ suitable for use as a pixel transistor Tpx and / or a driver transistor Tdr). In an embodiment, the threshold voltage Vth of a transistor suitable for use as a pixel transistor Tpx and a driver transistor Tdr may range from about -1V to about 0.5V, and the mobility μ may range from about 20cm 2 / Vs~about 50cm 2 / Vs. However, this may vary according to design conditions of the display panel 110, driving conditions of the pixel transistor Tpx and / or the driver transistor Tdr.

[0200] In an embodiment, when the content of indium (In) of the active layer is greater than about 54at%, for example, when the content of indium (In) of the active layer is about 60at%, the carrier concentration of the active layer is too large, and the transistor may exhibit the same operating characteristics as those of a conductor. For example, although the deposition pressure of the gate insulating layer GI is about 1400mTorr or about 1500mTorr, when the content of indium (In) of the active layer is about 60at%, the transistor may operate like a conductor.

[0201] In an embodiment, based on Figure 7 and Figure 8 According to the experimental results, the content of indium (In) constituting the active layer of each transistor and the deposition pressure of the gate insulating layer GI can be appropriately set and / or limited. For example, by setting or controlling the content of indium (In) in the active layer to about 54at% or less, the element characteristics (e.g., electrical characteristics) of the transistor suitable for use as the pixel transistor Tpx and / or the driver transistor Tdr can be ensured. In addition, in an embodiment, by setting or controlling the content of indium (In) in the active layer to about 40at% or more, although the transistor is formed in a micro size in a high-resolution display device 100, etc., the carrier concentration of the transistor can be controlled to a certain extent, so that appropriate mobility can be ensured and power consumption can be improved. For example, when the content of indium (In) in the active layer is less than about 40at%, the carrier concentration in the active layer is low, so that the power consumption will increase and / or the size of the transistor will need to be expanded to ensure the characteristics of the transistor. On the other hand, in other embodiments, by controlling the content of indium (In) in the active layer to about 40at% or more, the formation area of ​​the transistor can be reduced, and the power consumption of the display device 100 can be improved.

[0202] In addition, in an embodiment, by limiting the deposition pressure of the gate insulating layer GI to about 1400mTorr or more, the electrical characteristics of the transistor can be ensured to a degree suitable for use as a pixel transistor Tpx and / or a driver transistor Tdr. In addition, by limiting the deposition pressure of the gate insulating layer GI to about 1500mTorr or less, the reliability of the transistor manufactured thereby can be ensured. For example, when the deposition pressure of the gate insulating layer GI is greater than about 1500mTorr, it will be difficult to ensure the reliability of the transistor manufactured thereby, or the conductivity of the active layer will be excessively reduced. On the other hand, in an embodiment, the reliability and element characteristics of the transistor can be ensured by controlling the deposition pressure of the gate insulating layer GI to about 1500mTorr or less.

[0203] In an embodiment, Fig. 9 The emission amount of nitric oxide (NO) according to the deposition pressure of the gate insulating layer GI is explained. For example, Fig. 9The results of measuring the emission amount of nitrogen monoxide (NO) from the gate insulating layer GI according to the deposition pressure of the gate insulating layer GI in the analysis performed by thermal desorption spectroscopy (TDS) are explained.

[0204] In an embodiment, and except Figures 1 to 8 In addition, reference Fig. 9 In an analysis performed by thermal desorption spectroscopy (TDS), the gate insulating layer GI deposited at a pressure of each of about 1200 mTorr (mT), about 1225 mTorr, about 1250 mTorr, about 1300 mTorr, about 1400 mTorr, and about 1500 mTorr may emit nitric oxide (NO) at different concentrations according to the deposition pressure. As in the previously described embodiment, the gate insulating layer GI deposited at a pressure range of about 1400 mTorr to about 1500 mTorr may emit nitric oxide (NO) at about 1.04E+20 Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 In an embodiment, the analysis by thermal desorption spectroscopy (TDS) may be performed under a heat treatment condition performed at a temperature range of about 50° C. or more and about 550° C. or less, and the thickness of the gate insulating layer GI for measurement may be about

[0205] In an embodiment, Fig.10 The oxygen (O 2 ) emissions. For example, Fig.10 The present invention explains the measurement of oxygen (O ) from the gate insulating layer GI according to the deposition pressure of the gate insulating layer GI in the analysis performed by thermal desorption spectroscopy (TDS). 2 ) emissions results.

[0206] Apart from Figures 1 to 9 In addition, reference Fig.10 In an analysis performed by thermal desorption spectroscopy (TDS), the gate insulating layer GI deposited at a pressure of each of about 1200 mTorr (mT), about 1225 mTorr, about 1250 mTorr, about 1300 mTorr, about 1400 mTorr, and about 1500 mTorr may discharge oxygen (O) at different concentrations according to the deposition pressure. 2 As in the previously described embodiment, the gate insulating layer GI deposited under a pressure range of about 1400 mTorr to about 1500 mTorr may have a thickness of about 2.48E+19 Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 Oxygen emission within the range of 2In an embodiment, analysis by thermal desorption spectroscopy (TDS) may be performed under a heat treatment condition performed at a temperature range of about 50° C. or more and about 550° C. or less, and the thickness of the gate insulating layer GI for measurement may be about

[0207] In an embodiment and as described above, each transistor (e.g., the first transistor T1, the second transistor T2, or the third transistor T3) may include an active layer including an oxide semiconductor containing indium (In) having a content ranging from about 40 at % to about 54 at %. In addition, a gate insulating layer GI disposed on the active layer may have an emission amount of nitric oxide (NO) ranging from about 1.04E+20 Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3 and / or oxygen (O 2 ) has an emission range of about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 characteristics.

[0208] In an embodiment, Figure 7 to Figure 10 In the data disclosed in , the characteristics of the gate insulating layer GI are controlled by controlling the deposition pressure of the gate insulating layer GI related to the deposition conditions (e.g., chemical vapor deposition (CVD) parameters) of the gate insulating layer GI, but the present invention is not limited thereto. For example, at least one of the deposition pressure of the gate insulating layer GI, the deposition power, the distance between the deposition device and the target substrate (e.g., the substrate SUB provided with the first active layer ACT1 and the second active layer ACT2, respectively), and the flow rate ratio of the deposition gas is adjusted so that the gate insulating layer GI can be formed so that the emission amount of nitric oxide (NO) and / or oxygen (O 2 ) falls within the exemplified range.

[0209] Figures 11 to 18 1 is a cross-sectional view for explaining a method for manufacturing the display device 100 according to an embodiment. For example, Figures 11 to 18 The manufacturing Figure 4 or Figure 5 In the step of forming the display panel 110 of the substrate SUB, the pixel transistor Tpx is formed on the substrate SUB. In an embodiment, the driver transistor Tdr including the third transistor T3 may be formed simultaneously with the pixel transistor Tpx in a manner substantially the same as or similar to the pixel transistor Tpx. However, in the step of forming the first conductive layer CDL1, the corresponding lower electrode may or may not be formed in the driver transistor Tdr.

[0210] In an embodiment, and except Figures 1 to 10 In addition, reference Fig.11 , a substrate SUB including at least a display area DA may be prepared. The display area DA may include a pixel area PXA.

[0211] In an embodiment, the isolation layer BRL may be formed on the substrate SUB. The isolation layer BRL may be formed by a film forming process (e.g., a deposition process) of an insulating layer using at least one insulating material (e.g., an inorganic insulating material) exemplified above. The material and / or method for forming the isolation layer BRL may be variously changed according to the embodiment.

[0212] In an embodiment, and except Figures 1 to 11 In addition, reference Fig.12 , a first conductive layer CDL1 including at least one lower electrode may be formed on the substrate SUB. For example, the first lower electrode BG1 and the second lower electrode BG2 may be formed on the isolation layer BRL located on the substrate SUB. The first lower electrode BG1 and the second lower electrode BG2 may be formed in each of the pixel areas PXA.

[0213] In an embodiment, the first lower electrode BG1 and the second lower electrode BG2 may be formed by a film forming process (e.g., a deposition process) of a conductive layer using at least one conductive material exemplified above and a patterning process (e.g., an etching process using a mask) of the conductive layer. The material and / or method for forming the first lower electrode BG1 and the second lower electrode BG2 may be variously changed according to the embodiment.

[0214] In an embodiment, a buffer layer BFL covering the first conductive layer CDL1 may be formed on the substrate SUB. The buffer layer BFL may be formed by a film forming process using an insulating layer of at least one insulating material (e.g., an inorganic insulating material) exemplified above. The material and / or method for forming the buffer layer BFL may be variously changed according to the embodiment.

[0215] In an embodiment, and except Figures 1 to 12 In addition, reference Fig.13 , a semiconductor layer SCL including a first active layer ACT1 and a second active layer ACT2 may be formed on the buffer layer BFL. For example, the first active layer ACT1 and the second active layer ACT2 may be formed in each of the pixel areas PXA. The first active layer ACT1 may be formed to overlap the first lower electrode BG1, and the second active layer ACT2 may be formed to overlap the second lower electrode BG2.

[0216] In an embodiment, the active layer ACT provided in the semiconductor layer SCL may be simultaneously formed using the same oxide semiconductor. For example, the first active layer ACT1 and the second active layer ACT2 may be simultaneously formed using the same oxide semiconductor. For example, the first active layer ACT1 and the second active layer ACT2 may be formed in the pixel area PXA by a film formation process and a patterning process of an oxide semiconductor layer using at least one oxide semiconductor exemplified above.

[0217] In an embodiment, the first active layer ACT1 and the second active layer ACT2 may be formed using an oxide semiconductor containing indium (In) in a content range of about 40 at % to about 54 at %. For example, by controlling the indium (In) ratio of a sputtering target made of an oxide semiconductor containing indium (In) within a range of about 40 at % to about 54 at %, the first active layer ACT1 and the second active layer ACT2 each containing indium (In) in a content range of about 40 at % to about 54 at % may be formed.

[0218] In an embodiment, when the display panel 110 further includes Figure 6 When the third transistor T3 explained in FIG. 1 is formed, the first active layer ACT1 and the second active layer ACT2 may be formed in the pixel area PXA, and at the same time, the third active layer ACT3 may be formed in the driving circuit area DRA. For example, the third active layer ACT3 may be formed on the buffer layer BFL in the driving circuit area DRA by using the same oxide semiconductor as that of the first active layer ACT1 and the second active layer ACT2.

[0219] In an embodiment, and except Figures 1 to 13 In addition, reference Fig.14 A gate insulating layer GI covering the semiconductor layer SCL may be formed on the substrate SUB. For example, the gate insulating layer GI may be formed on an active layer (eg, the first active layer ACT1, the second active layer ACT2, and / or the third active layer ACT3) provided in the semiconductor layer SCL.

[0220] In an embodiment, the gate insulating layer GI may be first completely formed on the substrate SUB provided with the first active layer ACT1 and the second active layer ACT2. For example, after the gate insulating layer GI is formed by depositing an insulating material containing an oxide (e.g., silicon oxide) on the substrate SUB on which the semiconductor layer SCL is formed, a subsequent process such as heat treatment (e.g., annealing) may be performed. In an embodiment, the deposition conditions of the gate insulating layer GI may be controlled so that the emission amount of nitric oxide (NO) of the gate insulating layer GI is about 1.04E+20Molec. / cm 3 ~ about 1.15E+20Molec. / cm 3and / or the oxygen (O 2 ) has an emission of about 2.48E+19Molec. / cm 3 ~ about 2.76E+19Molec. / cm 3 within the range.

[0221] In an embodiment, the deposition conditions for controlling the film quality of the gate insulating layer GI may be at least one of a deposition pressure, a deposition power, a distance between a deposition device and a target substrate (e.g., a substrate SUB provided with a first active layer ACT1 and a second active layer ACT2), and a flow rate ratio of a deposition gas. For example, by depositing an insulating material containing an oxide (e.g., silicon oxide) at a pressure range of about 1400 mTorr to about 1500 mTorr, the gate insulating layer GI may be formed so that the gate insulating layer GI has the characteristics of satisfying the above-mentioned gas emission amount.

[0222] In an embodiment, and except Figure 1 to Figure 14 In addition, reference Fig.15 , a second conductive layer CDL2 including a first gate electrode GE1 and a second gate electrode GE2 may be formed on the gate insulating layer GI. For example, in each of the pixel areas PXA, the first gate electrode GE1 may be formed on the first active layer ACT1 to overlap a portion of the first active layer ACT1, and the second gate electrode GE2 may be formed on the second active layer ACT2 to overlap a portion of the second active layer ACT2.

[0223] In an embodiment, the first gate electrode GE1 and the second gate electrode GE2 provided in the second conductive layer CDL2 may be formed simultaneously using the same conductive material. For example, the first gate electrode GE1 and the second gate electrode GE2 may be formed simultaneously by a film forming process of a conductive layer using at least one conductive material exemplified above and a patterning process of the conductive layer. The materials and / or methods for forming the first gate electrode GE1 and the second gate electrode GE2 may be variously changed according to the embodiment.

[0224] In an embodiment, when the display panel 110 further includes Figure 6 When the third transistor T3 is explained in FIG. 1 , the first gate electrode GE1 and the second gate electrode GE2 may be formed in the pixel area PXA, and at the same time, the third gate electrode GE3 may be formed in the driving circuit area DRA. For example, the third gate electrode GE3 may be formed in the driving circuit area DRA by using the same conductive material as the first gate electrode GE1 and the second gate electrode GE2.

[0225] In an embodiment, and except Figure 1 to Figure 15 In addition, reference Fig.16, the gate insulating layer GI may be etched to have a shape corresponding to the shape of each gate electrode. As a result, the first gate insulating layer GI1 overlapping the first gate electrode GE1 and the second gate insulating layer GI2 overlapping the second gate electrode GE2 may be formed separately. For example, the gate insulating layer GI may be etched by using a mask for patterning the first gate electrode GE1 and the second gate electrode GE2 or using the first gate electrode GE1 and the second gate electrode GE2 as a mask. Accordingly, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed under the first gate electrode GE1 and the second gate electrode GE2, respectively. The first gate insulating layer GI1 may be formed on a portion of the first active layer ACT1 overlapping the first gate electrode GE1, and may have a shape and / or size corresponding to the shape and / or size of the first gate electrode GE1. The second gate insulating layer GI2 may be formed on a portion of the second active layer ACT2 overlapping the second gate electrode GE2, and may have a shape and / or size corresponding to the shape and / or size of the second gate electrode GE2.

[0226] In an embodiment, in a process of forming the first gate insulating layer GI1 and the second gate insulating layer GI2 by etching the gate insulating layer GI, the characteristics of the first active layer ACT1 and the second active layer ACT2 may be changed so that each portion of the first active layer ACT1 and the second active layer ACT2 has different characteristics. Accordingly, each of the first active layer ACT1 and the second active layer ACT2 may be divided into a plurality of regions having different characteristics.

[0227] For example, in an embodiment, oxygen vacancies may occur in the oxide semiconductor forming the first active layer ACT1 mainly in a portion not overlapping with the first gate electrode GE1 due to etching gas, etc. In an embodiment, oxygen vacancies may occur mainly in a portion of the first active layer ACT1 not overlapping with the first gate electrode GE1 (e.g., the first drain region DR1 and the first source region SR1). The oxygen vacancies in the first active layer ACT1 may diffuse to a portion of the region overlapping with the first gate electrode GE1. Accordingly, the first active layer ACT1 may be divided into a plurality of regions having different characteristics (e.g., the first channel region CH1, the first drain region DR1, and the first source region SR1).

[0228] Similarly, in an embodiment, oxygen vacancies may occur in the oxide semiconductor forming the second active layer ACT2 mainly in a portion not overlapping with the second gate electrode GE2. Accordingly, the second active layer ACT2 may be divided into a plurality of regions (e.g., a second channel region CH2, a second drain region DR2, and a second source region SR2) having different characteristics.

[0229] In another embodiment, the gate insulating layer GI may not be etched into a shape corresponding to the shape of the first gate electrode GE1 and / or the second gate electrode GE2, and the gate insulating layer GI may be formed to completely cover the display area DA, etc. In an embodiment, the following process may be additionally performed: a portion of the first active layer ACT1 not covered by the first gate electrode GE1 (e.g., the first drain region DR1 and the first source region SR1) and / or a portion of the second active layer ACT2 not covered by the second gate electrode GE2 (e.g., the second drain region DR2 and the second source region SR2) are doped to make them conductive. In another embodiment, the doping process may not be performed. In this case, during a subsequent formation process of the interlayer insulating layer ILD, hydrogen is introduced into the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2, so that the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2 may become conductive.

[0230] In an embodiment, when the display panel 110 further includes Figure 6 When the third transistor T3 is illustrated in FIG. 1 , the first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed in the pixel area PXA, and at the same time, the third gate insulating layer GI3 may be formed in the driving circuit area DRA. For example, the gate insulating layer GI may be integrally formed and may be etched and patterned into the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3.

[0231] In an embodiment, and except Figures 1 to 16 In addition, reference Fig.17 , an active layer (e.g., a first active layer ACT1 and a second active layer ACT2) provided in the semiconductor layer SCL and an interlayer insulating layer ILD covering a gate electrode (e.g., a first gate electrode GE1 and a second gate electrode GE2) provided in the second conductive layer CDL2 may be formed on the buffer layer BFL. The interlayer insulating layer ILD may be formed by a film forming process of an insulating layer using at least one insulating material (e.g., an inorganic insulating material) exemplified above. In an embodiment, after the interlayer insulating layer ILD is formed, a subsequent process such as a heat treatment may be performed. The material and / or method for forming the interlayer insulating layer ILD may be variously changed according to the embodiment.

[0232] In an embodiment, in a process of forming the interlayer insulating layer ILD, hydrogen may be introduced into an active layer of the semiconductor layer SCL including the first active layer ACT1 and the second active layer ACT2. When hydrogen is introduced into the first active layer ACT1 and the second active layer ACT2 (mainly in a portion containing many oxygen vacancies), the first active layer ACT1 and the second active layer ACT2 may partially become conductive (e.g., N-type). For example, the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2 may become conductive. In an embodiment, when the display panel 110 further includes Figure 6 When the third transistor T3 illustrated in FIG. 1 is turned on, the third drain region DR3 and the third source region SR3 may also become conductive.

[0233] In an embodiment, and except Figure 1 to Figure 17 In addition, reference Fig.18 , the first drain electrode DE1, the first source electrode SE1, the second drain electrode DE2, and the second source electrode SE2 may be formed on the interlayer insulating layer ILD. In an embodiment, when at least one of the first drain region DR1, the first source region SR1, the second drain region DR2, and the second source region SR2 replaces at least one of the first drain electrode DE1, the first source electrode SE1, the second drain electrode DE2, and the second source electrode SE2, respectively, at least one of the first drain electrode DE1, the first source electrode SE1, the second drain electrode DE2, and the second source electrode SE2 may not be formed.

[0234] In an embodiment, the first drain electrode DE1 and the first source electrode SE1 may be formed to be connected to different portions of the first active layer ACT1. For example, the first drain electrode DE1 may be formed to be connected to the first drain region DR1, and the first source electrode SE1 may be formed to be connected to the first source region SR1. The second drain electrode DE2 and the second source electrode SE2 may be formed to be connected to different portions of the second active layer ACT2. For example, the second drain electrode DE2 may be formed to be connected to the second drain region DR2, and the second source electrode SE2 may be formed to be connected to the second source region SR2. To this end, before forming the first drain electrode DE1, the first source electrode SE1, the second drain electrode DE2, and the second source electrode SE2, a plurality of contact holes may be formed in the interlayer insulating layer ILD.

[0235] In an embodiment, when the display panel 110 further includes Figure 6When the third transistor T3 explained in the above description is formed, the first drain electrode DE1 and the second drain electrode DE2 are respectively formed in the pixel area PXA and the first source electrode SE1 and the second source electrode SE2 are respectively formed, and at the same time, the third drain electrode DE3 and the third source electrode SE3 may be formed in the driving circuit area DRA. For example, the conductive layer formed on the interlayer insulating layer ILD may be etched and patterned to form the first drain electrode DE1, the second drain electrode DE2 and the third drain electrode DE3 and to form the first source electrode SE1, the second source electrode SE2 and the third source electrode SE3.

[0236] In an embodiment, through the above process, a plurality of pixel transistors Tpx including the first transistor T1 and the second transistor T2 may be formed in the display area DA. In an embodiment in which the display panel 110 includes the driving circuit area DRA, a plurality of driver transistors Tdr including the third transistor T3 may be formed in the driving circuit area DRA. In an embodiment, elements provided in the same conductive layer or the same semiconductor layer SCL of the display panel 110 may be formed simultaneously.

[0237] In an embodiment, after forming the pixel transistor Tpx and / or the driver transistor Tdr, the formation of Figure 4 and Figure 5 The first passivation layer PSV1 may cover the pixel transistor Tpx and / or the driver transistor Tdr. In an embodiment, a process of forming a fourth conductive layer CDL4 including a connection electrode CNE of each pixel PX on the first passivation layer PSV1 and a process of forming a second passivation layer PSV2 covering the fourth conductive layer CDL4 may be additionally performed. Accordingly, a panel circuit layer PCL of the display panel 110 may be formed.

[0238] In an embodiment, when the display panel 110 includes a light emitting element layer LEL and an encapsulation layer ENL disposed on the panel circuit layer PCL, the light emitting element layer LEL and the encapsulation layer ENL are sequentially formed on the panel circuit layer PCL. Through the above process, the display panel 110 according to the embodiment and the display device 100 including the display panel 110 can be manufactured.

[0239] At the end of the detailed description, those skilled in the art will recognize that many variations and modifications may be made to the present invention without substantially departing from the scope of the present invention. Therefore, the disclosed embodiments are used only in a general and descriptive sense, and not for the purpose of limitation. The present invention should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the concept of the present invention will be fully conveyed to those skilled in the art. Moreover, the embodiments or parts of the embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, comprising: substrate; a first transistor comprising a first active layer disposed on the substrate and a first gate electrode disposed on the first active layer; as well as a first gate insulating layer, disposed between the first active layer and the first gate electrode, The first active layer comprises an oxide semiconductor containing indium in a content range of 40 at % to 54 at %, and Under the heat treatment condition in the temperature range of 50°C to 550°C, the first gate insulating layer has a strength of 2.48E+19Molec. / cm 3 ~2.76E+19Molec. / cm 3 Oxygen emission range and / or 1.04E+20Molec. / cm 3 ~1.15E+20Molec. / cm 3 range of nitric oxide emissions. 2 . The display device according to claim 1 , wherein the first active layer further contains at least one of gallium, zinc and tin. 3 . The display device according to claim 2 , wherein the first active layer contains indium gallium zinc oxide, indium tin gallium oxide or indium tin gallium zinc oxide. The display device according to claim 1 , wherein the first gate insulating layer contains silicon oxide. 5 . The display device according to claim 1 , further comprising a pixel, wherein the pixel includes a pixel circuit including the first transistor and a light emitting element connected to the pixel circuit.

6. The display device according to claim 5, wherein the pixel further comprises: a second transistor comprising a second active layer disposed on the substrate and a second gate electrode disposed on the second active layer; as well as The second gate insulating layer is disposed between the second active layer and the second gate electrode. 7 . The display device according to claim 6 , wherein the second active layer is provided in the same layer as the first active layer, wherein the second active layer contains the same oxide semiconductor as that of the first active layer. 8 . The display device according to claim 6 , wherein the second gate insulating layer is provided in the same layer as the first gate insulating layer, wherein the second gate insulating layer contains the same insulating material as that of the first gate insulating layer. 9 . The display device according to claim 5 , further comprising a driver disposed on the substrate and electrically connected to the pixels.

10. The display device according to claim 9, wherein the driver comprises: a third transistor including a third active layer disposed on the substrate and containing an oxide semiconductor identical to that of the first active layer, wherein a third gate electrode is disposed on the third active layer; as well as A third gate insulating layer is disposed between the third active layer and the third gate electrode and contains the same insulating material as that of the first gate insulating layer.

11. The display device according to claim 1, wherein the first active layer comprises a first channel region overlapping the first gate electrode, and a first drain region and a first source region located on both sides of the first channel region, wherein: The first gate insulating layer is disposed only on a portion of the first active layer including the first channel region, and is an insulating pattern in a form exposing the first drain region and the first source region.

12. The display device according to claim 1, further comprising an interlayer insulating layer disposed on the substrate and covering the first active layer and the first gate electrode, The first transistor further includes at least one of a first drain electrode disposed on the interlayer insulating layer and connected to a portion of the first active layer and a first source electrode disposed on the interlayer insulating layer and connected to another portion of the first active layer. 13 . The display device of claim 12 , further comprising a first passivation layer disposed on the interlayer insulating layer and covering the first transistor. 14 . The display device of claim 13 , wherein the first passivation layer comprises an inorganic insulating layer including silicon nitride.

15. The display device according to claim 13, further comprising a second passivation layer disposed on the first passivation layer, wherein the first passivation layer comprises an inorganic insulating layer containing silicon oxide, and The second passivation layer includes an inorganic insulating layer containing silicon nitride.

16. The display device according to claim 1, wherein the first transistor has a 2 / Vs~50cm 2 / Vs range.

17. The display device according to claim 1, wherein the first transistor has a threshold voltage in the range of -1.0V to +0.5V.

18. A method for manufacturing a display device, comprising: forming an active layer on a substrate; forming a gate insulating layer on the active layer; as well as forming a gate electrode on the gate insulating layer, wherein in the formation of the active layer, an oxide semiconductor containing indium in a content range of 40 at % to 54 at % is used to form the active layer, and In the forming of the gate insulating layer, the gate insulating layer is formed by depositing an insulating material containing oxide on the substrate at a pressure ranging from 1400 mTorr to 1500 mTorr. 19 . The method of claim 18 , further comprising etching the gate insulating layer to have a shape corresponding to a shape of the gate electrode.

20. The method of claim 18, further comprising: forming an interlayer insulating layer covering the active layer and the gate electrode; as well as At least one of a drain electrode connected to a portion of the active layer and a source electrode connected to another portion of the active layer is formed on the interlayer insulating layer.

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