Semiconductor device and forming method thereof

Abstract

In a top view of the semiconductor device, the semiconductor device includes an integrated circuit and one or more guard rings around the integrated circuit. At least one guard ring of the one or more guard rings includes an active region in the substrate, a first plurality of elongated conductive structures extending in a first direction and arranged in a second direction in a top view of the semiconductor device and a second plurality of elongated conductive structures extending in the second direction and arranged in the first direction. The combination of the first plurality of elongated conductive structures and the second plurality of elongated conductive structures forms a conductive grid over the active region and provides increased coverage of a surface region of the active region relative to including only the first plurality of elongated conductive structures or only the second plurality of elongated conductive structures. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] A guard ring is a semiconductor structure typically included around an integrated circuit of a semiconductor device to provide electrical isolation, electrostatic discharge (ESD) protection, and / or structural integrity, among other examples. For example, a guard ring may be included to absorb charge carriers (e.g., electrons and / or holes) formed in a substrate of a semiconductor device due to substrate implantation. Otherwise, these charge carriers (if accumulated in the substrate) may cause a low impedance path to be formed between the integrated circuit and an adjacent integrated circuit through the substrate. Otherwise, such a low impedance path may create an electrical short between the integrated circuits, which is referred to as "latch-up." Latch-up may result in degraded operation of the semiconductor device and / or may cause damage to the semiconductor device, among other examples. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, including: an integrated circuit; a guard ring structure surrounding the integrated circuit in a top view of the semiconductor device, wherein the guard ring structure includes: an active area; a first plurality of conductive structures located above the active area, wherein the first plurality of conductive structures extend in a first direction in the semiconductor device and are arranged in a second direction approximately perpendicular to the first direction in the semiconductor device; and a second plurality of conductive structures located above the active area, wherein the second plurality of conductive structures extend in the second direction and are arranged in the first direction; and an interconnect structure located above the guard ring structure.

[0004] Some further embodiments of the present application provide a semiconductor device, comprising: an integrated circuit; a guard ring structure surrounding the integrated circuit in a top view of the semiconductor device, wherein the guard ring structure comprises: a first plurality of conductive structures, wherein the first plurality of conductive structures extend in a first direction in the semiconductor device and are arranged in a second direction approximately perpendicular to the first direction in the semiconductor device; a second plurality of conductive structures, wherein the second plurality of conductive structures extend in the second direction and are arranged in the first direction, and wherein a first length of a first subset of the second plurality of conductive structures is greater than a second length of a second subset of the second plurality of conductive structures; and a plurality of polysilicon structures extending in the first direction, wherein each of the polysilicon structures is located between adjacent pairs of the first plurality of conductive structures; a first interconnect structure located above the guard ring structure, wherein at least a first subset of the first plurality of conductive structures is located within a coverage area of ​​the first interconnect structure; and a second interconnect structure located above the guard ring structure, wherein at least a second subset of the first plurality of conductive structures is located within a coverage area of ​​the second interconnect structure.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: providing an active region around an integrated circuit of the semiconductor device; forming a first plurality of conductive structures extending in a first direction of the semiconductor device and arranged in a second direction approximately perpendicular to the first direction in the semiconductor device over the active region; forming a second plurality of conductive structures extending in the second direction and arranged in the first direction over the active region, wherein the first plurality of conductive structures and the second plurality of conductive structures intersect to form a guard ring structure over the active region; and forming one or more interconnect structures over the guard ring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 is a diagram of an exemplary environment in which the systems and / or methods described herein may be implemented.

[0008] FIG. 2A to FIG. 2I is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0009] FIG. 3A to FIG. 3D is a diagram of an exemplary embodiment of forming a guard ring for a semiconductor device described herein.

[0010] 4A to 4F is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0011] FIG. 5A to FIG. 5E is a diagram of an exemplary embodiment of forming a guard ring for a semiconductor device described herein.

[0012] Figure 6 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0013] Figure 7 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0014] Figure 8 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0015] Fig. 9 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0016] Fig.10 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0017] Fig.11 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0018] Fig.12 is a diagram of exemplary components of a device described herein.

[0019] Fig.13 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] In some instances, the guard ring may conduct charge carriers through a conductive structure above the active area of ​​the guard ring. The charge carrier absorption performance in the guard ring may be based at least in part on the surface area of ​​the active area covered by the conductive structure. If insufficient surface area of ​​the active area is covered by the conductive structure, the guard ring may not provide sufficient charge carrier absorption, which may increase the possibility of latch-up in the semiconductor device. However, due to the placement of the conductive structure within the footprint or boundary of the interconnect structure above the conductive structure, the size and / or density of the conductive structure may be limited. Therefore, the size and / or density of the conductive structure may not cause the conductive structure to extend laterally outward from the footprint or boundary of the interconnect structure. Optionally, the distance or spacing between adjacent integrated circuits in the semiconductor device can be increased to reduce the possibility of latch-up at the expense of reduced integrated circuit density and / or increased size of the semiconductor device.

[0023] In some embodiments described herein, in a top view of the semiconductor device, the semiconductor device includes an integrated circuit and one or more guard rings around the integrated circuit. At least one of the one or more guard rings includes an active area in a substrate, a first plurality of elongated conductive structures extending in a first direction in a top view of the semiconductor device and arranged in a second direction in a top view of the semiconductor device, and a second plurality of elongated conductive structures extending in a second direction and arranged in the first direction. The combination of the first plurality of elongated conductive structures and the second plurality of elongated conductive structures forms a conductive grid over the active area and provides increased coverage of a surface area of ​​the active area relative to only the first plurality of elongated conductive structures or only the second plurality of elongated conductive structures. The combination of the first plurality of elongated conductive structures and the second plurality of elongated conductive structures enables coverage of the surface area to be increased in both the first direction and the second direction within a footprint or boundary of an interconnect structure over the first plurality of conductive structures and the second plurality of conductive structures. In this manner, the first plurality of conductive structures and the second plurality of conductive structures enable a high amount of charge carrier absorption to be achieved in the semiconductor device (which can reduce the likelihood of latch-up in the semiconductor device) while enabling a short distance or spacing between adjacent integrated circuits in the semiconductor device.

[0024] Figure 1 1 is a diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown in , the exemplary environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer / die transport tool 114. The plurality of semiconductor processing tools 102-112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, an ion implantation tool 112, and / or another type of semiconductor processing tool. The tools included in the exemplary environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, among other examples.

[0025] The deposition tool 102 is a semiconductor processing tool including a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a high density plasma CVD (HDP-CVD) tool, a sub-atmospheric pressure CVD (SACVD) tool, a low pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to form a layer and / or region of a device by epitaxial growth. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0026] In some embodiments, the deposition tool 102 includes an electroplating tool and / or another type of plating tool capable of plating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion thereof with one or more metals. For example, the deposition tool 102 can include a copper electroplating tool, an aluminum electroplating tool, a nickel electroplating tool, a tin electroplating tool, a compound material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating tool, and / or an electroplating tool for one or more other types of conductive materials, metals, and / or similar types of materials.

[0027] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep UV light source, an extreme UV (EUV) source, etc.), an x-ray source, an electron beam (e-beam) source, etc. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, etc. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0028] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0029] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, etc. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 can use plasma etching or plasma assisted etching to etch one or more portions of the substrate, which can involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0030] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 may polish or planarize the surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free grinding polishing). The planarization tool 110 may utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head may rotate with different rotation axes to remove material and level any irregular topography of the semiconductor device, making the semiconductor device flat or flat.

[0031] The ion implantation tool 112 is a semiconductor processing tool for implanting ions into a substrate such as a semiconductor wafer. The ion implantation tool 112 generates ions from a source material such as a gas or a solid in an arc chamber. The source material is provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes are used to extract ions from the plasma in the arc chamber, and the ions are accelerated to form an ion beam. The ion beam can be directed toward the substrate so that the ions are implanted below the surface of the substrate to dope the substrate.

[0032] The wafer / die transporter 114 includes a mobile robot, a robotic arm, a tram or rail car, an overhead lift transport (OHT) system, an automatic material handling system (AMHS), and / or a device configured to transport substrates and / or semiconductor devices between semiconductor processing tools 102-112, to transport substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or to transport substrates and / or semiconductor devices to other locations (such as wafer racks, storage chambers, etc.) and from other locations. In some embodiments, the wafer / die transporter 114 can be a programmed device configured to travel a specific path and / or can be semi-automatically or automatically operated. In some embodiments, the exemplary environment 100 includes multiple wafer / die transporters 114.

[0033] For example, the wafer / die transporter 114 may be included in a cluster tool or another type of tool including multiple processing chambers, and may be configured to transport substrates and / or semiconductor devices between multiple processing chambers, between a processing chamber and a buffer, between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or between a processing chamber and a transport carrier (e.g., a front opening unified box (FOUP)), among other examples. In some embodiments, the wafer / die transporter 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport tool 114 is configured to transport substrates and / or semiconductor devices between processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) between the processing chambers and / or between processing operations in the deposition tool 102, as described herein.

[0034] In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 can be used to perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 can be used to provide an active region around an integrated circuit device of a semiconductor device; form a first plurality of conductive structures extending in a first direction of the semiconductor device and arranged in a second direction approximately perpendicular to the first direction over the active region; form a second plurality of conductive structures extending in a second direction and arranged in the first direction over the active region, wherein the first plurality of conductive structures and the second plurality of conductive structures intersect to form a guard ring structure over the active region; and / or form one or more interconnect structures over the guard ring structure, as well as other examples.

[0035] In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may be used to implement the bonding FIG. 3A to FIG. 3D , FIG. 5A to FIG. 5E and / or Fig.13 One or more semiconductor processing operations are described, among other examples.

[0036] Figure 1 The number and arrangement of the devices shown in are provided as examples. In practice, there may be Figure 1 Additional devices, fewer devices, different devices, or differently arranged devices than those shown in . In addition, Figure 1 Two or more of the devices shown in FIG. 1 may be implemented in a single device, or Figure 1 A single device shown in the example environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, a device group (eg, one or more devices) of the example environment 100 may implement one or more functions described as being implemented by another device group of the example environment 100.

[0037] FIG. 2A to FIG. 2I is a diagram of an exemplary embodiment of a semiconductor device 200 described herein. The semiconductor device 200 includes examples of semiconductor devices such as a microprocessor (e.g., a central processing unit (CPU), a graphics processing unit (GPU)), a memory device, an image sensor, and / or a radio frequency (RF) device (e.g., an RF amplifier, an RF front-end device), among other examples.

[0038] Figure 2A and Figure 2B 2 shows a top view of an exemplary embodiment of a semiconductor device 200. Figure 2A and Figure 2BAs shown in FIG, semiconductor device 200 includes integrated circuit 202 and guard ring structure 204 around integrated circuit 202. Integrated circuit 202 may include one or more transistors, memory cell arrays, and / or another type of integrated circuit 202. The transistor may include a planar transistor, a fin-based transistor (e.g., a fin field effect transistor (finFET)), a nanostructure transistor (e.g., a nanowire transistor, a nanosheet transistor, a nanoribbon transistor, a nanotube transistor, a multi-bridge channel transistor, a gate-all-around (GAA) transistor), and / or another type of transistor. Figure 2A and Figure 2B The sizes, shapes, and / or orientations of the integrated circuit 202 shown in are examples, and other sizes, shapes, and / or orientations for the integrated circuit 202 are within the scope of the disclosed embodiments.

[0039] Integrated circuit 202 may be formed in and / or on a substrate of semiconductor device 200. The substrate may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate.

[0040] In the top view of the semiconductor device 200, the guard ring structure 204 surrounds the integrated circuit 202. The guard ring structure 204 is included around the integrated circuit 202 to provide electrical isolation, electrostatic discharge (ESD) protection, and / or structural integrity for the integrated circuit 202 and / or other devices of the semiconductor device 200. The guard ring structure 204 includes an active area 206 around the integrated circuit 202 and a plurality of conductive structures 208 and 210 above the active area 206. The conductive structures 208 and 210 intersect to form a conductive grid of the guard ring structure 204 above the active area 206. The conductive structures 208 and 210 absorb charge carriers (e.g., electrons and / or holes) from the active area 206 formed in the substrate of the semiconductor device 200 due to substrate implantation. In this way, the guard ring structure 204 prevents or reduces the possibility of forming a low impedance path through the substrate between the integrated circuit 202 and adjacent devices in the semiconductor device 200.

[0041] The active region 206 may include a portion of the substrate of the semiconductor device 200 around the integrated circuit 202. In some embodiments, the active region 206 includes a doped portion of the substrate of the semiconductor device 200 around the integrated circuit 202, the doped portion being doped with one or more types of dopants (e.g., n-type dopants, p-type dopants). In some embodiments, the active region 206 includes a ring of epitaxially grown semiconductor material (e.g., silicon (Si)) in the substrate around the integrated circuit 202. The active region 206 may be continuous around the integrated circuit 202, meaning that there are no discontinuities in the active region 206 around the integrated circuit 202. Alternatively, the active region 206 may include multiple discontinuous segments around the integrated circuit 202.

[0042] The conductive structures 208 are arranged in the x-direction (e.g., spaced apart in the x-direction) in the top view of the semiconductor device 200, and extend in the y-direction in the top view of the semiconductor device 200. The conductive structures 208 may be included above and / or on the active region 206. The conductive structures 208 may be formed simultaneously with source / drain contacts of transistors in the integrated circuit 202. The conductive structures 208 may be formed of the same conductive material as the source / drain contacts, such as cobalt (Co), tungsten (W), ruthenium (Ru), titanium (Ti), copper (Cu), and / or aluminum (Al), among other examples.

[0043] Conductive structures 208 may be arranged in the guard ring structure 204 in multiple groups of one or more conductive structures 208. For example, the guard ring structure 204 may include multiple segments, including segment 204a, segment 204b, segment 204c, and segment 204d, among other examples. Segment 204a may include one or more conductive structures 208a, segment 204b may include one or more conductive structures 208b, segment 204c may include one or more conductive structures 208c, and segment 204d may include one or more conductive structures 208d.

[0044] Segments 204a and 204b may be located on opposite sides of the integrated circuit 202 and may extend in the x-direction so that segments 204a and 204b are approximately parallel. Segments 204c and 204d may be located on opposite sides of the integrated circuit 202 and may extend in the y-direction so that segments 204c and 204d are approximately parallel. Thus, segments 204a and 204b are approximately perpendicular to segments 204c and 204d. In some embodiments, segment 204c may include a number of conductive structures 208c included in a range from 1 to 8. However, other values ​​for ranges are within the scope of embodiments of the present disclosure. In some embodiments, segment 204d may include a number of conductive structures 208d included in a range from 1 to 8. However, other values ​​for ranges are within the scope of embodiments of the present disclosure.

[0045] Segments 204a and 204b may each have a Figure 2A The y-direction width of dimension D1 in FIG. In some embodiments, dimension D1 is included in the range of about 0.1 microns to about 5 microns. However, other values ​​for the range are within the scope of the embodiments of the present disclosure.

[0046] exist Figure 2A and Figure 2B In the exemplary embodiment shown in , the y-direction length of conductive structure 208a, and in some embodiments, the y-direction length of conductive structure 208b (corresponding to dimension D2) can be less than the y-direction width of segments 204a and 204b. Figure 2A and Figure 2B In the exemplary embodiment shown in , the conductive structures 208 a and / or 208 b are completely contained within the top view footprint of the active area 206 .

[0047] The distance between the end of conductive structure 208a and the edge of active area 206 in segment 204a (corresponding to dimension D3) and / or the distance between the end of conductive structure 208b and the edge of active area 206 in segment 204b may be included in the range of about 0.01 microns to about 1 micron. However, other values ​​for the ranges are within the scope of the disclosed embodiments.

[0048] Additionally and / or optionally, at least a subset of conductive structures 208a and / or at least a subset of conductive structures 208b may have a y-direction length approximately equal to the y-direction width of active region 206 in segments 204a and / or 204b (eg, dimension D2 may be approximately equal to dimension D1).

[0049] The x-direction width of the conductive structure 208 (corresponding to dimension D4) may be included in a range of about 0.02 microns to about 1 micron. However, other values ​​for the range are within the scope of the disclosed embodiments.

[0050] The conductive structures 210 are arranged in the y-direction (e.g., spaced apart in the y-direction) in the top view of the semiconductor device 200 and extend in the x-direction in the top view of the semiconductor device 200. The conductive structures 210 may be included above and / or on the active region 206. Thus, the conductive structures 210 are approximately perpendicular to the conductive structures 208. The conductive structures 210 may be formed simultaneously with gate contacts of transistors in the integrated circuit 202. The conductive structures 210 may be formed of the same conductive material as the source / drain contacts, such as cobalt (Co), tungsten (W), ruthenium (Ru), titanium (Ti), copper (Cu), and / or aluminum (Al), among other examples.

[0051] Conductive structures 210 may be arranged in the guard ring structure 204 in multiple groups of one or more conductive structures 210. For example, segment 204a may include one or more conductive structures 210a, segment 204b may include one or more conductive structures 210b, segment 204c may include one or more conductive structures 210c, and segment 204d may include one or more conductive structures 210d. In some embodiments, segment 204a may include a number of conductive structures 210a included in the range from 1 to 8. However, other values ​​for ranges are within the scope of the embodiments of the present disclosure. In some embodiments, segment 204b may include a number of conductive structures 210b included in the range from 1 to 8. However, other values ​​for ranges are within the scope of the embodiments of the present disclosure.

[0052] Segments 204c and 204d may each have a Figure 2A The x-direction width of dimension D5. Figure 2A and Figure 2B In the exemplary embodiment shown in , the x-direction length of conductive structure 210d, and in some embodiments, the x-direction length of conductive structure 210c (corresponding to dimension D6) can be approximately equal to the y-direction width of segments 204c and 204d. Figure 2A and Figure 2B In the exemplary embodiment shown in , the conductive structures 210 c and / or 210 d are completely contained within the top view footprint of the active area 206 .

[0053] Additionally and / or alternatively, at least a subset of the conductive structures 210c and / or at least a subset of the conductive structures 210d can have an x-direction length that is less than the x-direction width of the active region 206 in the segments 204c and / or 204d (e.g., dimension D5 can be less than dimension D6). In these embodiments, the distance between the end of the conductive structure 210d in the segment 204d and the edge of the active region 206 and / or the distance between the end of the conductive structure 210c in the segment 204c and the edge of the active region 206 can be included in the range of about 0.01 microns to about 1 micron. However, other values ​​for the ranges are within the scope of the disclosed embodiments.

[0054] The y-direction width of the conductive structure 210 (corresponding to dimension D7) may be included in a range of about 0.02 microns to about 1 micron. However, other values ​​for the range are within the scope of the disclosed embodiments.

[0055] Conductive structure 208a in segment 204a intersects conductive structure 210a in segment 204a. Conductive structure 210a may be continuous in segment 204a along the x-direction, and conductive structure 208a may be discontinuous in the y-direction because the continuity of conductive structure 208a is interrupted by conductive structure 210a. Conductive structure 208b in segment 204b intersects conductive structure 210b in segment 204b. Conductive structure 210b may be continuous in segment 204b along the x-direction, and conductive structure 208b may be discontinuous in the y-direction because the continuity of conductive structure 208b is interrupted by conductive structure 210b.

[0056] Conductive structure 208c in segment 204c intersects conductive structure 210c in segment 204c. Conductive structure 210c may be continuous in segment 204c along the x-direction, and conductive structure 208c may be discontinuous in the y-direction because the continuity of conductive structure 208c is interrupted by conductive structure 210c. Conductive structure 208d in segment 204d intersects conductive structure 210d in segment 204d. Conductive structure 210d may be continuous in segment 204d along the x-direction, and conductive structure 208d may be discontinuous in the y-direction because the continuity of conductive structure 208d is interrupted by conductive structure 210d.

[0057] The lengths of conductive structures 208c and 208d in segments 204c and 204d, respectively, are greater than the lengths of conductive structures 208a and 208b in segments 204a and 204b, respectively. The lengths of conductive structures 210a and 210b in segments 204a and 204b, respectively, are greater than the lengths of conductive structures 210c and 210d in segments 204c and 204d, respectively.

[0058] Segments 204a and 204c of guard ring structure 204 are connected by corner region 212a. Segments 204a and 204d of guard ring structure 204 are connected by corner region 212b. Segments 204b and 204c of guard ring structure 204 are connected by corner region 212c. Segments 204b and 204d of guard ring structure 204 are connected by corner region 212d.

[0059] Conductive structure 208c extends continuously through segment 204c and intersects one or more conductive structures 210a and 210b located in corner regions 212a and 212c, respectively. Conductive structure 208d extends continuously through segment 204d and intersects one or more conductive structures 210a and 210b located in corner regions 212b and 212d, respectively. Conductive structure 210a extends continuously through segment 204a and intersects one or more conductive structures 208c and 208d located in corner regions 212a and 212b, respectively. Conductive structure 210b extends continuously through segment 204b and intersects one or more conductive structures 208c and 208d located in corner regions 212c and 212d, respectively.

[0060] like Figure 2B As shown in , the interconnect structure 214 is included on the guard ring structure 204 around the integrated circuit 202. The interconnect structure 214 includes a metallization layer (e.g., M1 metallization layer) or a portion thereof of the semiconductor device 200. Charge carriers absorbed from the active area 206 in the guard ring structure 204 can be provided to the interconnect structure 214 through the conductive structures 208 and 210. The conductive mesh formed by the conductive structures 208 and 210 provides increased charge carrier absorption relative to only including the conductive structure 208 or only including the conductive structure 210 in the guard ring structure 204. The interconnect structure 214 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, as well as other examples of conductive materials.

[0061] The top view width (e.g., in the x-direction, in the y-direction) of the interconnect structure 214 (corresponding to dimension D8) can be less than the top view width (e.g., dimension D1, dimension D5) of the active area 206. In some embodiments, dimension D8 is included in the range of about 0.01 microns to about 4 microns. However, other values ​​for the range are within the scope of the disclosed embodiments. The interconnect structure 214 can be completely contained within the top view footprint of the active area 206. The distance between the edge of the interconnect structure 214 and the edge of the active area (corresponding to dimension D9) can be included in the range of about 0.01 microns to about 0.1 microns. However, other values ​​for the range are within the scope of the disclosed embodiments.

[0062] exist Figure 2B In the exemplary embodiment, conductive structure 208 is completely contained within the top view footprint of interconnect structure 214, and less than the entirety of conductive structure 210 is contained within the top view footprint of interconnect structure 214. In particular, ends of conductive structure 210 extend laterally outward from edges of interconnect structure 214.

[0063] Figure 2C and Figure 2D Shows Figure 2A and Figure 2B FIG. 2 is a cross-sectional view of an exemplary embodiment of a semiconductor device 200 . Figure 2C Shown along Figure 2B Cross-sectional view along line AA. Figure 2D Shown along Figure 2B Cross-sectional view along line BB in FIG.

[0064] like Figure 2C As shown in , in the semiconductor device 200, the conductive structure 210 is located above and / or on the active region 206 in the z-direction, and the interconnect structure 214 is located above and / or on the conductive structure 210 in the z-direction. The conductive structures 210 can be physically and / or electrically isolated from each other by the dielectric region 216. The dielectric region 216 may include an interlayer dielectric (ILD) layer and / or another type of dielectric layer of the semiconductor device 200. The z-direction height of the conductive structure 210 and the z-direction height of the dielectric region 216 can be approximately the same z-direction height, so that the conductive structure 210 and the dielectric region 216 are approximately coplanar.

[0065] The dielectric region 216 may include an oxide (eg, silicon oxide (SiO x ) and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorine silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric material. In some embodiments, the dielectric region 216 includes an extremely low dielectric constant (ELK) dielectric material having a dielectric constant of less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO x ), amorphous fluorinated carbon (aC x F y ), polyparaxylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbide (SiOC) polymer, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE) and / or porous silicon oxide (SiO x ), and other examples.

[0066] like Figure 2DAs shown in , in the semiconductor device 200, the conductive structure 208 is located above and / or on the active region 206 in the z-direction, and the interconnect structure 214 is located above and / or on the conductive structure 208 in the z-direction. The conductive structures 208 can be physically and / or electrically isolated from each other by the dielectric region 216. The z-direction height of the conductive structure 208 and the z-direction height of the dielectric region 216 can be approximately the same z-direction height, so that the conductive structure 208 and the dielectric region 216 are approximately coplanar. In addition, the z-direction height of the conductive structure 208 and the z-direction height of the conductive structure 210 can be approximately the same z-direction height, so that the conductive structure 208 and the conductive structure 210 are approximately coplanar.

[0067] Figure 2E A top view of another exemplary embodiment of a semiconductor device 200 is shown. Figure 2E The exemplary embodiment of the semiconductor device 200 shown in FIG. FIG. 2A to FIG. 2D , except that the edge of the interconnect structure 214 is substantially aligned with the edge of the active area 206. In other words, the top view width of the interconnect structure 214 (dimension D8) and the top view width of the active area 206 (dimension D1, dimension D5) are approximately equal. Figure 2E In the exemplary implementation of semiconductor device 200 shown in , conductive structure 208 and conductive structure 210 are completely contained within the top view footprint of interconnect structure 214 .

[0068] Figure 2F A top view of another exemplary embodiment of a semiconductor device 200 is shown. Figure 2F The exemplary embodiment of the semiconductor device 200 shown in FIG. FIG. 2A to FIG. 2D , except that a plurality of interconnect structures 214a and 214b are included on the guard ring structure 204. The interconnect structure 214a may be an external interconnect structure surrounding the interconnect structure 214b, and the interconnect structure 214b may be an internal interconnect structure. The interconnect structures 214a and 214b may be spaced apart so that the interconnect structures 214a and 214b are not in direct physical contact.

[0069] The interconnect structure 214a is located above a subset 218a of the conductive structures 208c in the segment 204c of the guard ring structure 204, and the interconnect structure 214b is located above another subset 218b of the conductive structures 208c in the segment 204c. The interconnect structures 214a and 214b extend across the conductive structures 210c in the segment 204c in the y-direction. In some embodiments, the conductive structures 210c in the segment 204c extend laterally outward in the x-direction beyond the interconnect structures 214a and 214b, such that portions of the conductive structures 210c are not located below the interconnect structures 214a and 214b.

[0070] The interconnect structure 214a is located above a subset 218d of the conductive structures 208d in the segment 204d of the guard ring structure 204, and the interconnect structure 214b is located above another subset 218c of the conductive structures 208d in the segment 204d. The interconnect structures 214a and 214b extend in the y-direction across the conductive structures 210d in the segment 204d. In some embodiments, the conductive structures 210d in the segment 204d extend laterally outward in the x-direction beyond the interconnect structures 214a and 214b, such that portions of the conductive structures 210d are not located below the interconnect structures 214a and 214b.

[0071] Interconnect structure 214a is located over a subset 220a of conductive structures 210a in segment 204a of guard ring structure 204, and interconnect structure 214b is located over another subset 220b of conductive structures 208a in segment 204a. Interconnect structures 214a and 214b extend in the x-direction across conductive structures 208a in segment 204a.

[0072] Interconnect structure 214a is located over a subset 220d of conductive structures 210b in segment 204b of guard ring structure 204, and interconnect structure 214b is located over another subset 220c of conductive structures 210b in segment 204b. Interconnect structures 214a and 214b extend in the x-direction across conductive structures 208b in segment 204b.

[0073] In the corner region 212a, the interconnect structure 214a is located over the subset 218a of the conductive structures 208c, over a portion of the subset 218b of the conductive structures 208c, over a subset 220a of the conductive structures 210a, and over a portion of the subset 220b of the conductive structures 210a. In the corner region 212a, the interconnect structure 214b is located over another portion of the subset 218b of the conductive structures 208c and over another portion of the subset 220b of the conductive structures 210d.

[0074] In the corner region 212b, the interconnect structure 214a is located over a subset 218d of the conductive structures 208d, over a portion of a subset 218c of the conductive structures 208d, over a subset 220a of the conductive structures 210a, and over a portion of a subset 220b of the conductive structures 210a. In the corner region 212b, the interconnect structure 214b is located over another portion of the subset 218c of the conductive structures 208d and over another portion of the subset 220b of the conductive structures 210d.

[0075] In corner region 212c, interconnect structure 214a is located over subset 218a of conductive structures 208c, over a portion of subset 218b of conductive structures 208c, over a portion of subset 220d of conductive structures 210b, and over a portion of subset 220c of conductive structures 210b. In corner region 212c, interconnect structure 214b is located over another portion of subset 218b of conductive structures 208c and over another portion of subset 220c of conductive structures 210b.

[0076] In the corner region 212d, the interconnect structure 214a is located over a subset 218d of the conductive structures 208d, over a portion of a subset 218c of the conductive structures 208d, over a subset 220d of the conductive structures 210b, and over a portion of a subset 220c of the conductive structures 210b. In the corner region 212d, the interconnect structure 214b is located over another portion of the subset 218c of the conductive structures 208d and over another portion of the subset 220c of the conductive structures 210b.

[0077] The interconnect structure 214a may have a top view width (corresponding to dimension D10) in the range of about 0.02 microns to about 1 micron in the x-direction and / or in the y-direction. However, other values ​​for the range are within the scope of the disclosed embodiments. The interconnect structure 214b may have a top view width (corresponding to dimension D11) in the range of about 0.02 microns to about 1 micron in the x-direction and / or in the y-direction. However, other values ​​for the range are within the scope of the disclosed embodiments. In some embodiments, dimension D10 and dimension D11 are approximately equal values. In some embodiments, dimension D10 and dimension D11 are different values.

[0078] In some embodiments, the distance between the outer edge of the active area 206 and the outer edge of the interconnect structure 214a (corresponding to dimension D12) can be included in the range of about 0.01 microns to about 0.1 microns. However, other values ​​for the range are within the scope of the embodiments of the present disclosure. In some embodiments, the distance between the inner edge of the active area 206 and the inner edge of the interconnect structure 214b (corresponding to dimension D13) can be included in the range of about 0.01 microns to about 0.1 microns. However, other values ​​for the range are within the scope of the embodiments of the present disclosure.

[0079] Figure 2G and Figure 2H Shows Figure 2F FIG. 2 is a cross-sectional view of an exemplary embodiment of a semiconductor device 200 . Figure 2G Shown along Figure 2F Cross-sectional view along line AA. Figure 2H Shown along Figure 2F Cross-sectional view along line BB in FIG.

[0080] like Figure 2G As shown in , interconnect structures 214a and 214b are located above and / or on at least a subset of conductive structures 210 in the z-direction. Figure 2H As shown in , the interconnect structures 214a and 214b are located above and / or on at least a subset (e.g., subset 218c, subset 218d) of the conductive structures 208 in the z-direction. The interconnect structures 214a and 214b can be physically and / or electrically isolated from each other by the dielectric region 222. The dielectric region 222 can include an ILD layer of the semiconductor device 200 and / or another type of dielectric layer. The z-direction height of the interconnect structures 214a and 214b and the z-direction height of the dielectric region 222 can be approximately the same z-direction height, so that the interconnect structures 214a and 214b and the dielectric region 222 are approximately coplanar.

[0081] The dielectric region 222 may include an oxide (eg, silicon oxide (SiO x ) and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorine silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric material. In some embodiments, dielectric region 222 includes an ELK dielectric material having a dielectric constant of less than about 2.5.

[0082] Fig.2I A top view of another exemplary embodiment of a semiconductor device 200 is shown. Fig.2I The exemplary embodiment of the semiconductor device 200 shown in FIG. FIG. 2A to FIG. 2D, except that one or more of the conductive structures 208 extend laterally outward beyond the edge of the active area 206, and / or one or more of the conductive structures 210 extend laterally outward beyond the edge of the active area 206. The conductive structures 208 can extend laterally outward beyond the edge of the active area 206 by a distance (corresponding to dimension D14) in the range of about 0.01 microns to about 1 micron. However, other values ​​for the range are within the scope of the disclosed embodiments. The conductive structures 210 can extend laterally outward beyond the edge of the active area 206 by a distance (corresponding to dimension D15) in the range of about 0.01 microns to about 1 micron. However, other values ​​for the range are within the scope of the disclosed embodiments.

[0083] As noted above, FIG. 2A to FIG. 2I Provided as an example. Other examples may be related to FIG. 2A to FIG. 2I The content described is different.

[0084] FIG. 3A to FIG. 3D 2 is a diagram of an exemplary embodiment 300 for forming a guard ring of the semiconductor device 200 described herein. The operations and / or techniques described in connection with the exemplary embodiment 300 may be performed to form a guard ring in connection with the semiconductor device 200. FIG. 2A to FIG. 2D , Figure 2E , Figures 2F to 2H and / or Fig.2I One or more of the exemplary embodiments of the semiconductor device 200 shown and described, as well as other examples. In some embodiments, in combination with FIG. 3A to FIG. 3D One or more of the described semiconductor processing operations may be performed using one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114. In some embodiments, in combination with FIG. 3A to FIG. 3D One or more of the described semiconductor processing operations may be performed using another semiconductor processing tool.

[0085] like Figure 3A As shown in FIG. 1 , an active region 206 of a guard ring structure 204 is provided around an integrated circuit 202 of a semiconductor device 200. In some embodiments, the active region 206 is provided as part of a substrate of the semiconductor device 200. In some embodiments, the active region 206 is formed by doping the substrate around the integrated circuit 202 with one or more types of dopants. For example, the ion implantation tool 112 can be used to implant dopants into the substrate around the integrated circuit 202 using an ion implantation technique and / or another type of technique to form the active region 206. In some embodiments, the deposition tool 102 can be used to implant dopants using a PVD technique, an ALD technique, a CVD technique, an epitaxial technique, a combination of the PVD technique, and / or the ALD technique. Figure 1Active region 206 may be deposited using another type of deposition technique as described and / or another suitable deposition technique.

[0086] like Figure 3B As shown in FIG. 2 , conductive structure 210 is formed over and / or on active region 206. Conductive structure 210 is formed such that conductive structure 210 is arranged in the y-direction and extends in the x-direction in semiconductor device 200.

[0087] The deposition tool 102 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 The conductive structure 210 may be deposited by another deposition technique described herein and / or another suitable deposition technique. The conductive structure 210 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the conductive structure 210 is deposited on the seed layer. In some embodiments, the planarization tool 110 may be used to planarize the conductive structure 210 after the conductive structure 210 is deposited.

[0088] In some embodiments, deposition tool 102 is used to form a dielectric layer, deposition tool 102, exposure tool 104, and development tool 106 are used to form a patterned mask layer on the dielectric layer, and etching tool 108 is used to etch the dielectric layer based on the patterned mask layer to form dielectric regions 216. Then, conductive structures 210 can be formed between dielectric regions 216.

[0089] like Figure 3C As shown in , conductive structure 208 is formed above and / or on active region 206. Conductive structure 208 is formed such that conductive structure 208 is arranged in the x-direction and extends in the y-direction in semiconductor device 200. In addition, conductive structure 208 is formed such that conductive structure 208 and conductive structure 210 intersect to form a conductive grid above active region 206.

[0090] The deposition tool 102 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 The conductive structure 208 may be deposited by another deposition technique described herein and / or another suitable deposition technique. The conductive structure 208 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the conductive structure 208 is deposited on the seed layer. In some embodiments, the planarization tool 110 may be used to planarize the conductive structure 208 after the conductive structure 208 is deposited.

[0091] In some embodiments, deposition tool 102 is used to form a dielectric layer, deposition tool 102, exposure tool 104, and development tool 106 are used to form a patterned mask layer on the dielectric layer, and etching tool 108 is used to etch the dielectric layer based on the patterned mask layer to form dielectric regions 216. Then, conductive structures 208 can be formed between dielectric regions 216.

[0092] Combination Figure 3B and Figure 3C The order of operations shown and described is an example, and another order of operations may be used to form conductive structures 208 and 210. For example, conductive structure 208 may be formed first, and then conductive structure 210 may be formed after conductive structure 208.

[0093] like Figure 3D As shown in , an interconnect structure 214 is formed above and / or on the guard ring structure 204, such that the interconnect structure 214 is physically and / or electrically coupled with the conductive structure 208 and the conductive structure 210. In some embodiments, a plurality of interconnect structures 214a and 214b are formed above and / or on the guard ring structure 204, such that the interconnect structures 214a and 214b are spaced apart from each other and do not physically contact each other.

[0094] The deposition tool 102 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 The interconnect structure 214 may be deposited using another deposition technique described herein and / or another suitable deposition technique. The interconnect structure 214 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the interconnect structure 214 is deposited on the seed layer. In some embodiments, the planarization tool 110 may be used to planarize the interconnect structure 214 after the interconnect structure 214 is deposited.

[0095] In some embodiments, deposition tool 102 is used to form a dielectric layer, deposition tool 102, exposure tool 104, and development tool 106 are used to form a patterned mask layer on the dielectric layer, and etching tool 108 is used to etch the dielectric layer based on the patterned mask layer to form dielectric regions 222. Then, interconnect structures 214 can be formed between dielectric regions 222.

[0096] As noted above, FIG. 3A to FIG. 3D Provided as an example. Other examples may be related to FIG. 3A to FIG. 3D The content described is different.

[0097] 4A to 4Fis a diagram of an exemplary implementation of a semiconductor device 400 described herein. The semiconductor device 400 includes examples of semiconductor devices such as a microprocessor, a memory device, an image sensor, and / or an RF device, among other examples.

[0098] Figure 4A and Figure 4B A top view of an exemplary embodiment of a semiconductor device 400 is shown. Figure 4A and Figure 4B The exemplary embodiment of the semiconductor device 400 shown in FIG. FIG. 2A to FIG. 2D , except that the edge of the exemplary embodiment of the semiconductor device 400 further includes a plurality of polysilicon structures 402. The polysilicon structures 402 can be formed during the same semiconductor processing operation that forms the gate structures (or dummy gate structures) of the transistors in the integrated circuit 202.

[0099] The polysilicon structure 402 may be included in the guard ring structure 204 to reduce, minimize, and / or prevent recesses in the guard ring structure 204. Recesses may occur in the dielectric layer in which the dielectric region 216 is formed. In particular, recesses may occur during a planarization operation (or CMP operation) to planarize the dielectric layer, and may occur in areas in the dielectric layer between gate structures of the semiconductor device 200. As the spacing between gate structures in the semiconductor device 200 increases, the likelihood and / or size of recesses in the dielectric layer increases. Including the polysilicon structure 402 in the guard ring structure 204 reduces the distance of the polysilicon structure between adjacent integrated circuits 202 of the semiconductor device 200, which may reduce the likelihood and / or size of recesses in the dielectric layer.

[0100] like Figure 4A and Figure 4B As shown in , polysilicon structure 402 extends in the y-direction and is arranged in the x-direction, similar to conductive structure 208. Polysilicon structure 402 and conductive structure 208 may be approximately parallel, and polysilicon structure 402 and conductive structure 210 may be approximately perpendicular. Polysilicon structure 402 may be formed of polysilicon material and / or another suitable material.

[0101] The polysilicon structure 402 includes one or more polysilicon structures 402a in the segment 204a of the guard ring structure 204, one or more polysilicon structures 402b in the segment 204b of the guard ring structure 204, one or more polysilicon structures 402c in the segment 204c of the guard ring structure 204, and / or one or more polysilicon structures 402d in the segment 204d of the guard ring structure 204. The polysilicon structure 402c may extend into the corner regions 212a and 212c, wherein the polysilicon structure 402c intersects the conductive structures 210a and 210b, respectively. The polysilicon structure 402d may extend into the corner regions 212b and 212d, wherein the polysilicon structure 402d intersects the conductive structures 210a and 210b, respectively.

[0102] The polysilicon structure 402a may be located between two or more of the conductive structures 208a and may intersect the conductive structure 210a. The polysilicon structure 402b may be located between two or more of the conductive structures 208b and may intersect the conductive structure 210b. The polysilicon structure 402c may be located between two or more of the conductive structures 208c and may intersect the conductive structure 210c. The polysilicon structure 402c in the segment 204c may be located between the subsets 218a and 218b of the conductive structures 208c. The polysilicon structure 402d in the segment 204d may be located between the subsets 218c and 218d of the conductive structures 208d and may intersect the conductive structure 210d. In some embodiments, the segment 204c includes a number of polysilicon structures 402c included in the range from 1 to 4. However, other values ​​for the range are within the scope of the disclosed embodiments. The polysilicon structure 402d may be located between two or more of the conductive structures 208d. In some embodiments, the segment 204d includes a number of polysilicon structures 402d included in a range from 1 to 4. However, other values ​​for the range are within the scope of the disclosed embodiments.

[0103] The y-direction length of the polysilicon structure 402a, and in some embodiments, the y-direction length of the polysilicon structure 402b (corresponding to dimension D16) can be less than the y-direction width (e.g., dimension D1) of the active region 206 in the segments 204a and 204b. Figure 4A and Figure 4B In the exemplary embodiment shown in , the polysilicon structures 402 a and / or 402 b are completely contained within the top view footprint of the active area 206 .

[0104] The distance between the end of polysilicon structure 402a and the edge of active area 206 in segment 204a (corresponding to dimension D17) and / or the distance between the end of polysilicon structure 402b and the edge of active area 206 in segment 204b may be included in a range of about 0.01 microns to about 1 micron. However, other values ​​for the ranges are within the scope of the disclosed embodiments.

[0105] Additionally and / or optionally, at least a subset of polysilicon structures 402a and / or at least a subset of polysilicon structures 402b may have a y-direction length approximately equal to the y-direction width of active region 206 in segments 204a and / or 204b (e.g., dimension D17 may be approximately equal to dimension D16).

[0106] The y-direction length of polysilicon structure 402c, and in some embodiments, the y-direction length of polysilicon structure 402d can be greater than the y-direction length of polysilicon structure 402a and / or 402b. The x-direction width (corresponding to dimension D18) of polysilicon structure 402 can be included in the range of about 0.01 microns to about 1 micron. However, other values ​​for the range are within the scope of the embodiments of the present disclosure.

[0107] like Figure 4B As shown in FIG. 1 , interconnect structure 214 is included over guard ring structure 204 surrounding integrated circuit 202 . Figure 4A and Figure 4B In the exemplary embodiment of FIG. 4 , the polysilicon structure 402 is completely contained within the top view footprint of the interconnect structure 214 .

[0108] Figure 4C and Figure 4D Shows Figure 4A and Figure 4B FIG. 4 is a cross-sectional view of an exemplary embodiment of a semiconductor device 400 in FIG. Figure 4C Shown along Figure 4B Cross-sectional view along line CC. Figure 4D Shown along Figure 4B Cross-sectional view along line DD in FIG.

[0109] like Figure 4C As shown in FIG. 4 , in a region of the semiconductor device 400 where the polysilicon structure 402 intersects with the conductive structure 210, the polysilicon structure 402 is located below the conductive structure 210. The conductive structure 210 wraps around the polysilicon structure 402 on at least three sides of the polysilicon structure 402. Figure 4D As shown in FIG. 4 , in areas of semiconductor device 400 where polysilicon structure 402 does not intersect conductive structure 210, polysilicon structure 402 is located below dielectric region 216. Dielectric region 216 wraps polysilicon structure 402 on at least three sides thereof.

[0110] like Figure 4C and Figure 4D As further shown in FIG. 4 , sidewall spacers 404 may be included on the sidewalls of the polysilicon structure 402. The sidewall spacers 404 may include one or more dielectric materials, such as silicon oxycarbide (SiOC), silicon nitride (Si x N y , such as Si 3 N 4 ) and / or another suitable dielectric layer. The sidewall spacers 404 may be formed during the same set of semiconductor processing operations that form gate spacers for gate structures of transistors in the integrated circuit 202 .

[0111] Figure 4E A top view of another exemplary embodiment of a semiconductor device 400 is shown. Figure 4E The exemplary embodiment of the semiconductor device 400 shown in FIG. 4A to 4D The exemplary embodiment of the semiconductor device 400 shown in FIG. 4 is different in that a plurality of interconnect structures 214 a and 214 b are included over the guard ring structure 204 .

[0112] The interconnect structure 214a is located over a portion of the polysilicon structure 402a in the segment 204a of the guard ring structure 204, and the interconnect structure 214b is located over other portions of the polysilicon structure 402a in the segment 204a of the guard ring structure 204. The interconnect structure 214a is located over a portion of the polysilicon structure 402b in the segment 204b of the guard ring structure 204, and the interconnect structure 214b is located over other portions of the polysilicon structure 402b in the segment 204b of the guard ring structure 204. The polysilicon structure 402c may be located between the interconnect structures 214a and 214b in the segment 204c of the guard ring structure 204. The polysilicon structure 402d may be located between the interconnect structures 214a and 214b in the segment 204d of the guard ring structure 204. The interconnect structure 214a may be located over a portion of the polysilicon structure 402c in the corner regions 212a and 212c of the guard ring structure 204. The interconnect structure 214 a may be located over portions of the polysilicon structure 402 d in the corner regions 212 b and 212 d of the guard ring structure 204 .

[0113] Figure 4F A top view of another exemplary embodiment of a semiconductor device 400 is shown. Figure 4F The exemplary embodiment of the semiconductor device 400 shown in FIG. 4A to 4D, except that one or more of the polysilicon structures 402, one or more of the conductive structures 208, and / or one or more of the conductive structures 210 extend laterally outward beyond the edge of the active area 206. The polysilicon structures 402 may extend laterally outward beyond the edge of the active area 206 by a distance (corresponding to dimension D19) in the range of about 0.01 microns to about 1 micron. However, other values ​​for the ranges are within the scope of the disclosed embodiments.

[0114] As noted above, 4A to 4F Provided as an example. Other examples may be related to 4A to 4F The content described is different.

[0115] FIG. 5A to FIG. 5E 4 is a diagram of an exemplary embodiment 500 for forming a guard ring of a semiconductor device 400 described herein. The operations and / or techniques described in connection with the exemplary embodiment 500 may be performed to form a guard ring in connection with the semiconductor device 400. 4A to 4D , Figure 4E and / or Figure 4F One or more of the exemplary embodiments of the semiconductor device 400 shown and described, as well as other examples. In some embodiments, in combination with FIG. 5A to FIG. 5E One or more of the described semiconductor processing operations may be performed using one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114. In some embodiments, in combination with FIG. 5A to FIG. 5E One or more of the described semiconductor processing operations may be performed using another semiconductor processing tool.

[0116] like Figure 5A As shown in FIG. 4 , an active region 206 of a guard ring structure 204 is provided around an integrated circuit 202 of a semiconductor device 400. In some embodiments, the active region 206 is provided as part of a substrate of the semiconductor device 400. In some embodiments, the active region 206 is formed by doping the substrate around the integrated circuit 202 with one or more types of dopants. For example, the ion implantation tool 112 can be used to implant dopants into the substrate around the integrated circuit 202 using an ion implantation technique and / or another type of technique to form the active region 206. In some embodiments, the deposition tool 102 can be used to implant dopants using a PVD technique, an ALD technique, a CVD technique, an epitaxial technique, a combination of the PVD technique, and / or the ALD technique. Figure 1 Active region 206 may be deposited using another type of deposition technique as described and / or another suitable deposition technique.

[0117] like Figure 5BAs shown in FIG. 4 , polysilicon structure 402 is formed above and / or on active region 206. Polysilicon structure 402 is formed such that polysilicon structure 402 is arranged in the y direction and extends in the y direction in semiconductor device 400. Deposition tool 102 may be used to deposit polysilicon using CVD technology, PVD technology, ALD technology, or a combination of the above. Figure 1 The polysilicon structure 402 may be deposited using another deposition technique as described and / or another suitable deposition technique.

[0118] like Figure 5C As shown in FIG. 4 , conductive structure 210 is formed over and / or on active region 206 and over and / or on polysilicon structure 402. Conductive structure 210 is formed such that conductive structure 210 is arranged in the y-direction in semiconductor device 400 and extends in the x-direction.

[0119] The deposition tool 102 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 The conductive structure 210 may be deposited by another deposition technique described herein and / or another suitable deposition technique. The conductive structure 210 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the conductive structure 210 is deposited on the seed layer. In some embodiments, the planarization tool 110 may be used to planarize the conductive structure 210 after the conductive structure 210 is deposited.

[0120] In some embodiments, deposition tool 102 is used to form a dielectric layer, deposition tool 102, exposure tool 104, and development tool 106 are used to form a patterned mask layer on the dielectric layer, and etching tool 108 is used to etch the dielectric layer based on the patterned mask layer to form dielectric regions 216. Then, conductive structures 210 can be formed between dielectric regions 216.

[0121] like Figure 5D As shown in , conductive structures 208 are formed over and / or on active regions 206. Conductive structures 208 are formed such that conductive structures 208 are arranged in the x-direction and extend in the y-direction in semiconductor device 400. Furthermore, conductive structures 208 are formed such that conductive structures 208 and conductive structures 210 intersect to form a conductive grid over active regions 206. At least a subset of conductive structures 208 are formed adjacent to opposite sides of one or more polysilicon structures 402.

[0122] The deposition tool 102 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1The conductive structure 208 may be deposited by another deposition technique described herein and / or another suitable deposition technique. The conductive structure 208 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the conductive structure 208 is deposited on the seed layer. In some embodiments, the planarization tool 110 may be used to planarize the conductive structure 208 after the conductive structure 208 is deposited.

[0123] In some embodiments, deposition tool 102 is used to form a dielectric layer, deposition tool 102, exposure tool 104, and development tool 106 are used to form a patterned mask layer on the dielectric layer, and etching tool 108 is used to etch the dielectric layer based on the patterned mask layer to form dielectric regions 216. Then, conductive structures 208 can be formed between dielectric regions 216.

[0124] like Figure 5E As shown in , an interconnect structure 214 is formed above and / or on the guard ring structure 204, such that the interconnect structure 214 is physically and / or electrically coupled with the conductive structure 208 and the conductive structure 210. In some embodiments, a plurality of interconnect structures 214a and 214b are formed above and / or on the guard ring structure 204, such that the interconnect structures 214a and 214b are spaced apart from each other and do not physically contact each other.

[0125] The deposition tool 102 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 The interconnect structure 214 may be deposited using another deposition technique described herein and / or another suitable deposition technique. The interconnect structure 214 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the interconnect structure 214 is deposited on the seed layer. In some embodiments, the planarization tool 110 may be used to planarize the interconnect structure 214 after the interconnect structure 214 is deposited.

[0126] In some embodiments, deposition tool 102 is used to form a dielectric layer, deposition tool 102, exposure tool 104, and development tool 106 are used to form a patterned mask layer on the dielectric layer, and etching tool 108 is used to etch the dielectric layer based on the patterned mask layer to form dielectric regions 222. Then, interconnect structures 214 can be formed between dielectric regions 222.

[0127] As noted above, FIG. 5A to FIG. 5E Provided as an example. Other examples may be related to FIG. 5A to FIG. 5E The content described is different.

[0128] Figure 6is a diagram of an exemplary implementation of a semiconductor device 600 described herein. The semiconductor device 600 includes examples of semiconductor devices such as a microprocessor, a memory device, an image sensor, and / or an RF device, among other examples. Figure 6 A top view of an exemplary embodiment of a semiconductor device 600 is shown. Figure 6 The exemplary embodiment of the semiconductor device 600 shown in FIG. FIG. 2A to FIG. 2I , except that semiconductor device 600 includes multiple guard ring structures around integrated circuit 202. For example, semiconductor device 600 includes a guard ring structure 204-1 (e.g., an inner guard ring) around integrated circuit 202 and a guard ring structure 204-2 (e.g., an outer guard ring) around guard ring structure 204-1.

[0129] Including multiple guard ring structures around integrated circuit 202 provides additional charge carrier absorption and, therefore, increased latch-up protection around integrated circuit 202. However, the single guard ring implementation described herein can be formed using less complex semiconductor manufacturing processes and, therefore, consumes fewer semiconductor manufacturing resources.

[0130] like Figure 6 As shown in FIG. 1 , the guard ring structure 204-1 includes a plurality of segments 204a, 204b, 204c, and / or 204d and a plurality of corner regions 212a, 212b, 212c, and / or 212d. The guard ring structure 204-1 includes an active region 206a, a plurality of conductive structures 208 arranged in the x-direction and extending in the y-direction (e.g., conductive structures 208a, 208b, 208c, and / or 208d), and a plurality of conductive structures 210 arranged in the y-direction and extending in the x-direction (e.g., conductive structures 210a, 210b, 210c, and / or 210d). The guard ring structure 204-1 additionally includes a plurality of conductive structures 210a, 210b, 210c, and / or 210d that are not shown in FIG. 1 for the sake of clarity. Figure 6 The guard ring structure 204-1 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b). FIG. 2A to FIG. 2I The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0131] like Figure 6As further shown in FIG. 1 , the guard ring structure 204-2 includes a plurality of segments 204e, 204f, 204g, and / or 204h and a plurality of corner regions 212e, 212f, 212g, and / or 212h. The guard ring structure 204-2 includes an active region 206b, a plurality of conductive structures 208 arranged in the x-direction and extending in the y-direction (e.g., conductive structures 208e, 208f, 208g, and / or 208h), and a plurality of conductive structures 210 arranged in the y-direction and extending in the x-direction (e.g., conductive structures 210e, 210f, 210g, and / or 210h). The guard ring structure 204-2 additionally includes a plurality of conductive structures 210a, 210b, 210c, and 210d, which are not shown in FIG. 1 for clarity. Figure 6 The guard ring structure 204-2 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. FIG. 2A to FIG. 2I The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0132] In some embodiments, the guard ring structures 204-1 and 204-2 are arranged in a similar configuration. For example, the guard ring structures 204-1 and 204-2 can each be arranged according to FIG. 2A to FIG. 2D In some embodiments, the guard ring structures 204-1 and 204-2 are arranged in different configurations. For example, the guard ring structure 204-1 can be arranged according to the exemplary embodiment shown in FIG. Figure 2E The exemplary embodiment shown in FIG. 2 is arranged, and the guard ring structure 204-2 can be arranged according to Figures 2F to 2H The exemplary embodiment shown in FIG.

[0133] As noted above, Figure 6 Provided as an example. Other examples may be related to Figure 6 The content described is different.

[0134] Figure 7 is a diagram of an exemplary implementation of a semiconductor device 700 described herein. The semiconductor device 700 includes examples of semiconductor devices such as a microprocessor, a memory device, an image sensor, and / or an RF device, among other examples. Figure 7 A top view of an exemplary embodiment of a semiconductor device 700 is shown. Figure 7 The exemplary embodiment of the semiconductor device 700 shown in FIG. 4A to 4F, except that semiconductor device 700 includes multiple guard ring structures around integrated circuit 202. For example, semiconductor device 700 includes guard ring structure 204-1 (e.g., inner guard ring) around integrated circuit 202 and guard ring structure 204-2 (e.g., outer guard ring) around guard ring structure 204-1. Guard ring structure 204-1 and / or guard ring structure 204-2 may also include multiple polysilicon structures 402.

[0135] Including multiple guard ring structures around integrated circuit 202 provides additional charge carrier absorption around integrated circuit 202, and thus provides increased latch-up protection. However, the single guard ring implementation described herein can be formed using a less complex semiconductor manufacturing process, and thus consumes fewer semiconductor manufacturing resources. In addition, the polysilicon structure 402 in guard ring structure 204-1 and / or guard ring structure 204-2 can reduce the possibility of recesses in the dielectric layer above guard ring structure 204-1 and / or above guard ring structure 204-2.

[0136] like Figure 7 As shown in , the guard ring structure 204-1 includes a plurality of segments 204a, 204b, 204c and / or 204d and a plurality of corner regions 212a, 212b, 212c and / or 212d. The guard ring structure 204-1 includes an active region 206a, a plurality of conductive structures 208 arranged in the x-direction and extending in the y-direction (e.g., conductive structures 208a, 208b, 208c and / or 208d), and a plurality of conductive structures 210 arranged in the y-direction and extending in the x-direction (e.g., conductive structures 210a, 210b, 210c and / or 210d). The guard ring structure 204-1 includes a plurality of polysilicon structures 402 arranged in the x-direction and extending in the y-direction (e.g., polysilicon structures 402a, 402b, 402c and / or 402d). The guard ring structure 204-1 additionally includes a plurality of conductive structures 402a, 402b, 402c and / or 402d that are not shown in the figure for the purpose of clarity. Figure 7 The guard ring structure 204-1 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b). 4A to 4F The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0137] like Figure 7As further shown in FIG. 1 , the guard ring structure 204-2 includes a plurality of segments 204e, 204f, 204g, and / or 204h and a plurality of corner regions 212e, 212f, 212g, and / or 212h. The guard ring structure 204-2 includes an active region 206b, a plurality of conductive structures 208 arranged in the x-direction and extending in the y-direction (e.g., conductive structures 208e, 208f, 208g, and / or 208h), and a plurality of conductive structures 210 arranged in the y-direction and extending in the x-direction (e.g., conductive structures 210e, 210f, 210g, and / or 210h). The guard ring structure 204-2 includes a plurality of polysilicon structures 402 arranged in the x-direction and extending in the y-direction (e.g., polysilicon structures 402e, 402f, 402g, and / or 402h). The guard ring structure 204-2 additionally includes a plurality of conductive structures 402a, 402b, 402c, 402d, and / or 402d that are not shown in FIG. 1 for purposes of clarity. Figure 7 The guard ring structure 204-2 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. 4A to 4F The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0138] In some embodiments, the guard ring structures 204-1 and 204-2 are arranged in a similar configuration. For example, the guard ring structures 204-1 and 204-2 can each be arranged according to 4A to 4D In some embodiments, the guard ring structures 204-1 and 204-2 are arranged in different configurations. For example, the guard ring structure 204-1 can be arranged according to the exemplary embodiment shown in FIG. Figure 4E The exemplary embodiment shown in FIG. 2 is arranged, and the guard ring structure 204-2 can be arranged according to Figure 4F The exemplary embodiment shown in FIG.

[0139] As noted above, Figure 7 Provided as an example. Other examples may be related to Figure 7 The content described is different.

[0140] Figure 8 8 is a diagram of an exemplary implementation of a semiconductor device 800 described herein. The semiconductor device 800 includes examples of semiconductor devices such as a microprocessor, a memory device, an image sensor, and / or an RF device, among other examples. Figure 8 A top view of an exemplary embodiment of a semiconductor device 800 is shown. Figure 8 The exemplary embodiment of the semiconductor device 800 shown in FIG. 8 is similar to FIG. 2A to FIG. 2I, except that the semiconductor device 800 includes a plurality of integrated circuits 202a and 202b. A corresponding guard ring structure 204 is included around each of the integrated circuits 202a and 202b. For example, the semiconductor device 800 includes a guard ring structure 204-1 around the integrated circuit 202a and a guard ring structure 204-2 around the integrated circuit 202b.

[0141] Including a plurality of guard ring structures around each of the integrated circuits 202a and 202b provides charge carrier absorption for complementary metal oxide semiconductor (CMOS) circuits of the semiconductor device 800. For example, the integrated circuit 202a may include a p-type metal oxide semiconductor (PMOS) integrated circuit (e.g., an integrated circuit including a PMOS transistor), and the integrated circuit 202b may include an n-type metal oxide semiconductor (NMOS) integrated circuit (e.g., an integrated circuit including an NMOS transistor). The guard ring structures 204-1 and 204-2 absorb charge carriers around the integrated circuits 202a and 202b, which prevents or reduces the possibility of a low impedance path being formed between the integrated circuits 202a and 202b through the substrate of the semiconductor device 800. Thus, the guard ring structures 204-1 and 204-2 prevent or reduce the possibility of an electrical short between the integrated circuits 202a and 202b (which may otherwise produce latch-up of the integrated circuits 202a and 202b). Furthermore, the conductive mesh formed by the conductive structures 208 and 210 in the guard ring structures 204-1 and 204-2 provides increased charge carrier absorption (e.g., due to increased surface area coverage of the active region 206 by the conductive structures 208 and 210) without increasing the distance (corresponding to the dimension D20) between the integrated circuits 202a and 202b. Thus, the guard ring structures 204-1 and 204-2 can maintain or reduce the size of the semiconductor device 800.

[0142] like Figure 8 As shown in FIG. 1 , the guard ring structure 204-1 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-1, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-1. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The guard ring structure 204-1 additionally includes a plurality of conductive structures 210 that are not shown in FIG. 1 for the purpose of clarity. Figure 8 The guard ring structure 204-1 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b). FIG. 2A to FIG. 2I The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0143] The guard ring structure 204-2 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-2, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-2. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The guard ring structure 204-2 additionally includes a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-2. Figure 8 The guard ring structure 204-2 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. FIG. 2A to FIG. 2I The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0144] In some embodiments, the guard ring structures 204-1 and 204-2 are arranged in a similar configuration. For example, the guard ring structures 204-1 and 204-2 can each be arranged according to FIG. 2A to FIG. 2D In some embodiments, the guard ring structures 204-1 and 204-2 are arranged in different configurations. For example, the guard ring structure 204-1 can be arranged according to the exemplary embodiment shown in FIG. FIG. 2A to FIG. 2D The exemplary embodiment shown in FIG. 2 is arranged, and the guard ring structure 204-2 can be arranged according to Fig.2I The exemplary embodiment shown in FIG.

[0145] As noted above, Figure 8 Provided as an example. Other examples may be related to Figure 8 The content described is different.

[0146] Fig. 9 is a diagram of an exemplary implementation of a semiconductor device 900 described herein. The semiconductor device 900 includes examples of semiconductor devices such as a microprocessor, a memory device, an image sensor, and / or an RF device, among other examples. Fig. 9 A top view of an exemplary embodiment of a semiconductor device 900 is shown. Fig. 9 The exemplary embodiment of the semiconductor device 900 shown in FIG. 4A to 4F , except that the semiconductor device 900 includes a plurality of integrated circuits 202a and 202b. A corresponding guard ring structure 204 is included around each of the integrated circuits 202a and 202b. For example, the semiconductor device 900 includes a guard ring structure 204-1 around the integrated circuit 202a and a guard ring structure 204-2 around the integrated circuit 202b. The guard ring structure 204-1 and / or the guard ring structure 204-2 may also include a plurality of polysilicon structures 402.

[0147] Including multiple guard ring structures around each of the integrated circuits 202a and 202b provides charge carrier absorption for the CMOS circuits of the semiconductor device 900. For example, the integrated circuit 202a may include a PMOS integrated circuit, and the integrated circuit 202b may include an NMOS integrated circuit. The guard ring structures 204-1 and 204-2 absorb charge carriers around the integrated circuits 202a and 202b, which prevents or reduces the possibility of forming a low impedance path between the integrated circuits 202a and 202b through the substrate of the semiconductor device 900. Therefore, the guard ring structures 204-1 and 204-2 prevent or reduce the possibility of an electrical short between the integrated circuits 202a and 202b (which may otherwise produce latch-up of the integrated circuits 202a and 202b). Furthermore, the conductive mesh formed by the conductive structures 208 and 210 in the guard ring structures 204-1 and 204-2 provides increased charge carrier absorption without increasing the distance between the integrated circuits 202a and 202b (e.g., due to the increased surface area coverage of the active area 206 by the conductive structures 208 and 210). Thus, the guard ring structures 204-1 and 204-2 can maintain or reduce the size of the semiconductor device 900. Furthermore, the polysilicon structure 402 in the guard ring structure 204-1 and / or in the guard ring structure 204-2 can reduce the likelihood of recesses in the dielectric layer above the guard ring structure 204-1 and / or above the guard ring structure 204-2.

[0148] like Fig. 9 As shown in FIG. 1 , the guard ring structure 204-1 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-1, a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-1, and a plurality of polysilicon structures 402 on the active region 206 of the guard ring structure 204-1. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The plurality of polysilicon structures 402 are arranged in the x-direction and extend in the y-direction. The guard ring structure 204-1 additionally includes a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-1, which are not shown in FIG. 1 for the purpose of clarity. Fig. 9 The guard ring structure 204-1 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b). 4A to 4F The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0149] The guard ring structure 204-2 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-2, a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-2, and a plurality of polysilicon structures 402 on the active region 206 of the guard ring structure 204-2. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The plurality of polysilicon structures 402 are arranged in the x-direction and extend in the y-direction. The guard ring structure 204-2 additionally includes a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-2, which are not shown in the figure for the sake of clarity. Fig. 9 The guard ring structure 204-2 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. 4A to 4F The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0150] In some embodiments, the guard ring structures 204-1 and 204-2 are arranged in a similar configuration. For example, the guard ring structures 204-1 and 204-2 can each be arranged according to 4A to 4D In some embodiments, the guard ring structures 204-1 and 204-2 are arranged in different configurations. For example, the guard ring structure 204-1 can be arranged according to the exemplary embodiment shown in FIG. Figure 4E The exemplary embodiment shown in FIG. 2 is arranged, and the guard ring structure 204-2 can be arranged according to Figure 4F The exemplary embodiment shown in FIG.

[0151] As noted above, Fig. 9 Provided as an example. Other examples may be related to Fig. 9 For example, the protection ring structure 204-1 may be based on FIG. 2A to FIG. 2I The exemplary embodiment shown in FIG. 2 is arranged, and the guard ring structure 204-2 can be arranged according to 4A to 4F As another example, the guard ring structure 204-2 may be arranged according to the exemplary embodiment shown in FIG. FIG. 2A to FIG. 2I The exemplary embodiment shown in FIG. 2 is arranged, and the guard ring structure 204-1 can be arranged according to 4A to 4F The exemplary embodiment shown in FIG.

[0152] Fig.10 1 is a diagram of an exemplary implementation of a semiconductor device 1000 described herein. The semiconductor device 1000 includes examples of semiconductor devices such as a microprocessor, a memory device, an image sensor, and / or an RF device, among other examples. Fig.10 A top view of an exemplary embodiment of a semiconductor device 1000 is shown. Fig.10The exemplary embodiment of the semiconductor device 1000 shown in FIG. 1 is similar to Figure 8 , except that the semiconductor device 1000 includes a plurality of guard ring structures around one or more of the integrated circuits 202a and / or 202b, similar to Figure 6 . For example, semiconductor device 1000 may include a guard ring structure 204-1 (e.g., an inner guard ring) around integrated circuit 202a and a guard ring structure 204-2 (e.g., an outer guard ring) around guard ring structure 204-1. As another example, semiconductor device 1000 may include a guard ring structure 204-3 (e.g., an inner guard ring) around integrated circuit 202b and a guard ring structure 204-4 (e.g., an outer guard ring) around guard ring structure 204-3. In some embodiments, guard ring structures 204-1 and 204-2 are included around integrated circuit 202a, and guard ring structures 204-3 and 204-4 are included around integrated circuit 202b.

[0153] Including a plurality of guard ring structures around the integrated circuits 202 a and / or 202 b provides additional charge carrier absorption around the integrated circuits 202 a and / or 202 b and, therefore, provides enhanced latch-up protection for the semiconductor device 1000 .

[0154] like Fig.10 As shown in FIG. 1 , the guard ring structure 204-1 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-1, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-1. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The guard ring structure 204-1 additionally includes a plurality of conductive structures 210 that are not shown in FIG. 1 for the purpose of clarity. Fig.10 The guard ring structure 204-1 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b). FIG. 2A to FIG. 2I The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0155] The guard ring structure 204-2 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-2, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-2. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The guard ring structure 204-2 additionally includes a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-2. Fig.10The guard ring structure 204-2 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. FIG. 2A to FIG. 2I The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0156] The guard ring structure 204-3 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-3, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-3. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The guard ring structure 204-3 additionally includes a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-3. Fig.10 The guard ring structure 204-3 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. FIG. 2A to FIG. 2I The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0157] The guard ring structure 204-4 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-4, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-4. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The guard ring structure 204-4 additionally includes a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-4. Fig.10 The guard ring structure 204-4 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. FIG. 2A to FIG. 2I The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0158] In some embodiments, two or more of the guard ring structures 204-1, 204-2, 204-3, and / or 204-4 are arranged in a similar configuration. For example, two or more of the guard ring structures 204-1, 204-2, 204-3, and / or 204-4 may each be arranged according to FIG. 2A to FIG. 2D In some embodiments, two or more of the guard ring structures 204-1, 204-2, 204-3, and / or 204-4 may be arranged in different configurations. For example, the guard ring structure 204-1 may be arranged according to the exemplary embodiment shown in FIG. Figure 2E The exemplary embodiment shown in FIG. 2 is arranged, and the guard ring structure 204-3 can be arranged according to Figures 2F to 2H The exemplary embodiment shown in FIG.

[0159] As noted above, Fig.10 Provided as an example. Other examples may be related to Fig.10 The content described is different.

[0160] Fig.11 1 is a diagram of an exemplary implementation of a semiconductor device 1100 described herein. The semiconductor device 1100 includes examples of semiconductor devices such as a microprocessor, a memory device, an image sensor, and / or an RF device, among other examples. Fig.11 A top view of an exemplary embodiment of a semiconductor device 1100 is shown. Fig.11 The exemplary embodiment of the semiconductor device 1100 shown in FIG. 1 is similar to Figure 7 , except that the semiconductor device 1100 includes a plurality of guard ring structures around the integrated circuit 202a and / or around the integrated circuit 202b. For example, the semiconductor device 1100 may include a guard ring structure 204-1 (e.g., an inner guard ring) around the integrated circuit 202a and a guard ring structure 204-2 (e.g., an outer guard ring) around the guard ring structure 204-1. As another example, the semiconductor device 1100 may include a guard ring structure 204-3 (e.g., an inner guard ring) around the integrated circuit 202b and a guard ring structure 204-4 (e.g., an outer guard ring) around the guard ring structure 204-3. In some embodiments, the guard ring structures 204-1 and 204-2 are included around the integrated circuit 202a, and the guard ring structures 204-3 and 204-4 are included around the integrated circuit 202b. One or more of the guard ring structures 204-1, 204-2, 204-3, and / or 204-4 may also include a plurality of polysilicon structures 402.

[0161] Including multiple guard ring structures around the integrated circuits 202a and / or 202b provides additional charge carrier absorption around the integrated circuits 202a and / or 202b and, therefore, provides enhanced latch-up protection for the semiconductor device 1100. Additionally, the polysilicon structures 402 in the guard ring structures 204-1, 204-2, 204-3, and / or 204-4 may reduce the likelihood of recesses in the dielectric layer above the guard ring structures 204-1, 204-2, 204-3, and / or 204-4.

[0162] like Fig.11As shown in FIG. 1 , the guard ring structure 204-1 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-1, a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-1, and a plurality of polysilicon structures 402. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The plurality of polysilicon structures 402 are arranged in the x-direction and extend in the y-direction. The guard ring structure 204-1 additionally includes a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-1, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-1. Fig.11 The guard ring structure 204-1 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b). 4A to 4F The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0163] like Fig.11 As shown in FIG. 1 , the guard ring structure 204-2 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-2, a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-2, and a plurality of polysilicon structures 402. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The plurality of polysilicon structures 402 are arranged in the x-direction and extend in the y-direction. The guard ring structure 204-2 additionally includes a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-2, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-2. Fig.11 The guard ring structure 204-2 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. 4A to 4F The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0164] like Fig.11 As shown in FIG. 1 , the guard ring structure 204-3 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-3, a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-3, and a plurality of polysilicon structures 402. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The plurality of polysilicon structures 402 are arranged in the x-direction and extend in the y-direction. The guard ring structure 204-3 additionally includes a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-3, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-3. Fig.11 The guard ring structure 204-3 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. 4A to 4FThe embodiment may be arranged in any one of the exemplary embodiments shown in .

[0165] like Fig.11 As shown in FIG. 1 , the guard ring structure 204-4 includes an active region 206, a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-4, a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-4, and a plurality of polysilicon structures 402. The plurality of conductive structures 208 are arranged in the x-direction and extend in the y-direction. The plurality of conductive structures 210 are arranged in the y-direction and extend in the x-direction. The plurality of polysilicon structures 402 are arranged in the x-direction and extend in the y-direction. The guard ring structure 204-4 additionally includes a plurality of conductive structures 208 on the active region 206 of the guard ring structure 204-4, and a plurality of conductive structures 210 on the active region 206 of the guard ring structure 204-4. Fig.11 The guard ring structure 204-4 and / or the interconnect structure 214 may be configured to provide a plurality of interconnect structures (eg, the interconnect structure 214, the interconnect structure 214a, and the interconnect structure 214b) as shown in FIG. 4A to 4F The embodiment may be arranged in any one of the exemplary embodiments shown in .

[0166] In some embodiments, two or more of the guard ring structures 204-1, 204-2, 204-3, and / or 204-4 are arranged in a similar configuration. For example, two or more of the guard ring structures 204-1, 204-2, 204-3, and / or 204-4 may each be arranged according to 4A to 4D In some embodiments, two or more of the guard ring structures 204-1, 204-2, 204-3, and / or 204-4 are arranged in different configurations. For example, the guard ring structure 204-2 may be arranged according to the exemplary embodiment shown in FIG. Figure 4F The exemplary embodiment shown in FIG. 2 is arranged, and the guard ring structure 204-4 can be arranged according to Figure 7 The exemplary embodiment shown in FIG.

[0167] As noted above, Fig.11 Provided as an example. Other examples may be related to Fig.11 For example, a single guard ring structure 204 may be included around the integrated circuit 202a, and multiple guard ring structures 204-3 and 204-4 may be included around the integrated circuit 202b, wherein according to FIG. 2A to FIG. 2I , 4A to 4F , Figure 6 and / or Figure 7In the exemplary embodiment of the present invention, the guard ring structures 204, 204-3 and 204-4 have the same configuration or different configurations. As another example, a single guard ring structure 204 can be included around the integrated circuit 202b, and multiple guard ring structures 204-1 and 204-2 can be included around the integrated circuit 202a, wherein according to FIG. 2A to FIG. 2I , 4A to 4F , Figure 6 and / or Figure 7 In the exemplary embodiment of the present invention, the guard ring structures 204, 204-1 and 204-2 have the same configuration or different configurations. As another example, multiple guard ring structures 204-1 and 204-2 can be included around the integrated circuit 202a, and multiple guard ring structures 204-3 and 204-4 can be included around the integrated circuit 202d, wherein according to FIG. 2A to FIG. 2I , 4A to 4F , Figure 6 and / or Figure 7 In the exemplary embodiment, the guard ring structures 204-1, 204-2, 204-3, and 204-4 have the same configuration or different configurations.

[0168] Fig.12 1 is a diagram of exemplary components of a device 1200 described herein. In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may include one or more devices 1200 and / or one or more components of the device 1200. Fig.12 As shown in , device 1200 may include a bus 1210 , a processor 1220 , a memory 1230 , an input component 1240 , an output component 1250 , and / or a communication component 1260 .

[0169] The bus 1210 may include one or more components that enable wired and / or wireless communication between components of the device 1200. The bus 1210 may include: Fig.12 Two or more components of the computer system 1210 are coupled together, such as via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 1210 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 1220 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 1220 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1220 may include one or more processors that can be programmed to implement one or more operations or processes described elsewhere herein.

[0170] The memory 1230 may include volatile and / or non-volatile memory. For example, the memory 1230 may include a random access memory (RAM), a read-only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 1230 may include an internal memory (e.g., RAM, ROM, or hard drive) and / or a removable memory (e.g., removable via a universal serial bus connection). The memory 1230 may be a non-temporary computer-readable medium. The memory 1230 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 1200. In some embodiments, the memory 1230 may include one or more memories such as coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1220) via bus 1210. The communicatively coupled between the processor 1220 and the memory 1230 may enable the processor 1220 to read and / or process information stored in the memory 1230 and / or store information in the memory 1230.

[0171] Input assembly 1240 can enable device 1200 to receive input, such as user input and / or sensed input. For example, input assembly 1240 can include touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope and / or actuator. Output assembly 1250 can enable device 1200 to provide output, such as via display, speaker and / or light emitting diode. Communication assembly 1260 can enable device 1200 to communicate with other devices via wired connection and / or wireless connection. For example, communication assembly 1260 can include receiver, transmitter, transceiver, modem, network interface card and / or antenna.

[0172] Device 1200 may implement one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1230) may store an instruction group (e.g., one or more instructions or codes) executed by processor 1220. Processor 1220 may execute the instruction group to implement one or more operations or processes described herein. In some embodiments, execution of the instruction group by one or more processors 1220 causes one or more processors 1220 and / or device 1200 to implement one or more operations or processes described herein. In some embodiments, hard-wired circuits may be used instead of instructions or in combination with instructions to implement one or more operations or processes described herein. Additionally or alternatively, processor 1220 may be configured to implement one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardware circuits and software.

[0173] Fig.12 The number and arrangement of components shown in FIG. 1 are provided as examples. Device 1200 may include Fig.12 Additional components, fewer components, different components, or differently arranged components than those shown in . Additionally or alternatively, a component group (eg, one or more components) of device 1200 may implement one or more functions described as being implemented by another component group of device 1200.

[0174] Fig.13 13 is a flow chart of an exemplary process 1300 associated with forming a semiconductor device described herein. In some embodiments, one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114) are used to implement Fig.13 Additionally or alternatively, Fig.13 One or more process blocks of may be implemented using one or more components of the device 1200 , such as the processor 1220 , the memory 1230 , the input component 1240 , the output component 1250 , and / or the communication component 1260 .

[0175] like Fig.13 As shown in FIG. 1 , process 1300 may include providing an active region around an integrated circuit device of a semiconductor device (block 1310). For example, one or more of semiconductor processing tools 102-112 and / or wafer / die transport tool 114 may be used to provide an active region (e.g., active region 206, 206a, 206b, 206c, and / or 206d) around an integrated circuit (e.g., integrated circuit 202, 202a, and / or 202b) of a semiconductor device (e.g., semiconductor device 200, 400, 600, 700, 800, 900, and / or 1000).

[0176] like Fig.13 As further shown in FIG. 1 , process 1300 may include forming a first plurality of conductive structures extending in a first direction of the semiconductor device and arranged in a second direction approximately perpendicular to the first direction in the semiconductor device over the active region (block 1320). For example, one or more of semiconductor processing tools 102-112 may be used to form a first plurality of conductive structures (e.g., conductive structures 208, 208a, 208b, 208c, 208d, 208e, 208f, 208g, and / or 208h) extending in a first direction (e.g., y-direction) of the semiconductor device and arranged in a second direction (e.g., x-direction) approximately perpendicular to the first direction in the semiconductor device over the active region, as described herein.

[0177] like Fig.13 As further shown in FIG. 1 , process 1300 may include forming a second plurality of conductive structures extending in a second direction and arranged in a first direction over the active area (block 1330). For example, one or more of semiconductor processing tools 102-112 may be used to form a second plurality of conductive structures (e.g., conductive structures 210, 210a, 210b, 210c, 210d, 210e, 210f, 210g, and / or 210h) extending in a second direction and arranged in a first direction over the active area, as described herein. In some embodiments, the first plurality of conductive structures and the second plurality of conductive structures intersect to form a guard ring structure (e.g., guard ring structures 204, 204-1, 204-2, 204-3, and / or 204-4) over the active area.

[0178] like Fig.13 As further shown in FIG. 1 , process 1300 may include forming one or more interconnect structures over the guard ring structure (block 1340). For example, one or more of semiconductor processing tools 102-112 may be used to form one or more interconnect structures (e.g., interconnect structures 214, 214a, and / or 214b) over the guard ring structure, as described herein.

[0179] Process 1300 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0180] In a first embodiment, the active region is a first active region of a semiconductor device (e.g., active region 206a), the guard ring structure is a first guard ring structure of a semiconductor device (e.g., guard ring structure 204-1, guard ring structure 204-3), and process 1300 includes: providing a second active region (e.g., active region 206b) around the first active region; forming a third plurality of conductive structures (e.g., conductive structures 208e, 208f, 208g, and / or 208h) extending in the first direction and arranged in the second direction over the second active region; and forming a fourth plurality of conductive structures (e.g., conductive structures 210e, 210f, 210g, and / or 210h) extending in the second direction and arranged in the first direction over the second active region, wherein the third plurality of conductive structures and the fourth plurality of conductive structures intersect to form a second guard ring structure (e.g., guard ring structure 204-2, guard ring structure 204-4) over the second active region.

[0181] In a second embodiment, alone or in combination with the first embodiment, process 1300 includes: forming a first plurality of polysilicon structures (e.g., polysilicon structure 402a, polysilicon structure 402b) above a first active region, the first plurality of polysilicon structures extending in a first direction; and forming a second plurality of polysilicon structures (e.g., polysilicon structure 402a, polysilicon structure 402b) above a second active region, the second plurality of polysilicon structures extending in the first direction.

[0182] In a third embodiment, alone or in combination with one or more of the first and second embodiments, the integrated circuit is a first integrated circuit of a semiconductor device (e.g., integrated circuit 202a), the active region is a first active region of the semiconductor device (e.g., active region 206a), the guard ring structure is a first guard ring structure of the semiconductor device (e.g., guard ring structure 204-1, guard ring structure 204-3), and the process 1300 includes: providing a second active region (e.g., active region 206a and active region 206b) around a second integrated circuit (e.g., integrated circuit 202b) adjacent to the first integrated circuit; forming a third plurality of conductive structures (e.g., conductive structure 208) extending in the first direction and arranged in the second direction over the second active region; and forming a fourth plurality of conductive structures (e.g., conductive structure 210) extending in the second direction and arranged in the first direction over the second active region, wherein the third plurality of conductive structures and the fourth plurality of conductive structures intersect to form a second guard ring structure (e.g., guard ring structure 204-2, guard ring structure 204-4) over the second active region.

[0183] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 1300 includes: forming a first plurality of polysilicon structures (e.g., polysilicon structure 402a, polysilicon structure 402b) above a first active region, wherein the first plurality of polysilicon structures extend in a first direction; and forming a second plurality of polysilicon structures (e.g., polysilicon structure 402a, polysilicon structure 402b) above a second active region, wherein the second plurality of polysilicon structures extend in the first direction.

[0184] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 1300 includes: providing a third active region (e.g., active region 206b) around the first active region; forming a fifth plurality of conductive structures (e.g., conductive structure 208) extending in the first direction and arranged in the second direction over the third active region; and forming a sixth plurality of conductive structures (e.g., conductive structure 210) extending in the second direction and arranged in the first direction over the second active region, wherein the fifth plurality of conductive structures and the sixth plurality of conductive structures intersect to form a third guard ring structure (e.g., guard ring structure 204-2) over the first active region.

[0185] Although Fig.13 An exemplary block diagram of process 1300 is shown, but in some embodiments, process 1300 includes Fig.13 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in process 1300. Additionally or alternatively, two or more of the blocks of process 1300 may be implemented in parallel.

[0186] In this manner, in a top view of the semiconductor device, the semiconductor device includes an integrated circuit and one or more guard rings around the integrated circuit. At least one of the one or more guard rings includes an active area in the substrate, a first plurality of elongated conductive structures extending in a first direction in a top view of the semiconductor device and arranged in a second direction in a top view of the semiconductor device, and a second plurality of elongated conductive structures extending in a second direction and arranged in the first direction. The combination of the first plurality of elongated conductive structures and the second plurality of elongated conductive structures forms a conductive grid over the active area and provides increased coverage of a surface area of ​​the active area relative to only the first plurality of elongated conductive structures or only the second plurality of elongated conductive structures. The combination of the first plurality of elongated conductive structures and the second plurality of elongated conductive structures enables coverage of the surface area to be increased in both the first direction and the second direction within a footprint or boundary of an interconnect structure over the first plurality of conductive structures and the second plurality of conductive structures. In this manner, the first plurality of conductive structures and the second plurality of conductive structures enable a high amount of charge carrier absorption to be achieved in the semiconductor device (which can reduce the likelihood of latch-up in the semiconductor device) while enabling a short distance or spacing between adjacent integrated circuits in the semiconductor device.

[0187] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes an integrated circuit. In a top view of the semiconductor device, the semiconductor device includes a guard ring structure surrounding the integrated circuit. The guard ring structure includes: an active area; a first plurality of conductive structures located above the active area, wherein the first plurality of conductive structures extend in a first direction in the semiconductor device and are arranged in a second direction approximately perpendicular to the first direction in the semiconductor device; a second plurality of conductive structures located above the active area, wherein the second plurality of conductive structures extend in a second direction and are arranged in the first direction. The semiconductor device includes an interconnect structure located above the guard ring structure.

[0188] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes an integrated circuit. In a top view of the semiconductor device, the semiconductor device includes a guard ring structure surrounding the integrated circuit. The guard ring structure includes: a first plurality of conductive structures, wherein the first plurality of conductive structures extend in a first direction in the semiconductor device and are arranged in a second direction approximately perpendicular to the first direction in the semiconductor device. The guard ring structure includes: a second plurality of conductive structures, located above the active area, wherein the second plurality of conductive structures extend in the second direction and are arranged in the first direction, and the first length of the first subset of the second plurality of conductive structures is greater than the second length of the second subset of the second plurality of conductive structures. The guard ring structure includes: a plurality of polysilicon structures extending in the first direction, wherein each of the polysilicon structures is located between adjacent pairs of the first plurality of conductive structures. The semiconductor device includes: a first interconnect structure located above the guard ring structure, wherein at least a first subset of the first plurality of conductive structures is located within a footprint of the first interconnect structure. The semiconductor device includes: a second interconnect structure located above the guard ring structure, wherein at least a second subset of the first plurality of conductive structures is located within a footprint of the second interconnect structure.

[0189] As described in more detail above, some embodiments described herein provide methods. The method includes: providing an active area around an integrated circuit of a semiconductor device. The method includes: forming a first plurality of conductive structures extending in a first direction of the semiconductor device and arranged in a second direction approximately perpendicular to the first direction in the semiconductor device above the active area. The method includes: forming a second plurality of conductive structures extending in a second direction and arranged in the first direction above the active area, wherein the first plurality of conductive structures and the second plurality of conductive structures intersect to form a guard ring structure above the active area. The method includes: forming one or more interconnect structures above the guard ring structure.

[0190] Some embodiments of the present application provide a semiconductor device, including: an integrated circuit; a guard ring structure surrounding the integrated circuit in a top view of the semiconductor device, wherein the guard ring structure includes: an active area; a first plurality of conductive structures located above the active area, wherein the first plurality of conductive structures extend in a first direction in the semiconductor device and are arranged in a second direction approximately perpendicular to the first direction in the semiconductor device; and a second plurality of conductive structures located above the active area, wherein the second plurality of conductive structures extend in the second direction and are arranged in the first direction; and an interconnect structure located above the guard ring structure.

[0191] In some embodiments, the entirety of the first plurality of conductive structures is located within the footprint of the interconnect structure; and wherein portions of the second plurality of conductive structures extend laterally outward from the interconnect structure. In some embodiments, the first plurality of conductive structures extend laterally outward from the active area. In some embodiments, the entirety of the first plurality of conductive structures and the entirety of the second plurality of conductive structures are located within the footprint of the interconnect structure. In some embodiments, the second plurality of conductive structures extend laterally outward from the active area. In some embodiments, the guard ring structure further comprises: a polysilicon structure located above the active area, wherein the polysilicon structure extends in a first direction and is located between a first subset of the first plurality of conductive structures and a second subset of the first plurality of conductive structures. In some embodiments, the polysilicon structure extends laterally outward from the active area.

[0192] Some further embodiments of the present application provide a semiconductor device, comprising: an integrated circuit; a guard ring structure surrounding the integrated circuit in a top view of the semiconductor device, wherein the guard ring structure comprises: a first plurality of conductive structures, wherein the first plurality of conductive structures extend in a first direction in the semiconductor device and are arranged in a second direction approximately perpendicular to the first direction in the semiconductor device; a second plurality of conductive structures, wherein the second plurality of conductive structures extend in the second direction and are arranged in the first direction, and wherein a first length of a first subset of the second plurality of conductive structures is greater than a second length of a second subset of the second plurality of conductive structures; and a plurality of polysilicon structures extending in the first direction, wherein each of the polysilicon structures is located between adjacent pairs of the first plurality of conductive structures; a first interconnect structure located above the guard ring structure, wherein at least a first subset of the first plurality of conductive structures is located within a coverage area of ​​the first interconnect structure; and a second interconnect structure located above the guard ring structure, wherein at least a second subset of the first plurality of conductive structures is located within a coverage area of ​​the second interconnect structure.

[0193] In some embodiments, at least a third subset of the first plurality of conductive structures is located below the first interconnect structure and the second interconnect structure and extends between the first interconnect structure and the second interconnect structure. In some embodiments, a third length of the third subset of the first plurality of conductive structures is greater than a fourth length of a fourth subset of the first plurality of conductive structures. In some embodiments, portions of the plurality of polysilicon structures are located below the second plurality of conductive structures. In some embodiments, the guard ring structure further comprises an active region; and wherein the plurality of polysilicon structures, the first plurality of conductive structures, and the second plurality of conductive structures are located above the active region. In some embodiments, at least one of the plurality of polysilicon structures is located between the first interconnect structure and the second interconnect structure. In some embodiments, at least one of the plurality of polysilicon structures is located below the first interconnect structure and the second interconnect structure and extends between the first interconnect structure and the second interconnect structure.

[0194] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: providing an active region around an integrated circuit of the semiconductor device; forming a first plurality of conductive structures extending in a first direction of the semiconductor device and arranged in a second direction approximately perpendicular to the first direction in the semiconductor device over the active region; forming a second plurality of conductive structures extending in the second direction and arranged in the first direction over the active region, wherein the first plurality of conductive structures and the second plurality of conductive structures intersect to form a guard ring structure over the active region; and forming one or more interconnect structures over the guard ring structure.

[0195] In some embodiments, the active region is a first active region of the semiconductor device; wherein the guard ring structure is a first guard ring structure of the semiconductor device; and wherein the method further comprises: providing a second active region around the first active region; forming a third plurality of conductive structures extending in the first direction and arranged in the second direction over the second active region; and forming a fourth plurality of conductive structures extending in the second direction and arranged in the first direction over the second active region, wherein the third plurality of conductive structures and the fourth plurality of conductive structures intersect to form a second guard ring structure over the second active region. In some embodiments, the method further comprises: forming a first plurality of polysilicon structures over the first active region, wherein the first plurality of polysilicon structures extend in the first direction; and forming a second plurality of polysilicon structures over the second active region, wherein the second plurality of polysilicon structures extend in the first direction. In some embodiments, the integrated circuit is a first integrated circuit of the semiconductor device; wherein the active region is a first active region of the semiconductor device; wherein the guard ring structure is a first guard ring structure of the semiconductor device; and wherein the method further comprises: providing a second active region around a second integrated circuit adjacent to the first integrated circuit; forming a third plurality of conductive structures extending in the first direction and arranged in the second direction over the second active region; and forming a fourth plurality of conductive structures extending in the second direction and arranged in the first direction over the second active region, wherein the third plurality of conductive structures and the fourth plurality of conductive structures intersect to form a second guard ring structure over the second active region. In some embodiments, the method further comprises: forming a first plurality of polysilicon structures over the first active region, wherein the first plurality of polysilicon structures extend in the first direction; and forming a second plurality of polysilicon structures over the second active region, wherein the second plurality of polysilicon structures extend in the first direction. In some embodiments, the method also includes: providing a third active region around the first active region; forming a fifth plurality of conductive structures extending in the first direction and arranged in the second direction above the third active region; and forming a sixth plurality of conductive structures extending in the second direction and arranged in the first direction above the second active region, wherein the fifth plurality of conductive structures and the sixth plurality of conductive structures intersect to form a third guard ring structure above the first active region.

[0196] The terms "approximately" and "substantially" may refer to a value of a given amount or magnitude that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that in view of the embodiments of the present disclosure, the terms "approximately" and "substantially" may refer to a percentage of a value of a given amount.

[0197] As used herein, "satisfying a threshold" may (depending on the context) refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc.

[0198] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: integrated circuit; a guard ring structure surrounding the integrated circuit in a top view of the semiconductor device, Wherein, the protection ring structure comprises: Active area; a first plurality of conductive structures located above the active area, wherein the first plurality of conductive structures extend in a first direction in the semiconductor device and are arranged in a second direction approximately perpendicular to the first direction in the semiconductor device; and a second plurality of conductive structures located above the active area, wherein the second plurality of conductive structures extend in the second direction and are arranged in the first direction; and The interconnection structure is located on the guard ring structure.

2. The semiconductor device according to claim 1, wherein the entirety of the first plurality of conductive structures being within a footprint of the interconnect structure; and Parts of the second plurality of conductive structures extend laterally outward from the interconnect structure.

3. The semiconductor device according to claim 1, wherein The first plurality of conductive structures extend laterally outward from the active area.

4. The semiconductor device according to claim 1, wherein: An entirety of the first plurality of conductive structures and an entirety of the second plurality of conductive structures are located within a footprint of the interconnect structure.

5. The semiconductor device according to claim 1, wherein The second plurality of conductive structures extend laterally outward from the active area.

6. The semiconductor device according to claim 1, wherein The protection ring structure further includes: A polysilicon structure located above the active area, The polysilicon structure extends in a first direction and is located between a first subset of the first plurality of conductive structures and a second subset of the first plurality of conductive structures.

7. The semiconductor device according to claim 6, wherein: The polysilicon structure extends laterally outward from the active area.

8. A semiconductor device comprising: integrated circuit; a guard ring structure surrounding the integrated circuit in a top view of the semiconductor device, Wherein, the protection ring structure comprises: a first plurality of conductive structures, wherein the first plurality of conductive structures extend in a first direction in the semiconductor device and are arranged in a second direction in the semiconductor device that is approximately perpendicular to the first direction; a second plurality of conductive structures, wherein the second plurality of conductive structures extend in the second direction and are arranged in the first direction, and wherein a first length of a first subset of the second plurality of conductive structures is greater than a second length of a second subset of the second plurality of conductive structures; and a plurality of polysilicon structures extending in the first direction, wherein each of the polysilicon structures is located between adjacent pairs of the first plurality of conductive structures; a first interconnect structure, located on the guard ring structure, wherein at least a first subset of the first plurality of conductive structures is located within a footprint of the first interconnect structure; and a second interconnect structure, located on the guard ring structure, Wherein, at least a second subset of the first plurality of conductive structures is located within a footprint of the second interconnect structure.

9. The semiconductor device according to claim 8, wherein: At least a third subset of the first plurality of conductive structures is located below and extends between the first interconnect structure and the second interconnect structure.

10. A method of forming a semiconductor device, comprising: Providing an active area around an integrated circuit of a semiconductor device; forming a first plurality of conductive structures extending in a first direction of the semiconductor device over the active region and arranged in a second direction approximately perpendicular to the first direction in the semiconductor device; forming a second plurality of conductive structures extending in the second direction and arranged in the first direction over the active region, wherein the first plurality of conductive structures intersect with the second plurality of conductive structures to form a guard ring structure above the active area; as well as One or more interconnect structures are formed over the guard ring structure.

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