A TBC battery structure with self-formed gap region and a PVD method for preparing the same

Abstract

The present invention relates to the field of photovoltaic technology, and discloses a TBC battery structure with a self-formed gap region and a PVD method for preparing the same, comprising a silicon substrate, wherein the back surface of the silicon substrate is provided with a p+ region and an n+ region, wherein the height positions of the p+ region and the n+ region on the back surface of the silicon substrate are staggered to form a step, and a gap region is formed at the step sidewall connecting the p+ region and the n+ region, wherein the gap region is used to electrically isolate the p+ region and the n+ region; the p+ region comprises a first tunneling oxide layer, a p‑poly layer, a second tunneling oxide layer and an n‑poly layer sequentially deposited on the silicon substrate; and the n+ region comprises a second tunneling oxide layer and an n‑poly layer sequentially deposited on the silicon substrate. The present invention utilizes p‑poly to superimpose n‑poly to form a tunneling junction, which can directly avoid using a second laser to remove the n‑poly on the p‑poly, avoids damage to the surface crystalline silicon layer by the laser, and simultaneously reduces a laser grooving process, thereby greatly reducing the production cost.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a TBC battery structure with a self-formed gap region and a PVD method for preparing the same. Background Art

[0002] Back contact (BC) crystalline silicon solar cells were proposed by Lammert and Schwartz in 1970. Due to its unique structural design, the p+ emitter, n+ back field and metal grid lines are all located on the back of the cell, and there is no grid line shading on the front, which can achieve higher conversion efficiency. Due to the extremely complex process flow, especially the cumbersome production of the back electrode, at least two laser high-precision patterning is required to open the groove and etch the mask to prepare the PN area cross structure to isolate the PN area. In addition, the metal grid lines and laser patterns need to be overprinted with high precision, which requires a high level of equipment stability, resulting in high equipment investment costs, high difficulty in process debugging, and low product yield, and large-scale production has not been achieved.

[0003] At present, domestic laser technology has achieved laser patterning slotting, but because the laser is used to open the mold on the battery surface, the pulse width is compressed to nanoseconds (ns, 10 -9 ) level, a plasma microscopic explosion produces a plasma jet, the film material on the battery surface will expand and sublimate, the mold material will be taken away, and the shock wave generated by this energy will also cause certain damage to the crystalline silicon surface under the battery film structure, increasing the recombination and reducing the battery conversion efficiency. Therefore, the fewer times of laser grooving, the less damage, but it is difficult to avoid at least 2 times of laser grooving in the current process.

[0004] In addition, in the back contact battery, if the n-region is connected to the heavily doped p-region, leakage will occur. Therefore, a gap region needs to be set between the two to separate the n-region from the p-region. However, the gap region design of the current battery structure is parallel to the n-region and the p-region. In the preparation of the gap region, since it is difficult to achieve precise control of the laser, even if a smaller energy spot size (such as (20-30um) is used, light leakage will occur in the area outside the laser patterning, thereby forming a complex alkali-resistant polymer. Therefore, it is difficult to clean out a high-precision and narrow gap region width, which will inevitably occupy too wide a width on the back surface, resulting in current loss.

[0005] In view of this, this application is hereby filed. Summary of the invention

[0006] The problem with the prior art is that the preparation of back-contact batteries currently requires at least two laser groovings, which causes certain damage to the crystalline silicon surface under the battery membrane structure, resulting in a decrease in the battery conversion efficiency. In order to solve the above problem, the present invention provides a TBC battery structure with a self-formed gap area and a PVD preparation method thereof, forming a longitudinal gap area, which not only ensures the effectiveness of electrical isolation but also can minimize the width of the gap area. At the same time, PVD single-sided collimated deposition of n-poly is used to complete the superposition of p-poly and n-poly to form a tunnel junction to replace the existing PN junction for selectively collecting holes, which can directly avoid the use of a second laser to remove the n-poly on the p-poly, thereby avoiding laser damage to the surface crystalline silicon layer; in addition, one second laser grooving production process is reduced, which also greatly reduces the production cost.

[0007] The present invention is achieved through the following technical solutions:

[0008] In a first aspect, the present invention provides a TBC battery structure with a self-formed gap region, comprising a silicon substrate, wherein a p+ region and an n+ region are arranged on the back surface of the silicon substrate, wherein the height positions of the p+ region and the n+ region on the back surface of the silicon substrate are staggered to form a step, and a gap region is formed at the side wall of the step connecting the p+ region and the n+ region, wherein the gap region is used to electrically isolate the p+ region from the n+ region;

[0009] The p+ region includes a first tunneling oxide layer, a p-poly layer, a second tunneling oxide layer and an n-poly layer sequentially deposited on a silicon substrate;

[0010] The n+ region comprises a second tunnel oxide layer and an n-poly layer deposited sequentially on a silicon substrate.

[0011] Firstly, the present invention arranges the gap region with the p+ region and the n+ region in a vertical manner, so that the p+ region and the n+ region are separated and staggered in the vertical height, which greatly narrows the lateral width of the gap region. It can not only maximize the lateral width of the p+ region and the n+ region, increase the carrier collection area, and reduce the collection difficulty, but also accurately isolate the p+ region and the n+ region, thereby reducing the leakage of the battery.

[0012] Secondly, the p+ region of the present invention includes a first tunneling oxide layer, a p-poly layer, a second tunneling oxide layer and an n-poly layer deposited in sequence. Through the structural arrangement of the p-poly layer, the second tunneling oxide layer and the n-poly layer, a tunneling junction can be formed, thereby replacing the existing PN junction structure to achieve selective collection of holes. Therefore, when preparing such a structure, there is no need to use a second laser to perform localized treatment on the PSG film layer due to the need to remove the n-poly layer deposited on the p-poly layer as in the conventional process, thereby reducing the second laser grooving process.

[0013] In addition, due to the high energy of the pulsed laser, complex polymer residues are easily generated on the surface of the crystalline silicon after laser treatment, which are highly resistant to alkali corrosion and difficult to clean. Therefore, the present invention does not require a second laser treatment, nor does it require cleaning of the n-poly layer deposited in the p+ region. It only requires direct cleaning and removal of the entire PSG film layer, thus avoiding the problem of increased difficulty in wet cleaning after laser treatment.

[0014] In a specific embodiment, AL is sequentially deposited on the n-poly layer of the p+ region and the n+ region and on the gap region. 2 O 3 film layer and SiNx film layer.

[0015] In a specific embodiment, the back surface of the silicon substrate in the gap region and the n+ region are both suede structures.

[0016] In a specific embodiment, the p+ region is provided with a first metal electrode, the n+ region is provided with a second metal electrode, the first metal electrode contacts the n-poly layer of the p+ region, and the second metal electrode contacts the n-poly layer of the n+ region.

[0017] In a specific embodiment, the front surface of the silicon substrate is sequentially deposited with AL 2 O 3 film layer and SiNx film layer.

[0018] In a specific embodiment, the silicon substrate is an N-type silicon substrate, and the height of the p+ region on the back surface of the silicon substrate is higher than the height of the n+ region on the back surface of the silicon substrate.

[0019] In a second aspect, the present invention provides a PVD method for preparing a TBC battery structure with a self-formed gap region, comprising the following steps:

[0020] S1, double-sided polishing of an N-type single crystal silicon wafer;

[0021] S2, selecting one side of an N-type single crystal silicon wafer as the back surface, and sequentially depositing a first tunnel oxide layer and an intrinsic poly film layer;

[0022] S3, depositing and advancing a boron source on the intrinsic poly film layer to obtain a p-poly layer, and growing a BSG film layer on the surface of the p-poly layer;

[0023] S4, using laser to perform patterning on the back surface, and partially removing the BSG film layer on the back surface, that is, removing the BSG film layer in the reserved n-poly deposition area;

[0024] S5, wet cleaning, so that the n-poly deposition area reserved on the back surface is exposed to the surface of the silicon substrate. Since the p-poly area has a BSG film layer as a mask layer, the wet cleaning will not corrode the p-poly area;

[0025] S6, using alkaline washing to corrode the silicon substrate in the reserved n-poly deposition area and form a step between the silicon substrate in the p-poly area; then using acid washing to remove the BSG film layer on the surface of the p-poly area;

[0026] S7, depositing a second tunnel oxide layer on the entire back side, and then depositing a layer of in-situ doped n-type amorphous silicon film layer by PVD deposition method, using PVD single-sided collimated deposition, no bypass plating is formed in the gap area located on the longitudinal surface, so the step formed by wet cleaning combined with PVD single-sided collimated deposition can automatically form a gap area with electrical isolation;

[0027] S8, performing a phosphorus source advancement and amorphous silicon crystallization process to obtain an n-poly layer and a PSG film layer;

[0028] S9, cleaning and removing the PSG film layer on the back surface;

[0029] S10, depositing a layer of AL on the front surface and the back surface of the structure obtained in step S9 2 O 3 Membrane layer;

[0030] S11, AL of the front surface and the back surface obtained in step S10 2 O 3 A layer of SiNx film is deposited on each of the film layers;

[0031] S12, the metal electrode is manufactured on the back surface of the structure obtained in step S11 by screen printing and drying and sintering, so that the first metal electrode and the second metal electrode are in contact with the n-poly layer.

[0032] In the preparation method of the present invention, a laser is used to perform a laser grooving on the p-poly area, and then alkaline washing is performed to form steps, and then the amorphous silicon film layer is deposited by a PVD single-sided collimated deposition method, and no plating is formed in the gap area located on the longitudinal surface. Therefore, the steps formed by wet cleaning combined with the PVD single-sided collimated deposition can automatically form a gap area with electrical isolation, and the width can be controlled to be less than 10um.

[0033] At present, the conventional gap area is formed in step S9, specifically, the PSG film layer is partially removed by laser, that is, the PSG layer in the p-poly area and the PSG layer in the reserved gap area are removed, and only the PSG film layer in the reserved n-poly deposition area is retained, and then the p-poly area and the n-poly layer in the reserved gap area are cleaned, and then the corresponding passivation film and anti-reflection film are deposited. Therefore, it is difficult for the laser to accurately control the width of the reserved gap area.

[0034] In the preparation method of the present invention, the width and depth of the gap area can be accurately controlled by controlling the alkaline washing corrosion rate. At the same time, the structural position of the gap area is changed from a horizontal to a vertical setting, which can reduce the space occupancy of the gap area while ensuring the effectiveness of electrical isolation.

[0035] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0036] 1. A TBC battery structure with a self-formed gap region and a PVD preparation method thereof provided in an embodiment of the present invention, wherein the gap region is arranged in a vertical manner with the p+ region and the n+ region, so that the p+ region and the n+ region are separated and staggered in the vertical height, which greatly narrows the width of the gap region in the horizontal direction, and can not only maximize the width of the p+ region and the n+ region in the horizontal direction, but also increase the carrier collection area, reduce the collection difficulty, and improve the short-circuit current;

[0037] 2. A TBC battery structure with a self-formed gap region and a PVD preparation method thereof provided in an embodiment of the present invention can form a tunnel junction through the structural arrangement of a p-poly layer, a second tunnel oxide layer and an n-poly layer, thereby replacing the existing PN junction structure to achieve selective collection of holes. Therefore, during preparation, it is not necessary to use a second laser to perform localized treatment on the PSG film layer due to the need to remove the n-poly layer deposited on the p-poly layer as in conventional processes, thereby reducing the second laser grooving process;

[0038] 3. A TBC battery structure with a self-formed gap region and a PVD preparation method thereof provided in an embodiment of the present invention uses a laser to perform a laser grooving on a p-poly layer, then performs alkaline washing to form a step, and then uses a PVD single-sided collimated deposition method to deposit an n-poly layer to complete the p-poly layer superposition of the n-poly layer to form a tunnel junction, and no plating is formed in the gap region located on the longitudinal surface. Therefore, the step formed by wet cleaning combined with PVD single-sided collimated deposition can automatically form a gap region with electrical isolation, and the width can be controlled to be less than 10um;

[0039] 4. A TBC battery structure with a self-formed gap region and a PVD preparation method thereof provided in an embodiment of the present invention can accurately control the width and depth of the gap region by controlling the alkali washing corrosion rate to ensure the effectiveness of electrical isolation and reduce the space occupation of the gap region;

[0040] 5. The TBC battery structure with a self-formed gap area and the PVD preparation method thereof provided in the embodiment of the present invention only need to use the laser once, which reduces the investment cost of the laser equipment and has the advantage of low cost. At the same time, it reduces one laser process, reduces the difficulty of process development and wet cleaning after laser, and makes the process flow simpler, shortens the production cycle, improves production efficiency, and is more suitable for large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A schematic diagram of the battery structure obtained in step S1 of the TBC battery preparation process provided in an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of the battery structure obtained in step S2 of the TBC battery preparation process provided in an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of the battery structure obtained in step S3 of the TBC battery preparation process provided in an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of the battery structure obtained in step S4 of the TBC battery preparation process provided in an embodiment of the present invention;

[0046] Figure 5A schematic diagram of the battery structure obtained in step S5 of the TBC battery preparation process provided in an embodiment of the present invention;

[0047] Figure 6 A schematic diagram of the battery structure obtained in step S6 of the TBC battery preparation process provided in an embodiment of the present invention;

[0048] Figure 7 A schematic diagram of the battery structure obtained in step S7 of the TBC battery preparation process provided in an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of the battery structure obtained in step S8 in the TBC battery preparation process provided in an embodiment of the present invention;

[0050] Fig. 9 A schematic diagram of the battery structure obtained in step S9 of the TBC battery preparation process provided in an embodiment of the present invention;

[0051] Fig.10 A schematic diagram of the battery structure obtained in step S10 in the TBC battery preparation process provided in an embodiment of the present invention;

[0052] Fig.11 A schematic diagram of the battery structure obtained in step S11 of the TBC battery preparation process provided in an embodiment of the present invention;

[0053] Fig.12 A schematic diagram of the TBC battery structure provided by an embodiment of the present invention;

[0054] Fig.13 Schematic diagram of the existing TBC battery structure.

[0055] Drawings and parts markings:

[0056] 1-silicon substrate, 2-first tunneling oxide layer, 3-p-poly layer, 4-BSG mask layer, 5-second tunneling oxide layer, 6-n-poly layer, 7-PSG layer, 8-AL 2 O 3 Film layer, 9-SiNx film layer, 10-first metal electrode, 11-second metal electrode. DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0058] In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent to one of ordinary skill in the art that these specific details need not be employed to practice the present invention. In other embodiments, in order to avoid obscuring the present invention, well-known materials or methods are not specifically described.

[0059] Throughout the specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "one embodiment," "an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily all refer to the same embodiment or example. In addition, particular features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combination and / or subcombination. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0060] In the description of the present invention, the directions or positional relationships indicated by terms such as “front”, “rear”, “left”, “right”, “up”, “down”, “vertical”, “horizontal”, “high”, “low”, “inside” and “outside” are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the scope of protection of the present invention.

[0061] At present, domestic laser technology has achieved laser patterning slotting, but because the laser is used to open the mold on the battery surface, the pulse width is compressed to nanoseconds (ns, 10 -9 ) level, a plasma microscopic explosion produces a plasma jet, the film material on the battery surface will expand and sublimate, the mold material will be taken away, and the shock wave generated by this energy will also cause certain damage to the crystalline silicon surface under the battery film structure, increasing the recombination and reducing the battery conversion efficiency. Therefore, the fewer times of laser grooving, the less damage, but it is difficult to avoid at least 2 times of laser grooving in the current process.

[0062] In addition, in the back contact battery, if the n-region is connected to the heavily doped p-region, leakage will occur. Therefore, a gap region needs to be set between the two to separate the n-region from the p-region. However, the design of the gap region of the current battery structure is parallel to the n-region and the p-region. In the preparation of the gap region, since it is difficult to achieve precise control of the laser, even if a smaller energy spot size (such as (20-30um) is used, light leakage will occur in the area outside the laser patterning, thereby forming a complex alkali-resistant polymer. Therefore, it is difficult to clean out a high-precision and narrow gap width, which will inevitably occupy too wide a width on the back surface, resulting in current loss.

[0063] In order to solve the above technical problems,

[0064] First, as Fig.12 As shown, the present invention provides a TBC battery structure with a self-formed gap region, comprising a silicon substrate 1, wherein a p+ region and an n+ region are arranged on the back surface of the silicon substrate 1, wherein the height positions of the p+ region and the n+ region on the back surface of the silicon substrate 1 are staggered to form a step, and a gap region is formed at the side wall of the step connecting the p+ region and the n+ region, and the gap region is used to electrically isolate the p+ region and the n+ region;

[0065] The p+ region includes a first tunneling oxide layer 2, a p-poly layer 3, a second tunneling oxide layer 5 and an n-poly layer 6 sequentially deposited on a silicon substrate 1;

[0066] The n+ region includes a second tunneling oxide layer 5 and an n-poly layer 6 which are sequentially deposited on the silicon substrate 1 .

[0067] First, the present invention arranges the gap region with the p+ region and the n+ region in a vertical manner, so that the p+ region and the n+ region are separated and staggered in the vertical height, which greatly narrows the width occupied by the gap region in the lateral direction. It can not only maximize the width of the lateral p+ region and the n+ region, increase the carrier collection area, reduce the collection difficulty, and improve the short-circuit current.

[0068] Secondly, the p+ region of the present invention includes a first tunneling oxide layer 2, a p-poly layer 3, a second tunneling oxide layer 5 and an n-poly layer 6 deposited in sequence. Through the structural arrangement of the p-poly layer 3, the second tunneling oxide layer 5 and the n-poly layer 6, a tunneling junction can be formed, thereby replacing the existing PN junction structure to achieve selective collection of holes. Therefore, when preparing such a structure, there is no need to use a second laser to perform localized treatment on the PSG film layer due to the need to remove the n-poly layer deposited on the p-poly layer as in the conventional process, thereby reducing the second laser grooving process.

[0069] In addition, due to the high energy of the pulsed laser, complex polymer residues are easily generated on the surface of the crystalline silicon after laser treatment, which are highly resistant to alkali corrosion and difficult to clean. Therefore, the present invention does not require a second laser treatment, nor does it require cleaning of the n-poly layer deposited in the p+ region. It only requires direct cleaning and removal of the entire PSG film layer, thus avoiding the problem of increased difficulty in wet cleaning after laser treatment.

[0070] In a specific embodiment, AL is sequentially deposited on the n-poly layer 6 in the p+ region and the n+ region and on the gap region. 2 O 3 Film layer 8 and SiNx film layer 9.

[0071] In a specific embodiment, the back surface of the silicon substrate 1 in the gap region and the n+ region are both suede structures.

[0072] In a specific embodiment, the p+ region is provided with a first metal electrode 10, and the n+ region is provided with a second metal electrode 11. The first metal electrode 10 contacts the n-poly layer 6 of the p+ region, and the second metal electrode 11 contacts the n-poly layer 6 of the n+ region.

[0073] In a specific embodiment, the front surface of the silicon substrate 1 is sequentially deposited with AL 2 O 3 Film layer 8 and SiNx film layer 9.

[0074] In a specific embodiment, the silicon substrate 1 is an N-type silicon substrate, and the height of the p+ region on the back surface of the silicon substrate 1 is higher than the height of the n+ region on the back surface of the silicon substrate 1 .

[0075] In a second aspect, the present invention provides a method for preparing a TBC battery structure with a self-formed gap region based on a PVD method, comprising the following steps:

[0076] S1, double-sided polishing of an N-type single crystal silicon wafer;

[0077] S2, selecting one side of an N-type single crystal silicon wafer as the back surface, and sequentially depositing a first tunnel oxide layer and an intrinsic poly film layer;

[0078] S3, depositing and advancing a boron source on the intrinsic poly film layer to obtain a p-poly layer, and growing a BSG film layer on the surface of the p-poly layer;

[0079] S4, using laser to perform patterning on the back surface, and partially removing the BSG film layer on the back surface, that is, removing the BSG film layer in the reserved n-poly deposition area;

[0080] S5, wet cleaning, so that the n-poly deposition area reserved on the back surface is exposed to the surface of the silicon substrate. Since the p-poly area has a BSG film layer as a mask layer, the wet cleaning will not corrode the p-poly area;

[0081] S6, using alkaline washing to corrode the silicon substrate in the reserved n-poly deposition area and form a step between the silicon substrate in the p-poly area; then using acid washing to remove the BSG film layer on the surface of the p-poly area;

[0082] S7, depositing a second tunnel oxide layer on the entire back surface, and then depositing a layer of in-situ doped n-type amorphous silicon film layer by PVD deposition method, using PVD single-sided collimated deposition, no bypass plating is formed in the gap area located on the longitudinal surface, so the step formed by wet cleaning combined with PVD single-sided collimated deposition can automatically form a gap area with electrical isolation;

[0083] S8, performing a phosphorus source advancement and amorphous silicon crystallization process to obtain an n-poly layer and a PSG film layer;

[0084] S9, cleaning and removing the PSG film layer on the back surface;

[0085] S10, depositing a layer of AL on the front surface and the back surface of the structure obtained in step S9 2 O 3 Membrane layer;

[0086] S11, AL of the front surface and the back surface obtained in step S10 2 O 3 A layer of SiNx film is deposited on each of the film layers.

[0087] S12, the metal electrode is manufactured on the back surface of the structure obtained in step S11 by screen printing and drying and sintering, so that the first metal electrode and the second metal electrode are in contact with the n-poly layer.

[0088] In the preparation method of the present invention, a laser is used to perform a laser grooving on the p-poly, and then alkaline washing is performed to form steps, and then the amorphous silicon film layer is deposited by a PVD single-sided collimated deposition method, and no plating is formed in the gap area located on the longitudinal surface. Therefore, the steps formed by wet cleaning combined with the PVD single-sided collimated deposition can automatically form a gap area with electrical isolation, and the width can be controlled to be less than 10um.

[0089] At present, the conventional gap area is formed in step S9, specifically, the PSG film layer is partially removed by laser, that is, the PSG film layer in the p-poly area and the PSG film layer in the reserved gap area are removed, and only the PSG film layer in the reserved n-poly deposition area is retained, and then the p-poly area and the n-poly layer in the reserved gap area are cleaned, and then the corresponding passivation film and anti-reflection film are deposited. Therefore, it is difficult for the laser to accurately control the width of the reserved gap area.

[0090] In the preparation method of the present invention, the width and depth of the gap area can be accurately controlled by controlling the alkaline washing corrosion rate. At the same time, the structural position of the gap area is changed from a horizontal to a vertical setting, which can reduce the space occupancy of the gap area while ensuring the effectiveness of electrical isolation.

[0091] Example

[0092] The embodiment of the present invention provides a PVD method for preparing a TBC battery structure with a self-formed gap region, comprising the following steps:

[0093] Step 1: Place the N-type single crystal silicon wafer in an alkaline solution (KOH or NaOH) for double-sided polishing. Figure 1 As shown;

[0094] Step 2: Select one side of the N-type polished wafer obtained in step 1 as the process surface, which is the back surface, and the other side is the front surface; deposit a 1.5-2nm SiOx layer and a 150nm-250nm intrinsic poly film layer on the back surface in sequence by LPCVD, with the structure as shown below: Figure 2 As shown;

[0095] Step 3: Use a tubular diffusion furnace to perform double-insertion single-sided boron deposition on the silicon wafer obtained in step 2 (boron source deposition on the back surface), deposit and push the boron source on the intrinsic poly film layer at a temperature of 900-950°C to obtain a p-poly layer, and grow a BSG (borosilicate glass) film layer on the surface of the p-poly layer, where the BSG film layer acts as a mask layer. The structure is as follows: Figure 3 As shown;

[0096] Step 4: Use a laser to pattern the back surface and partially remove the BSG film layer in the n-poly deposition area reserved on the back surface, such as Figure 4 As shown;

[0097] Step 5: The sample obtained in step 4 is wet-cleaned accordingly to remove the p-poly layer in the reserved n-poly deposition area, and the BSG film layer and the boron-doped p-poly layer generated by the plating at the edge of the front surface are wet-cleaned, so that the n-poly deposition area reserved on the back surface and the front surface are exposed to the surface of the silicon substrate, such as Figure 5 As shown;

[0098] Step 6: Place the structure obtained in step 5 in an alkaline solution with a mass fraction of 1%-3% KOH (or NaOH) and a volume fraction of 0.5%-0.7% texturing additive for texturing treatment, so that a step is formed between the p-poly area and the reserved n-poly deposition area, and at the same time, the reserved n-poly deposition area on the back surface, the step connecting the p-poly area and the reserved n-poly deposition area, and the front surface are all velvet-structured; then, the BSG film layer on the surface of the p-poly area is removed using an HF solution, such as Figure 6 As shown;

[0099] Step 7: A 1-2 nm tunnel oxide layer is deposited on the entire back surface by plasma oxidation technology, and then a PVD deposition method is used, with a silicon target as the silicon source, phosphine as the doped phosphorus source, and Ar gas is introduced to bombard the silicon target to deposit an in-situ doped n-type amorphous silicon film layer, such as Figure 7 As shown;

[0100] Step 8: Then, the structure obtained in step 7 is loaded into a quartz tube, and the phosphorus source is pushed in and the amorphous silicon is crystallized at a temperature of 850°C-910°C to obtain an n-poly layer and a PSG film layer, such as Figure 8 As shown;

[0101] Step 9: The sample obtained in step 8 is cleaned with HF solution to remove the PSG film layer. Fig. 9 As shown;

[0102] Step 10: Use atomic deposition to deposit a 6-15 nm thick AL layer on the front and back surfaces of the structure obtained in step 9. 2 O 3 Film layer, such as Fig.10 As shown;

[0103] Step 11: Deposit a layer of SiNx film on the front surface and the back surface respectively by PECVD deposition to complete the production of the front surface and the back surface anti-reflection layer. Fig.11 As shown;

[0104] Step 12: The metal electrodes are made on the back surface by screen printing and drying and sintering, so that the first metal electrode contacts the n-poly film layer in the p-poly region, and the second metal electrode contacts the n-poly film layer in the n-poly region. Fig.12 As shown; the first metal electrode collects holes through a tunnel junction and acts as the positive electrode of the battery structure; the second metal electrode collects electrons and acts as the negative electrode of the battery structure.

[0105] Comparative Example

[0106] The comparative example of the present invention provides a method for preparing an existing back contact battery structure, comprising the following steps:

[0107] Step 1: Place the N-type single crystal silicon wafer in an alkaline solution (KOH or NaOH) for double-sided polishing;

[0108] Step 2: One side of the N-type polished wafer obtained in step 1 is selected as the process surface. For better description, this process surface is defined as the back surface, and the other side is defined as the front surface. A layer of SiOx and a layer of intrinsic poly film are sequentially deposited on the back surface by LPCVD to obtain a new sample.

[0109] Step 3: The sample obtained in step 2 is subjected to double-insertion single-sided boron deposition in a tubular diffusion furnace (boron source deposition is performed on the back surface), and the boron source is deposited and pushed on the intrinsic poly film layer at a temperature of 900-950°C to obtain a p-poly layer, and a BSG (borosilicate glass) layer is grown on the surface of the p-poly layer, wherein the BSG serves as the first laser mask layer;

[0110] Step 4: Use a laser to pattern the back surface and partially remove the BSG film layer on the back surface;

[0111] Step 5: wet-clean the sample obtained in step 4 accordingly, and wet-clean the BSG film layer and the boron-doped p-poly layer at the edge of the front surface due to wrap-around plating, so that the n-poly deposition area reserved on the back surface and the front surface are exposed to the surface of the silicon substrate;

[0112] Step 6: Using LPCVD, a layer of SiOx and a layer of intrinsic poly film are sequentially deposited on the back surface of the sample obtained in step 5 to obtain a new sample;

[0113] Step 7: The sample obtained in step 2 is subjected to double insertion single-sided phosphorus diffusion (phosphorus source deposition on the back surface) using a tubular diffusion furnace, and the phosphorus source is deposited and pushed on the intrinsic poly film layer at a temperature of 850-950°C. The n-poly layer and PSG (phosphorus silicon glass) layer are obtained in the area on the back surface that is laser-blasted and cleaned. At the same time, an n-poly layer and a PSG (phosphorus silicon glass) layer are also grown on the p-poly layer and BSG (borosilicate glass) layer in the non-laser area, where PSG serves as the second laser mask layer;

[0114] Step 8: Use a laser to perform patterning on the back surface, and partially remove the PSG film layer on the back surface of the p-poly area and the gap area to be reserved;

[0115] Step 9: wet-clean the sample obtained in step 8 accordingly, and wet-clean the PSG film layer and phosphorus-doped n-poly layer at the edge of the front surface due to wrap-around plating, so that the front surface exposes the surface of the silicon substrate, and remove the p-poly layer on the back surface and the n-poly layer also grown on the BSG (borosilicate glass) layer by alkali washing. The bottom p-poly is not corroded by the alkaline solution due to the protection of the BSG (borosilicate glass) mask layer;

[0116] Step 10: Place the structure obtained in step 9 in an alkaline solution with a mass fraction of 1%-3% KOH (or NaOH) and a volume fraction of 0.5%-0.7% texturing additive for texturing treatment, so that the gap area and the front surface between the p-poly area and the reserved n-poly deposition area are all velvet-structured; at the same time, HF solution is used to remove the PSG on the surface of the reserved n-poly deposition area, thus completing the production of the n-poly area, p-poly area, and gap area;

[0117] Step 11: Use atomic deposition to deposit a 6~15 nm thick AL layer on both sides of the structure obtained in step 10. 2 O 3 Membrane layer;

[0118] Step 12: Deposit a layer of SiNx film on the front surface and the back surface respectively by PECVD deposition to complete the production of the anti-reflection layer on the front surface and the back surface;

[0119] Step 13: The metal electrodes are made on the back surface by screen printing and drying and sintering, so that the first metal electrode contacts the p-poly film layer and the second metal electrode contacts the n-poly layer; the first metal electrode collects holes and acts as the positive electrode of the battery structure; the second metal electrode collects electrons and acts as the negative electrode of the battery structure. The obtained battery structure is as follows: Fig.13 shown.

[0120] The back contact battery prepared by the preparation method of the embodiment of the present invention can achieve electrical properties equivalent to those of the back contact battery prepared in the comparative example. In the embodiment of the present invention, only one laser is needed, while two lasers are needed for preparation in the comparative example. In terms of the comparison of the input cost of the laser equipment, one process is reduced in the present invention, which has the advantage of lower cost. In terms of the comparison of the process flow, one process is reduced in the present invention, the process flow is simpler, the production cycle is shortened, and the production efficiency is improved. In terms of the comparison of the process development difficulty, since the use of the laser is reduced once in the present invention, the process development difficulty is reduced, and at the same time, the difficulty of wet cleaning after the laser is reduced. In terms of large-scale mass production comparison, compared with the comparative example, the present invention has a simpler process flow and less equipment input cost, and has greater economic value.

[0121] In summary, the present invention provides a back contact battery structure and a preparation method with a simpler process, lower cost, and more suitable for large-scale mass production.

[0122] The specific embodiments described above have further elaborated on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A PVD method for preparing a TBC battery structure with a self-formed gap region, characterized in that: The steps include: S1, double-sided polishing of an N-type single crystal silicon wafer; S2, selecting one side of an N-type single crystal silicon wafer as the back surface, and sequentially depositing a first tunnel oxide layer and an intrinsic poly film layer; S3, depositing and advancing a boron source on the intrinsic poly film layer to obtain a p-poly layer, and growing a BSG film layer on the surface of the p-poly layer; S4, patterning the back surface using laser to partially remove the BSG film layer on the back surface; S5, wet cleaning, so that the n-poly deposition area reserved on the back surface is exposed to the surface of the silicon substrate; S6, using alkaline washing to corrode the silicon substrate in the reserved n-poly deposition area and form a step between the silicon substrate in the p-poly area; using acid washing to remove the BSG film layer on the surface of the p-poly area; S7, depositing a second tunnel oxide layer on the entire back surface, and then depositing an in-situ doped n-type amorphous silicon film layer by a PVD deposition method; S8, performing a phosphorus source advancement and amorphous silicon crystallization process to obtain an n-poly layer and a PSG film layer; S9, cleaning and removing the PSG film layer on the back surface.

2. The PVD method for preparing a TBC battery structure with a self-formed gap region according to claim 1, characterized in that: The method also includes step S10, depositing a layer of Al2O3 film on the front surface and the back surface of the structure obtained in step S9.

3. The PVD method for preparing a TBC battery structure with a self-formed gap region according to claim 2, characterized in that: The method further comprises S11 , depositing a layer of SiNx film on the Al 2 O 3 film on the front surface and the back surface of the structure obtained in step S10 .

4. The PVD method for preparing a TBC battery structure with a self-formed gap region according to claim 3, characterized in that: The method further comprises S12, wherein a metal electrode is fabricated on the back surface of the structure obtained in step S11 by screen printing and drying and sintering, so that both the first metal electrode and the second metal electrode are in contact with the n-poly layer.

5. A TBC battery structure with a self-formed gap region prepared by the method according to any one of claims 1 to 4, characterized in that: It comprises a silicon substrate (1), wherein a p+ region and an n+ region are arranged on the back surface of the silicon substrate (1), the height positions of the p+ region and the n+ region on the back surface of the silicon substrate (1) are staggered to form a step, and a gap region is formed at the side wall of the step connecting the p+ region and the n+ region, and the gap region is used to electrically isolate the p+ region and the n+ region; The p+ region comprises a first tunneling oxide layer (2), a p-poly layer (3), a second tunneling oxide layer (5) and an n-poly layer (6) which are sequentially deposited on a silicon substrate (1); The n+ region comprises a second tunneling oxide layer (5) and an n-poly layer (6) which are sequentially deposited on a silicon substrate (1).

6. A TBC battery structure with a self-formed gap region according to claim 5, characterized in that: An Al2O3 film layer (8) and a SiNx film layer (9) are sequentially deposited on the n-poly layer (6) in the p+ region and the n+ region, and on the gap region.

7. A TBC battery structure with a self-formed gap region according to claim 5, characterized in that: The back surfaces of the gap region and the n+ region silicon substrate (1) are both velvet structures.

8. The TBC battery structure with self-formed gap region according to claim 5, characterized in that: The p+ region is provided with a first metal electrode (10), the n+ region is provided with a second metal electrode (11), the first metal electrode (10) is in contact with the n-poly layer (6) of the p+ region, and the second metal electrode (11) is in contact with the n-poly layer (6) of the n+ region.

9. The TBC battery structure with self-formed gap region according to claim 5, characterized in that: An Al2O3 film layer (8) and a SiNx film layer (9) are sequentially deposited on the front surface of the silicon substrate (1).

10. The TBC battery structure with self-formed gap region according to claim 6, characterized in that: The silicon substrate (1) is an N-type silicon substrate, and the height of the p+ region on the back surface of the silicon substrate (1) is higher than the height of the n+ region on the back surface of the silicon substrate (1).

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