Tunneling field effect transistor, preparation method thereof and photoelectric detector

Abstract

The invention provides a tunneling field effect transistor, a preparation method thereof and a photoelectric detector, and relates to the field of photoelectric devices.The tunneling field effect transistor comprises a substrate, an insulating layer, a conductive layer, a dielectric layer, a heterojunction layer and a packaging layer, the heterojunction layer comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is stacked on the dielectric layer, at least part of the second semiconductor layer is stacked on the first semiconductor layer, and the other part of the second semiconductor layer is stacked on the dielectric layer; the first semiconductor layer comprises a tin disulfide layer, the second semiconductor layer comprises a hafnium disulfide layer, and the encapsulation layer comprises a hafnium oxide layer. According to the invention, the plasma oxidation technology is adopted to package hafnium disulfide with ultrahigh carrier characteristics, so that a hafnium oxide dielectric layer with a high dielectric constant is formed, a high-quality interface is ensured, the tunneling characteristic of the field effect transistor is realized, and the performance of the field effect transistor is improved. And a foundation is laid for finally realizing a low-power-consumption tunneling device of a high-performance nano material in the future.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic devices, and in particular to a tunneling field effect transistor, a preparation method thereof and a photoelectric detector. Background Art

[0002] As the size of transistors, the core components of integrated circuits, continues to shrink to the nanometer level, problems such as short channel effects have become increasingly apparent, posing a huge challenge to device performance. At the same time, the rapid development of modern information technology requires that the density of devices on integrated circuits continue to increase, which leads to a sharp increase in power consumption. In this case, the development of low-power devices is not only crucial to improving device performance and applications, but also of great significance to environmental protection and energy conservation. Therefore, the development of low-power technology has become a key research direction in the field of integrated circuits.

[0003] In the pursuit of low-power devices, researchers are constantly trying and exploring new technical approaches. Tunneling field-effect transistors show great potential as low-power devices. Unlike traditional metal-oxide semiconductor field-effect transistors (MOSFETs), tunneling field-effect transistors can break through the theoretical limit of subthreshold swing of 60mV / dec, which makes them a promising new device that can replace MOSFET and lead the development of future low-power devices.

[0004] Although tunneling field-effect transistor devices theoretically show the potential for extremely low subthreshold swing, in practice, interface effects have a profound impact on the devices, severely restricting the application of tunneling field-effect transistors. Summary of the invention

[0005] The main purpose of the present invention is to provide a tunneling field effect transistor, a preparation method thereof and a photoelectric detector, aiming to provide a tunneling field effect transistor with a high-quality packaging interface.

[0006] To achieve the above object, the present invention provides a tunneling field effect transistor, comprising a substrate and an insulating layer, a conductive layer, a dielectric layer, a heterojunction layer and a packaging layer sequentially stacked on one side of the substrate; The heterojunction layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer includes a tin disulfide layer, the second semiconductor layer includes a hafnium disulfide layer, and the encapsulation layer includes a hafnium oxide layer.

[0007] In one embodiment, the hafnium oxide layer is obtained by oxidizing the hafnium disulfide layer.

[0008] In one embodiment, the tin disulfide layer and the hafnium disulfide layer are both disposed on the dielectric layer, and the hafnium disulfide layer is at least partially stacked on the tin disulfide layer, so that the tin disulfide layer and the hafnium disulfide layer are cross-disposed.

[0009] In one embodiment, the thickness of the tin disulfide layer is 5-15 nm, and the thickness of the hafnium disulfide layer is 20-30 nm.

[0010] In one embodiment, the tunneling field effect transistor further includes a source electrode, a drain electrode and a gate electrode, the source electrode is disposed on the first semiconductor layer, the drain electrode is disposed on the second semiconductor layer, and the gate electrode is disposed on the conductive layer.

[0011] In one embodiment, the materials of the source electrode, the drain electrode and the gate electrode include stacked titanium layers and gold layers; The thickness of the titanium layer is 4-6 nm, and the thickness of the gold layer is 45-55 nm.

[0012] In one embodiment, the substrate comprises a silicon substrate, the insulating layer comprises a silicon dioxide layer, the conductive layer comprises a graphene layer, and the dielectric layer comprises a hexagonal boron nitride layer; The thickness of the silicon dioxide layer is 285-300 nm, the thickness of the graphene layer is 8-12 nm, and the thickness of the hexagonal boron nitride layer is 8-12 nm.

[0013] The present invention also provides a method for preparing a tunneling field effect transistor, comprising the following steps: S10. Providing a substrate covered with an insulating layer; S20. Disposing a conductive layer on the insulating layer; S30. Disposing a dielectric layer on the conductive layer; S40. Disposing a first semiconductor layer and a second semiconductor layer on the dielectric layer, wherein the first semiconductor layer and the second semiconductor layer are partially stacked and the other parts are disposed on the dielectric layer to obtain a stacked body, wherein the first semiconductor layer includes a tin disulfide layer, and the second semiconductor layer includes a hafnium disulfide layer; S50. Plasma-oxidizing the stack to oxidize the surface of hafnium disulfide to obtain a hafnium oxide layer, wherein the hafnium oxide layer forms an encapsulation layer; S60. Perform vacuum annealing, set the source electrode on the first semiconductor layer, set the drain electrode on the second semiconductor layer, and set the gate electrode on the conductive layer to obtain a tunneling field effect transistor.

[0014] In one embodiment, step S20 comprises: after obtaining the graphene layer by a mechanical exfoliation method, transferring the graphene layer to the substrate, wherein the graphene layer forms the conductive layer; Step S30 includes: after peeling the hexagonal boron nitride layer to polydimethylsiloxane, transferring the hexagonal boron nitride layer to the conductive layer by dry transfer, wherein the hexagonal boron nitride layer forms the dielectric layer; Step S40 includes: disposing a first semiconductor layer on the dielectric layer, and disposing a second semiconductor layer on the first semiconductor layer and the dielectric layer; In step S50, during the plasma oxidation treatment, the plasma power is 25-35 W, the oxygen flow rate is 3-6 sccm, the pressure is 450-500 mTorr, and the duration is 8-12 min; In step S60, the vacuum annealing temperature is 100-150°C, the heating time is 20-30 min, and the holding time is 30-60 min; In step S60 , the source electrode and the drain electrode are disposed on the first semiconductor layer and the second semiconductor layer respectively by evaporation.

[0015] The present invention further provides a photoelectric detector, which includes the tunneling field effect transistor as described above, or a tunneling field effect transistor prepared by the preparation method of the tunneling field effect transistor as described above.

[0016] The technical solution of the present invention is to prepare a low-power tunneling device with a spanning semiconductor layer structure composed of tin disulfide / hafnium disulfide. In this structure, the natural hafnium oxide layer is obtained by plasma oxidation treatment of hafnium disulfide, has a high dielectric constant, and can be used as a dielectric layer to isolate the influence of water and oxygen on hafnium disulfide, and at the same time form an interface without impurities and defects, thereby improving the performance of the tunneling field effect tube and increasing its current level and mobility. The high-quality interface between the top dielectric of the heterojunction layer and the channel material is crucial for high-performance tunneling field effect tubes, and the heterojunction layer ensures the fast switching and low energy consumption requirements of the device; the present invention uses plasma oxidation technology to encapsulate hafnium disulfide with ultra-high carrier characteristics, forming a natural high dielectric constant hafnium oxide dielectric layer, ensuring a high-quality interface, greatly improving the tunneling performance of the two-dimensional tin disulfide / hafnium disulfide detector, and laying a foundation for the ultimate realization of low-power tunneling field effect tubes of high-performance nanomaterials in the future. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor provided in Example 1 of the present invention; Figure 2A stacking diagram of a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor provided in Example 1 of the present invention; Figure 3 An optical microscope image of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor provided in Example 1 of the present invention; Figure 4 This is a Raman spectrum of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor of Example 1 of the present invention; Figure 5 This is an atomic force microscope (AFM) image of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling field effect transistor of Example 1 of the present invention; Figure 6 is the output curve of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling device of Example 1 of the present invention ( I ds - V ds )picture; Figure 7 It is a time response diagram of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide tunneling device of Example 1 of the present invention at different wavelengths; Figure 8 The graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide / hexagonal boron nitride device of Comparative Example 1 of the present invention is I ds - V ds Graphs; Fig. 9 The graphene / hexagonal boron nitride / tin disulfide / tin diselenide device of Comparative Example 2 of the present invention is I ds - V ds Graphs; Fig.10 The tin disulfide / hafnium disulfide device of Comparative Example 3 of the present invention I ds - V ds Graph.

[0019] Description of Figure Numbers: 100. Tunneling field effect transistor; 1. substrate; 2. insulating layer; 3. conductive layer; 4. dielectric layer; 5. heterojunction layer; 51. first semiconductor layer; 52. second semiconductor layer; 6. source electrode; 7. drain electrode; 8. gate electrode; 9. packaging layer.

[0020] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0021] To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them.

[0022] It should be noted that, in the embodiments, those without specifying specific conditions are carried out according to conventional conditions or conditions recommended by the manufacturer. Those without specifying the manufacturer of reagents or instruments used are conventional products that can be purchased commercially. In addition, the technical schemes between the various embodiments can be combined with each other, but must be based on the ability of ordinary technicians in the field to achieve. When the combination of the technical schemes is mutually contradictory or cannot be achieved, it should be considered that the combination of such technical schemes does not exist, and is not within the scope of protection required by the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present invention.

[0023] Tunneling field-effect transistors show great potential as low-power devices. Unlike MOSFETs, tunneling field-effect transistors can break through the theoretical limit of subthreshold swing of 60 mV / dec, which makes them a promising new type of device that can replace MOSFET and lead the development of future low-power devices.

[0024] At present, although tunneling field-effect transistor devices show the potential of extremely low subthreshold swing in theory, in practice, interface effects have a profound impact on the devices, seriously restricting the application of tunneling field-effect transistors.

[0025] This goal can be effectively achieved by selecting suitable two-dimensional materials to construct heterojunctions. Two-dimensional materials have the characteristics of smooth surface and few defects, which are conducive to the efficient transmission of carriers. In addition, there are no dangling bonds on the surface of two-dimensional materials, which helps to reduce the negative impact of lattice mismatch on device performance, making two-dimensional materials an ideal choice for the preparation of new tunneling field-effect transistors.

[0026] The energy band arrangement of heterostructures formed by the superposition of two-dimensional materials is mainly divided into leaping, staggered and broken structures. In the leaping structure, the minimum of the conduction band and the maximum of the valence band are both located in the same material, which confines the photogenerated electrons and holes in the same material and promotes their radiative recombination. In addition, there is a carrier transport barrier from the narrow bandgap semiconductor layer to the wide bandgap semiconductor layer, which is conducive to achieving low dark current, thereby significantly improving the switching ratio of the tunneling current.

[0027] In view of this, see Figure 1The present invention proposes a tunneling field effect transistor 100, comprising a substrate 1 and an insulating layer 2, a conductive layer 3, a dielectric layer 4, a heterojunction layer 5 and a packaging layer 9 stacked in sequence on one side of the substrate 1; the heterojunction layer 5 comprises a first semiconductor layer 51 and a second semiconductor layer 52, the first semiconductor layer 51 comprises a tin disulfide layer, the second semiconductor layer 52 comprises a hafnium disulfide layer, and the packaging layer 9 comprises a hafnium oxide layer.

[0028] It should be noted that the field effect transistor prepared by hafnium disulfide has an ultra-high on-off ratio (more than 10 8 ), which is crucial for high-performance electronics.

[0029] The technical solution of the present invention is to prepare a low-power tunneling device with a cross-type semiconductor layer structure composed of tin disulfide / hafnium disulfide. In this structure, the hafnium oxide layer has a high dielectric constant and can be used as a dielectric layer to isolate the influence of water and oxygen on hafnium disulfide, and at the same time form an interface without impurities and defects, thereby improving the performance of the tunneling field effect transistor 100; in addition, the high-quality interface between the top medium of the heterojunction layer 5 and the channel material is crucial for high-performance tunneling field effect transistors 100, and the heterojunction layer 5 ensures the low energy consumption requirements of the device. The present invention uses plasma oxidation technology to encapsulate hafnium disulfide with ultra-high carrier characteristics, forming a natural high-dielectric constant hafnium oxide dielectric layer, ensuring a high-quality interface, greatly improving the tunneling performance of tin disulfide / hafnium disulfide detectors, and laying the foundation for the ultimate realization of low-power tunneling devices of high-performance nanomaterials in the future.

[0030] In one embodiment, the hafnium oxide layer is obtained by oxidizing the hafnium disulfide layer.

[0031] The technical solution of the present invention synthesizes a natural dielectric layer of hafnium oxide by an oxidation method, thereby forming a natural hafnium oxide dielectric layer with a high dielectric constant, ensuring a high-quality interface, thereby greatly reducing the influence of moisture and oxygen in the surrounding environment on it.

[0032] In one embodiment, the tin disulfide layer and the hafnium disulfide layer are both disposed on the dielectric layer 4 , and the hafnium disulfide layer is at least partially stacked on the tin disulfide layer, so that the tin disulfide layer and the hafnium disulfide layer are cross-disposed.

[0033] The technical solution of the present invention forms a heterojunction layer 5 by cross-arranging the tin disulfide layer and the hafnium disulfide layer. At the same time, the tin disulfide layer and the hafnium disulfide layer are arranged on the dielectric layer 4. The carrier distribution states in the tin disulfide layer and the hafnium disulfide layer can be adjusted respectively through the dielectric layer 4, so as to accurately control the tunneling probability, thereby realizing devices with different properties in the same heterojunction.

[0034] In one embodiment, the thickness of the tin disulfide layer is 5-15 nm, and the thickness of the hafnium disulfide layer is 20-30 nm.

[0035] In one embodiment, the tunneling field effect transistor 100 further includes a source electrode 6 , a drain electrode 7 and a gate electrode 8 , wherein the source electrode 6 is disposed on the first semiconductor layer 51 , the drain electrode 7 is disposed on the second semiconductor layer 52 , and the gate electrode 8 is disposed on the conductive layer 3 .

[0036] The technical solution of the present invention can effectively control the electron tunneling process by setting the source electrode 6 on the first semiconductor layer 51 and the drain electrode 7 on the second semiconductor layer 52; by setting the gate electrode 8 on the conductive layer 3, the tunneling barrier can be more effectively controlled, and the ability to regulate the carrier tunneling process is improved, thereby enhancing the overall controllability and stability of the device.

[0037] In one embodiment, the materials of the source electrode 6, the drain electrode 7 and the gate electrode 8 include stacked titanium layers and gold layers; The thickness of the titanium layer is 4-6 nm, and the thickness of the gold layer is 45-55 nm.

[0038] The technical solution of the present invention selects titanium and gold as electrode materials, wherein the titanium layer is used to improve the contact quality between the electrode and the semiconductor layer due to its good adhesion; the gold layer has excellent conductivity and chemical stability, which helps to reduce the contact resistance and improve the conductivity of the electrode; the combined electrode of titanium and gold helps to optimize the carrier transmission path and reduce the loss in the carrier transmission process; both titanium and gold have good thermal stability and can maintain stable performance in a wide temperature range, which helps to broaden the operating temperature range of the tunneling field effect transistor 100; by adopting a titanium layer with a thickness of 4~6 nm, sufficient adhesion is ensured, and at the same time, additional resistance increase caused by excessive thickness is avoided; by adopting a gold layer with a thickness of 45~55 nm, good conductivity can be guaranteed while maintaining low contact resistance; by precisely controlling the thickness of the titanium and gold layers, not only the high performance of the device is ensured, but also the cost can be effectively reduced.

[0039] In one embodiment, see Figures 1 to 3 , the substrate 1 includes a silicon substrate, the insulating layer 2 includes a silicon dioxide layer, the conductive layer 3 includes a graphene layer, and the dielectric layer 4 includes a hexagonal boron nitride layer; The thickness of the silicon dioxide layer is 285-300 nm, the thickness of the graphene layer is 8-12 nm, and the thickness of the hexagonal boron nitride layer is 8-12 nm.

[0040] The technical solution of the present invention adopts hexagonal boron nitride as the dielectric layer 4, and utilizes its high-quality insulation characteristics and excellent dielectric properties to effectively isolate the conductive layer 3 and the heterojunction layer 5, reduce unnecessary carrier recombination phenomena, and thus improve the photoelectric conversion efficiency; adopts graphene as the conductive layer 3, and utilizes its extremely high electron mobility and good conductivity to help accelerate the carrier transmission process, reduce the energy loss during the transmission process, and thus improve the response speed of the tunneling field effect transistor 100; in addition, both hexagonal boron nitride and graphene have good stability and can withstand high mechanical stress, which helps to improve the reliability and durability of the tunneling field effect transistor 100. By adopting a hexagonal boron nitride layer with a thickness of 8 to 12 nm as a high-quality insulating layer 2, it is possible to effectively isolate each layer, reduce unnecessary carrier recombination, and further improve the photoelectric conversion efficiency; by adopting a graphene layer, and utilizing its high electron mobility and good conductivity, it helps to accelerate the carrier transmission process, reduce the energy loss during the transmission process, and thus improve the response speed of the tunneling field effect transistor 100.

[0041] It should be noted that the silicon substrate is a doped silicon substrate. Specifically, in some embodiments of the present invention, the silicon substrate is a p-type doped silicon substrate.

[0042] The present invention also proposes a method for preparing a tunneling field effect transistor 100, comprising the following steps: S10. providing a substrate 1 covered with an insulating layer 2; S20. arranging a conductive layer 3 on the insulating layer 2; S30. arranging a dielectric layer 4 on the conductive layer 3; S40. arranging a first semiconductor layer 51 and a second semiconductor layer 52 on the dielectric layer 4, wherein the first semiconductor layer 51 and the second semiconductor layer 52 are partially stacked, and the other parts are arranged on the dielectric layer 4 to obtain a stack, wherein the first semiconductor layer 51 includes a tin disulfide layer, and the second semiconductor layer 52 includes a hafnium disulfide layer; S50. subjecting the stack to plasma oxidation, oxidizing the surface of the hafnium disulfide to obtain a hafnium oxide layer, and the hafnium oxide layer forms an encapsulation layer 9; S60. performing vacuum annealing, arranging a source electrode 6 on the first semiconductor layer 51, a drain electrode 7 on the second semiconductor layer 52, and a gate electrode 8 on the conductive layer 3 to obtain a tunneling field effect transistor 100.

[0043] The technical solution of the present invention uses tin disulfide and hafnium disulfide as the materials of the first semiconductor layer 51 and the second semiconductor layer 52, and utilizes the special band structure and high mobility characteristics of these two materials to improve the performance of the tunneling field effect transistor 100; through plasma oxidation treatment, the surface of hafnium disulfide is oxidized to form a hafnium oxide layer as the encapsulation layer 9, forming a natural oxide layer, which will not cause a series of interface problems, and reduces the preparation steps, further reducing the risk of interface contamination, thereby realizing the characteristics of a forward rectifier, an Esaki diode and a reverse rectifier in one structure; by stacking the first semiconductor layer 51 and the second semiconductor layer 52 in a partially stacked manner, it is helpful to optimize the tunneling path of the charge carriers, further reduce the leakage current, and improve the performance of the tunneling field effect transistor 100.

[0044] In addition, in some embodiments of the present invention, a layer of graphene electrode is further added to the encapsulation layer 9, thereby forming a double-gate regulation, namely, the bottom gate dielectric layer is hexagonal boron nitride and the top gate dielectric layer is hafnium oxide, thereby further improving the carrier regulation capability.

[0045] In one embodiment, step S20 includes: after mechanically exfoliating the graphene layer, transferring the graphene layer to the substrate 1, and the graphene layer forms the conductive layer 3; step S30 includes: after exfoliating the hexagonal boron nitride layer to polydimethylsiloxane, transferring the hexagonal boron nitride layer to the conductive layer 3 by dry transfer, and the hexagonal boron nitride layer forms the dielectric layer 4; step S40 includes: disposing the first semiconductor layer 51 on the dielectric layer 4, and disposing the second semiconductor layer 52 on the first semiconductor layer 51 and the dielectric layer 4; in step S50, during plasma oxidation treatment, the plasma power is 25~35 W, the oxygen flow rate is 3~6 sccm, the pressure is 450~500 mTorr, and the duration is 8~12 min; in step S60, the vacuum annealing temperature is 100~150°C, the heating time is 20~30 min, and the holding time is 30~60 min; in step S60, the source electrode 6 and the drain electrode 7 are respectively disposed on the first semiconductor layer 51 and the second semiconductor layer 52 by evaporation.

[0046] The technical solution of the present invention forms a conductive layer 3 by mechanically exfoliating a graphene layer and transferring it to a substrate 1. The graphene layer has a high electron mobility and good conductivity, which helps to accelerate the transmission process of carriers and reduce the energy loss in the transmission process, thereby improving the response speed of the tunneling field effect transistor 100; the hexagonal boron nitride layer is exfoliated onto polydimethylsiloxane and transferred to the graphene layer by a dry method to form a dielectric layer 4, which can provide good electrical insulation performance, reduce the radiation recombination of charge carriers, and help improve the photoelectric conversion efficiency, wherein the hexagonal boron nitride layer can effectively isolate each layer, reduce unnecessary carrier recombination, and further improve the photoelectric conversion efficiency; by arranging the first semiconductor layer 51 on the dielectric layer 4 and arranging the second semiconductor layer 52 on the first semiconductor layer 51 and the dielectric layer 4, the position and relationship of the semiconductor layers can be accurately controlled, the transmission path of the carriers can be optimized, and the energy loss in the carrier transmission process can be reduced, thereby improving the response speed of the tunneling field effect transistor 100; by performing vacuum annealing in a temperature range of 100 to 150°C, defects and impurities can be reduced, thereby enhancing the reliability and stability of the device. Reasonable heating time and holding time can also help optimize the performance of the material; the hafnium oxide layer prepared by plasma oxidation treatment is used as the encapsulation layer 9. Precise control of plasma power, oxygen flow rate, pressure and duration can help obtain high-quality encapsulation layer 9, which can not only provide good electrical insulation performance, but also enhance the thermal stability and chemical stability of the device.

[0047] The present invention further provides a photodetector, which includes the tunneling field effect transistor 100 as described above, or the tunneling field effect transistor 100 prepared by the preparation method of the tunneling field effect transistor 100 as described above.

[0048] Since the photoelectric detector adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0049] The technical solution of the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the following embodiments are only used to explain the present invention and are not used to limit the present invention. In the embodiments, some thickness data are ranges rather than precise point values. This is because the thickness of each layer formed in the preparation process fluctuates due to instrument errors, and the resulting thickness is a range rather than a point value.

[0050] Example 1 This embodiment provides a tunneling field effect transistor, whose structure is as follows Figure 1 As shown, the preparation method thereof comprises the following steps: 1. In SiO 2- 8~12nm graphene is peeled off from Si substrate; 8~12nm hexagonal boron nitride is peeled off onto polydimethylsiloxane; hexagonal boron nitride is transferred onto graphene via a transfer table; 5~15nm tin disulfide is transferred onto hexagonal boron nitride via a transfer table; 20~30nm hafnium disulfide is transferred onto the tin disulfide layer via a transfer table to form a heterojunction; 2. The stacked graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide heterojunction was subjected to plasma oxidation treatment with a plasma power of 30 W, an oxygen flow rate of 5 sccm, a pressure of 470 mTorr, and a duration of 10 min to obtain a hafnium oxide layer; 3. Place the oxidized heterojunction in a vacuum annealing furnace for annealing. Control the vacuum annealing temperature to 100°C, the heating time to 30 mins, the holding time to 1h, and cool to room temperature with the furnace. 4. Build electrodes on the annealed graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide by evaporating a titanium layer with a thickness of 5 nm and then continuing to evaporate a gold layer with a thickness range of 50 nm.

[0051] Comparative experiments and results Comparative Example 1 This comparative example provides a hexagonal boron nitride encapsulation layer, which is different from Example 1 in that a conventional hexagonal boron nitride encapsulation layer is used instead of a hafnium oxide layer in close contact with the heterojunction material to obtain a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide / hexagonal boron nitride heterojunction, and the specific steps are as follows: 1. Mechanically peel off 8-15 nm graphene onto a p-type doped silicon substrate with a 285-300 nm thick silicon dioxide insulating layer on the surface, peel off a 10-20 nm hexagonal boron nitride layer onto polydimethylsiloxane, transfer the hexagonal boron nitride onto part of the graphene by dry transfer, then transfer 10-20 nm tin disulfide onto the hexagonal boron nitride, and then transfer 60-80 nm hafnium disulfide onto part of the tin disulfide and hexagonal boron nitride, stacking to form a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide heterojunction; 2. Transferring hexagonal boron nitride to hafnium disulfide by dry transfer to form an encapsulation layer; 3. Build an electrode on the annealed graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide heterojunction by first evaporating a titanium layer with a thickness range of 5 nm, and then continue to evaporate a gold layer with a thickness range of 50 nm.

[0052] Comparative Example 2 This comparative example provides a heterojunction structure, which is different from that in Example 1 in that a graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction is used, and the specific steps are as follows: 1. Mechanically peel off 8-15 nm graphene onto a p-type doped silicon substrate with a 285-300 nm thick silicon dioxide insulating layer on the surface, peel off a 10-20 nm hexagonal boron nitride layer onto polydimethylsiloxane, transfer the hexagonal boron nitride onto part of the graphene by dry transfer, then transfer 10-20 nm tin disulfide onto the hexagonal boron nitride, and then transfer 60-80 nm tin diselenide onto part of the tin disulfide and hexagonal boron nitride, stacking to form a graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction; 2. Place the stacked graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction in a vacuum annealing furnace for annealing. Control the vacuum annealing temperature to 100°C, the heating time to 30 mins, the holding time to 1 h, and cool to room temperature with the furnace. 3. An electrode is constructed on the annealed graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction by first evaporating a titanium layer with a thickness range of 5 nm and then continuing to evaporate a gold layer with a thickness range of 50 nm.

[0053] Comparative Example 3 This comparative example provides a heterojunction structure, which is different from that in Example 1 in that a tin disulfide / hafnium disulfide heterojunction is used, and the specific steps are as follows: 1. Transfer 10~20 nm hafnium disulfide to part of tin disulfide by mechanical stripping, and stack to form a tin disulfide / hafnium disulfide heterojunction; 2. Electrodes were constructed on the annealed SnS2 / HfS2 heterojunction by first evaporating a Ti layer with a thickness range of 5 nm and then continuing to evaporate a Au layer with a thickness range of 50 nm.

[0054] Performance Testing The tunneling field effect transistor provided in Example 1 was used to perform Raman spectroscopy characterization, AFM testing, and current-voltage (IV) curve testing.

[0055] like Figure 4 As shown in the figure, the Raman spectrum of the SnS2 / Hf2 device was characterized, and the abscissa represents the Raman shift (cm -1 ), the ordinate represents the relative intensity (au). The Raman peaks of tin disulfide and hafnium disulfide can be observed from the figure, among which A 1g (318 cm -1 ) is the Raman peak of tin disulfide, E g (261 cm -1 ) and A 1g (340 cm -1) is the Raman peak of hafnium disulfide; from the above, it can be seen that the preparation method of the present invention can be used to successfully prepare a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide heterojunction.

[0056] like Figure 5 As shown, the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide device was subjected to AFM testing, the abscissa represents distance (μm), the ordinate represents height (au), and the thickness of hafnium disulfide was found to be approximately 30 nm, and the thickness of tin disulfide was approximately 6 nm.

[0057] like Figure 6 As shown, the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide device was I ds - V ds Curve test, the horizontal axis represents the source-drain voltage ( V ds ), the ordinate represents the source-drain current ( I ds ), when the gate voltage is 3V, a forward rectifier is obtained, when the gate voltage is 0.1V, an Esaki tube is obtained, and when the gate voltage is -3V, a reverse rectifier is obtained. In this way, the integration of three characteristics including a forward rectifier, an Esaki tube and a reverse rectifier is successfully realized in the same heterojunction.

[0058] like Figure 7 As shown in Figure 1, the optoelectronic properties of the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide device were characterized, and its time-dependent photoresponse performance was evaluated. Due to the light-induced band alignment regulation, the graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide device exhibited broadband detection characteristics and reached a maximum value at 455 nm.

[0059] The tunneling field effect transistors provided in Comparative Examples 1 to 3 were used to perform IV curve tests.

[0060] like Figure 8 As shown, in Comparative Example 1, a graphene / hexagonal boron nitride / tin disulfide / hafnium disulfide / hexagonal boron nitride heterojunction is used, the bottom hexagonal boron nitride is used as a dielectric layer, and the top hexagonal boron nitride is used as an encapsulation layer. A higher source current can be achieved under a small voltage. However, compared with the IV curve test results of Example 1, due to the complex preparation and the difficulty in avoiding interface problems, it is not possible to obtain three devices with different properties in the same heterojunction by adjusting the gate voltage.

[0061] like Fig. 9As shown, a graphene / hexagonal boron nitride / tin disulfide / tin diselenide heterojunction is used, with hexagonal boron nitride as the dielectric layer, and a higher source-drain current can be achieved at a small voltage. However, compared with the IV curve test results of Example 1, three devices with different properties are not obtained in the same structure by adjusting the gate voltage.

[0062] like Fig.10 As shown, using a tin disulfide / hafnium disulfide heterojunction, if a source-drain current of the same magnitude as that in Example 1 is to be obtained, the gate voltage needs to be greatly increased. Therefore, compared with the IV curve test results of Example 1, the gate voltage is high, the energy consumption is large, and the obtained device does not achieve different performance.

[0063] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A tunneling field effect transistor, characterized in that: It includes a substrate and an insulating layer, a conductive layer, a dielectric layer, a heterojunction layer and a packaging layer stacked in sequence on one side of the substrate; The heterojunction layer includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer includes a tin disulfide layer, the second semiconductor layer includes a hafnium disulfide layer, and the encapsulation layer includes a hafnium oxide layer.

2. The tunneling field effect transistor according to claim 1, characterized in that: The hafnium oxide layer is obtained by oxidizing the hafnium disulfide layer.

3. The tunneling field effect transistor according to claim 1, characterized in that: The tin disulfide layer and the hafnium disulfide layer are both disposed on the dielectric layer, and the hafnium disulfide layer is at least partially stacked on the tin disulfide layer, so that the tin disulfide layer and the hafnium disulfide layer are cross-disposed.

4. The tunneling field effect transistor according to claim 1, characterized in that: The thickness of the tin disulfide layer is 5-15 nm, and the thickness of the hafnium disulfide layer is 20-30 nm.

5. The tunneling field effect transistor according to claim 1, characterized in that: The tunneling field effect transistor further includes a source electrode, a drain electrode and a gate electrode. The source electrode is arranged on the first semiconductor layer, the drain electrode is arranged on the second semiconductor layer, and the gate electrode is arranged on the conductive layer.

6. The tunneling field effect transistor according to claim 5, characterized in that: The materials of the source electrode, the drain electrode and the gate electrode include stacked titanium layers and gold layers; The thickness of the titanium layer is 4-6 nm, and the thickness of the gold layer is 45-55 nm.

7. The tunneling field effect transistor according to claim 1, characterized in that: The substrate comprises a silicon substrate, the insulating layer comprises a silicon dioxide layer, the conductive layer comprises a graphene layer, and the dielectric layer comprises a hexagonal boron nitride layer; The thickness of the silicon dioxide layer is 285-300 nm, the thickness of the graphene layer is 8-12 nm, and the thickness of the hexagonal boron nitride layer is 8-12 nm.

8. A method for preparing a tunneling field effect transistor, characterized in that: The following steps are involved: S10. Providing a substrate covered with an insulating layer; S20. Disposing a conductive layer on the insulating layer; S30. Disposing a dielectric layer on the conductive layer; S40. Disposing a first semiconductor layer and a second semiconductor layer on the dielectric layer, wherein the first semiconductor layer and the second semiconductor layer are partially stacked and the other parts are disposed on the dielectric layer to obtain a stacked body, wherein the first semiconductor layer includes a tin disulfide layer, and the second semiconductor layer includes a hafnium disulfide layer; S50. Plasma-oxidizing the stack to oxidize the surface of hafnium disulfide to obtain a hafnium oxide layer, wherein the hafnium oxide layer forms an encapsulation layer; S60. Perform vacuum annealing, set the source electrode on the first semiconductor layer, set the drain electrode on the second semiconductor layer, and set the gate electrode on the conductive layer to obtain a tunneling field effect transistor.

9. The method for preparing a tunneling field effect transistor according to claim 8, characterized in that: Step S20 comprises: after obtaining a graphene layer by a mechanical exfoliation method, transferring the graphene layer to the substrate, wherein the graphene layer forms the conductive layer; Step S30 includes: after peeling the hexagonal boron nitride layer to polydimethylsiloxane, transferring the hexagonal boron nitride layer to the conductive layer by dry transfer, wherein the hexagonal boron nitride layer forms the dielectric layer; Step S40 includes: disposing a first semiconductor layer on the dielectric layer, and disposing a second semiconductor layer on the first semiconductor layer and the dielectric layer; In step S50, during the plasma oxidation treatment, the plasma power is 25-35 W, the oxygen flow rate is 3-6 sccm, the pressure is 450-500 mTorr, and the duration is 8-12 min; In step S60, the vacuum annealing temperature is 100-150°C, the heating time is 20-30 min, and the holding time is 30-60 min; In step S60 , the source electrode and the drain electrode are disposed on the first semiconductor layer and the second semiconductor layer respectively by evaporation.

10. A photoelectric detector, characterized in that: The photodetector comprises a tunneling field effect transistor as claimed in any one of claims 1 to 7, or a tunneling field effect transistor prepared by the method for preparing a tunneling field effect transistor as claimed in any one of claims 8 to 9.

Images