Flip LED chip and preparation method thereof

Abstract

The invention relates to the technical field of photoelectron manufacturing, and particularly discloses a flip LED chip and a preparation method thereof. The preparation method comprises the steps of providing an epitaxial wafer; forming a transparent conductive layer; etching to form an etching pit; forming a first passivation protection layer; forming a first photoresist layer; etching to form a groove for exposing the transparent conductive layer, and forming an evaporation hole; the width of the top of the evaporation hole is smaller than that of the groove; a reflecting layer and a connecting layer are sequentially evaporated in the evaporation hole, and a first angle is formed between the metal beam and the epitaxial wafer during evaporation; a protective layer is evaporated in the evaporation hole, during evaporation, a second angle is formed between the metal beam and the epitaxial wafer, and the second angle is smaller than the first angle; removing the fourth photoresist layer; forming a second passivation protection layer, and etching to form a hole; and forming a first electrode and a second electrode. According to the invention, the first passivation layer and the protection layer are compounded to form good wrapping of the reflection layer, metal migration of the reflection layer is greatly reduced, and reliability is improved.

Description

Technical Field

[0001] The invention relates to the technical field of optoelectronic manufacturing, and in particular to a flip-chip LED chip and a preparation method thereof. Background Art

[0002] The flip-chip silver mirror LED chip is a relatively advanced optoelectronic semiconductor technology, and its core advantage lies in improving the light efficiency and heat dissipation performance. Compared with traditional LED chips, the flip-chip silver mirror LED chip adopts a flip-chip structure, that is, the light-emitting surface of the LED chip faces downward. This design effectively reduces the light path loss and improves the light output efficiency and brightness. In addition, the flip-chip silver mirror LED chip also performs well in heat dissipation. The heat dissipation effect of traditional LED chips is often limited because the heat dissipation surface is on the front of the chip. The flip-chip silver mirror LED chip can conduct heat directly to the heat dissipation substrate through the metal layer, thereby achieving more effective heat dissipation. This improvement not only extends the service life of the LED, but also improves its long-term stability and light efficiency.

[0003] The flip-chip silver mirror LED chip has shown significant advantages in light efficiency, heat dissipation performance, and light color uniformity through its innovative structural design. It not only improves the lighting quality, but also contributes to energy saving and long life. It is widely used in modern lighting and display technology, and promotes the further development of LED technology. However, the process of flip-chip silver mirror LED chips is usually very complicated, and the problem of easy migration of metallic silver is troubling people, which also restricts the further development of flip-chip silver mirror related LED chips. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for preparing a flip-chip LED chip with high reliability.

[0005] Another technical problem to be solved by the present invention is to provide a flip-chip LED chip.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a flip-chip LED chip, which comprises the following steps:

[0007] (1) Providing an epitaxial wafer; wherein the epitaxial wafer comprises a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate;

[0008] (2) forming a transparent conductive layer on the epitaxial wafer;

[0009] (3) etching to form an etching pit penetrating the first semiconductor layer;

[0010] (4) forming a first passivation protective layer on the epitaxial wafer obtained in step (3);

[0011] (5) forming a first photoresist layer on the first passivation protection layer, and removing the photoresist layer above the transparent conductive layer by exposure and development to obtain an etched hole;

[0012] (6) removing the first passivation protection layer in the etched hole to obtain a groove exposing the transparent conductive layer, and converting the first photoresist layer into a second photoresist layer, wherein the second photoresist layer is provided with a vapor deposition hole exposing the groove; the width of the top of the vapor deposition hole is smaller than the width of the groove;

[0013] (7) sequentially evaporating a reflective layer and a connecting layer in the evaporation hole, and converting the second photoresist layer into a third photoresist layer; wherein during evaporation, the metal beam has a first angle with the epitaxial wafer;

[0014] (8) vapor-depositing a protective layer in the vapor-deposition hole, and converting the third photoresist layer into a fourth photoresist layer; wherein during the vapor-deposition, the metal beam has a second angle with the epitaxial wafer, and the second angle is smaller than the first angle;

[0015] (9) removing the fourth photoresist layer; wherein the thickness of the fourth photoresist layer is less than the thickness of the third photoresist layer, less than the thickness of the second photoresist layer, and less than the thickness of the first photoresist layer;

[0016] (10) forming a second passivation protection layer on the epitaxial wafer obtained in step (9), and forming a first opening etched to the first semiconductor layer and a second opening etched to the protection layer respectively;

[0017] (11) forming a first electrode and a second electrode, wherein the first electrode is electrically connected to the first semiconductor layer through the first opening, and the second electrode is electrically connected to the protective layer through the second opening.

[0018] As an improvement of the above technical solution, the first angle is 35° to 55°, and the second angle is 20° to 35°.

[0019] As an improvement of the above technical solution, the depth of the groove is D, the thickness of the reflective layer is T1, the thickness of the connecting layer is T2, the thickness of the protective layer is T3, and D>T1+T2+T3.

[0020] As an improvement of the above technical solution, the reflective layer is made of Ag and / or Al, and its thickness is 40nm to 300nm;

[0021] The connecting layer is made of one or more of Ni, Cr, and Ti, and has a thickness of 5nm to 50nm;

[0022] The protective layer is made of one or more of Cr, Ni, Ti, Pt, and Au, and has a thickness of 200nm to 600nm;

[0023] The first passivation protection layer is made of SiO2, Al2O3 or SiN x Made of, its thickness is 500nm~2000nm.

[0024] As an improvement of the above technical solution, the second passivation protective layer is made of SiO2, Al2O3 or SiN x Made of, its thickness is 100nm~1500nm;

[0025] The transparent conductive layer is an ITO layer, and its thickness is 4nm to 150nm;

[0026] The first electrode and the second electrode are both made of one or more of Al, Cr, Ti, Ni, Pt, and Au, and have a thickness of 500nm to 3000nm.

[0027] As an improvement of the above technical solution, the evaporation hole includes a first evaporation hole arranged close to the epitaxial wafer and a second evaporation hole arranged away from the epitaxial wafer; the width of the first evaporation hole is greater than the width of the second evaporation hole, and the width of the second evaporation hole is less than the width of the groove;

[0028] The width of the groove is greater than the width of the transparent conductive layer after etching.

[0029] As an improvement of the above technical solution, the second evaporation hole has an arc-shaped side wall, so that a preset portion of the first evaporation holes is covered by the arc-shaped side wall;

[0030] The width of the top of the second evaporation hole is smaller than the width of the transparent conductive layer after etching.

[0031] As an improvement of the above technical solution, the thickness of the first photoresist layer is 10μm to 12μm; the thickness of the second photoresist layer is 9μm to 11.5μm, the thickness of the third photoresist layer is 8.5μm to 11μm, and the thickness of the fourth photoresist layer is 8μm to 11μm.

[0032] As an improvement of the above technical solution, step (10) includes:

[0033] (10.1) forming a second passivation protective layer on the epitaxial wafer obtained in step (9);

[0034] (10.2) etching the second passivation protection layer to form a third opening etched to the first passivation protection layer and a second opening etched to the protection layer;

[0035] (10.3) Continue etching the first passivation protection layer along the third opening to obtain a first opening exposing the first semiconductor layer, wherein the first semiconductor layer is etched by SiCl4 with a flow rate of 50sccm to 150sccm, an upper etching power of 200W to 500W, a lower etching power of 100W to 200W, and an etching time of 50s to 200s.

[0036] Correspondingly, the present invention also discloses a flip-chip LED chip, which is prepared by the above-mentioned method for preparing the flip-chip LED chip.

[0037] The implementation of the present invention has the following beneficial effects:

[0038] In the method for preparing a flip-chip LED chip in one embodiment of the present invention, the angle (second angle) between the metal beam and the epitaxial wafer when the protective layer is evaporated is controlled to be smaller than the angle (first angle) between the metal beam and the epitaxial wafer when the reflector is evaporated, so that the protective layer can form a good coating on the reflective layer, reducing the metal migration of the reflective layer. Moreover, through the cooperation of the evaporation hole and the groove, the reflective layer can be formed in the groove formed by the first passivation protective layer, and then through the joint action of the first passivation protective layer and the protective layer, the metal migration of the reflective layer is greatly reduced. In addition, in this embodiment, the groove, the reflective layer, the connecting layer and the protective layer are formed by a yellow light process, which ensures the reliability of the process and simplifies the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic structural diagram of an epitaxial wafer in one embodiment of the present invention;

[0040] Figure 2 is a schematic diagram of the structure of the epitaxial wafer after step S3 in one embodiment of the present invention;

[0041] Figure 3 is a schematic diagram of the structure of the epitaxial wafer after step S4 in one embodiment of the present invention;

[0042] Figure 4 is a schematic diagram of the structure of the epitaxial wafer after step S6 in one embodiment of the present invention;

[0043] Figure 5 is a schematic diagram of the structure of the epitaxial wafer after step S9 in one embodiment of the present invention;

[0044] Figure 6 is a schematic diagram of the structure of an epitaxial wafer after step S101 in one embodiment of the present invention;

[0045] Figure 7 is a schematic diagram of the structure of the epitaxial wafer after step S102 in one embodiment of the present invention;

[0046] Figure 8is a schematic diagram of the structure of the epitaxial wafer after step S103 in one embodiment of the present invention;

[0047] Fig. 9 is a schematic structural diagram of a flip-chip LED chip obtained after step S11 in one embodiment of the present invention;

[0048] In the figure, 1 is an epitaxial wafer, 11 is a substrate, 12 is a first semiconductor layer, 13 is an active layer, 14 is a second semiconductor layer, 15 is an etching pit, 2 is a transparent conductive layer, 3 is a first passivation protection layer, 31 is a groove, 4 is a second photoresist layer, 41 is an evaporation hole, 411 is a first evaporation hole, 412 is a second evaporation hole, 412a is an arc-shaped side wall, 5 is a reflective layer, 6 is a protection layer, 7 is a second passivation protection layer, 71 is a first opening, 72 is a second opening, 73 is a third opening, 8 is a first electrode, and 9 is a second electrode. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0050] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0052] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0053] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0054] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the various specific processes and examples of materials provided in the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.

[0055] The present invention discloses a method for preparing a flip-chip LED chip, which comprises the following steps:

[0056] S1: providing epitaxial wafer 1;

[0057] Among them, see Figure 1, the epitaxial wafer 1 includes a substrate 11 and an epitaxial layer. Among them, the epitaxial layer includes a first semiconductor layer 12, an active layer 13 and a second semiconductor layer 14 stacked on the substrate 11 in sequence. The substrate 11 is a sapphire substrate, a silicon substrate or a SiC substrate, but is not limited thereto. The first semiconductor layer 12 may be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto. The active layer 13 may be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer or an AlGaN-AlGaN type MQW layer, but is not limited thereto. The second semiconductor layer 14 may be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto.

[0058] Preferably, in an embodiment of the present invention, the epitaxial layer may further include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer commonly used in the art, but is not limited thereto.

[0059] S2: forming a transparent conductive layer 2 on the epitaxial wafer 1;

[0060] The transparent conductive layer 2 may be a common ITO layer, IZO layer, AZO layer, ATO layer or FTO layer in the art, but is not limited thereto. Preferably, the transparent conductive layer 2 is an ITO layer. The thickness of the transparent conductive layer 2 is 5 nm to 150 nm, preferably 50 nm to 150 nm.

[0061] The transparent conductive layer 2 can be formed by a process such as magnetron sputtering, electron beam evaporation, etc., but is not limited thereto. Preferably, in one embodiment, after the transparent conductive layer 2 is formed, it is annealed at a temperature of 500° C. to 600° C. for a time of 3 min to 10 min. By annealing, its light transmittance can be optimized, and its ohmic contact with the second semiconductor layer 14 can be optimized.

[0062] S3: etching to form an etching pit 15 penetrating the first semiconductor layer 12;

[0063] Specifically, a mask (photoresist layer, SiO2 layer, etc.) can be first formed on the epitaxial wafer 1 obtained in step S2, and then the transparent conductive layer 2, the second semiconductor layer 14 and the active layer 13 in the preset area are removed by wet etching or dry etching to form etching pits 15, but not limited to this.

[0064] Preferably, in one embodiment, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S2, and after exposing and developing the photoresist layer to pattern, the transparent conductive layer 2 is first etched away by an etching solution, and then the second semiconductor layer 14 and the active layer 13 are removed by ICP etching to obtain an etched pit 15 (MESA step). After step S3, the structure of the epitaxial wafer 1 is as follows: Figure 2 shown.

[0065] S4: forming a first passivation protection layer 3 on the epitaxial wafer 1 obtained in step S3;

[0066] The first passivation protection layer 3 is composed of SiO2, Al2O3, SiN x 、SiO x N y The first passivation protection layer 3 has a thickness of 200 nm to 2000 nm, preferably 500 nm to 2000 nm.

[0067] The first passivation protection layer 3 can be formed by PECVD, ALD or MOCVD, but is not limited thereto. Preferably, a SiO2 layer is formed by PECVD as the first passivation protection layer 3 (see Figure 3 ).

[0068] S5: forming a first photoresist layer on the first passivation protection layer 3, and removing the photoresist layer above the transparent conductive layer 2 by exposure and development to obtain an etched hole;

[0069] S51: forming a first photoresist layer on the first passivation layer;

[0070] The photoresist may be a common positive photoresist or negative photoresist in the art, but is not limited thereto. Preferably, in one embodiment, a negative photoresist is used to form the first photoresist layer, which has high resolution and high aspect ratio, and can lay a good foundation for later forming a vapor deposition hole 41 with a specific morphology.

[0071] Specifically, a negative photoresist may be spin-coated on the first passivation protection layer 3 by a spin-coating process, and then cured by baking to form a first photoresist layer. The thickness of the first photoresist layer is 10 μm to 12 μm.

[0072] S52: exposing the first photoresist layer;

[0073] Specifically, during exposure, the exposure energy used is 900mJ to 1200mJ, the wavelength of the exposure light source is 320nm to 380nm, and the resolution of the exposure light source is 1.5μm to 3μm. The exposure energy used in this technical solution is relatively low, that is, an underexposure process is used, which makes the first photoresist layer near the epitaxial wafer 1 not fully cured, and then partially removed during subsequent development, forming a Figure 4 The photoresist morphology shown lays a good foundation for forming a reflective layer 5, a connecting layer and a protective layer 6 with a specific structure.

[0074] S53: developing the exposed first photoresist layer;

[0075] Specifically, the exposed epitaxial wafer 1 can be immersed in a developer to remove the first photoresist layer in the preset area. Specifically, the development time is 80s to 200s. If the development time is too long, too much photoresist will be removed, which will make the formed groove 31 too large. If the development time is too short, the groove 31 is too small, and the protective layer 6 is difficult to form a good coating on the reflective layer 5, the connecting layer, and the transparent conductive layer 2.

[0076] Preferably, in one embodiment, after development, baking and curing are performed again.

[0077] S6: removing the first passivation protection layer 3 in the etching hole to obtain a groove 31 exposing the transparent conductive layer 2, and converting the first photoresist layer into a second photoresist layer 4;

[0078] Specifically, the first passivation protection layer 3 can be removed by a dry etching process or a wet etching process, but is not limited thereto. During the etching process, the first photoresist layer is also affected by the etching gas / etching liquid, and is partially thinned, thereby obtaining the second photoresist layer 4. Specifically, the thickness of the second photoresist layer 4 is 9 μm to 11.5 μm. If too much of the first photoresist layer is removed during the etching process, the evaporation hole 41 of a specific structure cannot be formed.

[0079] Specifically, the width of the groove 31 may be smaller than the width of the transparent conductive layer 2, or may be greater than or equal to the width of the transparent conductive layer 2. Preferably, the width of the groove 31 is greater than the width of the transparent conductive layer 2, so that the side wall of the transparent conductive layer 2 is exposed after etching, and then the side wall of the transparent conductive layer 2 is protected by the protective layer 6 later, and the current distribution is further optimized.

[0080] Specifically, see Figure 4 A vapor deposition hole 41 is formed on the second photoresist layer 4 formed after etching. The vapor deposition hole 41 has a structure with a wide bottom and a narrow top, and its top width is smaller than the width of the groove 31, so as to form the reflective layer 5 in the groove 31, thereby protecting the metal (Ag, etc.) of the reflective layer 5 from migration.

[0081] More specifically, the evaporation holes 41 include a first evaporation hole 411 arranged close to the epitaxial wafer 1 and a second evaporation hole 412 arranged away from the epitaxial wafer 1; the width of the first evaporation hole 411 is greater than the width of the second evaporation hole 412, and the width of the second evaporation hole 412 is less than the width of the groove 31; based on this implementation scheme, the reflective layer 5 and the connecting layer can be formed in the groove 31, and then the protective layer 6 and the first passivation protective layer 3 can jointly form good protection in the later stage to prevent metal migration.

[0082] Furthermore, the second evaporation hole 412 has an arc-shaped side wall 412a to cover a preset portion of the first evaporation hole 411 through the arc-shaped side wall 412a; the width of the top of the second evaporation hole 412 is smaller than the width of the transparent conductive layer 2 after etching. Based on this implementation scheme, the reflective layer 5 and the connecting layer can be formed above the transparent conductive layer 2 in the groove 31, and then good protection is formed by the protective layer 6 in the later stage to prevent metal migration.

[0083] S7: sequentially evaporating the reflective layer 5 and the connecting layer in the evaporation hole 41, and converting the second photoresist layer 4 into a third photoresist layer;

[0084] Specifically, the reflective layer 5 and the connecting layer are sequentially evaporated by electron beam evaporation. During the evaporation, the reflective layer 5 and the connecting layer can be formed in the groove 31 by controlling the angle between the metal beam and the epitaxial wafer 1 and matching the evaporation hole 41 of a specific shape. Preferably, in one embodiment, the angle (first angle) between the metal beam and the epitaxial wafer 1 is 35° to 55°, preferably 40° to 50°.

[0085] The reflective layer 5 is made of Ag and / or Al, but is not limited thereto. Preferably, the reflective layer 5 is an Ag layer. The thickness of the reflective layer 5 is 20 nm to 300 nm, preferably 40 nm to 300 nm, and more preferably 100 nm to 200 nm.

[0086] The connection layer is made of one or more of Ni, Cr, and Ti, and the connection layer can optimize the connection between the reflective layer 5 and the protective layer 6, so that the protective layer 6 can better protect the reflective layer 5. Preferably, the connection layer is made of Ni or Cr. The thickness of the connection layer is 5nm to 50nm, preferably 10nm to 30nm, and more preferably 10nm to 20nm.

[0087] Specifically, in the process of forming the reflective layer 5 and the connecting layer by electron beam evaporation, the metal beam will also thin the second photoresist layer 4, thereby obtaining a third photoresist layer with a thickness of 8.5 μm to 11 μm. Accordingly, the width of the top of the second evaporation hole 412 is also expanded, which makes it easier to form a coating on the transparent conductive layer 2, the reflective layer 5 and the connecting layer when the protective layer 6 is evaporated later, thereby preventing metal migration.

[0088] S8: evaporating a protective layer 6 in the evaporation hole 41, and converting the third photoresist layer into a fourth photoresist layer;

[0089] Specifically, the protective layer 6 is evaporated by electron beam evaporation. During the evaporation, the angle (second angle) between the metal beam and the epitaxial wafer 1 is controlled to be greater than the first angle, and the evaporation holes 41 of a specific shape are matched, so that a well-covered protective layer 6 can be formed on the reflective layer 5 and the connecting layer in the groove 31. Preferably, in one embodiment, the angle (second angle) between the metal beam and the epitaxial wafer 1 is 20° to 35°, preferably 20° to 30°.

[0090] Among them, the protective layer 6 can protect the metal layer from being damaged and oxidized. Specifically, the protective layer 6 is made of one or more of Cr, Al, Ni, Ti, Pt, and Au, but is not limited thereto. Preferably, the protective layer 6 is made of one or more of Cr, Ni, Ti, Pt, and Au. More preferably, the protective layer 6 is a laminated structure, which can be Ti / Pt / Ti / Pt, Ni / Pt / Ni / Pt, etc. Specifically, the thickness of the protective layer 6 is 200nm to 800nm, preferably 200nm to 600nm.

[0091] Preferably, in one embodiment, the depth of the groove 31 is D, the thickness of the reflective layer 5 is T1, the thickness of the connecting layer is T2, the thickness of the protective layer 6 is T3, and D>T1+T2+T3. Based on this solution, the overall wrapping effect of the second passivation protective layer 7 on the metal layer, the connecting layer and the protective layer 6 can be optimized, further playing a role in preventing metal migration.

[0092] Specifically, during the process of forming the protective layer 6 by electron beam evaporation, the metal beam will also thin the second photoresist layer 4, thereby obtaining a fourth photoresist layer with a thickness of 8 μm to 11 μm.

[0093] S9: removing the fourth photoresist layer;

[0094] Specifically, the fourth photoresist layer can be removed by cleaning with a cleaning solution. In this technical solution, the photoresist layer prepared by a yellow light process is etched to form the first passivation protection layer 3 to form the reflective layer 5, the connecting layer and the protection layer 6, thereby ensuring the reliability of the process, simplifying the preparation process and reducing the production cost.

[0095] S10: forming a second passivation protection layer 7 on the epitaxial wafer 1 obtained in step S9, and forming a first opening 71 etched to the first semiconductor layer 12 and a second opening 72 etched to the protection layer 6 respectively;

[0096] Specifically, in one embodiment, step S10 includes:

[0097] S101: forming a second passivation protection layer 7 on the epitaxial wafer 1 obtained in step S9;

[0098] The second passivation protection layer 7 is made of SiO2, Al2O3, SiN x 、SiO x N y The second passivation protection layer 7 has a thickness of 100 nm to 2000 nm, preferably 100 nm to 1500 nm.

[0099] The second passivation protection layer 7 can be formed by PECVD, ALD or MOCVD, but is not limited thereto. Preferably, a SiO2 layer is formed by PECVD, or an Al2O3 layer is formed by ALD, as the second passivation protection layer 7.

[0100] S102: etching the second passivation protection layer 7 to form a third opening 73 etched to the first passivation protection layer 3 and a second opening 72 etched to the protection layer 6;

[0101] Specifically, the second passivation protection layer 7 can be removed by dry etching or wet etching to obtain the third opening 73 and the second opening 72, but the present invention is not limited thereto. Preferably, in one embodiment, the second passivation protection layer 7 is etched by ICP etching.

[0102] S103: Continue etching the first passivation protection layer 3 along the third opening 73 to obtain a first opening 71 exposing the first semiconductor layer 12;

[0103] Specifically, the first passivation protection layer 3 in the third opening 73 can be removed by a dry etching process or a wet etching process to obtain the first opening 71, but is not limited thereto. Preferably, in one embodiment, the first passivation protection layer 3 is etched by an ICP etching process. More specifically, the etching gas is SiCl4, the flow rate is 50sccm to 150sccm, the upper power of the etching is 200W to 500W, the lower power is 100W to 200W, and the etching time is 50s to 200s. Based on the above process, the first semiconductor layer 12 can be repaired and the contact resistance between the first electrode 8 and the first semiconductor layer 12 can be reduced.

[0104] S11: forming a first electrode 8 and a second electrode 9;

[0105] Specifically, the first electrode 8 and the second electrode 9 may be formed by PVD or evaporation process, but not limited thereto. The first electrode 8 and the second electrode 9 may be formed simultaneously or in steps, but not limited thereto.

[0106] The first electrode 8 is electrically connected to the first semiconductor layer 12 through the first opening 71, and the second electrode 9 is electrically connected to the protective layer 6 through the second opening 72. The first electrode 8 and the second electrode 9 are both made of one or more of Al, Cr, Ti, Ni, Pt, and Au, and have a thickness of 500nm to 3000nm.

[0107] In summary, in the method for preparing the flip-chip LED chip in this embodiment, the angle (second angle) between the metal beam and the epitaxial wafer 1 when the protective layer 6 is evaporated is controlled to be smaller than the angle (first angle) between the metal beam and the epitaxial wafer 1 when the reflector is evaporated, so that the protective layer 6 can form a good coating on the reflective layer 5, reducing the metal migration of the reflective layer 5. Moreover, through the cooperation of the evaporation hole 41 and the groove 31, the reflective layer 5 can be formed in the groove 31 formed by the first passivation protective layer 3, and then through the joint action of the first passivation protective layer 3 and the protective layer 6, the metal migration of the reflective layer 5 is greatly reduced. In addition, in this embodiment, the groove 31, the reflective layer 5, the connecting layer and the protective layer 6 are formed by a yellow light process, which ensures the reliability of the process and simplifies the preparation process.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0109] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a flip-chip LED chip, characterized in that: The following steps are involved: (1) Providing an epitaxial wafer; wherein the epitaxial wafer comprises a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; (2) forming a transparent conductive layer on the epitaxial wafer; (3) etching to form an etching pit penetrating the first semiconductor layer; (4) forming a first passivation protective layer on the epitaxial wafer obtained in step (3); (5) forming a first photoresist layer on the first passivation protection layer, and removing the photoresist layer above the transparent conductive layer by exposure and development to obtain an etched hole; (6) removing the first passivation protection layer in the etched hole to obtain a groove exposing the transparent conductive layer, and converting the first photoresist layer into a second photoresist layer, wherein the second photoresist layer is provided with a vapor deposition hole exposing the groove; the width of the top of the vapor deposition hole is smaller than the width of the groove; (7) sequentially evaporating a reflective layer and a connecting layer in the evaporation hole, and converting the second photoresist layer into a third photoresist layer; wherein during evaporation, the metal beam has a first angle with the epitaxial wafer; (8) vapor-depositing a protective layer in the vapor-deposition hole, and converting the third photoresist layer into a fourth photoresist layer; wherein during the vapor-deposition, the metal beam has a second angle with the epitaxial wafer, and the second angle is smaller than the first angle; (9) removing the fourth photoresist layer; wherein the thickness of the fourth photoresist layer is less than the thickness of the third photoresist layer, less than the thickness of the second photoresist layer, and less than the thickness of the first photoresist layer; (10) forming a second passivation protection layer on the epitaxial wafer obtained in step (9), and forming a first opening etched to the first semiconductor layer and a second opening etched to the protection layer respectively; (11) forming a first electrode and a second electrode, wherein the first electrode is electrically connected to the first semiconductor layer through the first opening, and the second electrode is electrically connected to the protective layer through the second opening.

2. The method for preparing a flip-chip LED chip according to claim 1, characterized in that: The first angle is 35° to 55°, and the second angle is 20° to 35°.

3. The method for preparing a flip-chip LED chip according to claim 1 or 2, characterized in that: The depth of the groove is D, the thickness of the reflective layer is T1, the thickness of the connecting layer is T2, the thickness of the protective layer is T3, and D>T1+T2+T3.

4. The method for preparing a flip-chip LED chip according to claim 1, characterized in that: The reflective layer is made of Ag and / or Al, and has a thickness of 40nm to 300nm; The connecting layer is made of one or more of Ni, Cr, and Ti, and has a thickness of 5nm to 50nm; The protective layer is made of one or more of Cr, Ni, Ti, Pt, and Au, and has a thickness of 200nm to 600nm; The first passivation protection layer is made of SiO2, Al2O3 or SiN x Made of, its thickness is 500nm~2000nm.

5. The method for preparing a flip-chip LED chip according to claim 1, characterized in that: The second passivation protection layer is made of SiO2, Al2O3 or SiN x Made of, its thickness is 100nm~1500nm; The transparent conductive layer is an ITO layer, and its thickness is 4nm to 150nm; The first electrode and the second electrode are both made of one or more of Al, Cr, Ti, Ni, Pt, and Au, and have a thickness of 500nm to 3000nm.

6. The method for preparing a flip-chip LED chip according to claim 1, characterized in that: The evaporation holes include a first evaporation hole arranged close to the epitaxial wafer and a second evaporation hole arranged away from the epitaxial wafer; the width of the first evaporation hole is greater than the width of the second evaporation hole, and the width of the second evaporation hole is less than the width of the groove; The width of the groove is greater than the width of the transparent conductive layer after etching.

7. The method for preparing a flip-chip LED chip according to claim 6, characterized in that: The second evaporation hole has an arc-shaped side wall, so that a predetermined portion of the first evaporation hole is covered by the arc-shaped side wall; The width of the top of the second evaporation hole is smaller than the width of the transparent conductive layer after etching.

8. The method for preparing a flip-chip LED chip according to claim 6 or 7, characterized in that: The thickness of the first photoresist layer is 10 μm to 12 μm; the thickness of the second photoresist layer is 9 μm to 11.5 μm, the thickness of the third photoresist layer is 8.5 μm to 11 μm, and the thickness of the fourth photoresist layer is 8 μm to 11 μm.

9. The method for preparing a flip-chip LED chip according to claim 1, wherein: Step (10) comprises: (10.1) forming a second passivation protective layer on the epitaxial wafer obtained in step (9); (10.2) etching the second passivation protection layer to form a third opening etched to the first passivation protection layer and a second opening etched to the protection layer; (10.3) Continue etching the first passivation protection layer along the third opening to obtain a first opening exposing the first semiconductor layer, wherein the first semiconductor layer is etched by SiCl4 with a flow rate of 50sccm to 150sccm, an upper etching power of 200W to 500W, a lower etching power of 100W to 200W, and an etching time of 50s to 200s.

10. A flip-chip LED chip, characterized in that: The flip-chip LED chip is prepared by the method for preparing the flip-chip LED chip as described in any one of claims 1 to 9.

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