Flip LED Chip and Its Fabrication Method

Abstract

This invention relates to the field of optoelectronic manufacturing technology, specifically disclosing a flip-chip LED and its fabrication method. The fabrication method includes: providing an epitaxial wafer; forming a transparent conductive layer; etching to form etching pits; forming a first passivation protective layer; forming a first photoresist layer; etching to form a groove exposing the transparent conductive layer and forming a vapor deposition hole; the width of the top of the vapor deposition hole is smaller than the width of the groove; sequentially vapor deposition a reflective layer and a bonding layer within the vapor deposition hole, during which the metal beam and the epitaxial wafer have a first angle; vapor deposition a protective layer within the vapor deposition hole, during which the metal beam and the epitaxial wafer have a second angle, the second angle being smaller than the first angle; removing a fourth photoresist layer; forming a second passivation protective layer; etching an opening; and forming a first electrode and a second electrode. By implementing this invention, the composite formation of the first passivation layer and the protective layer can effectively encapsulate the reflective layer, significantly reducing metal migration in the reflective layer and improving reliability.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic manufacturing technology, and in particular to a flip-chip LED and its fabrication method. Background Technology

[0002] Flip-chip LEDs are a relatively advanced optoelectronic semiconductor technology, with core advantages in improved luminous efficacy and heat dissipation. Compared to traditional LEDs, flip-chip LEDs utilize a flip-chip structure, meaning the light-emitting surface of the LED chip faces downwards. This design effectively reduces optical path loss and improves light output efficiency and brightness. Furthermore, flip-chip LEDs excel in heat dissipation. Traditional LEDs, with their heat dissipation surface on the front, often suffer from limited heat dissipation. Flip-chip LEDs, however, can directly conduct heat through the metal layer to the heat dissipation substrate, achieving more efficient heat dissipation. This improvement not only extends the LED's lifespan but also enhances its long-term stability and luminous efficacy.

[0003] Flip-chip LEDs, through their innovative structural design, exhibit significant advantages in luminous efficacy, heat dissipation, and color uniformity. They not only improve lighting quality but also contribute to energy conservation and long lifespan, leading to their widespread application in modern lighting and display technologies and driving further development of LED technology. However, the manufacturing process of flip-chip LEDs is typically very complex, and issues such as the easy migration of metallic silver pose challenges, hindering the further development of flip-chip LEDs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for preparing a flip-chip LED with high reliability.

[0005] Another technical problem that this invention aims to solve is to provide a flip-chip LED.

[0006] To address the aforementioned technical problems, this invention provides a method for fabricating a flip-chip LED, comprising the following steps:

[0007] (1) Provide an epitaxial wafer; wherein the epitaxial wafer includes a substrate and a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on the substrate;

[0008] (2) A transparent conductive layer is formed on the epitaxial wafer;

[0009] (3) Etching forms an etching pit that extends into the first semiconductor layer;

[0010] (4) A first passivation protective layer is formed on the epitaxial wafer obtained in step (3);

[0011] (5) A first photoresist layer is formed on the first passivation protective layer, and the photoresist layer above the transparent conductive layer is removed by exposure and development to obtain an etched hole;

[0012] (6) Remove the first passivation protective layer inside the etched hole to obtain a groove that exposes the transparent conductive layer, and convert the first photoresist layer into a second photoresist layer. The second photoresist layer is provided with a vapor deposition hole that exposes the groove. The width of the top of the vapor deposition hole is smaller than the width of the groove.

[0013] (7) A reflective layer and a connecting layer are sequentially deposited in the evaporation hole, and the second photoresist layer is transformed into a third photoresist layer; wherein, during evaporation, the metal beam and the epitaxial wafer have a first angle;

[0014] (8) A protective layer is deposited in the evaporation hole, and the third photoresist layer is transformed into a fourth photoresist layer; wherein, during evaporation, the metal beam and the epitaxial wafer have a second angle, the second angle being smaller than the first angle;

[0015] (9) Remove the fourth photoresist layer; wherein the thickness of the fourth photoresist layer is less than the thickness of the third photoresist layer, less than the thickness of the second photoresist layer, and less than the thickness of the first photoresist layer.

[0016] (10) A second passivation protection layer is formed on the epitaxial wafer obtained in step (9), and a first opening etched to the first semiconductor layer and a second opening etched to the protection layer are formed respectively.

[0017] (11) A first electrode and a second electrode are formed, wherein the first electrode is electrically connected to the first semiconductor layer through a first opening, and the second electrode is electrically connected to the protective layer through a second opening.

[0018] As an improvement to the above technical solution, the first angle is 35° to 55°, and the second angle is 20° to 35°.

[0019] As an improvement to the above technical solution, the depth of the groove is D, the thickness of the reflective layer is T1, the thickness of the connecting layer is T2, and the thickness of the protective layer is T3, where D > T1 + T2 + T3.

[0020] As an improvement to the above technical solution, the reflective layer is made of Ag and / or Al, and its thickness is 40nm to 300nm;

[0021] The connecting layer is made of one or more of Ni, Cr, and Ti, and its thickness is 5 nm to 50 nm.

[0022] The protective layer is made of one or more of Cr, Ni, Ti, Pt, and Au, and its thickness is 200 nm to 600 nm.

[0023] The first passivation protective layer is composed of SiO2, Al2O3 or SiN x It is made with a thickness of 500nm to 2000nm.

[0024] As an improvement to the above technical solution, the second passivation protective layer is made of SiO2, Al2O3 or SiN. x It is manufactured with a thickness of 100nm to 1500nm;

[0025] The transparent conductive layer is an ITO layer with a thickness of 4nm to 150nm;

[0026] The first electrode and the second electrode are both made of one or more of Al, Cr, Ti, Ni, Pt and Au, and their thickness is 500 nm to 3000 nm.

[0027] As an improvement to the above technical solution, the vapor deposition hole includes a first vapor deposition hole disposed close to the epitaxial wafer and a second vapor deposition hole disposed away from the epitaxial wafer; the width of the first vapor deposition hole is greater than the width of the second vapor deposition hole, and the width of the second vapor deposition hole is less than the width of the groove;

[0028] The width of the groove is greater than the width of the transparent conductive layer after etching.

[0029] As an improvement to the above technical solution, the second vapor deposition hole has an arc-shaped sidewall to cover a predetermined portion of the first vapor deposition hole through the arc-shaped sidewall.

[0030] The width of the top of the second vapor-deposited hole is smaller than the width of the transparent conductive layer after etching.

[0031] As an improvement to the above technical solution, the thickness of the first photoresist layer is 10μm to 12μm; the thickness of the second photoresist layer is 9μm to 11.5μm; the thickness of the third photoresist layer is 8.5μm to 11μm; and the thickness of the fourth photoresist layer is 8μm to 11μm.

[0032] As an improvement to the above technical solution, step (10) includes:

[0033] (10.1) A second passivation protective layer is formed on the epitaxial wafer obtained in step (9);

[0034] (10.2) Etch the second passivation protective layer to form a third opening etched to the first passivation protective layer and a second opening etched to the protective layer;

[0035] (10.3) Continue etching the first passivation protective layer along the third opening to obtain a first opening that exposes the first semiconductor layer. The first semiconductor layer is etched with SiCl4 at a flow rate of 50 sccm to 150 sccm, an upper etching power of 200 W to 500 W, a lower etching power of 100 W to 200 W, and an etching time of 50 s to 200 s.

[0036] Accordingly, the present invention also discloses a flip-chip LED, which is prepared by the above-described flip-chip LED preparation method.

[0037] Implementing this invention has the following beneficial effects:

[0038] In one embodiment of the present invention, the method for fabricating a flip-chip LED is such that the angle between the metal beam and the epitaxial wafer (second angle) during the deposition of the protective layer is smaller than the angle between the metal beam and the epitaxial wafer (first angle) during the deposition of the reflector. This allows the protective layer to effectively cover the reflective layer, reducing metal migration in the reflective layer. Furthermore, the combination of the deposition holes and grooves allows the reflective layer to form within the grooves created by the first passivation protective layer. Through the combined effect of the first passivation protective layer and the protective layer, metal migration in the reflective layer is significantly reduced. In addition, this embodiment uses a single photolithography process to form the grooves, reflective layer, connecting layer, and protective layer, ensuring process reliability and simplifying the fabrication process. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the epitaxial wafer structure in one embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the epitaxial wafer structure after step S3 in one embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of the epitaxial wafer structure after step S4 in one embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of the epitaxial wafer structure after step S6 in one embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of the epitaxial wafer structure after step S9 in one embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of the epitaxial wafer structure after step S101 in one embodiment of the present invention;

[0045] Figure 7 This is a schematic diagram of the epitaxial wafer structure after step S102 in one embodiment of the present invention;

[0046] Figure 8This is a schematic diagram of the epitaxial wafer structure after step S103 in one embodiment of the present invention;

[0047] Figure 9 This is a schematic diagram of the structure of the flip-chip LED obtained after step S11 in one embodiment of the present invention;

[0048] In the figure, 1 is the epitaxial wafer, 11 is the substrate, 12 is the first semiconductor layer, 13 is the active layer, 14 is the second semiconductor layer, 15 is the etching pit, 2 is the transparent conductive layer, 3 is the first passivation protection layer, 31 is the groove, 4 is the second photoresist layer, 41 is the vapor deposition hole, 411 is the first vapor deposition hole, 412 is the second vapor deposition hole, 412a is the arc-shaped sidewall, 5 is the reflective layer, 6 is the protective layer, 7 is the second passivation protection layer, 71 is the first opening, 72 is the second opening, 73 is the third opening, 8 is the first electrode, and 9 is the second electrode. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0050] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0053] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0054] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0055] This invention discloses a method for fabricating a flip-chip LED, which includes the following steps:

[0056] S1: Provide epitaxial wafer 1;

[0057] Among them, see Figure 1The epitaxial wafer 1 includes a substrate 11 and an epitaxial layer. The epitaxial layer includes a first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 sequentially stacked on the substrate 11. The substrate 11 can be a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited to these. The first semiconductor layer 12 can be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited to these. The active layer 13 can be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer, or an AlGaN-AlGaN type MQW layer, but is not limited to these. The second semiconductor layer 14 can be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited to these.

[0058] Preferably, in one embodiment of the present invention, the epitaxial layer may further include one or more of the buffer layer, intrinsic semiconductor layer, stress buffer layer, electron blocking layer, and ohmic contact layer commonly used in the art, but is not limited thereto.

[0059] S2: A transparent conductive layer 2 is formed on the epitaxial wafer 1;

[0060] The transparent conductive layer 2 can be a commonly used ITO layer, IZO layer, AZO layer, ATO layer, or FTO layer, but is not limited to these. Preferably, the transparent conductive layer 2 is an ITO layer. The thickness of the transparent conductive layer 2 is 5nm to 150nm, preferably 50nm to 150nm.

[0061] The transparent conductive layer 2 can be formed by processes such as magnetron sputtering and electron beam evaporation, but is not limited thereto. Preferably, in one embodiment, after the transparent conductive layer 2 is formed, it is annealed at a temperature of 500°C to 600°C for 3 to 10 minutes. Annealing can optimize its light transmittance and the ohmic contact between it and the second semiconductor layer 14.

[0062] S3: Etching to form an etching pit 15 that extends through the first semiconductor layer 12;

[0063] Specifically, a mask (photoresist layer, SiO2 layer, etc.) can be formed on the epitaxial wafer 1 obtained in step S2 first, and then the transparent conductive layer 2, the second semiconductor layer 14 and the active layer 13 in the preset area can be removed by wet etching or dry etching to form etching pits 15, but it is not limited to this.

[0064] Preferably, in one embodiment, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S2. After exposure, development, and patterning, the transparent conductive layer 2 is first removed by etching with an etchant, and then the second semiconductor layer 14 and the active layer 13 are removed by ICP etching to obtain etch pits 15 (MESA steps). The structure of the epitaxial wafer 1 after step S3 is as follows: Figure 2 As shown.

[0065] S4: A first passivation protective layer 3 is formed on the epitaxial wafer 1 obtained in step S3;

[0066] The first passivation protective layer 3 is composed of SiO2, Al2O3, and SiN. x SiO x N y It may be made of one or more of the following, but is not limited thereto. The thickness of the first passivation protective layer 3 is 200nm to 2000nm, preferably 500nm to 2000nm.

[0067] The first passivation protective layer 3 can be formed by PECVD, ALD, or MOCVD, but is not limited to these methods. Preferably, a SiO2 layer is formed by PECVD as the first passivation protective layer 3 (see [link to documentation]). Figure 3 ).

[0068] S5: A first photoresist layer is formed on the first passivation protective layer 3, and the photoresist layer above the transparent conductive layer 2 is removed by exposure and development to obtain an etched hole;

[0069] S51: A first photoresist layer is formed on the first passivation layer;

[0070] The photoresist can be a common positive or negative photoresist in the art, but is not limited thereto. Preferably, in one embodiment, a negative photoresist is used to form the first photoresist layer. The negative photoresist has high resolution and a high aspect ratio, which can lay a good foundation for the subsequent formation of vapor-deposited holes 41 with specific morphologies.

[0071] Specifically, a negative photoresist can be spin-coated onto the first passivation protective layer 3 using a spin-coating process, and then cured by baking to form the first photoresist layer. The thickness of the first photoresist layer is 10μm to 12μm.

[0072] S52: Expose the first photoresist layer;

[0073] Specifically, during exposure, the exposure energy used is 900mJ to 1200mJ, the wavelength of the exposure light source is 320nm to 380nm, and the resolution of the exposure light source is 1.5μm to 3μm. The exposure energy used in this technical solution is relatively low, i.e., an underexposure process is employed. This results in the first photoresist layer near epitaxial wafer 1 not being fully cured, thus allowing for partial removal during subsequent development, forming a layer as shown... Figure 4 The photoresist morphology shown lays a good foundation for forming the reflective layer 5, the connecting layer and the protective layer 6 with specific structures.

[0074] S53: Develop the first photoresist layer after exposure;

[0075] Specifically, the exposed epitaxial wafer 1 can be immersed entirely in the developing solution to remove the first photoresist layer in the preset area. Specifically, the developing time is 80s to 200s. If the developing time is too long, too much photoresist will be removed, resulting in an excessively large groove 31. If the developing time is too short, the groove 31 will be too small, and the protective layer 6 will have difficulty forming a good coating on the reflective layer 5, the connecting layer, and the transparent conductive layer 2.

[0076] Preferably, in one embodiment, after development, a second baking and curing process is performed.

[0077] S6: Remove the first passivation protective layer 3 inside the etched hole to obtain a groove 31 that exposes the transparent conductive layer 2, and transform the first photoresist layer into the second photoresist layer 4.

[0078] Specifically, the first passivation protective layer 3 can be removed using a dry etching process or a wet etching process, but is not limited to these. During the etching process, the first photoresist layer is also subjected to the etching gas / etching liquid, resulting in partial thinning and thus obtaining the second photoresist layer 4. Specifically, the thickness of the second photoresist layer 4 is 9μm to 11.5μm. If too much of the first photoresist layer is removed during this etching process, the vapor-deposited holes 41 with the specific structure cannot be formed.

[0079] Specifically, the width of the groove 31 can be less than the width of the transparent conductive layer 2, or greater than or equal to the width of the transparent conductive layer 2. Preferably, the width of the groove 31 is greater than the width of the transparent conductive layer 2, so that the sidewalls of the transparent conductive layer 2 are exposed after etching, and then the protective layer 6 is formed on the sidewalls of the transparent conductive layer 2 for protection in the later stage, while further optimizing the current distribution.

[0080] Specifically, see Figure 4 A vapor deposition hole 41 is formed on the second photoresist layer 4 formed after etching. The vapor deposition hole 41 has a structure that is wider at the bottom and narrower at the top, and its top width is smaller than the width of the groove 31, so that the reflective layer 5 is formed in the groove 31, thereby protecting the metal (Ag, etc.) of the reflective layer 5 from migration.

[0081] More specifically, the vapor deposition hole 41 includes a first vapor deposition hole 411 disposed near the epitaxial wafer 1 and a second vapor deposition hole 412 disposed away from the epitaxial wafer 1; the width of the first vapor deposition hole 411 is greater than the width of the second vapor deposition hole 412, and the width of the second vapor deposition hole 412 is less than the width of the groove 31; based on this embodiment, the reflective layer 5 and the connecting layer can be formed in the groove 31, and then the protective layer 6 and the first passivation protective layer 3 together form good protection to prevent metal migration.

[0082] Furthermore, the second vapor deposition hole 412 has an arc-shaped sidewall 412a to cover the first vapor deposition hole 411 in the preset portion through the arc-shaped sidewall 412a; the width of the top of the second vapor deposition hole 412 is smaller than the width of the transparent conductive layer 2 after etching. Based on this embodiment, the reflective layer 5 and the connecting layer can be formed above the transparent conductive layer 2 in the groove 31, and then a good protection can be formed by the protective layer 6 in the later stage to prevent metal migration.

[0083] S7: The reflective layer 5 and the connecting layer are sequentially vapor-deposited in the vapor deposition hole 41, and the second photoresist layer 4 is transformed into the third photoresist layer.

[0084] Specifically, the reflective layer 5 and the connecting layer are sequentially deposited by electron beam evaporation. During evaporation, by controlling the angle between the metal beam and the epitaxial wafer 1, and using a evaporation hole 41 of a specific shape, the reflective layer 5 and the connecting layer can be formed within the groove 31. Preferably, in one embodiment, the angle (first angle) between the metal beams and the epitaxial wafers 1 is 35° to 55°, and more preferably 40° to 50°.

[0085] The reflective layer 5 is made of Ag and / or Al, but is not limited thereto. Preferably, the reflective layer 5 is an Ag layer. The thickness of the reflective layer 5 is 20 nm to 300 nm, preferably 40 nm to 300 nm, and more preferably 100 nm to 200 nm.

[0086] The connecting layer is made of one or more of Ni, Cr, and Ti. The connecting layer optimizes the connection between the reflective layer 5 and the protective layer 6, allowing the protective layer 6 to better protect the reflective layer 5. Preferably, the connecting layer is made of Ni or Cr. The thickness of the connecting layer is 5 nm to 50 nm, more preferably 10 nm to 30 nm, and even more preferably 10 nm to 20 nm.

[0087] Specifically, during the electron beam evaporation process to form the reflective layer 5 and the connecting layer, the metal beam also thins the second photoresist layer 4, resulting in a third photoresist layer with a thickness of 8.5 μm to 11 μm. Correspondingly, the width of the top of the second evaporation hole 412 is also increased, which makes it easier to form a coating of the transparent conductive layer 2, the reflective layer 5, and the connecting layer during the subsequent evaporation of the protective layer 6, thus preventing metal migration.

[0088] S8: Deposit the protective layer 6 in the evaporation hole 41 and transform the third photoresist layer into the fourth photoresist layer;

[0089] Specifically, the protective layer 6 is deposited by electron beam evaporation. During evaporation, by controlling the angle (second angle) between the metal beam and the epitaxial wafer 1 to be greater than the first angle, and in conjunction with the evaporation holes 41 of a specific shape, a well-covered protective layer 6 can be formed on the reflective layer 5 and the connecting layer within the groove 31. Preferably, in one embodiment, the angle (second angle) between the metal beam and the epitaxial wafer 1 is 20° to 35°, more preferably 20° to 30°.

[0090] The protective layer 6 protects the metal layer from damage and oxidation. Specifically, the protective layer 6 is made of one or more of Cr, Al, Ni, Ti, Pt, and Au, but is not limited thereto. Preferably, the protective layer 6 is made of one or more of Cr, Ni, Ti, Pt, and Au. More preferably, the protective layer 6 has a stacked structure, such as Ti / Pt / Ti / Pt, Ni / Pt / Ni / Pt, etc. Specifically, the thickness of the protective layer 6 is 200 nm to 800 nm, preferably 200 nm to 600 nm.

[0091] Preferably, in one embodiment, the depth of the groove 31 is D, the thickness of the reflective layer 5 is T1, the thickness of the connecting layer is T2, and the thickness of the protective layer 6 is T3, where D > T1 + T2 + T3. Based on this scheme, the overall encapsulation effect of the second passivation protective layer 7 on the metal layer, connecting layer, and protective layer 6 can be optimized, further preventing metal migration.

[0092] Specifically, during the process of electron beam evaporation to form the protective layer 6, the metal beam also thins the second photoresist layer 4, thereby obtaining a fourth photoresist layer with a thickness of 8μm to 11μm.

[0093] S9: Remove the fourth photoresist layer;

[0094] Specifically, the fourth photoresist layer can be removed by cleaning with a cleaning solution. In this technical solution, the photoresist layer prepared by a single photolithography process is etched to form the first passivation protective layer 3, thereby forming the reflective layer 5, the connecting layer, and the protective layer 6. This ensures the reliability of the process, simplifies the preparation process, and reduces production costs.

[0095] S10: A second passivation protection layer 7 is formed on the epitaxial wafer 1 obtained in step S9, and a first opening 71 etched to the first semiconductor layer 12 and a second opening 72 etched to the protection layer 6 are formed respectively.

[0096] Specifically, in one embodiment, step S10 includes:

[0097] S101: A second passivation protective layer 7 is formed on the epitaxial wafer 1 obtained in step S9;

[0098] The second passivation protective layer 7 is composed of SiO2, Al2O3, and SiN. x SiO x N y It may be made of one or more of the following, but is not limited thereto. The thickness of the second passivation protective layer 7 is 100nm to 2000nm, preferably 100nm to 1500nm.

[0099] The second passivation protective layer 7 can be formed by PECVD, ALD, or MOCVD, but is not limited to these methods. Preferably, a SiO2 layer is formed by PECVD, or an Al2O3 layer is formed by ALD, as the second passivation protective layer 7.

[0100] S102: Etch the second passivation protection layer 7 to form a third opening 73 etched to the first passivation protection layer 3 and a second opening 72 etched to the protection layer 6;

[0101] Specifically, the second passivation protective layer 7 can be removed by a dry etching process or a wet etching process to obtain the third opening 73 and the second opening 72, but is not limited thereto. Preferably, in one embodiment, the second passivation protective layer 7 is etched by an ICP etching process.

[0102] S103: Continue etching the first passivation protection layer 3 along the third opening 73 to obtain the first opening 71 that exposes the first semiconductor layer 12;

[0103] Specifically, the first passivation layer 3 within the third opening 73 can be removed using a dry etching process or a wet etching process to obtain the first opening 71, but this is not limited to these methods. Preferably, in one embodiment, the first passivation layer 3 is etched using an ICP etching process. More specifically, the etching gas is SiCl4, with a flow rate of 50 sccm to 150 sccm, an upper etching power of 200 W to 500 W, a lower etching power of 100 W to 200 W, and an etching time of 50 s to 200 s. Based on the above process, the first semiconductor layer 12 can be repaired, reducing the contact resistance between the first electrode 8 and the first semiconductor layer 12.

[0104] S11: Form the first electrode 8 and the second electrode 9;

[0105] Specifically, the first electrode 8 and the second electrode 9 can be formed by PVD or vapor deposition processes, but are not limited thereto. The first electrode 8 and the second electrode 9 can be formed simultaneously or in steps, but are not limited thereto.

[0106] The first electrode 8 is electrically connected to the first semiconductor layer 12 through the first opening 71, and the second electrode 9 is electrically connected to the protective layer 6 through the second opening 72. Both the first electrode 8 and the second electrode 9 are made of one or more of Al, Cr, Ti, Ni, Pt, and Au, and their thickness is 500 nm to 3000 nm.

[0107] In summary, in the flip-chip fabrication method of this embodiment, the angle (second angle) between the metal beam and the epitaxial wafer 1 during the deposition of the protective layer 6 is controlled to be smaller than the angle (first angle) between the metal beam and the epitaxial wafer 1 during the deposition of the reflector. This allows the protective layer 6 to effectively cover the reflective layer 5, reducing metal migration in the reflective layer 5. Furthermore, the cooperation between the deposition hole 41 and the groove 31 allows the reflective layer 5 to be formed within the groove 31 formed by the first passivation protective layer 3. Through the combined action of the first passivation protective layer 3 and the protective layer 6, metal migration in the reflective layer 5 is significantly reduced. In addition, this embodiment uses a single photolithography process to form the groove 31, the reflective layer 5, the connecting layer, and the protective layer 6, ensuring process reliability and simplifying the fabrication process.

[0108] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0109] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for fabricating a flip-chip LED, characterized in that, Includes the following steps: (1) Provide an epitaxial wafer; wherein the epitaxial wafer includes a substrate and a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on the substrate; (2) A transparent conductive layer is formed on the epitaxial wafer; (3) Etching forms an etching pit that extends into the first semiconductor layer; (4) A first passivation protective layer is formed on the epitaxial wafer obtained in step (3); (5) A first photoresist layer is formed on the first passivation protective layer, and the photoresist layer above the transparent conductive layer is removed by exposure and development to obtain an etched hole; (6) Remove the first passivation protective layer in the etched hole to obtain a groove that exposes the transparent conductive layer, and convert the first photoresist layer into a second photoresist layer. The second photoresist layer is provided with a vapor deposition hole that exposes the groove. The width of the top of the vapor deposition hole is smaller than the width of the groove. (7) A reflective layer and a connecting layer are sequentially deposited in the evaporation hole, and the second photoresist layer is transformed into a third photoresist layer; wherein, during evaporation, the metal beam and the epitaxial wafer have a first angle; (8) A protective layer is deposited in the evaporation hole, and the third photoresist layer is transformed into a fourth photoresist layer; wherein, during evaporation, the metal beam and the epitaxial wafer have a second angle, the second angle being smaller than the first angle; (9) Remove the fourth photoresist layer; wherein the thickness of the fourth photoresist layer is less than the thickness of the third photoresist layer, less than the thickness of the second photoresist layer, and less than the thickness of the first photoresist layer; (10) A second passivation protection layer is formed on the epitaxial wafer obtained in step (9), and a first opening etched to the first semiconductor layer and a second opening etched to the protection layer in step (8) are formed respectively; (11) Form a first electrode and a second electrode, wherein the first electrode is electrically connected to the first semiconductor layer through a first opening, and the second electrode is electrically connected to the protective layer in step (8) through a second opening.

2. The method for fabricating a flip-chip LED as described in claim 1, characterized in that, The first angle is 35°~55°, and the second angle is 20°~35°.

3. The method for fabricating a flip-chip LED as described in claim 1 or 2, characterized in that, The depth of the groove is D, the thickness of the reflective layer is T1, the thickness of the connecting layer is T2, and the thickness of the protective layer in step (8) is T3, where D > T1 + T2 + T3.

4. The method for fabricating a flip-chip LED as described in claim 1, characterized in that, The reflective layer is made of Ag and / or Al and has a thickness of 40 nm to 300 nm. The connecting layer is made of one or more of Ni, Cr, and Ti, and its thickness is 5nm~50nm; The protective layer in step (8) is made of one or more of Cr, Ni, Ti, Pt, and Au, and its thickness is 200 nm to 600 nm. The first passivation protective layer is composed of SiO2, Al2O3 or SiN x It is made with a thickness of 500nm~2000nm.

5. The method for fabricating a flip-chip LED as described in claim 1, characterized in that, The second passivation protective layer is composed of SiO2, Al2O3 or SiN x It is manufactured with a thickness of 100nm~1500nm; The transparent conductive layer is an ITO layer with a thickness of 4nm~150nm; The first electrode and the second electrode are both made of one or more of Al, Cr, Ti, Ni, Pt and Au, and their thickness is 500nm~3000nm.

6. The method for fabricating a flip-chip LED as described in claim 1, characterized in that, The vapor deposition hole includes a first vapor deposition hole disposed near the epitaxial wafer and a second vapor deposition hole disposed away from the epitaxial wafer; the width of the first vapor deposition hole is greater than the width of the second vapor deposition hole, and the width of the second vapor deposition hole is less than the width of the groove; The width of the groove is greater than the width of the transparent conductive layer after etching.

7. The method for fabricating a flip-chip LED as described in claim 6, characterized in that, The second vapor deposition hole has an arc-shaped sidewall to cover a predetermined portion of the first vapor deposition hole through the arc-shaped sidewall; The width of the top of the second vapor-deposited hole is smaller than the width of the transparent conductive layer after etching.

8. The method for fabricating a flip-chip LED as described in claim 6 or 7, characterized in that, The thickness of the first photoresist layer is 10μm~12μm; the thickness of the second photoresist layer is 9μm~11.5μm; the thickness of the third photoresist layer is 8.5μm~11μm; and the thickness of the fourth photoresist layer is 8μm~11μm.

9. The method for fabricating a flip-chip LED as described in claim 1, characterized in that, Step (10) includes: (10.1) A second passivation protective layer is formed on the epitaxial wafer obtained in step (9); (10.2) Etch the second passivation protective layer to form a third opening etched to the first passivation protective layer and a second opening etched to the protective layer; (10.3) Continue etching the first passivation protective layer along the third opening to obtain a first opening that exposes the first semiconductor layer. The first semiconductor layer is etched with SiCl4 at a flow rate of 50 sccm to 150 sccm, an upper etching power of 200 W to 500 W, a lower etching power of 100 W to 200 W, and an etching time of 50 s to 200 s.

10. A flip-chip LED, characterized in that, It is prepared by the method for preparing a flip-chip LED as described in any one of claims 1 to 9.

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