A memristor with sub-1 nanometer × sub-1 nanometer electrodes and a method for preparing the same

Abstract

The present invention provides a memristor with a sub-1 nanometer × sub-1 nanometer electrode and a preparation method thereof, which relates to the technical field of memristors. The memristor comprises: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, a sub-1 nanometer electrode, a high dielectric constant insulating layer and a contact electrode; the substrate insulating layer is arranged on the substrate; the low dielectric constant insulating layer is arranged on the substrate insulating layer; the sub-1 nanometer electrode is arranged on the low dielectric constant insulating layer and is composed of a single layer or a few layers of two-dimensional material, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material; the high dielectric constant insulating layer is arranged on the electrode and serves as a dielectric layer of the memristor; the contact electrode is arranged on the two-dimensional material and is used to connect the two-dimensional material. The memristor provided by the present invention achieves the indicators of the sub-1 nanometer × sub-1 nanometer memristor, which is helpful to promote the integration of ultra-small size memristors.

Description

Technical Field

[0001] The present invention relates to the technical field of memristors, and in particular to a memristor with sub-1 nanometer×sub-1 nanometer electrodes and a preparation method thereof. Background Art

[0002] In the field of information technology and semiconductor manufacturing, as the demand for data storage and processing continues to grow, the performance requirements for memory devices are also getting higher and higher. Memristors are considered to be an important direction for future storage technology due to their unique physical properties and storage capacity. With the development of Moore's Law, device miniaturization has been a consistent trend in recent years. In recent years, researchers have been committed to developing memristor technology with smaller size, higher integration and lower power consumption.

[0003] In the existing technology, Eric Pop's group published a 1-nanometer memristor on carbon nanotubes (CNT), demonstrating the potential for miniaturization of memristors. However, the solution in this work cannot be applied to large-scale array preparation. Nature Nanotechnology reported a memristor cross array with a 6-nanometer half-line width and a 2-nanometer feature size, which can be prepared on a large scale. However, there is still a certain gap from the sub-nanometer size.

[0004] How to promote the integration of ultra-small memristors is a technical problem that needs to be solved at present. Summary of the invention

[0005] The present invention provides a memristor with sub-1 nanometer×sub-1 nanometer electrodes and a preparation method thereof, so as to solve the defects existing in the prior art.

[0006] The present invention provides a memristor with sub-1 nanometer × sub-1 nanometer electrodes, comprising: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, a sub-1 nanometer electrode, a high dielectric constant insulating layer and a contact electrode;

[0007] The substrate insulating layer is disposed on the substrate;

[0008] The low dielectric constant insulating layer is disposed on the substrate insulating layer;

[0009] The sub-1 nanometer electrode is disposed on the low dielectric constant insulating layer and is composed of a single layer or a few layers of a two-dimensional material, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material;

[0010] The high dielectric constant insulating layer is disposed on the electrode and serves as a dielectric layer of the memristor;

[0011] The contact electrode is disposed on the two-dimensional material and is used for connecting the two-dimensional material.

[0012] According to the present invention, a memristor having sub-1 nanometer×sub-1 nanometer electrodes is provided, wherein the sub-1 nanometer electrodes are made of vertical graphene material.

[0013] According to a memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, the interdigital structure of the memristor is formed by alternately stacking sub-1 nanometer electrodes and the high dielectric constant insulating layers and crossing each other, and the cross-sectional area of ​​the interdigital structure is sub-1 nanometer. 2 .

[0014] According to the present invention, a memristor with sub-1 nanometer × sub-1 nanometer electrodes is provided. The memristor is completed by face-to-face wafer-level bonding of two wafers with sub-1 nanometer electrodes, wherein one wafer is bonded to the other wafer after being rotated 90 degrees after depositing a dielectric layer.

[0015] According to a memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, each wafer comprises: a step substrate, a vertical two-dimensional material, a low dielectric constant insulating layer, and a contact electrode;

[0016] The step base comprises: a step side wall and a horizontal portion;

[0017] The vertical two-dimensional material is applied to the side wall of the step;

[0018] The low dielectric constant insulating layer is used to backfill the step structure and form a smooth surface;

[0019] The contact electrode is arranged on the vertical two-dimensional material.

[0020] The present invention also provides a method for preparing a memristor having a sub-1 nanometer × sub-1 nanometer electrode, wherein the memristor comprises: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, a sub-1 nanometer electrode, a high dielectric constant insulating layer and a contact electrode;

[0021] The method comprises:

[0022] forming the substrate insulating layer on the substrate;

[0023] forming the low dielectric constant insulating layer on the substrate insulating layer;

[0024] Using a step wet transfer process, a single layer or a few layers of two-dimensional material are transferred to a preset position of the low dielectric constant insulating layer to form the sub-1 nanometer electrode, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material;

[0025] forming the high dielectric constant insulating layer on the electrode, the high dielectric constant insulating layer being the dielectric layer of the memristor;

[0026] The contact electrode is formed on the two-dimensional material, and the contact electrode is used to connect the two-dimensional material.

[0027] According to a method for preparing a memristor having sub-1 nanometer×sub-1 nanometer electrodes provided by the present invention, the sub-1 nanometer electrodes are vertical graphene materials.

[0028] According to a method for preparing a memristor having sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, the interdigital structure of the memristor is formed by alternately stacking sub-1 nanometer electrodes and the high dielectric constant insulating layers and crossing each other, and the cross-sectional area of ​​the interdigital structure is sub-1 nanometer 2 .

[0029] According to a method for preparing a memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, the memristor is completed by face-to-face wafer-level bonding of two wafers with sub-1 nanometer electrodes, wherein one wafer is bonded to the other wafer after being rotated 90 degrees after depositing a dielectric layer.

[0030] According to a method for preparing a memristor having sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, each wafer comprises: a step substrate, a vertical two-dimensional material, a low dielectric constant insulating layer, and a contact electrode;

[0031] The wafer preparation process includes:

[0032] Providing a wafer having a step substrate, wherein the step substrate comprises: a step sidewall and a horizontal portion;

[0033] forming a low dielectric constant insulating layer in a step shape on the step substrate as a supporting layer;

[0034] Transferring the two-dimensional material to the sidewall of the step by wet transfer to form the vertical two-dimensional material;

[0035] Performing photolithographic patterning on the vertical two-dimensional material to form a preset structural area;

[0036] depositing the contact electrode on the vertical two-dimensional material;

[0037] Backfilling the low dielectric constant insulating layer in the step region and completely filling the step structure;

[0038] A smooth surface is created by chemical mechanical polishing.

[0039] The present invention provides a memristor with a sub-1 nanometer × sub-1 nanometer electrode and a preparation method thereof, comprising: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, a sub-1 nanometer electrode, a high dielectric constant insulating layer and a contact electrode; the substrate insulating layer is arranged on the substrate; the low dielectric constant insulating layer is arranged on the substrate insulating layer; the sub-1 nanometer electrode is arranged on the low dielectric constant insulating layer and is composed of a single layer or a few layers of two-dimensional material, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material; the high dielectric constant insulating layer is arranged on the electrode and serves as a dielectric layer of the memristor; the contact electrode is arranged on the two-dimensional material and is used to connect the two-dimensional material. It can be seen that the present invention uses the side edge of the two-dimensional material to define the electrode width of the memristor, completes the index of the sub-1 nanometer × sub-1 nanometer memristor, and helps promote the integration of ultra-small size memristors. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 It is a schematic structural diagram of a memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention.

[0042] Figure 2 It is a schematic diagram of the manufacturing structure of the substrate of the memristor with sub-1 nanometer×sub-1 nanometer electrodes provided by the present invention.

[0043] Figure 3 It is a schematic flow chart of a method for preparing a memristor having sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention.

[0044] Figure 4 It is a schematic diagram of the manufacturing process of a memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention.

[0045] Figure 5 It is a light microscope schematic diagram of a substrate of a memristor having sub-1 nanometer×sub-1 nanometer electrodes provided by the present invention before and after a CMP process.

[0046] Figure 6 It is a light microscope image of a memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention.

[0047] Figure 7 It is a schematic diagram of an electrical test curve provided by the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Combine the following Figure 1-Figure 7 The present invention describes a memristor having sub-1 nanometer×sub-1 nanometer electrodes and a method for preparing the same.

[0050] Figure 1 is a schematic diagram of the structure of a memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, such as Figure 1 As shown, the memristor comprises: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, a sub-1 nanometer electrode, a high dielectric constant insulating layer and a contact electrode;

[0051] The substrate insulating layer is disposed on the substrate;

[0052] The low dielectric constant insulating layer is disposed on the substrate insulating layer;

[0053] The sub-1 nanometer electrode is disposed on the low dielectric constant insulating layer and is composed of a single layer or a few layers of a two-dimensional material, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material;

[0054] The high dielectric constant insulating layer is disposed on the electrode and serves as a dielectric layer of the memristor;

[0055] The contact electrode is disposed on the two-dimensional material and is used for connecting the two-dimensional material.

[0056] It should be noted that the width of the electrode provided in this embodiment is sub-1 nanometer, and the width of the electrode is determined by the side edge of the two-dimensional material, and the two-dimensional material is, for example, graphene; the interdigital structure of the memristor is formed by alternately stacking and crossing sub-1 nanometer electrodes and high dielectric constant insulating layers, and the cross-sectional area of ​​the interdigital structure is sub-1 nanometer. 2 .

[0057] Specifically, the memristor of this embodiment includes the following components. Substrate: As the basis of the device, silicon is usually used and a step structure is etched, and the surface is smoothed by thermal oxide BOE etching. Substrate insulating layer: Located on the substrate, it is used to isolate the substrate and subsequent structures to prevent current leakage. Memristor sub-1 nanometer electrode layer: Two-dimensional materials are used as electrode materials, taking advantage of their excellent electrical conductivity and mechanical strength. Contact electrode: Used to connect the memristor to the external circuit, usually metal or conductive non-metal. Low dielectric constant insulating layer: Used to reduce the capacitance effect, increase the switching speed of the device, and also used to backfill the step structure. High dielectric constant insulating layer: Serves as the resistive switching layer of the memristor. The interdigital structure of the memristor is composed of alternately stacked sub-1 nanometer electrodes and high dielectric constant insulating layers, which is similar to the traditional memristor, but the size of the cross-section of the interdigital structure of the present invention is sub-1 nanometer², which significantly improves the storage density.

[0058] Based on the above embodiment, the memristor is completed by face-to-face wafer-level bonding of two wafers with sub-1 nanometer electrodes, wherein one wafer is bonded to the other wafer after being rotated 90 degrees after depositing a dielectric layer.

[0059] Each wafer includes: a step substrate, a vertical two-dimensional material, a low dielectric constant insulating layer, and a contact electrode;

[0060] The step base comprises: a step side wall and a horizontal portion;

[0061] The vertical two-dimensional material is applied to the side wall of the step;

[0062] The low dielectric constant insulating layer is used to backfill the step structure and form a smooth surface;

[0063] The contact electrode is arranged on the vertical two-dimensional material.

[0064] Specifically, see Figure 1 , Figure 1 The left side shows the substrate that needs to be prepared before bonding. The structure has a vertical two-dimensional material (102) graphene. The vertical two-dimensional material graphene is placed on the step substrate (101). After the backfill material low dielectric constant insulating layer (103) covers the step structure, it is polished using CMP to complete the entire substrate. Then the resistive dielectric layer is grown, and then wafer-level bonding is performed to complete the preparation of the entire memristor. See more Figure 1 , Figure 1The right side shows two wafers with sub-1 nanometer electrodes face-to-face wafer-level bonding. After the dielectric layer is deposited, one wafer is bonded to the other wafer after being rotated 90 degrees to complete the preparation of the memristor. In the figure, 104 is the graphene electrode of the bottom wafer, 105 is the dielectric layer, and 106 is the graphene electrode of the top wafer. These three materials constitute a sub-1 nanometer × sub-1 nanometer memristor. Figure 2 Schematic diagram of the manufacturing structure of the substrate of the memristor with sub-1 nanometer × sub-1 nanometer electrode provided by the present invention. The actual schematic diagram is as follows Figure 2 As shown, there are two contact electrodes for the two-dimensional material, which are used to evaluate the conductivity of the two-dimensional material after the process. Among them, 201 is the step substrate, 202 is the graphene layer, 203 is the contact metal, 204 is the backfilled low dielectric constant dielectric layer, and 205 is the position that needs to be polished by chemical mechanical polishing.

[0065] It should be noted that the core of the embodiment of the present invention is that the electrode width is defined by the side edge of a single layer or a few layers of a two-dimensional material of sub-1 nanometer, so there is a sub-1 nanometer electrode, and the cross-section of the interdigitated structure is sub-1 nanometer. 2 In fact, the theoretical optimal limit of the device electrode is 0.34 nanometers × 0.34 nanometers, which is the minimum level that the current process can achieve. The present invention uses the edge of the two-dimensional material as the electrode of the memristor, achieving the index of sub-1 nanometer × sub-1 nanometer memristor, which helps to promote the integration of ultra-small size memristors.

[0066] The above is a structural description of the memristor with sub-1 nanometer × sub-1 nanometer electrode provided by the present invention. From the description of the above structure, it can be seen that the memristor with sub-1 nanometer × sub-1 nanometer electrode provided by the present invention includes: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, an electrode, a high dielectric constant insulating layer and a contact electrode; the substrate insulating layer is arranged on the substrate; the low dielectric constant insulating layer is arranged on the substrate insulating layer; the electrode is arranged on the low dielectric constant insulating layer and is composed of a single layer or a few layers of two-dimensional material, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material; the high dielectric constant insulating layer is arranged on the electrode as the dielectric layer of the memristor; the contact electrode is arranged on the high dielectric constant insulating layer for connecting to an external circuit. It can be seen that the present invention uses the edge of the two-dimensional material to define the electrode width of the memristor, completes the index of the sub-1 nanometer × sub-1 nanometer memristor, and helps promote the integration of ultra-small size memristors.

[0067] The following is a description of a method for preparing a memristor having a sub-1 nm × sub-1 nm electrode provided by the present invention. The method for preparing a memristor having a sub-1 nm × sub-1 nm electrode described below and the memristor having a sub-1 nm × sub-1 nm electrode described above can correspond to each other.

[0068] Figure 3 is a schematic flow chart of a method for preparing a memristor having sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, such as Figure 3 As shown, the present invention provides a method for preparing a memristor having a sub-1 nanometer × sub-1 nanometer electrode, wherein the memristor comprises: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, a sub-1 nanometer electrode, a high dielectric constant insulating layer and a contact electrode;

[0069] The method comprises:

[0070] Step 310: forming the substrate insulating layer on the substrate.

[0071] Step 320: Form the low dielectric constant insulating layer on the substrate insulating layer.

[0072] Step 330: Use a step wet transfer process to transfer a single layer or a few layers of two-dimensional material to a preset position of the low dielectric constant insulating layer to form the sub-1 nanometer electrode, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material.

[0073] Step 340: forming the high dielectric constant insulating layer on the electrode, wherein the high dielectric constant insulating layer is the dielectric layer of the memristor.

[0074] Step 350: Form the contact electrode on the two-dimensional material, wherein the contact electrode is used to connect the two-dimensional material.

[0075] It should be noted that the manufacturing process of the sub-1 nanometer memristor of the present invention includes the following key steps. Step wet transfer process: used to accurately transfer the two-dimensional material to the side wall of the step, and ensure that the two-dimensional material on the step is not damaged by the different stress distribution. Photolithography patterning: The vertical two-dimensional material graphene needs to be photolithographically patterned after the transfer to complete the appropriate structural area. Chemical mechanical polishing process: used to form a smooth surface so that bonding can be performed to complete the preparation of the entire device. Since the cut surface is prepared from materials grown in several different periods, how to choose the grinding liquid and grinding rate to achieve the appropriate effect is very critical. Heterogeneous interface bonding process: used to firmly combine two wafers together. Thereby completing the preparation of the entire memristor.

[0076] Based on the above embodiment, the memristor is completed by face-to-face wafer-level bonding of two wafers with sub-1 nanometer electrodes, wherein one wafer is bonded to the other wafer after being rotated 90 degrees after depositing a dielectric layer.

[0077] Each wafer includes: a step substrate, a vertical two-dimensional material, a low dielectric constant insulating layer, and a contact electrode;

[0078] The wafer preparation process includes:

[0079] A wafer having a step substrate is provided, wherein the step substrate comprises: a step sidewall and a horizontal portion, the step substrate has a smooth surface and is insulating, and generally, the substrate material is SiO2;

[0080] forming a low dielectric constant insulating layer in a step shape on the step substrate as a supporting layer;

[0081] The two-dimensional material is transferred to the step sidewall by a wet transfer method to form the vertical two-dimensional material, and during the transfer process, a special stress release process is used to complete the vertical application of the two-dimensional material on the step sidewall without damage;

[0082] Performing photolithographic patterning on the vertical two-dimensional material to form a preset structural area;

[0083] Depositing the contact electrode on the vertical two-dimensional material to complete the preparation of the entire electrode, the contact electrode is made of metal or conductive non-metal;

[0084] Backfilling the low dielectric constant insulating layer in the step area and completely filling the step structure, the low dielectric constant insulating layer backfilling the step and the low dielectric constant insulating layer in the step shape are usually the same dielectric;

[0085] A smooth surface is formed by chemical mechanical polishing;

[0086] One of the wafers with sub-1-nanometer electrodes is grown with an upper dielectric layer, and then face-to-face heterojunction bonding is performed with the other wafer after being rotated 90 degrees, thereby completing the preparation of the entire sub-1-nanometer memristor;

[0087] After bonding, the wafer needs to be etched from one side so that the electrode can be exposed for testing or the next process.

[0088] Figure 4 Schematic diagram of the manufacturing process of the memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, such as Figure 4 As shown, the preparation process includes the following steps:

[0089] S101: Use silicon deep etching equipment to etch a step structure of about 500 nanometers (corresponding to Figure 4 a).

[0090] S102: Using the THERMCO oxidation LPCVD equipment to generate a silicon dioxide layer of about 350 nanometers on the step surface (corresponding to Figure 4 b).

[0091] S103: Use a buffered oxide etchant to remove the silicon dioxide layer to obtain a smooth silicon surface; this embodiment uses a BOE solution (corresponding to Figure 4 c).

[0092] S104: Using ICP-PECVD to grow a smooth silicon dioxide dielectric, an insulating silicon dioxide layer is formed on the step surface. In this embodiment, 400 nanometers of SiO2 (corresponding to Figure 4 d).

[0093] S105: Wet transfer graphene to the vertical sidewalls and pattern them. The transfer requires a special transfer process (corresponding to Figure 4 e).

[0094] S106: Deposition of graphene contact metal is completed by photolithography, which can be metal and other conductive non-metal, highly doped p-type and n-type silicon, germanium semiconductor, flexible electrode material, etc. For this embodiment, the metal Ti / Pd with a thickness of 5 nanometers / 30 nanometers (corresponding to Figure 4 f).

[0095] S107: Deposit the silicon oxide seed layer by angle deposition, and then complete the 1.5um SiO2 layer by ICP-PECVD. Perform annealing process at 250 degrees for more than 1h (corresponding to Figure 4 g).

[0096] S108: The surface is cut by chemical mechanical polishing to obtain a vertical graphene interface (corresponding to Figure 4 h, where the vertical graphene interface can be found in Figure 4 h).

[0097] S109: growing a high dielectric layer. Usually HfO2, ZrO2, Al2O3, in this embodiment, HfO2 with a thickness of 15 nanometers is used as the gate dielectric layer, and holes are cut on the dielectric layer for the gate (see Figure 4 j).

[0098] S110: Wafer-level bonding, a substrate with HfO2 grown on it (see Figure 4 j) and a substrate without HfO2 growth (see Figure 4 i), after rotating 90 degrees, wafer-level bonding is performed. Bonding at high temperature for more than 7 hours can obtain a good bonded wafer, and finally the electrode etching process is completed (see Figure 4 k).

[0099] Figure 5 FIG. 1 is a light microscope schematic diagram of a substrate of a memristor having a sub-1 nm×sub-1 nm electrode provided by the present invention before and after a CMP process. The change of the substrate after CMP is schematically shown as follows Figure 5 As shown, it can be seen that CMP can well complete the planarization of the substrate and remove surface metal and two-dimensional materials. Figure 6 is a light microscope image of a memristor with sub-1 nanometer × sub-1 nanometer electrodes provided by the present invention, and a physical image of a sub-1 nanometer electrode memristor is shown in FIG. Figure 6 shown.

[0100] It should be noted that the core of the embodiment of the present invention is that the electrode width is defined by the side edge of a single layer or a few layers of a two-dimensional material of sub-1 nanometer, so there is a sub-1 nanometer electrode, and the cross-section of the interdigitated structure is sub-1 nanometer. 2 In fact, the theoretical optimal limit of the device electrode is 0.34 nanometers × 0.34 nanometers, which is the minimum level that the current process can achieve. Unlike traditional memristors, this invention has a sub-1 nanometer structure and uses a special step wet transfer process, a low dielectric constant backfill process, a chemical mechanical polishing process, and a heterogeneous interface bonding process to complete the preparation of the entire device. The present invention uses the edge of a two-dimensional material as the electrode of the memristor, achieving the indicators of a sub-1 nanometer × sub-1 nanometer memristor, which helps promote the integration of ultra-small size memristors.

[0101] The present invention provides a method for preparing a memristor, wherein the memristor comprises: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, an electrode, a high dielectric constant insulating layer and a contact electrode; the method comprises: forming the substrate insulating layer on the substrate; forming the low dielectric constant insulating layer on the substrate insulating layer; using a step wet transfer process to transfer a single layer or a few layers of two-dimensional material to a preset position of the low dielectric constant insulating layer to form the electrode, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material; forming the high dielectric constant insulating layer on the electrode, the high dielectric constant insulating layer being the dielectric layer of the memristor; forming the contact electrode on the high dielectric constant insulating layer, the contact electrode being used to connect to an external circuit. It can be seen that the present invention uses the measured edge of the two-dimensional material to define the electrode width of the memristor, completes the index of the sub-1 nanometer × sub-1 nanometer memristor, and helps promote the integration of ultra-small size memristors.

[0102] Based on the above embodiments, in this embodiment, the effectiveness is verified. In order to verify the effect of the embodiment of the present invention, the prepared device is tested. Figure 7 This is a schematic diagram of the electrical test curve provided by the present invention, see Figure 7 , is the IV curve of the memristor prepared in the example of the present invention, which shows the test curve of the memristor. It can be seen that the memristor is a volatile memristor, and it can be seen that the memristor has a resistance of more than 10 3 The switching ratio is good and has good switching characteristics.

[0103] The embodiment of the present invention provides a memristor with a sub-1 nanometer × sub-1 nanometer electrode and a method for preparing the same. The memristor with a characteristic size of sub-1 nanometer is realized by introducing two-dimensional materials, and the size of the transistor is further reduced. This design can improve the density of the memristor, and the process has the potential for large-scale preparation. Therefore, it is an advanced high-density memristor production solution and provides a feasible route for advanced process chips.

[0104] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memristor having sub-1 nm x sub-1 nm electrodes, characterized in that: include: Substrate, substrate insulating layer, low dielectric constant insulating layer, sub-1 nanometer electrode, high dielectric constant insulating layer and contact electrode; The substrate insulating layer is disposed on the substrate; The low dielectric constant insulating layer is disposed on the substrate insulating layer; The sub-1 nanometer electrode is disposed on the low dielectric constant insulating layer and is composed of a single layer or a few layers of a two-dimensional material, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material; The high dielectric constant insulating layer is disposed on the electrode and serves as a dielectric layer of the memristor; The contact electrode is disposed on the two-dimensional material and is used to connect the two-dimensional material; The interdigital structure of the memristor is formed by alternately stacking sub-1 nanometer electrodes and the high dielectric constant insulating layer and crossing each other, and the cross-sectional area of ​​the interdigital structure is sub-1 nanometer. 2 .

2. The memristor with sub-1 nm×sub-1 nm electrodes according to claim 1, characterized in that: The sub-1 nanometer electrode is a vertical graphene material.

3. The memristor with sub-1 nm×sub-1 nm electrodes according to claim 2, characterized in that: The memristor is completed by face-to-face wafer-level bonding of two wafers with sub-1 nanometer electrodes, wherein one wafer is bonded to the other wafer after being rotated 90 degrees after a dielectric layer is deposited.

4. The memristor with sub-1 nm×sub-1 nm electrodes according to claim 3, characterized in that: Each wafer includes: a step substrate, a vertical two-dimensional material, a low dielectric constant insulating layer, and a contact electrode; The step base comprises: a step side wall and a horizontal portion; The vertical two-dimensional material is applied to the side wall of the step; The low dielectric constant insulating layer is used to backfill the step structure and form a smooth surface; The contact electrode is arranged on the vertical two-dimensional material.

5. A method for preparing a memristor having sub-1 nm × sub-1 nm electrodes, characterized in that: The memristor comprises: a substrate, a substrate insulating layer, a low dielectric constant insulating layer, a sub-1 nanometer electrode, a high dielectric constant insulating layer and a contact electrode; The method comprises: forming the substrate insulating layer on the substrate; forming the low dielectric constant insulating layer on the substrate insulating layer; Using a step wet transfer process, a single layer or a few layers of two-dimensional material are transferred to a preset position of the low dielectric constant insulating layer to form the sub-1 nanometer electrode, wherein the width of the sub-1 nanometer electrode is determined by the side edge of the two-dimensional material; forming the high dielectric constant insulating layer on the electrode, the high dielectric constant insulating layer being the dielectric layer of the memristor; forming the contact electrode on the two-dimensional material, wherein the contact electrode is used to connect the two-dimensional material; The interdigital structure of the memristor is formed by alternately stacking sub-1 nanometer electrodes and the high dielectric constant insulating layer and crossing each other, and the cross-sectional area of ​​the interdigital structure is sub-1 nanometer. 2 .

6. The method for preparing a memristor having sub-1 nanometer × sub-1 nanometer electrodes according to claim 5, characterized in that: The sub-1 nanometer electrode is a vertical graphene material.

7. The method for preparing a memristor having sub-1 nanometer × sub-1 nanometer electrodes according to claim 6, characterized in that: The memristor is completed by face-to-face wafer-level bonding of two wafers with sub-1 nanometer electrodes, wherein one wafer is bonded to the other wafer after being rotated 90 degrees after a dielectric layer is deposited.

8. The method for preparing a memristor having sub-1 nanometer × sub-1 nanometer electrodes according to claim 7, characterized in that: Each wafer includes: a step substrate, a vertical two-dimensional material, a low dielectric constant insulating layer, and a contact electrode; The wafer preparation process includes: Providing a wafer having a step substrate, wherein the step substrate comprises: a step sidewall and a horizontal portion; forming a low dielectric constant insulating layer in a step shape on the step substrate as a supporting layer; Transferring the two-dimensional material to the sidewall of the step by wet transfer to form the vertical two-dimensional material; Performing photolithographic patterning on the vertical two-dimensional material to form a preset structural area; depositing the contact electrode on the vertical two-dimensional material; Backfilling the low dielectric constant insulating layer in the step region and completely filling the step structure; A smooth surface is created by chemical mechanical polishing.

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