Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the steps of providing a substrate; forming a first metal structure and a first interlayer dielectric layer on the substrate; wherein the first metal structure comprises a first polar plate, a first lead-out wire and a second lead-out wire, and the first polar plate, the first lead-out wire and the second lead-out wire form a first groove; the first interlayer dielectric layer fills the first groove; removing part of the first interlayer dielectric layer to expose the side wall of the first outgoing line and the side wall of the second outgoing line; forming a second interlayer dielectric layer on the exposed side wall of the first lead-out wire, the side wall of the second lead-out wire and one side, far away from the first polar plate, of the first interlayer dielectric layer; forming a second metal structure and a third interlayer dielectric layer on one side, far away from the first groove, of the second interlayer dielectric layer; the second metal structure comprises a second pole plate, a third outgoing line and a fourth outgoing line. By adopting the preparation method provided by the invention, the preparation difficulty of the MIM capacitor can be reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] Metal-Insulator-Metal (MIM) capacitors consist of two plates and an insulating layer between the plates. They have the advantages of low loss, high withstand voltage and low equivalent series resistance.

[0003] Normally, multiple masks are used to define the positions of the lower electrode plate, upper electrode plate, metal connecting wires, and connecting through holes, and then etching and deposition are performed to finally form the required MIM capacitor connection structure. However, as the size of devices decreases, the existing preparation process makes it difficult to prepare small-sized, high-quality MIM capacitors. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure that can prepare a small-sized, high-quality MIM capacitor.

[0005] In order to achieve the above objectives, on the one hand, the present application provides a method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] A first metal structure and a first interlayer dielectric layer are formed on the substrate; wherein the first metal structure includes a first electrode plate, a first lead wire and a second lead wire, a first end of the first electrode plate contacts the first lead wire, and a second end of the first electrode plate contacts the second lead wire to form a first groove; and the first interlayer dielectric layer fills the first groove;

[0008] Removing a portion of the first interlayer dielectric layer to expose the sidewalls of the first lead wire and the sidewalls of the second lead wire;

[0009] forming a second interlayer dielectric layer on the exposed sidewalls of the first lead wire, the sidewalls of the second lead wire, and a side of the first interlayer dielectric layer away from the first electrode plate;

[0010] A second metal structure and a third interlayer dielectric layer are formed on a side of the second interlayer dielectric layer away from the first groove; wherein the second metal structure includes a second electrode plate, a third lead wire, and a fourth lead wire, the first end of the second electrode plate contacts the third lead wire, and the second end of the second electrode plate contacts the fourth lead wire to form a second groove, and the third interlayer dielectric layer fills the second groove.

[0011] In one embodiment, forming a second interlayer dielectric layer on the exposed sidewalls of the first lead wire, the sidewalls of the second lead wire, and a side of the first interlayer dielectric layer away from the first electrode plate includes:

[0012] forming a first dielectric material layer on the first metal structure and the first interlayer dielectric layer;

[0013] At least the first dielectric material layer on the top surface of the first lead-out line and the second lead-out line is removed to form the second interlayer dielectric layer, and the second interlayer dielectric layer is flush with the first lead-out line and the second lead-out line.

[0014] In one embodiment, forming a first metal structure and a first interlayer dielectric layer on the substrate includes:

[0015] forming the first electrode plate and a first interlayer dielectric layer located on the first electrode plate on the substrate;

[0016] forming a first metal material layer on the surface of the substrate and the first interlayer dielectric layer;

[0017] The first metal material layer located on the top surface of the first interlayer dielectric layer and a portion of the first metal material layer located on the substrate are removed to form the first lead wire and the second lead wire respectively located at two ends of the first electrode plate.

[0018] In one embodiment, forming a first metal structure and a first interlayer dielectric layer on the substrate includes:

[0019] forming a fourth interlayer dielectric layer having a third groove on the substrate; the third groove exposes the substrate;

[0020] Sequentially forming a first metal material layer and a second dielectric material layer on the surfaces of the third groove and the fourth interlayer dielectric layer;

[0021] The first metal material layer and the second dielectric material layer are subjected to grinding treatment to expose the fourth interlayer dielectric layer; the remaining first metal material layer constitutes the first metal structure, and the remaining second dielectric material layer constitutes the first interlayer dielectric layer.

[0022] In one embodiment, the method further comprises:

[0023] The thickness of the second interlayer dielectric layer along a direction perpendicular to the top surface of the substrate is greater than or equal to 500 angstroms.

[0024] In one embodiment, forming a second metal structure and a third interlayer dielectric layer on a side of the second interlayer dielectric layer away from the first groove includes:

[0025] forming a second metal material layer and a third dielectric material layer in sequence at least on the exposed surface of the second interlayer dielectric layer;

[0026] The second metal material layer and the third dielectric material layer are subjected to grinding treatment to expose the second interlayer dielectric layer; the remaining second metal material layer constitutes the second metal structure, and the remaining third dielectric material layer constitutes the third interlayer dielectric layer.

[0027] In one embodiment, after forming the second metal structure and the third interlayer dielectric layer in the first groove, the method further includes:

[0028] forming a first connecting member on an exposed surface of the first lead wire or the second lead wire;

[0029] A second connection member is formed on an exposed surface of the third lead wire or the fourth lead wire.

[0030] In one embodiment, the thickness of the first electrode plate in a direction perpendicular to the top surface of the substrate ranges from 700 angstroms to 1500 angstroms.

[0031] In one embodiment, the method further comprises at least one of the following features:

[0032] The thickness of the first lead wire and the second lead wire along the direction in which the first lead wire and the second lead wire are arranged spaced apart is in the range of 40 nanometers to 80 nanometers;

[0033] The height of the first lead wire and the second lead wire in a direction perpendicular to the top surface of the substrate ranges from 2000 angstroms to 3000 angstroms;

[0034] The thickness of the third lead wire and the fourth lead wire along the direction in which the first lead wire and the second lead wire are arranged at intervals ranges from 40 nanometers to 80 nanometers.

[0035] In a second aspect, the present application further provides a semiconductor structure, which is prepared using a semiconductor structure preparation method as described in any one of the embodiments of the present application.

[0036] In the above semiconductor structure and preparation method thereof, a substrate is provided, and a first metal structure and a first interlayer dielectric layer are formed on the substrate, wherein the first metal structure includes a first electrode plate, a first lead wire and a second lead wire, the first electrode plate can be used as a lower electrode plate of the MIM capacitor finally formed, and the first lead wire and the second lead wire can be used to lead out the first electrode plate; further, a portion of the first interlayer dielectric layer is removed to expose the side wall of the first lead wire and the side wall of the second lead wire, and a second interlayer dielectric layer is formed on the exposed side wall of the first lead wire, the side wall of the second lead wire, and the side of the first interlayer dielectric layer away from the first electrode plate, and the retained first interlayer dielectric layer and the second interlayer dielectric layer are The dielectric layer can be used as the capacitor dielectric layer of the MIM capacitor that is finally formed. The capacitance value of the MIM capacitor can be adjusted by controlling the thickness of the retained first interlayer dielectric layer and the thickness of the formed second interlayer dielectric layer. The thickness of the second interlayer dielectric layer can also be controlled to avoid electrical crosstalk caused by adjacent lead wires being too close. In addition, the second interlayer dielectric layer inherits the cross-sectional shape of the first metal structure. The shape of the second interlayer dielectric layer can be used to form a second electrode, a third lead wire, a fourth lead wire and a third interlayer dielectric layer through a deposition process. There is no need to perform photolithography to form connecting through holes, which not only reduces the process difficulty, but also saves masks and reduces preparation costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A schematic diagram of a process for preparing a MIM capacitor provided in an embodiment;

[0039] Figure 2a A schematic diagram of a cross-sectional structure of a structure obtained in step S104 in a method for preparing a MIM capacitor provided in an embodiment;

[0040] Figure 2b Schematic diagram of the cross-sectional structure of the structure obtained in step S106 in the method for preparing a MIM capacitor provided in one embodiment;

[0041] Figure 2c A schematic diagram of a cross-sectional structure of a structure obtained in step S108 in a method for preparing a MIM capacitor provided in an embodiment;

[0042] Figure 2d A schematic diagram of a cross-sectional structure of a structure obtained in step S110 in a method for preparing a MIM capacitor provided in an embodiment;

[0043] Figure 2e A schematic diagram of a cross-sectional structure of a structure obtained in step S112 in a method for preparing a MIM capacitor provided in an embodiment;

[0044] Figure 2f Schematic diagram of the cross-sectional structure of the structure obtained in step S114 in the method for preparing a MIM capacitor provided in one embodiment;

[0045] Figure 2g A schematic diagram of a cross-sectional structure of a structure obtained in step S116 in a method for preparing a MIM capacitor provided in an embodiment;

[0046] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0047] Figure 4a A schematic diagram of a cross-sectional structure of a structure obtained in step S702 in a method for preparing a semiconductor structure provided in an embodiment;

[0048] Figure 4b A schematic diagram of a cross-sectional structure of a structure obtained in step S704 in a method for preparing a semiconductor structure provided in an embodiment;

[0049] Figure 4c A schematic diagram of a cross-sectional structure of a structure obtained in step S304 in a method for preparing a semiconductor structure provided in an embodiment;

[0050] Figure 4d A schematic diagram of a cross-sectional structure of a structure obtained in step S306 in a method for preparing a semiconductor structure provided in an embodiment;

[0051] Figure 4e A schematic diagram of a cross-sectional structure of a structure obtained in step S602 in a method for preparing a semiconductor structure provided in an embodiment;

[0052] Figure 4f A schematic diagram of a cross-sectional structure of a structure obtained in step S308 in a method for preparing a semiconductor structure provided in an embodiment;

[0053] Figure 4g A schematic diagram of a cross-sectional structure of a structure obtained in step S504 in a method for preparing a semiconductor structure provided in an embodiment;

[0054] Figure 4h A schematic diagram of a cross-sectional structure of a structure obtained in step S902 in a method for preparing a semiconductor structure provided in an embodiment;

[0055] Figure 4i A schematic diagram of a cross-sectional structure of a structure obtained in step S310 in a method for preparing a semiconductor structure provided in an embodiment;

[0056] Figure 4j A schematic cross-sectional view of a method for preparing a semiconductor structure provided in an embodiment of the present invention includes steps of: forming a first connector on an exposed surface of a second lead wire, and forming a second connector on an exposed surface of a third lead wire;

[0057] Figure 5a A schematic diagram of a cross-sectional structure of a structure obtained in step S802 in a method for preparing a semiconductor structure provided in an embodiment;

[0058] Figure 5b A schematic diagram of a cross-sectional structure of a structure obtained in step S804 in a method for preparing a semiconductor structure provided in an embodiment;

[0059] Figure 5c A schematic cross-sectional view of a structure obtained in step S304 in a method for preparing a semiconductor structure provided in another embodiment;

[0060] Figure 5d A schematic cross-sectional view of a structure obtained in step S306 in a method for preparing a semiconductor structure provided in another embodiment;

[0061] Figure 5e A schematic cross-sectional view of a structure obtained in step S602 of a method for preparing a semiconductor structure provided in another embodiment;

[0062] Figure 5f A schematic cross-sectional view of a structure obtained in step S308 in a method for preparing a semiconductor structure provided in another embodiment;

[0063] Figure 5g A schematic cross-sectional view of a structure obtained in step S504 in a method for preparing a semiconductor structure provided in another embodiment;

[0064] Figure 5h A schematic cross-sectional view of a structure obtained in step S902 in a method for preparing a semiconductor structure provided in another embodiment;

[0065] Figure 5i A schematic cross-sectional view of a structure obtained in step S310 in a method for preparing a semiconductor structure provided in another embodiment;

[0066] Figure 5j A schematic cross-sectional view of a method for preparing a semiconductor structure provided in another embodiment, wherein the steps include forming a first connector on an exposed surface of a second lead, and forming a second connector on an exposed surface of a third lead;

[0067] Figure 6 is a flow chart of step S308 in a method for preparing a semiconductor structure provided in an embodiment;

[0068] Figure 7 is a flow chart of step S304 in a method for preparing a semiconductor structure provided in an embodiment;

[0069] Figure 8 is a flow chart of step S304 in a method for preparing a semiconductor structure provided in another embodiment;

[0070] Fig. 9 FIG. 4 is a flow chart of step S310 in a method for preparing a semiconductor structure provided in an embodiment.

[0071] Description of reference numerals:

[0072] 101-substrate, 102-first dielectric layer, 103-lower electrode, 104-first patterned photoresist layer, 105-second dielectric layer, 106-upper electrode, 107-second patterned photoresist layer, 108-third dielectric layer, 109-third patterned photoresist layer, 110-metal connecting groove, 111-connecting through hole, 112-metal material, 410-first metal structure, 412-first electrode, 414-first lead, 416-second lead, 420-first layer interlayer dielectric layer, 422-second dielectric material layer, 430-first metal material layer, 440-first dielectric material layer, 442-second interlayer dielectric layer, 450-second metal material layer, 460-third dielectric material layer, 462-third interlayer dielectric layer, 470-second metal structure, 472-second electrode plate, 474-third lead line, 476-fourth lead line, 482-first connecting piece, 484-second connecting piece, 490-fourth interlayer dielectric layer, 492-third groove. DETAILED DESCRIPTION

[0073] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0075] It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to, or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to, or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various layers, these layers should not be limited by these terms. These terms are merely used to distinguish one layer from another. Therefore, without departing from the teachings of the present application, the first layer discussed below may be represented as a second layer or portion.

[0076] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0077] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0078] In the embodiment of the present application, the substrate may include a top surface located at the front side and a bottom surface located at the back side opposite to the front side. In the embodiment of the present application, the side of the first metal structure in contact with the substrate is used as the top surface of the substrate, and the side opposite to the top surface is used as the bottom surface of the substrate.

[0079] Please refer to Figure 1 , Figure 2a-2g In some general technologies, forming a MIM capacitor connection structure may include: step S102 to step S116.

[0080] Step S102: providing a substrate; the substrate includes a substrate 101 and a first dielectric layer 102 located on the top surface of the substrate 101;

[0081] Step S104: Based on the first patterned photoresist layer 104 , a lower electrode plate 103 is formed on the first dielectric layer 102 by using a photolithography process;

[0082] Step S106: removing the first patterned photoresist layer 104 and forming a second dielectric layer 105 on the first dielectric layer 102 by chemical vapor deposition, wherein the top surface of the second dielectric layer 105 is higher than the top surface of the lower electrode plate 103;

[0083] Step S108: Based on the second patterned photoresist layer 107 , a photolithography process is used to form an upper electrode plate 106 on the second dielectric layer 105 ;

[0084] Step S110: removing the second patterned photoresist layer 107 and forming a third dielectric layer 108 on the second dielectric layer 105 by chemical vapor deposition, wherein the top surface of the third dielectric layer 108 is higher than the top surface of the upper electrode plate 106;

[0085] Step S112: Based on the third patterned photoresist layer 109 , a photolithography process is used to form two spaced-apart metal connection grooves 110 in the third dielectric layer 108 ;

[0086] Step S114: Based on the fourth patterned photoresist layer (not shown), a photolithography process is used to form connecting through holes 111 in the third dielectric layer 108 at the bottom of the two metal connecting line grooves 110; the connecting through holes 111 expose the lower electrode plate 103 and the upper electrode plate 106;

[0087] Step S116 : using a physical vapor deposition (PVD) process to form a metal material 112 in the metal connection trench 110 and the connection through hole 111 , and using a chemical-mechanical polishing (CMP) process to planarize the metal material 112 .

[0088] As mentioned in the background technology, as the size of MIM capacitor devices decreases, the size of metal connecting wire grooves 110 and connecting through holes 111 is getting smaller and smaller, and the difficulty of the photolithography process increases accordingly. At the same time, in the process of filling the metal connecting wire grooves 110 and connecting through holes 111 with high aspect ratios, it is easy to form air gaps in the metal connecting wire grooves 110 and connecting through holes 111 due to the early sealing of the metal material 112, resulting in low performance of the MIM capacitor. In addition, in order to ensure the compactness of the metal material 112 in the metal connecting wire grooves 110 and connecting through holes 111, it is usually necessary to use metal material 112 that is 2 to 3 times the volume of the metal connecting wire grooves 110 and connecting through holes 111, resulting in serious material waste, and the cost of the photomask for multiple photolithography processes is also high.

[0089] Based on the above questions, please refer to Figure 3 , the present application provides a method for preparing a semiconductor structure, including steps S302 to S310.

[0090] Step S302, providing a substrate.

[0091] Among them, the substrate 101 can be made of semiconductor materials, insulating materials, conductor materials or any combination thereof. The substrate 101 can be a single-layer structure or a multi-layer structure. For example, the substrate 101 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 101 can be a layered substrate 101 including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 101 should not limit the scope of protection of the present disclosure.

[0092] A shallow trench isolation structure (STI) may be formed in the substrate 101, and the shallow trench isolation structure may isolate a plurality of active areas (AA) arranged at intervals in the substrate 101. The active area may include a plurality of doped regions for forming devices such as transistors. Therefore, the present application does not impose any specific restrictions on the structure in the substrate 101.

[0093] Step S304: forming a first metal structure and a first interlayer dielectric layer on the substrate.

[0094] like Figure 4c or Figure 5cAs shown, the first metal structure 410 includes a first electrode plate 412, a first lead wire 414 and a second lead wire 416, the first end of the first electrode plate 412 contacts the first lead wire 414, and the second end of the first electrode plate 412 contacts the second lead wire 416 to form a first groove. The extension direction of the first electrode plate 412 is parallel to the extension direction of the substrate 101, and the first electrode plate 412 can be used as the lower electrode plate of the MIM capacitor finally formed. The extension direction of the first lead wire 414 and the extension direction of the second lead wire 416 are respectively perpendicular to the extension direction of the first electrode plate 412, and the first lead wire 414 and the second lead wire 416 can be used to lead the first electrode plate 412 out and connect it to the metal layer or other external circuits.

[0095] The material of the first electrode plate 412 includes, but is not limited to, one or more of cobalt (Co), nickel (Ni), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al). The first electrode plate 412 may be formed on the substrate 101 by a deposition process such as physical vapor deposition (PVD), magnetron sputtering, or evaporation.

[0096] The material of the first lead wire 414 and the second lead wire 416 may be the same as or different from the first electrode plate 412. Exemplarily, the material of the first lead wire 414 and the second lead wire 416 includes, but is not limited to, one or more of cobalt (Co), nickel (Ni), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0097] The first interlayer dielectric layer 420 fills the first groove. The material of the first interlayer dielectric layer 420 includes but is not limited to nitride, for example, silicon oxynitride, silicon nitride or a combination thereof. The first interlayer dielectric layer 420 can be formed by a deposition process, such as a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition (High Density Plasma, HDP) process or a plasma enhanced deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD) process.

[0098] Step S306 , removing a portion of the first interlayer dielectric layer to expose the sidewalls of the first lead wire and the sidewalls of the second lead wire.

[0099] like Figure 4d or Figure 5d As shown, a wet etching process may be used to remove a portion of the first interlayer dielectric layer to expose the sidewalls of the first lead line 414 and the sidewalls of the second lead line 416 .

[0100] Step S308 , forming a second interlayer dielectric layer on the exposed sidewalls of the first lead wire, the sidewalls of the second lead wire, and a side of the first interlayer dielectric layer away from the first electrode plate.

[0101] like Figure 4f or Figure 5f As shown, a deposition process such as CVD, ALD, HDP or PECVD can be used to form a second interlayer dielectric layer 442 on the exposed sidewalls of the first lead 414, the sidewalls of the second lead 416, and the side of the first interlayer dielectric layer 420 away from the first electrode 412. The material of the second interlayer dielectric layer 442 includes but is not limited to nitride, for example, silicon oxynitride, silicon nitride or a combination thereof.

[0102] Step S310 , forming a second metal structure 470 and a third interlayer dielectric layer on a side of the second interlayer dielectric layer away from the first groove.

[0103] like Figure 4i or Figure 5i As shown, the second metal structure 470 includes a second plate 472, a third lead 474, and a fourth lead 476, wherein the first end of the second plate 472 contacts the third lead 474, and the second end of the second plate 472 contacts the fourth lead 476 to form a second groove. The extension direction of the second plate 472 is parallel to the extension direction of the substrate 101, and the second plate 472 can be used as the upper plate of the MIM capacitor. The extension directions of the third lead 474 and the fourth lead 476 are respectively perpendicular to the extension direction of the substrate 101, and the third lead 474 and the fourth lead 476 are used to lead the second plate 472 to connect with other metal layers or external circuits. In addition, the first interlayer dielectric layer 420 and the second interlayer dielectric layer 442 between the second plate 472 and the first plate 412 can be used as the capacitor dielectric layer that finally forms the MIM capacitor, wherein the thickness of the part of the capacitor dielectric layer perpendicular to the substrate 101 is different from the thickness of the part of the capacitor dielectric layer parallel to the substrate 101.

[0104] The second electrode plate 472 is made of the same material as the third lead line 474 and the fourth lead line 476, including but not limited to one or more of cobalt (Co), nickel (Ni), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al).

[0105] The third interlayer dielectric layer 462 fills the second groove. The material of the third interlayer dielectric layer 462 includes but is not limited to nitride, for example, silicon oxynitride, silicon nitride or a combination thereof.

[0106] In the embodiment of the present application, by providing a substrate 101, a first metal structure 410 and a first interlayer dielectric layer 420 are formed on the substrate 101, wherein the first metal structure 410 includes a first electrode 412, a first lead 414 and a second lead 416, the first electrode 412 can be used as the lower electrode of the MIM capacitor finally formed, and the first lead 414 and the second lead 416 can be used to lead out the first electrode 412; further, a portion of the first interlayer dielectric layer is removed to expose the side wall of the first lead 414 and the side wall of the second lead 416, and the side wall of the first lead 414, the side wall of the second lead 416, and the first interlayer dielectric layer 420 away from the first electrode 412, a second interlayer dielectric layer 442 is formed, wherein the retained first layer The interlayer dielectric layer 420 and the second interlayer dielectric layer 442 can be used as the capacitor dielectric layers of the MIM capacitor that is finally formed. The capacitance value of the MIM capacitor can be adjusted by controlling the thickness of the retained first interlayer dielectric layer 420 and the thickness of the formed second interlayer dielectric layer 442. The thickness of the second interlayer dielectric layer 442 can also be controlled to avoid electrical crosstalk caused by adjacent lead lines being too close. In addition, the second interlayer dielectric layer 442 inherits the cross-sectional shape of the first metal structure 410. The shape of the second interlayer dielectric layer 442 can be used to form the second electrode 472, the third lead line 474, the fourth lead line 476 and the third interlayer dielectric layer 462 through a deposition process. There is no need to perform photolithography to form connecting through holes, which not only reduces the process difficulty, but also saves masks and reduces preparation costs.

[0107] In one embodiment, Figure 6 As shown, a second interlayer dielectric layer is formed on the exposed sidewalls of the first lead wire, the sidewalls of the second lead wire, and the side of the first interlayer dielectric layer away from the first electrode plate, including steps S602 to S604.

[0108] Step S602 , forming a first dielectric material layer on the first metal structure and the first interlayer dielectric layer.

[0109] like Figure 4e or Figure 5e As shown, a first dielectric material layer 440 may be formed on the first metal structure 410 and the first interlayer dielectric layer 420 by using a deposition process such as CVD, ALD, HDP or PECVD.

[0110] Step S604 , removing at least the first dielectric material layer on the top surfaces of the first lead-out line and the second lead-out line to form a second interlayer dielectric layer.

[0111] like Figure 4f or Figure 5f As shown, a dry etching process can be used to remove at least the first dielectric material layer on the top surface of the first lead 414 and the second lead 416, and the first dielectric material layer 440 remaining on the sidewalls of the first lead 414 and the second lead 416 and the surface of the first interlayer dielectric layer 420 constitutes a second interlayer dielectric layer 442. The second interlayer dielectric layer is flush with the first lead 414 and the second lead 416.

[0112] exist Figure 4e In the structure shown, the first dielectric material layer 440 also covers the surface of the substrate 101 . When a portion of the first dielectric material layer 440 is removed by dry etching, the first dielectric material layer 440 on the surface of the substrate 101 is also removed.

[0113] exist Figure 5e In the structure shown, the first dielectric material layer 440 also covers the surfaces of other film layers except the first metal structure 410 and the first interlayer dielectric layer 420. When a portion of the first dielectric material layer 440 is removed by a dry etching process, the first dielectric material layer 440 on the surfaces of other film layers will also be removed, leaving only the side walls of the first lead line 414, the side walls of the second lead line 416, and the first dielectric material layer 440 on the surface of the first interlayer dielectric layer 420.

[0114] In one embodiment, Figure 7 As shown, a first metal structure and a first interlayer dielectric layer are formed on a substrate, including steps S702 to S706.

[0115] Step S702 , forming a first electrode plate and a first interlayer dielectric layer on the first electrode plate on the substrate.

[0116] like Figure 4a As shown, a first electrode plate 412 may be formed on the substrate 101 by using deposition processes such as CVD, ALD, HDP or PECVD, and then a first interlayer dielectric layer 420 may be formed on a side of the first electrode plate 412 away from the substrate 101 .

[0117] The thickness of the first plate 412 along the direction perpendicular to the top surface of the substrate 101 ranges from 700 angstroms to 1500 angstroms. The thickness of the first plate 412 is associated with the resistance value of the first plate 412, which will affect the RC Delay capability of the MIM capacitor. The thickness of the first plate 412 along the direction perpendicular to the top surface of the substrate 101 can be 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, or 1500 angstroms, etc.

[0118] Step S704: forming a first metal material layer on the surface of the substrate and the first interlayer dielectric layer.

[0119] like Figure 4b As shown, the first metal material layer 430 can be formed on the surface of the substrate 101 and the first interlayer dielectric layer 420 by using deposition processes such as CVD, ALD, HDP or PECVD.

[0120] Step S706 , removing the first metal material layer located on the top surface of the first interlayer dielectric layer and a portion of the first metal material layer located on the substrate to form a first lead wire and a second lead wire respectively located at two ends of the first electrode plate.

[0121] like Figure 4c As shown, a self-alignment process can be used to remove the first metal material layer on the top surface of the first interlayer dielectric layer 420 and part of the first metal material layer on the substrate 101 to form a first lead 414 and a second lead 416 respectively located at both ends of the first electrode 412.

[0122] In this embodiment, a first electrode plate 412 and a first interlayer dielectric layer 420 located on the first electrode plate 412 are formed on the substrate 101, and a first metal material layer 430 is formed on the surface of the substrate 101 and the first interlayer dielectric layer 420. Further, the first metal material layer 430 located on the top surface of the first interlayer dielectric layer 420 and a portion of the first metal material layer 430 located on the substrate 101 are removed to form a first lead 414 and a second lead 416 located at both ends of the first electrode plate 412, respectively. Since the width of the removed first metal material layer in a direction parallel to the substrate 101 is much larger than the width of the first lead 414 and the second lead 416, the etching window is increased and the difficulty of etching is reduced.

[0123] In one embodiment, Figure 8 As shown, a first metal structure and a first interlayer dielectric layer are formed on the substrate 101, including steps S802 to S806.

[0124] Step S802 , forming a fourth interlayer dielectric layer having a third groove on the substrate; the third groove exposes the substrate.

[0125] like Figure 5a As shown, a fourth interlayer dielectric layer 490 may be formed on the substrate 101 by a deposition process, and then a third groove 492 may be formed in the fourth interlayer dielectric layer 490 by photolithography and etching processes. The material of the fourth interlayer dielectric layer 490 may include but is not limited to oxides, oxynitrides, oxycarbons, and the like.

[0126] Step S804 , forming a first metal material layer and a second dielectric material layer in sequence on the surfaces of the third groove and the fourth interlayer dielectric layer.

[0127] like Figure 5b As shown, the first metal material layer 430 and the second dielectric material layer 422 may be sequentially formed on the surfaces of the third groove 492 and the fourth interlayer dielectric layer 490 by deposition processes such as CVD, ALD, HDP or PECVD.

[0128] Step S806 , grinding the first metal material layer and the second dielectric material layer to expose the fourth interlayer dielectric layer.

[0129] like Figure 5c As shown, the first metal material layer 430 and the second dielectric material layer 422 are polished to expose the fourth interlayer dielectric layer 490. The remaining first metal material layer constitutes the first metal structure 410, and the remaining second dielectric material layer constitutes the first interlayer dielectric layer 420. Optionally, after forming the first metal structure 410, the fourth interlayer dielectric layer 490 may be removed to form Figure 4c The structure shown.

[0130] Compared with the traditional method of forming a connecting through hole by etching a dielectric layer, in the present embodiment, since the width of the third groove 492 in the direction parallel to the substrate 101 is much larger than the width of the first lead line 414 and the second lead line 416, the third groove 492 is formed by etching, and the first electrode 412, the first lead line 414 and the second lead line 416 are formed in the third groove 492 through a deposition process and a grinding treatment, which can increase the etching window and reduce the difficulty of etching.

[0131] In one embodiment, the thickness of the second interlayer dielectric layer 442 along a direction perpendicular to the top surface of the substrate 101 is greater than or equal to 500 angstroms.

[0132] The thickness of the second interlayer dielectric layer 442 along the direction perpendicular to the top surface of the substrate 101 is associated with the distance between the first lead line 414 and the second lead line 416. The thickness of the second interlayer dielectric layer 442 along the direction perpendicular to the top surface of the substrate 101 may be 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms or 1000 angstroms, etc.

[0133] In one embodiment, Fig. 9 As shown, a second metal structure and a third interlayer dielectric layer are formed on a side of the second interlayer dielectric layer away from the first groove, including steps S902 to S904.

[0134] Step S902 , forming a second metal material layer and a third dielectric material layer in sequence at least on the exposed surface of the second interlayer dielectric layer.

[0135] like Figure 4g~Figure 4h or Figure 5g~Figure 5hAs shown, the second metal material layer 450 and the third dielectric material layer 460 can be sequentially formed on the exposed surface of the second interlayer dielectric layer 442 by deposition processes such as CVD, ALD, HDP or PECVD.

[0136] exist Figure 4g In the structure shown, the second metal material layer also covers a portion of the surface of the substrate 101. Figure 5g In the structure shown, the second metal material layer also covers the surface of the fourth interlayer dielectric layer 490 .

[0137] Step S904 , grinding the second metal material layer and the third dielectric material layer to expose the second interlayer dielectric layer.

[0138] like Figure 4i or Figure 5i As shown, the second metal material layer 450 and the third dielectric material layer 460 may be polished to expose the second interlayer dielectric layer 442. The remaining second metal material layer constitutes the second metal structure 470, and the remaining third dielectric material layer constitutes the third interlayer dielectric layer 462.

[0139] In this embodiment, by utilizing the morphology of the second interlayer dielectric layer 442 to form the second electrode plate 472, the third lead 474 and the fourth lead 476, there is no need to perform photolithography and etching to form the connecting through holes for the third lead 474 and the fourth lead 476, thereby reducing the process difficulty and saving the photomask. In addition, in the process of grinding the second metal material layer 450 and the third dielectric material layer 460, very little of the second metal material layer and the third dielectric material layer are removed, which has little effect on the extension length of the second interlayer dielectric layer 442, the first lead 414, the second lead 416 and other structures in the direction perpendicular to the substrate 101, that is, it has little effect on the capacitance of the formed MIM capacitor.

[0140] In one embodiment, after forming the second metal structure and the third interlayer dielectric layer in the first groove, the method for preparing the semiconductor structure further includes the steps of forming a first connector on the exposed surface of the second lead and forming a second connector on the exposed surface of the third lead.

[0141] like Figure 4j or Figure 5jAs shown, the first connector 482 can be formed on the exposed surface of the second lead 416, and the second connector 484 can be formed on the exposed surface of the third lead 474 by deposition, photolithography and etching processes. Specifically, the third metal material layer can be deposited on the exposed surfaces of the first metal structure, the second interlayer dielectric layer, the second metal structure and the third interlayer dielectric layer, and then a portion of the third metal material layer is removed, and only the third metal material layer located on the surface of the second lead 416 and the third lead 474 is retained to form the first connector 482 and the second connector 484. Since the width of the removed third metal material layer in the direction parallel to the substrate is much larger than the width of the first connector 482 and the second connector 484, compared with the method of forming a metal connection line groove in the dielectric layer by photolithography, the etching window can be enlarged and the etching difficulty can be reduced.

[0142] Optionally, in one embodiment, the first connecting member 482 may be formed on the exposed surface of the first lead wire 414 , and the second connecting member 484 may be formed on the exposed surface of the fourth lead wire 476 .

[0143] Optionally, in one embodiment, the first connecting member 482 may be formed on the exposed surface of the first lead wire 414 , and the second connecting member 484 may be formed on the exposed surface of the third lead wire 474 .

[0144] Optionally, in one embodiment, the first connection member 482 may be formed on the exposed surface of the second lead line 416 , and the second connection member 484 may be formed on the exposed surface of the fourth lead line 476 .

[0145] In one embodiment, the thickness of the first lead line 414 and the second lead line 416 along the direction in which the first lead line 414 and the second lead line 416 are arranged at intervals ranges from 40 nanometers to 80 nanometers, for example, it can be 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers, or 80 nanometers.

[0146] In one embodiment, the thickness of the third lead line 474 and the fourth lead line 476 in the direction in which the first lead line 414 and the second lead line 416 are arranged at intervals ranges from 40 nanometers to 80 nanometers, for example, it can be 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers, or 80 nanometers.

[0147] In one embodiment, the height range of the first lead line 414 and the second lead line 416 along the direction perpendicular to the top surface of the substrate 101 is 2000 angstroms-3000 angstroms, for example, it can be 2000 angstroms, 2100 angstroms, 2200 angstroms, 2300 angstroms, 2400 angstroms, 2500 angstroms, 2600 angstroms, 2700 angstroms, 2800 angstroms, 2900 angstroms or 3000 angstroms, etc.

[0148] It should be understood that, although the steps in the above-mentioned flowcharts are sequentially displayed in the order shown in the figure, these steps are not necessarily executed in sequence in this order. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in each flowchart may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0149] In one embodiment, the present application further provides a semiconductor structure, which can be prepared by the method for preparing the semiconductor structure provided by any of the above embodiments.

[0150] As an example, see Figure 4i or Figure 5i The semiconductor structure includes a substrate 101, a first metal structure 410, a first interlayer dielectric layer 420, a second interlayer dielectric layer 442, a second metal structure 470 and a third interlayer dielectric layer 462. The first metal structure 410 includes a first electrode 412, a first lead 414 and a second lead 416. The first end of the first electrode 412 contacts the first lead 414, and the second end of the first electrode 412 contacts the second lead 416 to form a first groove. The first interlayer dielectric layer 420 is located on a side of the first electrode 412 away from the substrate 101, and the second interlayer dielectric layer 442 is located on a side of the first dielectric layer 420 away from the first electrode 412, as well as the sidewalls of the first lead 414 and the sidewalls of the second lead 416. The second metal structure 470 includes a second electrode plate 472, a third lead 474, and a fourth lead 476. The first end of the second electrode plate 472 contacts the third lead 474, and the second end of the second electrode plate 472 contacts the fourth lead 476 to form a second groove. The third interlayer dielectric layer 462 fills the second groove.

[0151] The first electrode plate 412, the first interlayer dielectric layer 420, the second interlayer dielectric layer 442 and the second electrode plate 472 constitute a MIM capacitor. The first lead wire 414 and the second lead wire 416 can be used to lead the first electrode plate 412 to connect with other structures, and the third lead wire 474 and the fourth lead wire 476 can be used to lead the second electrode plate 472 to connect with other structures.

[0152] The specific definition of each film layer in the semiconductor structure can be found in the above description of the preparation method of the semiconductor structure, which will not be repeated here.

[0153] The semiconductor structure preparation method and semiconductor structure of the present application have the following unexpected beneficial effects:

[0154] First, in the process of forming the first metal structure 410, the positions of the first lead line 414 and the second lead line 416 are defined by removing a film layer whose width in a direction parallel to the substrate is much larger than the width of the first lead line 414 and the second lead line 416. Compared with the traditional method of forming a connecting through hole through a photolithographic dielectric layer, the etching window is increased and the etching difficulty is reduced.

[0155] Second, the first interlayer dielectric layer 420 and the second interlayer dielectric layer 442 serve as the capacitor dielectric layers of the MIM capacitor that is finally formed. The capacitance value of the MIM capacitor can be adjusted by controlling the thickness of the retained first interlayer dielectric layer 420 and the thickness of the formed second interlayer dielectric layer 442, thereby achieving controllable capacitance of the MIM capacitor. The thickness of the second interlayer dielectric layer 442 can also be controlled to avoid electrical crosstalk caused by adjacent lead lines being too close.

[0156] Third, in the process of forming the second metal structure 470, since the second interlayer dielectric layer 442 inherits the cross-sectional shape of the first metal structure 410 and presents a "concave" shape, the shape of the second interlayer dielectric layer 442 can be used to form the second electrode 472, the third lead line 474, the fourth lead line 476 and the third interlayer dielectric layer 462 through a deposition process, without the need to perform photolithography operations to form connecting through holes, which not only reduces the process difficulty, but also saves masks and reduces preparation costs.

[0157] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0158] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0159] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; A first metal structure and a first interlayer dielectric layer are formed on the substrate; wherein the first metal structure includes a first electrode plate, a first lead wire and a second lead wire, a first end of the first electrode plate contacts the first lead wire, and a second end of the first electrode plate contacts the second lead wire to form a first groove; and the first interlayer dielectric layer fills the first groove; Removing a portion of the first interlayer dielectric layer to expose the sidewalls of the first lead wire and the sidewalls of the second lead wire; forming a second interlayer dielectric layer on the exposed sidewalls of the first lead wire, the sidewalls of the second lead wire, and a side of the first interlayer dielectric layer away from the first electrode plate; A second metal structure and a third interlayer dielectric layer are formed on a side of the second interlayer dielectric layer away from the first groove; wherein the second metal structure includes a second electrode plate, a third lead wire, and a fourth lead wire, the first end of the second electrode plate contacts the third lead wire, and the second end of the second electrode plate contacts the fourth lead wire to form a second groove, and the third interlayer dielectric layer fills the second groove.

2. The method according to claim 1, characterized in that The second interlayer dielectric layer is formed on the exposed sidewall of the first lead wire, the sidewall of the second lead wire, and the side of the first interlayer dielectric layer away from the first electrode plate, including: forming a first dielectric material layer on the first metal structure and the first interlayer dielectric layer; At least the first dielectric material layer on the top surface of the first lead-out line and the second lead-out line is removed to form the second interlayer dielectric layer, and the second interlayer dielectric layer is flush with the first lead-out line and the second lead-out line.

3. The method according to claim 1, characterized in that The step of forming a first metal structure and a first interlayer dielectric layer on the substrate comprises: forming the first electrode plate and a first interlayer dielectric layer located on the first electrode plate on the substrate; forming a first metal material layer on the surface of the substrate and the first interlayer dielectric layer; The first metal material layer located on the top surface of the first interlayer dielectric layer and a portion of the first metal material layer located on the substrate are removed to form the first lead wire and the second lead wire respectively located at two ends of the first electrode plate.

4. The method according to claim 1, characterized in that: The step of forming a first metal structure and a first interlayer dielectric layer on the substrate comprises: forming a fourth interlayer dielectric layer having a third groove on the substrate; the third groove exposes the substrate; Sequentially forming a first metal material layer and a second dielectric material layer on the surfaces of the third groove and the fourth interlayer dielectric layer; The first metal material layer and the second dielectric material layer are subjected to grinding treatment to expose the fourth interlayer dielectric layer; the remaining first metal material layer constitutes the first metal structure, and the remaining second dielectric material layer constitutes the first interlayer dielectric layer.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: The thickness of the second interlayer dielectric layer along a direction perpendicular to the top surface of the substrate is greater than or equal to 500 angstroms.

6. The method according to claim 1, characterized in that A second metal structure and a third interlayer dielectric layer are formed on a side of the second interlayer dielectric layer away from the first groove, including: forming a second metal material layer and a third dielectric material layer in sequence at least on the exposed surface of the second interlayer dielectric layer; The second metal material layer and the third dielectric material layer are subjected to grinding treatment to expose the second interlayer dielectric layer; the remaining second metal material layer constitutes the second metal structure, and the remaining third dielectric material layer constitutes the third interlayer dielectric layer.

7. The method according to claim 1, characterized in that After forming a second metal structure and a third interlayer dielectric layer in the first groove, the method further includes: forming a first connecting member on an exposed surface of the first lead wire or the second lead wire; A second connection member is formed on an exposed surface of the third lead wire or the fourth lead wire.

8. The method according to claim 1, characterized in that The thickness of the first electrode plate along a direction perpendicular to the top surface of the substrate ranges from 700 angstroms to 1500 angstroms.

9. The method according to claim 1, characterized in that: The method further comprises at least one of the following features: The thickness of the first lead wire and the second lead wire along the direction in which the first lead wire and the second lead wire are arranged spaced apart is in the range of 40 nanometers to 80 nanometers; The height of the first lead wire and the second lead wire in a direction perpendicular to the top surface of the substrate ranges from 2000 angstroms to 3000 angstroms; The thickness of the third lead wire and the fourth lead wire along the direction in which the first lead wire and the second lead wire are arranged at intervals ranges from 40 nanometers to 80 nanometers.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9.

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